Semiconductor device

Abstract

A semiconductor device includes a base insulating pattern, a separation wall disposed on the base insulating pattern, a first channel structure and a second channel structure disposed apart from each other with the separation wall between the first channel structure and the second channel structure, a gate structure surrounding the first channel structure and the second channel structure, a first source / drain pattern connected to opposite sides of the first channel structure, a second source / drain pattern connected to opposite sides of the second channel structure and spaced apart from the first source / drain pattern with the separation wall between the first source / drain pattern and the second source / drain pattern, and a lower contact electrode structure connected to lower portions of the first source / drain pattern and the second source / drain pattern. The separation wall extends in a direction toward a lower surface of the base insulating pattern, and the separation wall extends through the lower contact electrode structure.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0193163, filed on December 20, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices. Background Technology

[0003] Semiconductors are materials that fall between conductors and insulators, and are defined as materials that conduct electricity under predetermined conditions. By using such semiconductor materials, various semiconductor devices can be manufactured, including, for example, memory devices. These semiconductor devices can be used in a variety of electronic devices.

[0004] As the electronics industry develops, the requirements for the characteristics of semiconductor devices are increasing. For example, there are increasing demands for high reliability, high speed, and / or versatility in semiconductor devices. To meet these requirements, the structure within semiconductor devices is becoming increasingly complex and integrated. As transistor size decreases, coupling can occur between components, which can reduce the operating speed of semiconductor devices and degrade their reliability.

[0005] Recently, research has been conducted to improve routing congestion and scale up the size of semiconductor devices by setting up a power delivery network (PDN) on the back surface of the substrate for providing signal wiring to semiconductor devices. Summary of the Invention

[0006] The embodiments attempt to provide a semiconductor device that can improve reliability.

[0007] Embodiments of this disclosure provide a semiconductor device comprising: a substrate insulating pattern; a partition wall disposed on the substrate insulating pattern; a first channel structure and a second channel structure disposed separately from each other, the partition wall being between the first channel structure and the second channel structure; a gate structure surrounding the first channel structure and the second channel structure; a first source / drain pattern connected to an opposite side of the first channel structure; a second source / drain pattern connected to an opposite side of the second channel structure and spaced apart from the first source / drain pattern, the partition wall being between the first source / drain pattern and the second source / drain pattern; and a lower contact electrode structure connected to a lower portion of the first source / drain pattern and a lower portion of the second source / drain pattern, wherein the partition wall extends in a direction toward a lower surface of the substrate insulating pattern and extends through the lower contact electrode structure.

[0008] Embodiments of this disclosure provide a semiconductor device comprising: a substrate insulating pattern; a partition wall disposed on the substrate insulating pattern; a first channel structure and a second channel structure disposed separately from each other, the partition wall being between the first channel structure and the second channel structure; a gate structure surrounding the first channel structure and the second channel structure; a first source / drain pattern connected to an opposite side of the first channel structure; a second source / drain pattern connected to an opposite side of the second channel structure and spaced apart from the first source / drain pattern, the partition wall being between the first source / drain pattern and the second source / drain pattern; a lower contact electrode structure connected to a lower portion of the first source / drain pattern and a lower portion of the second source / drain pattern; a power rail disposed below the substrate insulating pattern; a device isolation layer disposed on a first side of the first source / drain pattern or the second source / drain pattern; and one or more connecting lines disposed within the device isolation layer and spaced apart from the power rail.

[0009] Embodiments of this disclosure provide a semiconductor device comprising: a substrate insulating pattern; a partition wall extending in a first direction parallel to a first surface of the substrate insulating pattern and including a first end extending into the interior of the substrate insulating pattern; a first channel structure and a second channel structure disposed on the substrate insulating pattern and spaced apart from each other in a second direction intersecting the first direction, the partition wall being between the first channel structure and the second channel structure, each of the first channel structure and the second channel structure including a first side surface in contact with the partition wall; a gate structure surrounding the first channel structure and the second channel structure; a first source / drain pattern connected to opposite sides of the first channel structure; a second source / drain pattern connected to opposite sides of the second channel structure and spaced apart from the first source / drain pattern, the partition wall being between the first source / drain pattern and the second source / drain pattern; a lower contact electrode structure connected to the lower portion of the first source / drain pattern and the lower portion of the second source / drain pattern; a power rail disposed below the substrate insulating pattern; a first lower insulating pattern disposed between the lower contact electrode structure and the power rail; and a lower contact via. The device isolation layer is disposed on a first side of the first source / drain pattern or the second source / drain pattern and covers the side surface of the substrate insulation pattern; and one or more connecting lines are disposed within the device isolation layer and spaced apart from the power rail, wherein the partition wall extends through the lower contact electrode structure and has a lower surface disposed at a height between the height of the upper surface of the power rail and the height of the lower surface of the lower contact electrode structure, the lower contact electrode structure includes a first lower contact electrode and a second lower contact electrode, the first lower contact electrode is connected to one of the first source / drain patterns, the second lower contact electrode is connected to one of the second source / drain patterns, and the one or more connecting lines include a first connecting line and a second connecting line, the first connecting line connecting the first lower contact electrode and the second lower contact electrode to each other, and the second connecting line connecting at least one of the first source / drain pattern and the second source / drain pattern to the gate structure.

[0010] Embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a partition wall on a substrate, the partition wall extending in a downward direction of the substrate; forming a first channel structure and a second channel structure on opposite sides of the partition wall; forming a gate structure surrounding the first channel structure and the second channel structure; forming a first source / drain pattern on opposite sides of the first channel structure and forming a second source / drain pattern on opposite sides of the second channel structure; and forming a lower contact electrode structure below the first source / drain pattern and the second source / drain pattern, the lower contact electrode structure being connected to the first source / drain pattern and the second source / drain pattern, wherein the step of forming the lower contact electrode structure may include disposing the lower surface of the lower contact structure at a height higher than the height of the lower surface of the partition wall.

[0011] In a method for manufacturing a semiconductor device according to an embodiment, the step of setting the lower surface of the lower contact structure at a height higher than the lower surface of the separator wall may include: removing a substrate disposed below a first source / drain pattern and a second source / drain pattern; forming a substrate insulating pattern by filling the portion of the removed substrate with an insulating material; removing a portion of the substrate insulating pattern to expose the lower regions of the first source / drain pattern and the second source / drain pattern; filling a portion of the removed substrate insulating layer with a conductive material; and exposing the lower regions of the separator wall by etching the conductive material.

[0012] In the manufacturing method for a semiconductor device according to an embodiment, as the lower region of the partition wall is exposed, the lower contact electrode structure can be separated into a first lower contact electrode and a second lower contact electrode.

[0013] The method of manufacturing a semiconductor device according to an embodiment may further include: forming a lower insulating layer below a substrate insulating layer; forming a lower contact via extending through a portion of the lower insulating layer and having an upper surface connected to a lower surface of a first source / drain pattern or a second source / drain pattern; and forming a power rail below the substrate insulating layer, in which the lower contact via and a portion of the upper surface are in contact with each other.

[0014] The method for manufacturing a semiconductor device according to the embodiments may further include: forming a device isolation layer disposed on a first side of a first source / drain pattern or a second source / drain pattern; and forming a connecting line disposed separately from a power rail.

[0015] In a method for manufacturing a semiconductor device according to an embodiment, the step of forming interconnects may include: removing a portion of a substrate insulating layer, and forming a conductive material at a location that may include a portion of the substrate insulating layer that has been removed.

[0016] The method of manufacturing a semiconductor device according to the embodiments may further include: forming a lower insulating pattern disposed between a connecting line and a power rail.

[0017] According to an embodiment, it may be feasible to provide a semiconductor device that can improve reliability. Attached Figure Description

[0018] Figure 1 A top view of a semiconductor device according to an embodiment is shown.

[0019] Figure 2 Show along Figure 1 A sectional view taken from line I1-I1'.

[0020] Figure 3 Show along Figure 1 A sectional view taken from line I2-I2'.

[0021] Figure 4 Show along Figure 1 A sectional view taken from line I3-I3'.

[0022] Figure 5 Show along Figure 1 A sectional view taken from line I4-I4'.

[0023] Figure 6 Show along Figure 1 The sectional view taken from line I5-I5'.

[0024] Figure 7 Show along Figure 1 A sectional view taken from line I6-I6'.

[0025] Figure 8 A view is shown for describing a semiconductor device according to an embodiment.

[0026] Figure 9 A view is shown for describing a semiconductor device according to an embodiment.

[0027] Figure 10 A view is shown for describing a semiconductor device according to an embodiment.

[0028] Figure 11 A view is shown for describing a semiconductor device according to an embodiment.

[0029] Figures 12 to 62 A process cross-sectional view is shown to describe a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0030] The present disclosure will be described more fully below with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure.

[0031] Furthermore, since the dimensions and thicknesses of the constituent components shown in the accompanying drawings may be arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. Throughout this disclosure, the same reference numerals refer to the same or similar components.

[0032] Furthermore, unless explicitly stated otherwise, the words “comprising” and variations such as “including” or “containing” will be understood to imply inclusion of the stated elements but not exclusion of any other elements. When a component is described as “comprising” a particular element or group of elements, it will be understood that, unless the context otherwise indicates, the component is formed solely by the element or group of elements, or by elements or groups of elements that may be combined with additional elements to form the component. On the other hand, the term “consisting of” indicates that the component is formed solely by the listed element(s).

[0033] Furthermore, throughout the instruction manual, the phrase "in a plan view" refers to a view of the object viewed from above, and the phrase "in a sectional view" refers to a view of a section, which can be a vertical section (e.g., as if the object were viewed from the side after being cut vertically).

[0034] Ordinal numbers (such as "first," "second," "third," etc.) can simply be used as labels for specific elements, steps, etc., to distinguish them from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0035] As used herein, components described as “electrical connections” are configured such that electrical signals can be transmitted from one component to another (although such electrical signals may attenuate in strength as they are transmitted and may be transmitted selectively).

[0036] For example, spatial relative terms (such as “below,” “under,” “below,” “above,” “top,” “bottom,” “front,” “back,” etc.) may be used herein for ease of description to describe positional relationships such as those shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms also encompass different orientations of the apparatus.

[0037] It will be understood that when a component is referred to as being "connected" or "bonded" to another component or "on" another component, the component may be directly connected or bonded to the other component or directly on the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly connected," "directly attached," "directly linked," or "directly bonded" to another component, or referred to as being "in contact" with another component or "in contact" with another component (or any form of using the word "in contact"), there are no intermediate components at the point of contact. Furthermore, in the specification, the phrase "on" may refer to being positioned above, to the side, or below an object, and does not necessarily mean being positioned on the upper side of the object.

[0038] The accompanying drawings of the semiconductor device according to embodiments illustrate transistors including nanowires or nanosheets, multi-bridge channel field-effect transistors (MBCFET™), and fin transistors (FinFETs) including fin-patterned channel regions, but this disclosure is not limited thereto. It may be noted that the semiconductor device according to some embodiments may include tunneling FETs, 3D stacked field-effect transistors (3DSFETs), complementary field-effect transistors (CFETs), etc.

[0039] In the following text, reference will be made to Figures 1 to 6 A semiconductor device according to an embodiment is described. Specifically, Figure 1 A top view of a semiconductor device according to an embodiment is shown.

[0040] Figure 2 Show along Figure 1 A sectional view taken from line I1-I1'.

[0041] Figure 3 Show along Figure 1 A sectional view taken from line I2-I2'.

[0042] Figure 4 Show along Figure 1 A sectional view taken from line I3-I3'.

[0043] Figure 5 Show along Figure 1 A sectional view taken from line I4-I4'.

[0044] Figure 6 Show along Figure 1 The sectional view taken from line I5-I5'. Figure 7 Show along Figure 1 A sectional view taken from line I6-I6'. Figure 1 The semiconductor device according to the embodiment is shown as having a planar shape when viewed from above or below the substrate insulating pattern 103 in a third-direction D3.

[0045] Reference Figures 1 to 7 The semiconductor device according to the embodiment may include: a substrate insulating pattern 103; a partition wall 161 disposed on the substrate insulating pattern 103; channel structures CH disposed spaced apart from each other, with the partition wall 161 between the channel structures CH; a gate structure GS surrounding the channel structures CH; source / drain patterns 151 and 152 connected to opposite sides of each of the channel structures CH; and a lower contact electrode structure 197 connected to the lower portion of the source / drain patterns 151 and 152.

[0046] The substrate insulating pattern 103 may be formed of an insulating material. The substrate insulating pattern 103 may be formed of oxides, nitrides, oxynitrides, or combinations thereof. For example, the substrate insulating pattern 103 may be formed of silicon oxide (SiO2). The substrate insulating pattern 103 is shown as a single film, but this is only for better understanding and ease of description, and this disclosure is not limited thereto. The substrate insulating pattern 103 may be formed by etching the substrate 101 described below (see...). Figure 14 ) or pattern 105 below (see Figure 13 Then, the etched portion is filled with insulating material to form the part.

[0047] The first and second surfaces of the substrate insulating pattern 103 can be formed as surfaces parallel to the first direction D1 and the second direction D2, with the second direction D2 intersecting the first direction D1. For example, the first surface of the substrate insulating pattern 103 can be the upper surface of the substrate insulating pattern 103 and can be parallel to the first direction D1 and the second direction D2, and the second surface of the substrate insulating pattern 103 can be the lower surface of the substrate insulating pattern 103 and can be parallel to the first direction D1 and the second direction D2. The upper surface of the substrate insulating pattern 103 can be a surface opposite to the lower surface of the substrate insulating pattern 103 in a third direction D3. The third direction D3 can be a direction perpendicular to the first direction D1 and the second direction D2. The lower surface of the substrate insulating pattern 103 can be referred to as the back side of the substrate insulating pattern 103. In some embodiments, the logic circuitry of the cell region can be implemented on the upper surface of the substrate insulating pattern 103.

[0048] A semiconductor device according to an embodiment may include a plurality of substrate insulating patterns 103 spaced apart from each other along a second direction D2. The substrate insulating patterns 103 may extend in a first direction D1. The substrate insulating patterns 103 may be separated from each other along the second direction D2. For example, the substrate insulating patterns 103 may be disposed in a region where a P-channel metal-oxide-semiconductor (PMOS) will be formed. As another example, the substrate insulating patterns 103 may be disposed in a region where an N-channel metal-oxide-semiconductor (NMOS) will be formed. For example, in Figure 5In this embodiment, a PMOS may be formed in a substrate insulating pattern 103 disposed on the left side, and an NMOS may be formed in a substrate insulating pattern 103 disposed on the right side, but this disclosure is not limited thereto.

[0049] The semiconductor device according to an embodiment may include device isolation layers 112 disposed between substrate insulating patterns 103. Device isolation layers 112 electrically isolate components that are separated from each other. Specifically, device isolation layers 112 may be disposed on opposite sides of substrate insulating patterns 103 extending along a first direction D1. Device isolation layers 112 may be disposed on a first side of a first source / drain pattern 151 or a second source / drain pattern 152. Device isolation layers 112 may extend in the first direction D1. A plurality of device isolation layers 112 may be arranged spaced apart from each other in a second direction D2. Device isolation layers 112 and substrate isolation patterns 103 may be arranged alternately along the second direction D2.

[0050] In one embodiment, the lower surface of the device isolation layer 112 may be disposed at a height substantially the same as the lower surface of the substrate insulating pattern 103. The upper surface of the device isolation layer 112 may be disposed at a height lower than the upper surface of the substrate insulating pattern 103. However, this disclosure is not limited thereto, and the upper surface of the device isolation layer 112 may be disposed at a height substantially the same as the upper surface of the substrate insulating pattern 103. The device isolation layer 112 may cover at least a portion of the region on the opposite side of the substrate insulating pattern 103.

[0051] The device isolation layer 112 may be formed of an insulating material. The device isolation layer 112 may be formed of an insulating material different from the insulating material of the substrate insulating pattern 103, but this disclosure is not limited thereto. The device isolation layer 112 may be made of, for example, silicon oxide (SiO2) or silicon nitride (SiN). x The device isolation layer 112 is formed of silicon oxynitride (SiON) or a combination thereof. However, this disclosure is not limited thereto, and the device isolation layer 112 may be formed of various insulating materials. In one embodiment, as described herein, connecting lines 192a and 192b may be disposed inside the device isolation layer 112.

[0052] Partition walls 161 may be disposed on the substrate insulation pattern 103. For example, each partition wall 161 may be disposed on a corresponding one of the substrate insulation patterns 103. Partition walls 161 may extend along a first direction D1. Multiple partition walls 161 disposed on corresponding substrate insulation patterns 103 may be spaced apart from each other along a second direction D2. Figure 5As shown, one of the multiple partition walls 161 may be disposed on one of the substrate insulation patterns 103, while the other partition walls 161 may be disposed on different substrate insulation patterns 103, and the two partition walls 161 are spaced apart from each other along the second direction D2.

[0053] A partition wall 161 may be disposed between the side surfaces of the substrate insulating pattern 103. The partition wall 161 may include a region overlapping the substrate insulating pattern 103 in the second direction D2. The partition wall 161 may have a lower portion surrounded by the substrate insulating pattern 103. (Refer to...) Figure 5 The partition wall 161 may extend through the upper surface of the substrate insulating pattern 103 and toward the lower surface of the substrate insulating pattern 103. At least a portion of the lower and side surfaces of the partition wall 161 at a height equal to or lower than that at which the upper surface of the substrate insulating pattern 103 is disposed may be surrounded by the substrate insulating pattern 103. The substrate insulating pattern 103 may thus surround the lower portion of the partition wall 161, which extends partially but not completely through the substrate insulating pattern 103 in a third direction D3.

[0054] A partition wall 161 may be disposed between the side surfaces of each of the channel structure CH, gate structure GS, and source / drain pattern 150, which will be described later. The channel structure CH, gate structure GS, and source / drain pattern 150 disposed on the substrate insulating pattern 103 may each be spaced apart from each other, with the partition wall 161 between the channel structures CH, between the gate structures GS, and between the source / drain patterns 150. Specifically, two channel structures CH may be spaced apart from each other along a second direction D2, and a partition wall 161 extending along a first direction D1 is disposed between the two channel structures CH such that a partition wall 161 can separate the first channel structure CH and the second channel structure CH (e.g., and may be disposed between the first channel structure CH and the second channel structure CH) (e.g., as shown in the image). Figure 5 (As shown in the diagram). Two gate structures GS can be spaced apart from each other along the second direction D2, and a partition wall 161 extending along the first direction D1 is disposed between the two gate structures GS, such that the partition wall 161 can separate the first gate structure GS and the second gate structure GS (e.g., and can be disposed between the first gate structure GS and the second gate structure GS) (e.g., as shown in the diagram). Figure 5(As shown in the diagram). Two source / drain patterns 150 may be spaced apart from each other along a second direction D2, and a partition wall 161 extending along a first direction D1 is disposed between the two source / drain patterns 150, such that the partition wall 161 can separate the first source / drain pattern 151 and the second source / drain pattern 152 (e.g., and may be disposed between the first source / drain pattern 151 and the second source / drain pattern 152) (e.g., as shown in the diagram). Figure 4 and Figure 6 As shown in the diagram). Specifically, when in a sectional view (e.g., Figure 4 , Figure 5 and Figure 6 When observed in the image, two transistor structures, each including a corresponding channel structure CH, a corresponding gate structure GS, and a corresponding source / drain pattern 150, can be spaced apart from each other, with a partition wall 161 disposed between the two transistor structures on a substrate insulating pattern 103.

[0055] The upper surface of the partition wall 161 may contact the lower surface of the cover layer 142, which will be described later. The upper surface of the partition wall 161 may be positioned at a height substantially the same as the height of the upper surface of the gate structure GS, which will be described later. The lower surface of the partition wall 161 may be positioned between the upper and lower surfaces of the substrate insulating pattern 103. For example... Figure 5 As shown, the upper surface of the substrate insulating pattern 103 may be located within the uppermost plane, wherein the uppermost plane is at the top or uppermost boundary of the substrate insulating pattern 103, and the partition wall 161 may extend through the uppermost plane. The lower surface of the substrate insulating pattern 103 may be located within the lowermost plane, wherein the lowermost plane is at the bottom or lowermost boundary of the substrate insulating pattern 103, and the partition wall 161 may not extend through the lowermost plane. In one embodiment, the lower surface of the partition wall 161 may be disposed between the upper surface of the power rail 220, which will be described later, and the lower surface of the lower contact electrode structure 197. For example, as Figure 4 and Figure 6 As shown, the upper surface of the power rail 220 may be located in a first plane, and the lower surface of the lower contact electrode structure 197 may be located in a second plane, and the lower surface of the partition wall 161 may be located between the first plane and the second plane (e.g., at the height between the first plane and the second plane).

[0056] In one embodiment, the partition wall 161 may include a lower region 161a and an upper region 161b disposed on the lower region 161a. Specifically, refer to Figure 1 , Figure 4 and Figure 6 The partition wall 161 may be located in a region close to or adjacent to the source / drain pattern 150 along the second direction D2 (see...). Figure 1The lower region 161a and the upper region 161b are included. In a process of recessing a portion of a substrate or semiconductor layer to form a source / drain pattern 150, the formation of the lower region 161a and the upper region 161b may occur when a portion of the partition wall 161 is etched together with an etching material (etchant, etching gas, etc.).

[0057] The upper surface of the lower region 161a can contact the lower surface of the upper region 161b. The interface between the lower region 161a and the upper region 161b can be provided between the upper and lower surfaces of the source / drain pattern 150. For example, as Figure 4 and Figure 6 As shown, the upper surface of the source / drain pattern 150 may lie in a first plane, and the lower surface of the source / drain pattern 150 may lie in a second plane, and the interface between the lower region 161a and the upper region 161b may lie between the first and second planes (e.g., at a height between the first and second planes). The upper surface of the upper region 161b may be integrally formed with the capping layer 142, which will be described later (e.g., the upper region 161b and the capping layer 142, which will be described later, are formed simultaneously).

[0058] The partition wall 161 may be formed of an insulating material. The partition wall 161 may be made of, for example, silicon oxide (SiO2) or silicon nitride (SiN). x It is formed of silicon oxynitride (SiON) or combinations thereof. However, this disclosure is not limited thereto, and the separator 161 may be formed of various insulating materials. In some embodiments, the separator 161 may be formed of a low dielectric constant material. The separator 161 may be formed of a material having etch selectivity relative to the channel structure CH, which will be described later.

[0059] The channel structure CH can be disposed on a first surface of the substrate insulating pattern 103. The channel structures CH can be spaced apart on the substrate insulating pattern 103 in a first direction D1. The channel structures CH can also be spaced apart on the substrate insulating pattern 103 in a second direction D2. In one embodiment, a partition wall 161 can be disposed between two channel structures CH spaced apart in the second direction D2. In another embodiment, a partition wall 161 can be disposed between two channel structures CH spaced apart in the second direction D2 and disposed on one substrate insulating pattern 103. For example, and as... Figure 5 As shown, a first axis extending in the third direction D3 and perpendicular to the upper surface of the substrate insulating pattern 103 can pass through the first channel structure CH, a second axis extending in the third direction D3 and parallel to the first axis can pass through the second channel structure CH, and a third axis extending in the third direction D3 and parallel to the first and second axes and between the first and second axes can pass through the partition wall 161, which extends vertically along the third axis.

[0060] Each of the channel structures CH may include a first channel pattern 110a, a second channel pattern 110b, a third channel pattern 110c, and a fourth channel pattern 110d. Channel patterns 110a, 110b, 110c, and 110d may be arranged spaced apart from each other on a third direction D3. For example, each of the channel patterns 110a, 110b, 110c, and 110d may have a sheet shape. Each of the channel patterns 110a, 110b, 110c, and 110d may be a nanosheet having a thickness of several nanometers (e.g., in the range of 1 nanometer to 20 nanometers) along the third direction D3.

[0061] The channel structure CH provides a path for current to flow between the source / drain patterns 150, which will be described below. (Refer to...) Figure 2 and Figure 3 A channel structure CH may be disposed between source / drain patterns 150 to connect the source / drain patterns 150. The channel structure CH may extend through a portion of the gate structure GS in a direction intersecting the direction of the gate structure GS described below (e.g., a first direction D1). Figure 2 and Figure 4 In the diagram, the channel structure CH is shown having four channel patterns 110a, 110b, 110c and 110d arranged spaced apart on a third direction D3, but this disclosure is not limited thereto, and the number of stacked channel patterns 110a, 110b, 110c and 110d included in a channel structure CH may vary.

[0062] The channel structure CH can be formed of a semiconductor material. For example, the channel structure CH can be formed of a group IV semiconductor (such as Si, Ge), a group III-V compound semiconductor, a group II-VI compound semiconductor, etc. In one embodiment, a substrate insulating pattern 103 can be disposed below the lower part of the channel structure CH.

[0063] Channel patterns 110a, 110b, 110c, and 110d may each have a side surface that contacts the source / drain pattern 150 described later. (Refer to...) Figure 2 The opposite side surfaces of each of the channel patterns 110a, 110b, 110c and 110d may contact two source / drain patterns 150 disposed on opposite sides of the channel structure CH (e.g., adjacent to the opposite side surfaces of the channel structure CH).

[0064] Channel patterns 110a, 110b, 110c, and 110d may have regions that contact the main gate insulating layer 130M or the sub-gate insulating layer 130S, which will be described later. (Refer to...) Figure 5The upper and lower surfaces of each of the channel patterns 110a, 110b, 110c, and 110d may contact the main gate insulating layer 130M or the sub-gate insulating layer 130S. The first side surfaces of the channel patterns 110a, 110b, 110c, and 110d may contact the main gate insulating layer 130M. In one embodiment, the second side surfaces of the channel patterns 110a, 110b, 110c, and 110d may contact the side surface of the partition wall 161.

[0065] In one embodiment, the channel structure CH disposed on two different substrate insulating patterns 103 spaced apart from each other in the second direction D2 may comprise different types of semiconductor materials. For example, in Figure 5 In the diagram, the two channel structures CH disposed on the substrate insulating pattern 103 on the left side may include P-type semiconductor material, and the two channel structures CH disposed on the substrate insulating pattern 103 on the right side may include N-type semiconductor material. However, this disclosure is not limited thereto, and the channel structures CH disposed on two different substrate insulating patterns 103 may both include the same type of semiconductor material.

[0066] A gate structure GS may be disposed on a substrate insulating pattern 103. The gate structure GS may extend on the substrate insulating pattern 103 in a direction different from the extending direction of the substrate insulating pattern 103 and the partition wall 161. For example, the gate structure GS may extend on the substrate insulating pattern 103 in a direction intersecting the extending directions of the substrate insulating pattern 103 and the partition wall 161 (e.g., a second direction D2). The gate structures GS may be arranged spaced apart from each other in a first direction D1. The gate structure GS may include a sub-gate structure S_GS and a main gate structure M_GS. The sub-gate structure S_GS may be disposed on the substrate insulating pattern 103, and the main gate structure M_GS may be disposed on the sub-gate structure S_GS.

[0067] Each of the sub-gate structures S_GS can be formed from multiple layers. For example, each of the sub-gate structures S_GS may include a sub-gate electrode 120S and a sub-gate insulating layer 130S. The sub-gate structures S_GS and channel patterns 110a, 110b, 110c, and 110d may be alternately stacked on a third-direction D3. Figure 2 In this diagram, four sub-gate structures S_GS are depicted as arranged and spaced apart on the third-direction D3, but the number of arranged and spaced sub-gate structures S_GS is not limited to this. For example, the gate structure GS may include three sub-gate structures S_GS.

[0068] Multiple sub-gate electrodes 120S may be spaced apart from each other on the substrate insulating pattern 103. The sub-gate electrodes 120S and channel patterns 110a, 110b, 110c, and 110d may be stacked alternately and repeatedly (e.g., one channel pattern may be positioned above and below two sub-gate electrodes 120S, and one sub-gate electrode 120S may be positioned above and below two channel patterns). At least one of the upper and lower surfaces of the channel patterns 110a, 110b, 110c, and 110d may be covered by a sub-gate electrode 120S. For example, the lower surface of the first channel pattern 110a may be covered by a sub-gate electrode 120S, and the upper surface of the fourth channel pattern 110d may be covered by a sub-gate electrode 120S. The upper and lower surfaces of each of the second channel pattern 110b and the third channel pattern 110c may be covered by a sub-gate electrode 120S.

[0069] For example, the gate electrode 120S may be formed of at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxide nitride. For example, the sub-gate electrode 120S may be formed of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum ( The conductive metal oxides and conductive metal nitrides may include at least one of the above-mentioned materials, but this disclosure is not limited thereto. The conductive metal oxides and conductive metal nitrides may include the oxidized forms of the above-mentioned materials, but this disclosure is not limited thereto.

[0070] The sub-gate insulating layer 130S may be disposed along the periphery of the channel patterns 110a, 110b, 110c, and 110d. The sub-gate insulating layer 130S may be disposed between the channel patterns 110a, 110b, 110c, and 110d and the sub-gate electrode 120S. For example, refer to… Figure 2A portion of the sub-gate insulating layer 130S may be disposed above one of the channel patterns and below one of the sub-gate electrodes 120S, and another portion of the sub-gate insulating layer 130S may be disposed above one of the sub-gate electrodes 120S and below one of the channel patterns. The sub-gate insulating layer 130S may be formed of various insulating materials.

[0071] In one embodiment, the sub-gate insulating layer 130S is depicted as a single film, but this disclosure is not limited thereto. For example, the sub-gate insulating layer 130S may also be formed of a multilayer film comprising silicon dioxide (SiO2) and a high dielectric constant material. In this case, the high dielectric constant material may include substances having a higher dielectric constant than silicon dioxide (SiO2) (such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)).

[0072] The main gate structure M_GS can be disposed on the sub-gate structure S_GS and channel patterns 110a, 110b, 110c, and 110d. The main gate structure M_GS can be disposed on the upper surface of the uppermost channel pattern 110a among the channel patterns 110a, 110b, 110c, and 110d. (Refer to...) Figure 3 and Figure 5 The main gate structure M_GS can also be disposed on the device isolation layer 112. The main gate structure M_GS can cover the opposite side surface of the sub-gate structure S_GS.

[0073] The main gate structure M_GS may include a main gate electrode 120M and a main gate insulating layer 130M.

[0074] A main gate electrode 120M may be disposed on the sub-gate structure S_GS and channel patterns 110a, 110b, 110c, and 110d. The main gate electrode 120M may extend in a direction intersecting the direction of extension of the substrate insulating pattern 103. At least a portion of the main gate electrode 120M may be disposed on the alternately stacked sub-gate electrodes 120S and channel patterns 110a, 110b, 110c, and 110d. The remaining portion of the main gate electrode 120M may cover the side surfaces of each of the alternately stacked sub-gate electrodes 120S and channel patterns 110a, 110b, 110c, and 110d. Four surfaces of each of the channel patterns 110a, 110b, 110c, and 110d may be surrounded by the sub-gate electrodes 120S and / or the main gate electrode 120M.

[0075] The main gate electrode 120M may be formed of the same material as the sub-gate electrode 120S. For example, the main gate electrode 120M may be formed of at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0076] The main gate insulating layer 130M may extend along the side surface of the main gate electrode 120M. The main gate insulating layer 130M may extend along the side surface of the gate spacer 141, which will be described later. The main gate insulating layer 130M may be formed of various insulating materials. The main gate insulating layer 130M may be formed of the same material as the sub-gate insulating layer 130S.

[0077] In one embodiment, the main gate insulating layer 130M is depicted as a single film, but this disclosure is not limited thereto. For example, the main gate insulating layer 130M may also be formed of a multilayer film comprising silicon dioxide (SiO2) and a high dielectric constant material. In this case, the high dielectric constant material may include substances having a higher dielectric constant than silicon dioxide (SiO2) (such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)).

[0078] In one embodiment, the gate structures GS disposed on two different substrate insulating patterns 103 spaced apart from each other in the second direction D2 can be formed of different materials. For example, in Figure 5 In this context, when different types of transistor structures are respectively disposed on the substrate insulating pattern 103 disposed on the left and the substrate insulating pattern 103 disposed on the right, the materials contained in the gate electrode of each transistor structure can be different from each other. For example, in Figure 5 In this embodiment, when the P-type transistor structure is disposed on the substrate insulating pattern 103 disposed on the left, the gate electrodes 120M and 120S included in the first gate electrode structure GS1 can be formed of titanium nitride (TiN), but this disclosure is not limited thereto. For example, in Figure 5 In the present disclosure, when the N-type transistor structure is disposed on the substrate insulating pattern 103 disposed on the right, the gate electrodes 120M and 120S included in the second gate electrode structure GS2 may be formed of titanium aluminum carbide (TiAlC), but the present disclosure is not limited thereto.

[0079] In one embodiment, portions of the gate structure GS may contact the side surface of the partition wall 161. (See reference...) Figure 5 The first side surface of a plurality of sub-gate structures S_GS spaced apart on the third-party D3 may contact the side surface of the partition wall 161 (e.g., the first side surface of the partition wall 161). In one embodiment, the side surface of the main gate structure M_GS may contact the opposite side surface of the partition wall 161 (e.g., the second side surface of the partition wall 161 opposite to the first side surface).

[0080] The semiconductor device according to the embodiment may further include a cover layer 142 and a gate spacer 141.

[0081] Gate spacer 141 may be disposed on the side surface of the main gate electrode 120M. Gate spacer 141 may be disposed on the channel structure CH. Gate spacer 141 may not be disposed on the side surface of the sub-gate electrode 120S. Gate spacer 141 may not be disposed on the side surface of each of the channel patterns 110a, 110b, 110c, and 110d. Gate spacer 141 may not be disposed between the substrate insulating pattern 103 and the channel patterns 110a, 110b, 110c, and 110d. Gate spacer 141 may not be disposed between the channel patterns 110a, 110b, 110c, and 110d arranged on a third-direction D3. Gate spacer 141 is shown as a single film, but this is only for better understanding and ease of description, and this disclosure is not limited thereto.

[0082] For example, the gate spacer 141 may be made of silicon nitride (SiN). x At least one of silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof is formed. The gate spacer 141 is shown as a single film, but this is only for better understanding and ease of description, and the present disclosure is not limited thereto.

[0083] A capping layer 142 may be disposed on the main gate structure M_GS and the gate spacer 141, and may be stacked on the main gate structure M_GS and the gate spacer 141. In one embodiment, the capping layer 142 may extend in a first direction D1. The capping layer 142 may also be disposed on the interlayer insulating layer 171, which will be described later.

[0084] The capping layer 142 may be formed of at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof. The capping layer 142 may be formed of a material having etch selectivity relative to the first interlayer insulating layer 171 described below.

[0085] The source / drain pattern 150 may be disposed on the upper surface of the substrate insulating pattern 103. The channel structure CH and the gate structure GS may be disposed between the source / drain pattern 150 in the first direction D1. The source / drain pattern 150 and the channel structure CH may be arranged alternately along the first direction D1.

[0086] The source / drain pattern 150 can also be arranged in the second direction D2. (Refer to...) Figure 1 and Figures 4 to 6The substrate insulating patterns 103 may be arranged spaced apart from each other along the second direction D2, and the source / drain patterns 150 may be disposed on each of the substrate insulating patterns 103 such that the source / drain patterns 150 are also spaced apart from each other in the second direction D2 (e.g., as shown). Figure 4 As shown, the partition wall 161 is between the source / drain patterns 150.

[0087] In one embodiment, two source / drain patterns 150 disposed on a substrate insulating pattern 103 may be spaced apart from each other in the second direction D2, with a partition wall 161 between the two source / drain patterns 150. For example, refer to Figure 4 and Figure 6 The first source / drain pattern 151 and the second source / drain pattern 152 disposed on the substrate insulating pattern 103 are spaced apart from each other in the second direction D2, and a partition wall 161 is disposed between the first source / drain pattern 151 and the second source / drain pattern 152. In one embodiment, the first source / drain pattern 151 and the second source / drain pattern 152 can be separated from each other by the partition wall 161.

[0088] In one embodiment, the source / drain pattern 150 may include different types of semiconductor materials. For example, see reference... Figure 4 In the first source / drain pattern 151 and the second source / drain pattern 152 disposed on opposite side surfaces of the partition wall 161, the first may include a P-type semiconductor material, and the second may include an N-type semiconductor material. Specifically, the first source / drain pattern 151 may include a P-type semiconductor material, and the second source / drain pattern 152 may include an N-type semiconductor material. However, this disclosure is not limited thereto, and both the first source / drain pattern 151 and the second source / drain pattern 152 may include N-type semiconductor materials, or both may include P-type semiconductor materials.

[0089] Reference Figure 4 and Figure 6At least a portion of the first side surface of the source / drain pattern 150 may contact the partition wall 161. The source / drain pattern 150 may contact the lower region 161a and the side surface of the lower region 161a of the partition wall 161, but may not contact the upper region 161b of the partition wall 161. For example, the first source / drain pattern 151 may contact the first side of the lower region 161a of the partition wall 161, and the second source / drain pattern 152 may contact the opposite second side of the lower region 161a of the partition wall 161. In one embodiment, an etch stop film (or etch stop layer) 185, which will be described later, may be disposed between the upper region 161b of the partition wall 161 and the source / drain pattern 150 (e.g., the etch stop film 185 is disposed between the upper region 161b and the second source / drain pattern 152).

[0090] Source / drain patterns 150 can be disposed on opposite sides of the channel structure CH or the sub-gate structure S_GS. Specifically, two source / drain patterns 150 disposed on a substrate insulating pattern 103 can be spaced apart in a direction intersecting the direction of extension of the gate structure GS (e.g., a first direction D1), with the channel structure CH and / or the sub-gate structure S_GS between the two source / drain patterns 150. The source / drain patterns 150 can contact the channel structure CH or the sub-gate structure S_GS. The source / drain patterns 150 can contact the sub-gate insulating layer 130S of the sub-gate structure S_GS. Figure 2 As shown, the source / drain pattern 150 is disposed at a height that is lower than the height of the lowermost surface of the lowermost sub-gate electrode 120S among the sub-gate electrodes 120S spaced apart on the third direction D3. The side surface and the lower surface are in contact with the substrate insulating pattern 103.

[0091] Reference Figure 4 and Figure 6 The source / drain pattern 150 is depicted with the same width along the second direction D2, but this disclosure is not limited thereto. For example, the source / drain pattern 150 may have different widths along the second direction D2.

[0092] The semiconductor device according to an embodiment may further include an inner gate spacer 145 disposed between the source / drain pattern 150 and the sub-gate insulating layer 130S. The inner gate spacer 145 may be made of silicon nitride (SiN). x The semiconductor device may be formed from at least one of silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. However, this disclosure is not limited thereto, and the semiconductor device according to the embodiments may not include the inner gate spacer 145.

[0093] The source / drain pattern 150 can be formed from an epitaxial layer formed by selective epitaxial growth (SEG). The source / drain pattern 150 can be formed by removing the layer disposed on the substrate 101 (see...). Figure 14 At least a portion of the semiconductor layer on the substrate is then formed in the corresponding region using a selective epitaxial growth method.

[0094] The source / drain pattern 150 may include a semiconductor material. The source / drain pattern 150 may be formed of silicon (Si) or germanium (Ge). Furthermore, the source / drain pattern 150 may be formed of a binary or ternary compound comprising, for example, carbon (C), silicon (Si), germanium (Ge), and tin (Sn). For example, the source / drain pattern 150 may include silicon (Si), silicon-germanium (SiGe), germanium (Ge), silicon carbide (SiC), etc., but this disclosure is not limited thereto.

[0095] The semiconductor device according to an embodiment may further include a dummy semiconductor pattern 143 disposed below the source / drain pattern 150. The dummy semiconductor pattern 143 may be configured to connect the source / drain pattern 150 to the lower contact electrodes 197a and 197b, which will be described later. Figures 2 to 6 As shown in the illustration, the semiconductor device according to the embodiment may not include the dummy semiconductor pattern 143. For example, the dummy semiconductor pattern 143 may be formed below the source / drain pattern 150 that will be connected to the lower contact electrodes 197a and 197b. However, in other embodiments, the semiconductor device may not include the illustrated dummy semiconductor pattern 143, such that the dummy semiconductor pattern 143 may not be formed below the source / drain pattern 150, and the source / drain pattern 150 may not be connected to the lower contact electrodes 197a and 197b via the dummy semiconductor pattern 143.

[0096] Reference Figure 2 The dummy semiconductor pattern 143 may extend into the substrate insulating pattern 103 in a direction toward the lower surface of the substrate insulating pattern 103. The lower surface of the dummy semiconductor pattern 143 may be positioned relative to a third direction D3 between the height of the upper surface of the substrate insulating pattern 103 and the height of the lower surface of the substrate insulating pattern 103. The upper surface of the dummy semiconductor pattern 143 may contact the lower surface of the source / drain pattern 150. (Refer to...) Figure 2 The side and bottom surfaces of the dummy semiconductor pattern 143 can be covered by the substrate insulating pattern 103.

[0097] The dummy semiconductor pattern 143 may include a semiconductor material. In one embodiment, the dummy semiconductor pattern 143 may be formed of the same material as the source / drain pattern 150. For example, the dummy semiconductor pattern 143 may be formed of silicon germanium (SiGe). In this case, the germanium (Ge) concentration of the dummy semiconductor pattern 143 may differ from the germanium (Ge) concentration of the source / drain pattern 150. For example, the germanium (Ge) concentration of the dummy semiconductor pattern 143 may be higher than that of the source / drain pattern 150.

[0098] The semiconductor device according to the embodiment may further include an etch stop layer 185. The etch stop layer 185 may cover at least a portion of the upper surface and side surface of the source / drain pattern 150. The etch stop layer 185 may be disposed on at least a portion of the upper surface and side surface of the source / drain pattern 150. The etch stop layer 185 may also be disposed on the upper surface of the device isolation layer 112.

[0099] In one embodiment, the etch stop layer 185 may also be disposed between the source / drain pattern 150 and the partition wall 161. For example, the etch stop layer 185 may be disposed between the upper region 161b of the partition wall 161 and the source / drain pattern 150 (e.g., the second source / drain pattern 152). The etch stop layer 185 may not be disposed between the lower region 161a of the partition wall 161 and the source / drain pattern 150. The etch stop layer 185 may include a portion that contacts the upper region 161b of the partition wall 161.

[0100] The etch stop layer 185 may be formed of an insulating material. For example, the etch stop layer 185 may be formed of at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. The etch stop layer 185 is shown as a single film, but this is only for better understanding and ease of description, and this disclosure is not limited thereto.

[0101] and Figures 1 to 6 As shown in the diagram, the etch stop layer 185 can be omitted. In this case, the upper and side surfaces of the source / drain pattern 150 can be covered by the interlayer insulating layer 171, which will be described later.

[0102] The semiconductor device according to an embodiment may further include an interlayer insulating layer 171 disposed on the device isolation layer 112 and on the upper and side surfaces of the source / drain pattern 150. In one embodiment, an etch stop layer 185 may be disposed between the interlayer insulating layer 171 and the device isolation layer 112.

[0103] An interlayer insulating layer 171 may be disposed on the etch stop layer 185. In one embodiment, the interlayer insulating layer 171 may be configured to be adjacent to the side surface of the source / drain pattern 150, with the etch stop layer 185 located between the interlayer insulating layer 171 and the source / drain pattern 150. Optionally, when the semiconductor device does not include the etch stop layer 185, the interlayer insulating layer 171 may cover the side surface of the source / drain pattern 150 and may be in contact with the side surface of the source / drain pattern 150.

[0104] Interlayer insulating layer 171 may be formed of an insulating material. For example, interlayer insulating layer 171 may be formed of at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. Interlayer insulating layer 171 is shown as a single film, but this is only for better understanding and ease of description, and this disclosure is not limited thereto.

[0105] The semiconductor device according to an embodiment may further include a first upper contact electrode 191. The first upper contact electrode 191 may be disposed on the source / drain pattern 150. The first upper contact electrode 191 may be disposed between two main gate structures M_GS spaced apart from each other in a first direction D1.

[0106] Reference Figure 2 The semiconductor device according to the embodiment may further include an insulating liner 187 disposed between the first upper contact electrode 191 and the gate spacer 141. For example, the insulating liner 187 may be made of silicon oxide (SiO2) or silicon nitride (SiN). x It is formed from at least one of silicon oxynitride (SiON).

[0107] In one embodiment, the first side surface of the first upper contact electrode 191 may contact the partition wall 161. (See reference...) Figure 4 and Figure 6 The first side surface of the first upper contact electrode 191 can contact the upper region 161b of the partition wall 161.

[0108] and Figure 2 As shown, the width of the first upper contact electrode 191 along the horizontal direction (e.g., the first direction D1 and / or the second direction D2) may not be constant. For example, the first upper contact electrode 191 may have a sloping side surface, wherein, depending on the aspect ratio, the width of the lower portion of the first upper contact electrode 191 is narrower than the width of the upper portion of the first upper contact electrode 191. For example, the width of the first upper contact electrode 191 in the horizontal direction may gradually narrow towards the upper surface of the source / drain pattern 150 in the vertical third direction D3. Therefore, although Figure 2The first upper contact electrode 191 is shown as having a constant width from its lowermost surface to its uppermost surface; however, the first upper contact electrode 191 is not so limited, and it may have an increased width from its lowermost surface to its uppermost surface. In this case, at least a portion of the side surface of the first upper contact electrode 191 may not contact the insulating liner 187. In one embodiment, the upper surface of the first upper contact electrode 191 may be disposed in the same plane as either or both of the upper surfaces of the gate structure GS or the partition wall 161, and may be coplanar with either or both of the upper surfaces of the gate structure GS or the partition wall 161.

[0109] Reference Figure 2 and Figure 4 The first upper contact electrode 191 may be disposed within a recess in the source / drain pattern 150, and the first upper contact electrode 191 may extend to a predetermined depth. For example, the first upper contact electrode 191 may extend through a portion of an etch stop layer 185 disposed on the upper surface of the source / drain pattern 150, and extend into the interior of the source / drain pattern 150 to a predetermined depth. The semiconductor device according to the embodiment may further include a silicide layer 157a disposed between the first upper contact electrode 191 and the source / drain pattern 150.

[0110] When the semiconductor device according to the embodiment does not include the silicide layer 157a, a portion of the side surface and the lower surface of the first upper contact electrode 191 may contact the source / drain pattern 150.

[0111] The semiconductor device according to an embodiment may further include a second upper contact electrode 193 disposed on the gate structure GS. The second upper contact electrode 193 may extend through a portion of the capping layer 142. The lower surface of the second upper contact electrode 193 may contact the upper surface of the main gate electrode 120M.

[0112] The semiconductor device according to an embodiment may further include an upper contact via 195 disposed on the first upper contact electrode 191. The upper contact via 195 may extend through a portion of the cover layer 142. The lower surface of the upper contact via 195 may contact the upper surface of the first upper contact electrode 191. The upper contact via 195 may be connected to the source / drain pattern 150 through the first upper contact electrode 191.

[0113] The first upper contact electrode 191, the second upper contact electrode 193, and the upper contact via 195 may be formed of a conductive material. For example, the first upper contact electrode 191, the second upper contact electrode 193, and the upper contact via 195 may be formed of at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0114] The lower contact electrode structure 197 can be connected to the source / drain pattern 150. The lower contact electrode structure 197 can be connected to the source / drain pattern 150 and can provide power or an electrical signal to the source / drain pattern 150. (See reference...) Figure 1 , Figure 2 , Figure 4 and Figure 6 The lower contact electrode structure 197 can be connected to the lower portion of the source / drain pattern 150. The semiconductor device according to the embodiment may further include a silicide layer 157b disposed along the interface between the lower contact electrode structure 197 and the source / drain pattern 150, the silicide layer 157b contacting the lower surface of the source / drain pattern 150 and the upper surface of the lower contact electrode structure 197.

[0115] In one embodiment, the lower contact electrode structure 197 may be connected to two source / drain patterns 150 disposed on a substrate insulating pattern 103. The lower contact electrode structure 197 may include a first lower contact electrode 197a connected to the lower portion of a first source / drain pattern 151 and a second lower contact electrode 197b connected to the lower portion of a second source / drain pattern 152. In one embodiment, the lower contact electrode structure 197 may be penetrated by a partition wall 161 extending in a third direction D3, the partition wall 161 separating the lower contact electrode structure 197 into a first lower contact electrode 197a (e.g., disposed on one side of the partition wall 161) and a second lower contact electrode 197b (e.g., disposed on the opposite side of the partition wall 161). In one embodiment, the lower surface of the partition wall 161 may be disposed relative to the third direction D3 between the lower surface of the lower contact electrode structure 197 and the upper surface of the power rail 220, which will be described later. The first lower contact electrode 197a and the second lower contact electrode 197b can be separated from each other by a partition wall 161. The first side surface of the partition wall 161 is in contact with the first lower contact electrode 197a, and the opposite second side surface of the partition wall 161 is in contact with the second lower contact electrode 197b.

[0116] In one embodiment, the lower contact electrode structure 197 may be disposed within the substrate insulating pattern 103. The lower surface of the lower contact electrode structure 197 may be disposed at a height higher than the lower surface of the substrate insulating pattern 103 and the lower surface of the device isolation layer 112. The lower contact electrode structure 197 may have a side surface that contacts the substrate insulating pattern 103. The lower contact electrode structure 197 may have a side surface that contacts the device isolation layer 112.

[0117] The lower contact electrode structure 197 may be formed of a conductive material. For example, the lower contact electrode structure 197 may be formed of at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0118] The semiconductor device according to an embodiment may further include a power rail 220 disposed below the substrate insulating pattern 103. The power rail 220 may supply power to the semiconductor device according to an embodiment. The semiconductor device according to an embodiment may include a plurality of power rails 220 extending in, for example, a first direction D1 and / or a second direction D2. Each of the power rails 220 may extend in a direction intersecting the direction in which the gate structure GS extends. For example, referring to… Figure 1 The power rails 220 may extend in the first direction D1. For example, the power rails 220 may be spaced apart from each other in the second direction D2. Thus, the first power rail may extend in the first direction D1, while the second power rail may be spaced apart from the first power rail in the second direction D2 (e.g., Figure 4 (as shown in the diagram), and the second electric rail may extend substantially parallel to the first electric rail in the first direction D1. Figure 1 As shown in the diagram, the power rail 220 may also extend in a direction parallel to the direction in which the gate structure GS extends (e.g., the second direction D2).

[0119] In one embodiment, each of the power rails 220 may be connected to an external power supply. For example, the power rails 220 may be connected to an external input power supply to provide power to the semiconductor device according to the embodiment. For example, the power rails 220 may also be grounded. In one embodiment, the power rails 220 may be electrically connected to a circuit (e.g., an external power supply) such that the circuit can provide power to the power rails 220 and thus to the semiconductor device. In this way, the power supplied to the power rails 220 can be distributed to various components, circuits, etc., of the semiconductor device. The circuits or components of the semiconductor device can draw current from the power rails 220, thus allowing the circuits or components to function. In an embodiment, the power rails 220 may be connected to external pins, pads, etc., and may receive voltage from a power supply (such as, for example, a voltage regulator, a DC-DC converter, a battery, a power management integrated circuit, etc.). In an embodiment, the power rail 220 may have a line width greater than that of the signal line (e.g., the power rail 220 may have a line width between 2 times (2x) and 10 times (10x) the width of the signal line), and the power rail 220 may carry a current in the range of 1 mA to 100 mA or higher.

[0120] Each of the power rails 220 can be connected to a corresponding lower contact electrode structure 197 to provide power to the source / drain pattern 150. Specifically, in Figure 4 and Figure 6In the diagram, two power rails 220 located on the left side can be connected to the first lower contact electrode 197a and the second lower contact electrode 197b, respectively. For example, one power rail 220 can be connected to the first lower contact electrode 197a through one of the lower contact vias 210, while the other power rail 220 can be connected to the second lower contact electrode 197b through a different lower contact via 210. In one embodiment, the power rails 220 and the lower contact electrodes 197a and 197b can be connected to each other through the lower contact vias 210, which will be described later.

[0121] The semiconductor device according to an embodiment may further include a lower insulating layer 167 disposed below the lower surface of the substrate insulating pattern 103 and the lower surface of the device isolation layer 112. The lower insulating layer 167 may surround the side surface of the power rail 220. The lower insulating layer 167 may electrically isolate the first power rail 220 from the second power rail 220. Figure 4 As shown, the lower insulation layer 167 and the power rail 220 may be arranged alternately along the second direction D2.

[0122] The semiconductor device according to an embodiment may further include a lower insulating pattern 163 disposed between the lower contact electrode structure 197 and the power rail 220. The lower insulating pattern 163 may have at least some regions on its upper surface that contact the lower surface of the lower contact electrode structure 197. For example, a first upper surface of the lower insulating pattern 163 may contact a first lower contact electrode 197a, and a second upper surface of the lower insulating pattern 163 may contact a second lower contact electrode 197b. In one embodiment, the lower surface of the lower insulating pattern 163 may be disposed at a height substantially the same as the height of the lower surface of the substrate insulating pattern 103. The lower insulating pattern 163 may have at least some regions on its lower surface that contact the upper surface of the power rail 220.

[0123] In one embodiment, the lower insulating pattern 163 may surround at least a portion of the lower region of the partition wall 161. Specifically, the lower insulating pattern 163 may surround a portion of the partition wall 161 disposed at a height lower than the lower surface of the lower contact electrode structure 197. The lower region of the partition wall 161 may extend into and contact the lower insulating pattern 163. The partition wall 161 may extend partially but not completely through the lower insulating pattern 163 such that the lowermost surface of the lower insulating pattern 163 is below the lowermost surface of the partition wall 161, and the uppermost surface of the lower insulating pattern 163 is above the lowermost surface of the partition wall 161.

[0124] The lower insulating pattern 163 can be formed of an insulating material. For example, the lower insulating pattern 163 can be formed of silicon oxide (SiO2), silicon nitride (SiN2), etc. x It may be formed from at least one of silicon oxynitride (SiON), but this disclosure is not limited thereto.

[0125] The semiconductor device according to an embodiment may further include a lower contact via 210 disposed between the lower contact electrode structure 197 and the power rail 220. The lower contact via 210 can connect the lower contact electrodes 197a and 197b to the power rail 220. (See also...) Figure 1 , Figure 4 and Figure 6 The lower contact via 210 may extend through the lower insulating pattern 163 in the third direction D3. The upper surface of the lower contact via 210 may be connected to the lower surface of one of the lower contact electrodes 197a and 197b, and the lower surface of the lower contact via 210 may be connected to the upper surface of one of the power rails 220.

[0126] In one embodiment, the width of the lower contact via 210 in the horizontal direction may be narrower and smaller than the width of each of the lower contact electrodes 197a and 197b in the horizontal direction. However, this disclosure is not limited thereto, and the width of the lower contact via 210 in the horizontal direction may be substantially the same as the width of each of the lower contact electrodes 197a and 197b in the horizontal direction. Figure 4 As shown, the lower contact via 210 may include a width in the second direction D2 that increases from the uppermost surface of the lower contact via 210 toward the lowermost surface of the lower contact via 210 in the third direction D3 (that is, the lower contact via 210 may have a tapered shape). However, the lower contact via 210 is not limited to this shape, and instead, the lower contact via 210 may include a constant width in the second direction D2.

[0127] The lower contact via 210 may be formed of a conductive material. For example, the lower contact via 210 may be formed of at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0128] Reference Figure 6 The semiconductor device according to the embodiment may further include a connection pattern 194 connecting two different lower contact electrode structures 197 to each other. The connection pattern 194 may be commonly connected to two different source / drain patterns 150, so that signals output from the two different source / drain patterns 150 can be transmitted to other nodes. Specifically, the connection pattern 194 may transmit signals output from at least one of the two different source / drain patterns 150 to another node. For example, the connection pattern 194 may transmit signals output from at least one of the two different source / drain patterns 150 to the main gate electrode 120M via a second connection line 192b, which will be described later.

[0129] Reference Figure 1 and Figure 6The connection pattern 194 can connect the lower contact electrode structures 197 of the two source / drain patterns 150 respectively disposed on two different substrate insulating patterns 103.

[0130] In one embodiment, the lower surface of the connecting pattern 194 may be disposed at the same height as the lower surface of the lower contact electrode structure 197. The upper surface of the connecting pattern 194 may be disposed at a height lower than the upper surface of the lower contact electrode structure 197. However, this disclosure is not limited thereto, and the upper surface of the connecting pattern 194 may be disposed at a height substantially the same as the upper surface of the lower contact electrode structure 197.

[0131] In one embodiment, the connection pattern 194 may be formed simultaneously with the lower contact electrode structure 197 in the same process. In another embodiment, the connection pattern 194 may be integrally formed with the lower contact electrode structure 197 (e.g., the connection pattern 194 and the lower contact electrode structure 197 are formed of the same material).

[0132] The connection pattern 194 may include a conductive material. In one embodiment, the connection pattern 194 may be formed of the same material as the material of the lower contact electrode structure 197. For example, the connection pattern 194 may be formed of at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0133] The semiconductor device according to the embodiment may further include connection lines 192a and 192b. Connection lines 192a and 192b can transmit electrical signals between components included in the semiconductor device according to the embodiment. For example, connection lines 192a and 192b can transmit a signal output from source / drain pattern 150 to another source / drain pattern 150 or main gate electrode 120M. For example, the electrical signals transmitted via connection lines 192a and 192b may be smaller in amplitude compared to the input power connected to power rail 220.

[0134] In the semiconductor device according to the embodiment, the connecting lines 192a and 192b may be disposed within the substrate insulating pattern 103 or the device isolation layer 112. Specifically, the connecting lines 192a and 192b may be disposed at a height higher than the height of the upper surface of the power rail 220, and at a height lower than the height of the upper surface of the substrate insulating pattern 103 or the upper surface of the device isolation layer 112. In one embodiment, the connecting lines 192a and 192b may not be disposed at the same height as the power rail 220.

[0135] In one embodiment, the connecting lines 192a and 192b may be disposed inside the substrate insulating pattern 103 or the device isolation layer 112, thereby ensuring process margin when the power rail 220 is formed under the substrate insulating pattern 103, thereby improving the reliability of the semiconductor device.

[0136] Reference Figure 4 and Figure 6 The first connecting line 192a can connect two adjacent source / drain patterns 150 to each other. Specifically, the first connecting line 192a can be disposed within a substrate insulating pattern 103 and can connect two source / drain patterns 150 that are separately disposed in the second direction D2, with a partition wall 161 disposed between the two source / drain patterns 150. The first connecting line 192a can extend in the second direction D2. The first connecting line 192a can be connected to the source / drain pattern 150 via lower contact electrodes 197a and 197b. (Refer to...) Figure 4 and Figure 6 The first connecting line 192a can connect the first lower contact electrode 197a and the second lower contact electrode 197b, which are separated from each other by the partition wall 161.

[0137] At least a portion of the upper surface of the first connecting line 192a may contact the lower surface of the lower contact electrode structure 197. For example, a first portion of the upper surface of the first connecting line 192a may contact the lower surface of the first lower contact electrode 197a, and a second portion of the upper surface of the first connecting line 192a may contact the lower surface of the second lower contact electrode 197b. The first and second portions of the upper surface may be spaced apart and separated from each other by a partition wall 161. In one embodiment, the first connecting line 192a may surround at least a portion of the lower region of the partition wall 161. Specifically, the first connecting line 192a may surround a portion of the partition wall 161 located at a height lower than the lower surface of the lower contact electrode structure 197. The partition wall 161 may extend partially but not completely through the first connecting line 192a, such that the first connecting line 192a can electrically connect the first lower contact electrode 197a and the second lower contact electrode 197b. The side surface of the first connecting line 192a may contact the lower insulating pattern 163.

[0138] In one embodiment, the lower surface of the partition wall 161, which includes a lower region surrounded by the first connecting line 192a, may be positioned at a height higher than the lower surface of the partition wall 161, which includes a lower region surrounded by the lower insulating pattern 163. This may be due to a process characteristic where a portion of the lower region of the partition wall 161 is etched together with the lower insulating pattern 163 during the process of etching the lower insulating pattern 163 to form the first connecting line 192a.

[0139] In one embodiment, the first connecting line 192a may be spaced apart from the power rail 220. The first connecting line 192a may be spaced apart from the power rail 220 on a third direction D3. The lower insulation pattern 165, which will be described later, may be disposed between the first connecting line 192a and the power rail 220.

[0140] The second connection line 192b can connect the source / drain pattern 150 and the gate structure GS. Specifically, the second connection line 192b can connect two source / drain patterns 150 disposed on different substrate insulating patterns 103 to the gate structure GS. In one embodiment, the second connection line 192b can send a signal output from at least one of the two different source / drain patterns 150 to the gate structure GS. The second connection line 192b can transmit a signal output from at least one of the two different source / drain patterns 150 to the main gate electrode 120M.

[0141] Reference Figure 1 , Figure 3 , Figure 4 and Figure 6 The second connection line 192b may extend in the first direction D1, with its first end connected to the connection pattern 194, and its second end connected to the gate contact electrode 198, which will be described later. The second connection line 192b may be connected to the source / drain pattern 150 (e.g., as shown in the diagram) via the connection pattern 194. Figure 6 As shown, connection pattern 194 is electrically connected to the second connection line 192b and the source / drain pattern 150, and is connected to the main gate electrode 120M via the gate contact electrode 198 (e.g., as shown). Figure 3 As shown, the gate contact electrode 198 is electrically connected to the second connection line 192b and the main gate electrode 120M.

[0142] In one embodiment, the second connection line 192b may be disposed within the device isolation layer 112. The upper surface of the second connection line 192b may contact the device isolation layer 112, the connection pattern 194, and / or the gate contact electrode 198. The side surface of the second connection line 192b may contact the device isolation layer 112.

[0143] In one embodiment, the second connecting line 192b may be separately disposed from the power rail 220. The second connecting line 192b may be separately disposed from the power rail 220 on a third direction D3. A lower insulating pattern 164, which will be described later, may be disposed between the second connecting line 192b and the power rail 220. The second connecting line 192b may be separated from the power rail 220 by the lower insulating pattern 164.

[0144] The connecting lines 192a and 192b may be formed of a conductive material. The connecting lines 192a and 192b may be formed of at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0145] The semiconductor device according to an embodiment may include lower insulating patterns 164 and 165 disposed between the connection lines 192a and 192b and the power rail 220. The lower insulating patterns 164 and 165 may be formed of an insulating material. For example, the lower insulating patterns 164 and 165 may be made of silicon oxide (SiO2) or silicon nitride (SiN). x At least one of silicon oxynitride (SiON) is formed. Due to the arrangement of the lower insulating patterns 164 and 165, the connecting lines 192a and 192b can be separated from the power rail 220. For example, the lower insulating pattern 164 can be vertically disposed below and in contact with the second connecting line 192b. The lower insulating pattern 164 can be disposed on and vertically disposed above the lower insulating layer 167, such that the lower insulating pattern 164 is between the second connecting line 192b and the lower insulating layer 167. The lower insulating pattern 165 can be vertically disposed below and in contact with the first connecting line 192a. The lower insulating pattern 165 may be disposed on the lower insulating layer 167 and the power rail 220 and disposed vertically above the lower insulating layer 167 and the power rail 220, such that the lower insulating pattern 165 may be between the first connecting line 192a (e.g., on the upper side of the lower insulating pattern 165) and the lower insulating layer 167 and the power rail 220 (e.g., on the lower side of the lower insulating pattern 165).

[0146] Another semiconductor device according to an embodiment may also include a gate contact electrode 198 disposed between the second connection line 192b and the gate structure GS. For example... Figure 3 As shown, the gate contact electrode 198 can transmit an electrical signal from the second connection line 192b to the gate structure GS. The gate contact electrode 198 can extend on the third direction D3. A first end of the gate contact electrode 198 can be connected to the second connection line 192b, and a second end of the gate contact electrode 198 can be connected to the main gate electrode 120M.

[0147] The gate contact electrode 198 may be formed of a conductive material. For example, the gate contact electrode 198 may be formed of at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0148] Reference Figure 7The semiconductor device according to an embodiment may include node contact electrodes 199. For example, in some embodiments, the gate electrode and the source or drain electrode included in a transistor structure may be directly connected. In this case, such as Figure 7 As shown, the source / drain pattern 150 connected to the gate structure GS and the channel patterns 110a, 110b, 110c and 110d surrounded by the gate structure GS can be connected using node contact electrodes 199.

[0149] In one embodiment, the node contact electrode 199 may be disposed within the substrate insulating pattern 103. The node contact electrode 199 may have an upper surface that contacts the gate structure GS, and the node contact electrode 199 may have a first side surface that contacts the lower contact electrode structure 197. (Refer to...) Figure 7 The width of the node contact electrode 199 in the first direction D1 may gradually decrease as it approaches the lower surface of the gate structure GS. For example, the width of the node contact electrode 199 (e.g., the width of the node contact electrode 199 in the first direction D1) may decrease in the third direction D3 away from the power rail 220. (Refer to...) Figure 7 The node contact electrode 199 may have an inclined side surface having a width in a first direction D1 that narrows from the lower surface of the node contact electrode 199 to the upper surface of the node contact electrode 199.

[0150] The node contact electrode 199 may be formed of at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal nitride.

[0151] The lower insulating pattern 163 may be disposed between the node contact electrode 199 and the power rail 220 (e.g., the lower insulating pattern 163 contacts the lowermost surface of the node contact electrode 199 and the uppermost surface of the power rail 220). The node contact electrode 199 may be separated from the power rail 220 by the lower insulating pattern 163.

[0152] Figure 8 A semiconductor device according to an embodiment is shown. Figure 8 The semiconductor device shown has many similarities to the previous embodiments, so the following description focuses primarily on the differences from the previous embodiments. Figure 8 Show along Figure 1 The cross section taken from line I3-I3'.

[0153] Figure 8 A semiconductor device is shown according to an embodiment that differs in certain aspects from the previous embodiment, because the semiconductor device includes an insulating liner 168 surrounding a partition wall 161.

[0154] Reference Figure 8The semiconductor device according to the embodiment may further include a first insulating liner 168a surrounding the side surface and lower surface of the lower region 161a of the partition wall 161 and a second insulating liner 168b surrounding the side surface and lower surface of the upper region 161b of the partition wall 161.

[0155] A first insulating liner 168a may be conformally disposed on the side surface and the lower surface of the lower region 161a of the partition wall 161. In one embodiment, the first insulating liner 168a may be formed of an insulating material different from the insulating material of the lower region 161a of the partition wall 161. The first insulating liner 168a may be made of silicon oxide (SiO2), silicon nitride (SiN2), etc. x It may be formed from at least one of silicon oxynitride (SiON), but this disclosure is not limited thereto.

[0156] The second insulating liner 168b may be conformally disposed on the side and lower surfaces of the upper region 161b of the partition wall 161. In one embodiment, the second insulating liner 168b may be formed of an insulating material different from the insulating material of the upper region 161b of the partition wall 161. The second insulating liner 168b may be made of silicon oxide (SiO2), silicon nitride (SiN2), etc. x It may be formed from at least one of silicon oxynitride (SiON), but this disclosure is not limited thereto.

[0157] and Figure 8 As shown, the lower region 161a or upper region 161b of the partition wall 161 may not include an insulating liner (e.g., a first insulating liner 168a and a second insulating liner 168b). For example, the lower region 161a may be surrounded by the first insulating liner 168a, while the upper region 161b may not be surrounded by the second insulating liner 168b, allowing the upper region 161b to contact the surrounding structure (e.g., the upper contact electrode 191, etc.). Alternatively, the lower region 161a may not be surrounded by the first insulating liner 168a, while the upper region 161b may be surrounded by the second insulating liner 168b, allowing the lower region 161a to contact the surrounding structure (e.g., the source / drain pattern 150, the lower contact electrode structure 197, etc.).

[0158] Figure 9 A view is shown for describing a semiconductor device according to an embodiment. Figure 9 The semiconductor device shown here has many similarities to the foregoing embodiments, so the following description focuses primarily on the differences from the previous embodiments. Figure 9 Show along Figure 1 The cross section taken from line I3-I3'.

[0159] Reference Figure 9The semiconductor device according to an embodiment may include a contact isolation pattern 169 disposed on a partition wall 161. The contact isolation pattern 169 can be used to electrically insulate an upper contact electrode 191 from another upper contact electrode 191. The contact isolation pattern 169 according to an embodiment may be disposed between two source-drain patterns 150 disposed on opposite sides of the partition wall 161. Figure 9 As shown, the contact isolation pattern 169 may be disposed above and superimposed on the partition wall 161, such that (e.g., with) Figure 4 (Compared to the position of the upper region 161b of the partition wall 161) the contact isolation pattern 169 can be set at the same position as the upper region 161b of the partition wall 161.

[0160] The upper surface of the contact isolation pattern 169 may contact the lower surface of the cover layer 142. The lower surface of the contact isolation pattern 169 may contact the upper surface of the partition wall 161. The contact isolation pattern 169 may contact a portion of the side surface of the source / drain pattern 150 and a portion of the side surface of the upper contact electrode 191. In one embodiment, the etch stop layer 185 may not be disposed at the interface between the contact isolation pattern 169 and the source / drain pattern 150.

[0161] and Figure 9 As shown, the insulating liner may also be provided on the side and bottom surfaces of the contact isolation pattern 169. For example, with Figure 8 The second insulating liner 168b is positioned similarly to the first insulating liner 168b, and the second insulating liner 168b can be set in a similar position. Figure 9 The contact isolation pattern 169 is on the side and bottom surfaces.

[0162] Figure 10 A view is shown for describing a semiconductor device according to one embodiment. Figure 10 The semiconductor device shown here has many similarities to the previous embodiments, so the following description focuses primarily on the differences from the previous embodiments. Figure 10 Show along Figure 1 The cross section taken from line I3-I3'.

[0163] The semiconductor device according to the embodiment may further include an insulating liner disposed on at least a portion of the side and upper surfaces of the lower contact electrodes 197a and 197b and the connecting lines 192a and 192b.

[0164] Specifically, refer to Figure 10An insulating liner 188a may be disposed on the side surfaces of the first lower contact electrode 197a and the second lower contact electrode 197b, such that the insulating liner 188a (e.g., on the inward first side of the insulating liner 188a) contacts the lower contact electrodes 197a and 197b, and the insulating liner 188a (e.g., on the outward second side of the insulating liner 188a) contacts adjacent structures (such as the lower region 161a, the device isolation layer 112, etc.). An insulating liner 188b may be disposed on the side and top surfaces of the second connection line 192b, such that the insulating liner 188b (e.g., on the inward first side of the insulating liner 188b) contacts the second connection line 192b, and the insulating liner 188b (e.g., on the outward second side of the insulating liner 188b) contacts the device isolation layer 112. An insulating liner 188c may be disposed on a side surface of the first connecting line 192a such that the insulating liner 188c (e.g., on the inward first side of the insulating liner 188c) contacts the first connecting line 192a and the insulating liner 188c (e.g., on the outward second side of the insulating liner 188c) contacts the lower insulating pattern 163.

[0165] Figure 11 A view is shown for describing a semiconductor device according to an embodiment. Figure 11 The semiconductor device shown here has many similarities to the previous embodiments, so the following description focuses primarily on the differences from the previous embodiments. Figure 11 Show along Figure 1 The cross-section taken by line I6-I6'. The semiconductor device according to the embodiment may have a shape similar to... Figure 7 The node contact electrode 199 has a slightly different shape.

[0166] Specifically, refer to Figure 11 In the embodiments, compared with the reference Figure 7 The width of the node contact electrode 199 along the first direction D1 can be wider than the width of the node contact electrode 199 along the first direction D1. In one embodiment, the node contact electrode 199 may have a constant width measured along the first direction D1 from the lowermost surface of the node contact electrode 199 to the uppermost surface of the node contact electrode 199 in the third direction D3.

[0167] Figures 12 to 62 A process cross-sectional view is shown to describe a method for manufacturing a semiconductor device according to an embodiment.

[0168] Figure 17 , Figure 42 , Figure 46 and Figure 56 Showing and respectively along Figure 1A cross-sectional view corresponding to the regions intercepted by lines I1-I1', I3-I3', I2-I2', and I3-I3' shows a method for manufacturing a semiconductor device according to an embodiment.

[0169] Figure 12 , Figure 31 , Figure 36 , Figure 39 , Figure 44 , Figure 53 and Figure 58 A top plan view is shown for each operation of the manufacturing process of the semiconductor device according to an embodiment. Figure 13 , Figure 17 , Figure 20 , Figure 23 , Figure 27 , Figure 32 , Figure 40 , Figure 45 , Figure 49 , Figure 54 and Figure 59 Showing along Figure 1 The sectional view corresponding to the area intercepted by line I1-I1'.

[0170] Figure 14 , Figure 24 , Figure 28 , Figure 33 , Figure 37 , Figure 41 , Figure 46 , Figure 50 , Figure 55 and Figure 60 Showing along Figure 1 The sectional view corresponding to the area intercepted by line I2-I2'.

[0171] Figure 15 , Figure 18 , Figure 21 , Figure 25 , Figure 29 , Figure 34 , Figure 42 , Figure 47 , Figure 51 , Figure 56 and Figure 61 Showing along Figure 1 The sectional view corresponding to the area intercepted by line I3-I3'.

[0172] Figure 16 , Figure 19 , Figure 22 , Figure 26 , Figure 30 , Figure 35 , Figure 38 , Figure 43 , Figure 48 , Figure 52 , Figure 57 and Figure 62 Showing along Figure 1 The sectional view corresponding to the area intercepted by line I4-I4'.

[0173] like Figures 12 to 16 As shown, a substrate 101, a lower pattern 105 on the substrate 101, a partition wall 161 disposed on the lower pattern 105, a device isolation layer 112 disposed on opposite sides of the lower pattern 105, a channel structure CH, a gate structure GS surrounding the channel structure CH, source / drain patterns 150 respectively connected to opposite sides of each in the channel structure CH, and upper contact electrodes 193 and 191 respectively connected to the gate structure GS and the source / drain patterns 150.

[0174] First, a lower pattern 105 may be formed on a substrate 101, and sacrificial layers and channel patterns 110a, 110b, 110c, and 110d may be alternately stacked on the lower pattern 105. A device isolation layer 112 may be formed on the opposite side of the lower pattern 105. In one embodiment, the substrate 101 may be silicon-on-insulator (SOI) or bulk silicon. Optionally, the substrate 101 may be a silicon substrate, or may be formed of other materials such as silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but this disclosure is not limited thereto.

[0175] Subsequently, the sacrificial layer and some areas of the channel patterns 110a, 110b, 110c, and 110d can be etched, and then an insulating material can be applied to form a separator 161. In one embodiment, the separator 161 may extend into the interior of the lower pattern 105. Next, after etching some areas of the sacrificial layer and the channel patterns 110a, 110b, 110c, and 110d, source and drain patterns 150 can be formed using epitaxial growth methods. In this case, during the process of etching some areas of the sacrificial layer and the channel patterns 110a, 110b, 110c, and 110d, a portion of the upper region of the separator 161 may be etched together. In this case, the height of the upper surface of the separator 161 disposed between the two source / drain patterns 150 may be lower than the height of the upper surface of the separator 161 disposed between the two channel structures CH.

[0176] In one embodiment, a dummy semiconductor pattern 143 may also be formed in some regions of the lower pattern 105 below the source / drain pattern 150. Next, after removing the sacrificial layer, a gate structure GS may be formed in the region where the sacrificial layer is formed. Next, the source / drain pattern 150, the interlayer insulating layer 171, and the capping layer 142 covering the gate structure GS are formed, and a second upper contact electrode 193 and an upper contact via 195 may be formed by photolithography and etching processes.

[0177] like Figures 17 to 19 As shown, the lower portion of the substrate 101 can be etched. To etch the lower portion of the substrate 101, at least one of a polishing process, a chemical mechanical polishing process, and a wet etching process can be performed. In one embodiment, the substrate 101 disposed below the lower pattern 105 can be completely removed. In this case, the lower surface of the device isolation layer 112 can be used as an etch stop layer.

[0178] like Figures 20 to 22 As shown, after removing the underpattern 105, the area where the underpattern 105 is disposed can be filled with an insulating material to form a substrate insulating pattern 103. For example, the underpattern 105 can be etched using a wet etching process. In this case, an etchant with higher etch selectivity can be used to completely etch the underpattern 105 compared to the device isolation layer 112, the spacer 161, and the dummy semiconductor pattern 143. The substrate insulating pattern 103 can be formed by depositing an insulating material in the area where the underpattern 105 is disposed. The insulating material can be silicon oxide (SiO2), silicon nitride (SiN), etc. x The substrate insulating pattern 103 may be formed from at least one of silicon oxynitride (SiON), but this disclosure is not limited thereto. In an embodiment, after forming the substrate insulating pattern 103, a chemical mechanical polishing process may be performed to planarize the lower surface of the substrate insulating pattern 103. In this case, the lower surfaces of the substrate insulating pattern 103 and the device isolation layer 112 may be disposed at substantially the same height.

[0179] like Figures 23 to 26 As shown, a hard mask pattern HM can be formed on a portion of the lower surface of the device isolation layer 112 and the substrate insulation pattern 103.

[0180] First, insulating material can be deposited over the entire area of ​​the lower surface of the device isolation layer 112 and the substrate insulating pattern 103. Then, a portion of the insulating material can be etched to form a hard mask pattern HM. For this purpose, a photolithography process can be performed. In this case, some areas of the lower surface of the substrate insulating pattern 103 can be exposed through the hard mask pattern HM. (Refer to...) Figure 25The portion of the substrate insulating pattern 103 exposed by the hard mask pattern HM may include a region on the third direction D3 that overlaps with the separator 161 and the source / drain pattern 150 disposed on the opposite side of the separator 161.

[0181] like Figures 27 to 30 As shown, the portion of the etchable substrate insulating pattern 103 exposed by the hard mask pattern HM. Compared to the separator 161, the dummy semiconductor pattern 143, and the device isolation layer 112, an etchant or etching gas with higher etch selectivity relative to the substrate insulating pattern 103 can be used to perform the etching process of a portion of the substrate insulating pattern 103. As a portion of the substrate insulating pattern 103 is etched, a portion of the lower part of the separator 161 and portions of the lower parts of the two dummy semiconductor patterns 143 disposed on opposite sides of the separator 161 can be exposed to the outside.

[0182] like Figures 31 to 34 As shown, conductive material can be deposited on the etched portion of the substrate insulating pattern 103 to form the lower contact electrode structure 197.

[0183] First, the dummy semiconductor pattern 143 exposed to the outside can be etched. Next, conductive material can be deposited on the etched portions of the substrate insulating pattern 103 and the dummy semiconductor pattern 143 to form a lower contact electrode structure 197. In this case, the portion of the lower region of the partition wall 161 exposed to the outside by the etching process can be covered by the lower contact electrode structure 197.

[0184] like Figures 36 to 38 As shown, a gate contact electrode 198 and a node contact electrode 199 connected to the gate structure GS at a first end can be formed. First, a portion of the device isolation layer 112 overlapping the gate structure GS in the third direction D3 and a portion of the substrate insulating pattern 103 can be etched using a photolithography process. Subsequently, the etched areas can be filled with a conductive material to form each of the gate contact electrode 198 and the node contact electrode 199.

[0185] Next, as Figures 39 to 43 As shown, some areas of the lower contact electrode structure 197 (e.g., the first lower contact electrode 197a and the second lower contact electrode 197b), as well as the gate contact electrode 198 and the node contact electrode 199, can be etched again, and then insulating material can be filled into the etched portions to form a lower insulating pattern 163.

[0186] In one embodiment, a portion of the lower region of the partition wall 161 can be re-exposed to the outside through a re-etching process of the lower contact electrode structure 197. The lower contact electrode structure 197 can be separated into two lower contact electrodes 197a and 197b by the partition wall 161. In one embodiment, when forming a contact between two source / drain patterns 150 adjacent to each other along the second direction D2, a self-aligned contact can be formed by using the partition wall 161 disposed between the two source / drain patterns. For example, refer to Figure 34 and Figure 42 The lower contact electrode structure 197 may initially surround (e.g., Figure 34 As shown in the diagram, the lower portion of the partition wall 161 is such that the lowermost surface of the partition wall 161 is surrounded by and in contact with the lower contact electrode structure 197. The etch-back process can result in the removal of the lower portion of the lower contact electrode structure 197 without removing or only minimally removing the partition wall 161. After the etch-back process, and as shown in the diagram... Figure 42 As shown, the lowest region of the lower contact electrode structure 197 has been removed, thus exposing the lower portion of the partition wall 161. Thus, the lower contact electrode structure 197 is separated into a first lower contact electrode 197a and a second lower contact electrode 197b, with the partition wall 161 extending between and through the first and second lower contact electrodes 197a and 197b. Therefore, process margin can be increased in the patterning process used to form the lower contact electrodes 197a and 197b, and the reliability of the semiconductor device according to the embodiment can be improved. A lower insulating pattern 163 may be provided below the lower surface of the lower contact electrode structure 197. In one embodiment, the lower insulating pattern 163 may surround the portion of the lower region of the partition wall 161 located below the lower surface of the lower contact electrode structure 197.

[0187] In one embodiment, an insulating pattern 163 may also be provided below the gate contact electrode 198 and the node contact electrode 199.

[0188] like Figures 44 to 48 As shown, a reference can be formed. Figures 1 to 7 The connecting lines 192a and 192b are described.

[0189] The first connection line 192a can be formed by etching the portion of the lower insulating pattern 163 that overlaps with the separator wall 161 on the third direction D3 and then filling that portion with a conductive material. In this case, the lower contact electrodes 197a and 197b, which were separated from each other by the separator wall 161 in the previous process, can be connected to each other by the first connection line 192a. Therefore, the two source / drain patterns connected to the respective lower contact electrodes 197a and 197b can be connected to each other.

[0190] A second interconnect 192b can be formed within the device isolation layer 112. The second interconnect 192b can be formed to extend along a first direction D1. First, the portion of the device isolation layer 112 overlapping the interconnect pattern 194 and the gate contact electrode 198 in a third direction D3 can be etched to expose the lower surface of the interconnect pattern 194 and the lower surface of the gate contact electrode 198. Thereafter, conductive material can be deposited in the etched area of ​​the device isolation layer 112 to form the second interconnect 192b. The second interconnect 192b can connect the interconnect pattern 194 and the gate contact electrode 198 to each other.

[0191] like Figures 49 to 52 As shown, lower insulating patterns 164 and 165 can be formed to electrically isolate the connecting lines 192a and 192b from the power rail 220 to be formed thereafter. First, the connecting lines 192a and 192b can be etched to a predetermined depth using an etch-back process. In this case, the depth to which the connecting lines 192a and 192b are etched forms an etched area between the upper and lower surfaces of the lower insulating pattern 163. Subsequently, insulating material can be deposited in the etched area to form a lower insulating pattern 165 located below the first connecting line 192a and a lower insulating pattern 164 located below the second connecting line 192b.

[0192] like Figures 53 to 57 As shown, a lower contact via 210 can be formed to connect the lower contact electrode structure 197 and the power rail 220 to be formed thereafter. The portion of the entire area of ​​the lower insulating pattern 163 overlapping the first lower contact electrode 197a or the second lower contact electrode 197b in the third direction D3 can be etched using photolithography and etching processes. A conductive material can then be deposited on the etched area to form the lower contact via 210. In one embodiment, the upper surface of the lower contact via 210 can contact one of the lower contact electrodes 197a and 197b.

[0193] like Figures 58 to 62As shown, power rails 220 for supplying power to the semiconductor device according to an embodiment can be formed beneath the substrate insulating pattern 103 and the device isolation layer 112. First, a lower insulating layer 167 covering the entire area of ​​the substrate insulating pattern 103 and the device isolation layer 112 can be formed. Subsequently, a portion of the lower insulating layer 167 can be patterned using photolithography and etching processes, and then conductive material can be deposited to form the power rails 220. In one embodiment, interconnects 192a and 192b for transmitting electrical signals between internal components of the semiconductor device can be arranged within the device isolation layer 112 or the substrate insulating pattern 103, thus ensuring process margin during the formation of the power rails 220, thereby improving the reliability of the semiconductor device. In one embodiment, a chemical mechanical polishing process can be performed to planarize the lower surfaces (e.g., the lower insulating layer 167 and / or the lower surface of the power rails 220).

[0194] While this disclosure has been described in conjunction with embodiments now considered to be actual embodiments, it will be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Substrate insulation pattern; The partition wall is set on the substrate insulation pattern; The first channel structure and the second channel structure are set separately from each other, with a partition wall between the first channel structure and the second channel structure. Gate structure surrounding the first channel structure and the second channel structure; The first source / drain pattern is connected to the opposite side of the first channel structure; The second source / drain pattern is connected to the opposite side of the second channel structure and spaced apart from the first source / drain pattern, with a partition wall between the first source / drain pattern and the second source / drain pattern; as well as The lower contact electrode structure is connected to the lower part of the first source / drain pattern and the lower part of the second source / drain pattern. The separator extends in a direction toward the lower surface of the substrate insulating pattern and extends through the lower contact electrode structure.

2. The semiconductor device according to claim 1, further comprising: The power rail is positioned below the base insulation pattern. The lower surface of the partition wall is positioned at a height between the upper surface of the power rail and the lower surface of the lower contact electrode structure.

3. The semiconductor device according to claim 2, wherein, The lower contact electrode structure includes: a first lower contact electrode connected to one of the first source / drain patterns; and a second lower contact electrode connected to one of the second source / drain patterns. The first and second lower contact electrodes are separated from each other by a partition wall.

4. The semiconductor device according to claim 3, further comprising: The lower contact via connects the lower surface of the first lower contact electrode to the upper surface of the power rail. The width of the lower contact via in the horizontal direction is smaller than the width of the lower surface of the first lower contact electrode in the horizontal direction.

5. The semiconductor device according to claim 4, further comprising: The first insulating pattern is positioned at a height between the height of the lower contact electrode structure and the height of the power rail. The lower contact via extends through the first lower insulation pattern to connect the first lower contact electrode and the power rail.

6. The semiconductor device according to claim 5, wherein, The partition wall is located at a height between the lower surface of the lower contact electrode structure and the upper surface of the power rail, and has an area surrounded by a first lower insulating pattern.

7. The semiconductor device according to claim 3, further comprising: A device isolation layer is disposed on the first side of the first source / drain pattern or the second source / drain pattern; as well as One or more connecting lines are located within the device's isolation layer and are separated from the power rail.

8. The semiconductor device according to claim 7, wherein, The one or more connecting lines include: a first connecting line that connects the first lower contact electrode and the second lower contact electrode to each other.

9. The semiconductor device according to claim 8, wherein, The partition wall is located at a height between the lower surface of the lower contact electrode structure and the upper surface of the power rail, and has a region surrounded by the first connecting line.

10. The semiconductor device according to claim 7, wherein, The one or more connection lines include: a second connection line that connects at least one of the first source / drain pattern and the second source / drain pattern to the gate structure.

11. The semiconductor device of claim 10, further comprising: A connecting pattern is set at the same height as the lower contact electrode structure, and the connecting pattern connects the lower contact electrode structure to another adjacent lower contact electrode structure.

12. The semiconductor device of claim 11, further comprising: The gate contact electrode includes a first end connected to the lower part of the gate structure and a second end extending into the interior of the device isolation layer.

13. The semiconductor device according to claim 12, wherein, The second connection line has a first end connected to the connection pattern and a second end connected to the gate contact electrode.

14. The semiconductor device of claim 7, further comprising: The second insulating pattern is disposed between one or more connecting lines and the power rail.

15. The semiconductor device according to any one of claims 1 to 14, wherein, The partition wall includes: a first side surface that contacts a first source / drain pattern; and a second side surface that contacts a second source / drain pattern.

16. A semiconductor device, comprising: Substrate insulation pattern; The partition wall is set on the substrate insulation pattern; The first channel structure and the second channel structure are set separately from each other, with a partition wall between the first channel structure and the second channel structure. Gate structure surrounding the first channel structure and the second channel structure; The first source / drain pattern is connected to the opposite side of the first channel structure; The second source / drain pattern is connected to the opposite side of the second channel structure and spaced apart from the first source / drain pattern, with a partition wall between the first source / drain pattern and the second source / drain pattern; The lower contact electrode structure is connected to the lower part of the first source / drain pattern and the lower part of the second source / drain pattern; The power rail is positioned below the base insulation pattern; A device isolation layer is disposed on the first side of the first source / drain pattern or the second source / drain pattern; as well as One or more connecting lines are located within the device's isolation layer and are separated from the power rail.

17. The semiconductor device according to claim 16, wherein, The lower contact electrode structure includes: a first lower contact electrode connected to one of the first source / drain patterns; and a second lower contact electrode connected to one of the second source / drain patterns. The one or more connecting lines include: a first connecting line that connects the first lower contact electrode and the second lower contact electrode to each other.

18. The semiconductor device according to claim 17, wherein, The separator extends in a direction toward the lower surface of the substrate insulation pattern and extends through the lower contact electrode structure, and The first and second lower contact electrodes are separated from each other by a partition wall.

19. The semiconductor device according to claim 16, wherein, The one or more connection lines include: a second connection line that connects at least one of the first source / drain pattern and the second source / drain pattern to the gate structure.

20. A semiconductor device, comprising: Substrate insulation pattern; The partition wall extends in a first direction parallel to a first surface of the substrate insulating pattern and includes a first end extending into the interior of the substrate insulating pattern; The first channel structure and the second channel structure are disposed on the substrate insulation pattern and spaced apart from each other in a second direction intersecting the first direction. The partition wall is between the first channel structure and the second channel structure. Each of the first channel structure and the second channel structure includes a first side surface that contacts the partition wall. Gate structure surrounding the first channel structure and the second channel structure; The first source / drain pattern is connected to the opposite side of the first channel structure; The second source / drain pattern is connected to the opposite side of the second channel structure and spaced apart from the first source / drain pattern, with a partition wall between the first source / drain pattern and the second source / drain pattern; The lower contact electrode structure is connected to the lower part of the first source / drain pattern and the lower part of the second source / drain pattern; The power rail is positioned below the base insulation pattern; The first insulating pattern is set between the lower contact electrode structure and the power rail; The lower contact via extends upward through the first lower insulating pattern in a third direction perpendicular to the first and second directions, and has an upper surface that contacts the lower contact electrode structure and a lower surface that contacts the upper surface of the power rail. A device isolation layer is disposed on the first side of the first source / drain pattern or the second source / drain pattern, and covers the side surface of the substrate insulating pattern; as well as One or more connecting lines are housed within the device's isolation layer and are spaced apart from the power rails. The partition wall extends through the lower contact electrode structure and has a lower surface positioned at a height between the upper surface of the power rail and the lower surface of the lower contact electrode structure. The lower contact electrode structure includes: a first lower contact electrode connected to one of the first source / drain patterns; and a second lower contact electrode connected to one of the second source / drain patterns. The one or more connection lines include: a first connection line connecting the first lower contact electrode and the second lower contact electrode to each other; and a second connection line connecting at least one of the first source / drain pattern and the second source / drain pattern to the gate structure.

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