Circuit structures and methods having resistors for reducing voltage at a device control node

Abstract

The present disclosure relates to circuit structures and methods having a resistor for reducing voltage at a device control node. Embodiments of the present disclosure provide circuit structures and methods having a resistor for reducing a released pad voltage. Structures of the present disclosure include a resistor having a first end connected to a pad and a second end opposite the first end. A trigger circuit is connected between the pad and ground. A discharge circuit is connected between the second end of the resistor and ground. The discharge circuit is connected to an output node of the trigger circuit.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to electronic circuits. More specifically, various embodiments of this disclosure provide circuit structures and methods that affect the pad voltage of a release. Background Technology

[0002] Circuitry including integrated circuits (ICs) may include discharge elements to protect device hardware from events such as electrostatic discharge (ESD) voltages, which can cause short circuits, dielectric breakdown, and / or other failure modes. In an ideal setup, the ESD element has no effect on device operation until an ESD event occurs on a pin of the IC, where the ESD event acts as a trigger voltage (or, in some cases, activates a trigger circuit to output a trigger voltage). This trigger voltage turns on the ESD device and releases current through the ESD element to the power or ground rail. The ESD element is not used for any operational purpose until a trigger voltage is applied to it to activate it.

[0003] As device dimensions continue to shrink, the operating parameters of discharge elements, such as those in ESD protection circuits, are becoming increasingly sensitive. For example, for all operations below a predetermined maximum operating voltage, the discharge element needs to remain in an "off" state. However, at voltages above the predetermined maximum operating voltage but below the device's breakdown voltage level, the discharge element needs to become active. Conventional configurations of discharge elements can no longer provide a stable maximum operating voltage sufficiently below the breakdown voltage, potentially posing a risk of negatively impacting some devices even when the discharge element operates as intended. Summary of the Invention

[0004] Some aspects of this disclosure provide a structure including: a resistor having a first end connected to a pad and a second end opposite to the first end; a trigger circuit connected between the pad and ground; and a discharge circuit connected between the second end of the resistor and ground, wherein the discharge circuit is connected to the output node of the trigger circuit.

[0005] Another aspect of this disclosure provides a structure comprising: a resistor having a first end coupled to an input / output (I / O) pad and a second end coupled to a device; a trigger circuit coupled between the I / O pad and a ground pad and configured to output a trigger voltage in response to detecting that a pad voltage on the I / O pad is higher than a predetermined operating voltage; and a discharge circuit coupled between the second end of the resistor and the ground pad and configured to receive the trigger voltage from the trigger circuit, wherein the trigger voltage causes the discharge circuit to release an intermediate voltage from the second end of the resistor.

[0006] An additional aspect of this disclosure provides a method comprising: coupling a first end of a resistor to an input / output (I / O) pad and coupling a second end of the resistor to a device; outputting a trigger voltage from the trigger circuit in response to a trigger circuit coupled between the I / O pad and a ground pad detecting that the pad voltage on the I / O pad is higher than a predetermined operating voltage; and transmitting the trigger voltage to a discharge circuit coupled between the second end of the resistor and the ground pad and configured to receive the trigger voltage from the trigger circuit, wherein the trigger voltage causes the discharge circuit to release an intermediate voltage from the second end of the resistor. Attached Figure Description

[0007] These and other features of the present disclosure will be more readily understood through a detailed description of various aspects of the present disclosure in conjunction with the accompanying drawings, which depict various embodiments thereof, in which:

[0008] Figure 1 A schematic diagram of a circuit structure having a resistor for reducing pad voltage is provided according to an embodiment of the present disclosure.

[0009] Figure 2 Enlarged schematic diagrams of circuit structures and devices according to embodiments of the present disclosure are provided.

[0010] Figure 3 A cross-sectional view of a high electron mobility transistor (HEMT) configured to be implemented within a discharge circuit according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A schematic diagram of an example implementation of a circuit structure having a trigger circuit and a discharge circuit according to embodiments of the present disclosure is provided.

[0012] Figure 5 The device voltage (V) during operation with different resistances according to embodiments of this disclosure is shown. B ) relative to pad voltage (V A Example diagram.

[0013] Figure 6 An illustrative flowchart of a method for reducing pad voltage according to embodiments of the present disclosure is provided.

[0014] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict typical aspects of this disclosure and should therefore not be considered as limiting the scope of this disclosure. In the drawings, the same reference numerals denote the same elements between the figures. Detailed Implementation

[0015] In this description, reference is made to the accompanying drawings, which form a part thereof, illustrating specific exemplary embodiments in which the present teachings may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and changes may be made within the scope of the present teachings. Therefore, the description herein is merely illustrative.

[0016] As device dimensions continue to shrink, the operating parameters of discharge elements, such as those in ESD protection circuits, are becoming increasingly sensitive. For example, for all operations below a predetermined maximum operating voltage, the discharge element needs to remain in an "off" state. However, at voltages above the predetermined maximum operating voltage but below the device's breakdown voltage level, the discharge element needs to become active. Conventional configurations of discharge elements can no longer provide a stable maximum operating voltage sufficiently below the breakdown voltage, potentially posing a risk of negatively impacting certain devices even when the discharge element operates as intended.

[0017] Embodiments of this disclosure provide circuit structures and methods having a resistor for reducing voltage at a device control node. The structure includes a resistor having a first end connected to a pad and a second end opposite the first end. A trigger circuit is connected between the pad and ground. A discharge circuit is connected between the second end of the resistor and ground. The discharge circuit is connected to the output node of the trigger circuit.

[0018] refer to Figure 1 This diagram illustrates a circuit structure (hereinafter referred to as "structure") 100 according to an embodiment of the present disclosure. Structure 100 can be embodied as any type of electronic circuit and, in various embodiments, can be provided as an integrated circuit (IC) structure or included as part of an integrated circuit (IC) structure. Structure 100 may include a pad 101. Pad 101 may be, for example, an input / output pad, a power supply pad, etc., which is at risk of being subjected to high-voltage operating conditions such as electrostatic discharge (ESD) events. Pad 101 may be further electrically connected to a device 110 for performing various functions of operating circuitry 111 (e.g., a transceiver front end or other circuitry). According to one example, such as... Figure 2 As shown, device 110 may be a transistor 105 (e.g., a "ground transistor") or any other electrically controllable device configured to operate in response to a signal from pad 101. Transistor 105 may have a first source / drain (S / D) terminal coupled to at least one other component of the operating circuit 110, coupled to the ground pad (GND, e.g., via terminal V). SS The second S / D terminal of the device and the gate coupled to the pad 101. As discussed in more detail below, the structure 100 can be configured to protect the device 110 from damage caused by ESD events such as those at the pad 101.

[0019] The first node A of structure 100 is connected to pad 101. The gate (or alternatively, switching terminal) of device 110 is coupled to a second node B within structure 100. As discussed herein, one S / D terminal (or other input terminal) of device 110 is coupled to another device (not shown) within operating circuit 101, and another S / D terminal (or output terminal) is coupled to terminal V via a third node C. SS The device 110 is coupled to ground (GND). Device 110 may also include a gate terminal coupled to the second node B (or another voltage-controlled node for enabling or disabling current flowing through device 110). Although device 110 is indicated as a single transistor (e.g., a protective transistor or ground transistor as discussed herein), device 110 may be coupled to and / or may include more complex circuitry with several electrically active elements, including several resistors, capacitors, diodes, and / or other devices. Additional components and / or circuitry can be connected via input line V. in They are coupled to structure 100, but the nature and operation of such components are not important to the configuration and operation of structure 100, so they will not be discussed in further detail.

[0020] In the illustrated configuration, the first node A can be set to the level of the input or "high voltage" input terminal of structure 100, and the third node C can be set to the voltage level of the "ground" or "output" terminal of structure 100. The second node B can specify the junction between the gate terminal (or other control terminal) of device 110 and the discharge circuit 114 of structure 100, as discussed in further detail herein. The second node B can be used to control the operation of device 110, but is susceptible to current spikes during ESD events, as discussed herein. Structure 100 is configured to respond to excess charge and current originating from ESD events by establishing a short circuit to bypass device 110, while simultaneously reducing the voltage amplitude applied to device 110. During operation, while establishing an intentional electrical short circuit through structure 100 with trigger circuit 112 and discharge circuit 114, resistor 116 of structure 100 reduces the voltage applied to device 110 ground (V). SS The voltage of the gate (or other control terminal) of the device from an ESD event.

[0021] Structure 100 can be in the form of a clamp, which is configured to establish a connection from input pad 101 through output terminal V. SSA short circuit to ground is established without decoupling device 110 from input pad 101. Structure 100 can also be configured to operate under non-ESD conditions with voltage variations, for example, by including a connection from input pad 101 to device 110 in the operating circuit 111. However, structure 100 includes additional components configured to be inactive during non-ESD scenarios or within predetermined voltage limits, provided that such voltage fluctuations are insufficient to trigger the transistor gate of trigger circuit 112. Therefore, structure 100 is designed to establish a short circuit from input pad 101 to ground only when an ESD event is detected. SS Electrical short circuit.

[0022] A set of ESD elements 120 can couple the first node A to the gate terminal (or other control terminal) of the device 110 at the second node B and the ground terminal V at the third node C. SS ESD element 120 can be selectively activated during an ESD event in response to a voltage or current higher than a predetermined amplitude of device 110 and / or its connected operating circuitry 111, to establish a connection from input pad 101 to ground terminal V. SS The ESD element 120 may be electrically inactive unless at least a predetermined voltage is applied to the trigger circuit 112 of the ESD element 120. In various other examples, additional circuitry and / or current paths may be located between the device 110 and the ESD element 120 to further control the situation in which the ESD element 120 becomes electrically active.

[0023] As this article is about Figure 4 As discussed in further detail, the trigger circuit 112 of structure 100 may include a plurality of interconnected transistors, each configured to detect only a predetermined high voltage amplitude at pad 101, for example, during an ESD event. A transistor is an electrical component in which the flow of current between an input node and an output node (e.g., a source terminal and a drain terminal) is controlled by a voltage applied to a third “gate” terminal. The trigger circuit 112 may include one or more transistors having a gate coupled to terminal A of structure 100, such that a voltage of predetermined amplitude at pad 101 controls whether the trigger circuit 112 is turned on or off. The trigger circuit 112 may be coupled to a discharge circuit 114 at its output. During operation, the trigger circuit 112 remains inactive until a predetermined operating voltage (e.g., an ESD voltage) is applied from pad 101 to the trigger circuit 112 at node A. Upon receiving the predetermined operating voltage, the trigger circuit 112 outputs a trigger voltage (VTRIG) to the discharge circuit 114 to enable protective interaction with device 110. Specifically, the trigger circuit 112 allows current to flow through the discharge circuit 114 to discharge the gate control terminal of device 110 to the ground terminal V.SS .

[0024] Structure 100 includes a resistor 116 having a first end (at a first node A) coupled to pad 101 to receive a pad voltage (VPAD) and a second end (at a second node B) coupled to a discharge circuit 114 and the gate terminal of device 110. Resistor 116 is present in structure 100 to reduce the VPAD received at the first end to an intermediate voltage (VINT) of a lower amplitude output at the second end (e.g., output to device 110, as a gate voltage, for example, if device 110 is a transistor having a gate connected to pad 101). The voltage reduction across resistor 116 from the first node A to the second node B occurs by applying Ohm's law, generally understood in the relevant art. When activated by trigger circuit 112, discharge circuit 114 selectively couples the second node B (i.e., the second end of resistor 116) to ground (VINT) at a third node C. SS When discharge circuit 114 is inactive (i.e., no trigger voltage is applied from trigger circuit 112 to discharge circuit 114), no current will travel from the second node B through discharge circuit 114 to the third node C. When trigger circuit 112 applies its trigger voltage to discharge circuit 114 (e.g., during an ESD event or other high-voltage operating scenarios at a predetermined operating voltage), discharge circuit 114 becomes active, establishing a current from the second node B to the third node C to ground (V). SS The electrical short circuit of the device 110 causes the current path from pad 101 to the gate terminal of the device 110 during an ESD event or other high-voltage operating scenario. This path then proceeds through the first node A, resistor 116, to the second node B, then to the discharge circuit 114 (due to the trigger voltage applied from the trigger circuit 112 to the discharge circuit 114), to the third node C, and finally to terminal V. SS The ground (GND) is located at the device 110. Resistor 116 is thus used to reduce the voltage applied to the gate terminal of the device 110 to an intermediate voltage level (VINT) that is less than the high voltage (VPAD) at the pad 101.

[0025] Figure 3 An example of a high electron mobility transistor (HEMT) that can be implemented within the discharge element 114 of circuit 100 is provided. Traditionally, resistive elements in ESD protection circuits pose a risk that the ESD detection component will not be triggered when a sufficiently high voltage occurs. Resistor 116 can be incorporated into structure 100 without such risk, partly through a HEMT device architecture within discharge element 114. It should be emphasized that... Figure 3The HEMT 200 shown is an example of a specific device configuration; for the embodiment of the HEMT 200 shown herein, different devices with different polarities, doping distributions, electrical couplings, etc., can be replaced in the discharge element 114.

[0026] HEMT 200 can be provided using a stack of substantially the same group III-V semiconductor layers above a substrate. More specifically, in the disclosed embodiments, the semiconductor structure may include a stack of group III-V semiconductor layers. Therefore, HEMT 200 may include any conceivable HEMT III-V semiconductor device constructed on such a structure, such as another HEMT enhancement mode HEMT with or without raised group III-V semiconductor source / drain regions, enhancement mode MISHEMT with or without raised group III-V semiconductor source / drain regions, etc. As discussed herein, HEMT 200 can differ from other transistor architectures by including (among other components) a barrier layer located above and adjacent to the group III-V semiconductor surface at the top of the stack in a first region. Various isolation materials (e.g., one or more isolation wells) may be located within the stack and adjacent to the group III-V semiconductor surface, for example, to electrically isolate HEMT 200 from other transistors with different architectures.

[0027] Figure 3A cross-sectional view illustrating an example embodiment of HEMT 200 is provided. HEMT 200 may include a substrate 201. Substrate 201 may be, for example, a silicon substrate or a silicon-based substrate (e.g., silicon carbide or silicon-germanium substrate), a sapphire substrate, a III-V semiconductor substrate (e.g., a gallium nitride substrate or other suitable III-V semiconductor substrate), or any other substrate suitable for III-V semiconductor processing. HEMT 200 may include a stack of III-V semiconductor layers located on substrate 201. Those skilled in the art will recognize that III-V semiconductors refer to compounds obtained by combining one or more group III elements (e.g., boron (B), aluminum (Al), gallium (Ga), or indium (in)) with one or more group V elements (e.g., nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)). Therefore, examples of III-V semiconductors include, but are not limited to, gallium nitride, indium phosphide, gallium arsenide, aluminum gallium nitride, indium gallium nitride, etc. The III-V semiconductor layers in the stack can be epitaxially grown on substrate 201 and can include at least a buffer layer 202 and a channel layer 203 located on the buffer layer 202. For example, the buffer layer 202 can be located above and adjacent to the top surface of substrate 201. The buffer layer 202 can serve as an anchor to enable nucleation and replicate orientation in the subsequently grown epitaxial layer. The buffer layer 202 can be, for example, a gallium nitride layer and / or one or more layers of any other III-V semiconductor suitable for use as a buffer layer in HEMT or metal-insulator-semiconductor HEMT (MISHEMT). Optionally, the buffer layer 202 can be carbon-doped or iron-doped. The channel layer 203 can be located above and adjacent to the top surface of the buffer layer 202. The channel layer 203 can be, for example, a gallium nitride layer and / or one or more layers of any other III-V semiconductor suitable for use as a channel layer in HEMT or MISHEMT. In any case, the top surface of the stack, especially the top surface of the channel layer 203, can be a III-V semiconductor surface 203t.

[0028] In addition to the other components discussed in more detail below, HEMT 200 may also include a barrier layer 204 (specifically, another III-V semiconductor layer) located above and adjacent to the III-V semiconductor surface 203t. HEMT 200 may also be located around and / or above various components of HEMT 200. DM layer 250 may include a first DM layer 251, specifically a silicon nitride layer. DM layers may optionally include, but are not limited to, one or more of a second DM layer 252, a third DM layer 253, a fourth DM layer 254, a fifth DM layer 255, and a sixth DM layer 256. Any of DM layers 252-156 may include a single DM layer (e.g., a silicon dioxide layer or some other suitable DM) or two or more DM sublayers (e.g., a conformal silicon nitride layer and some other suitable combination of a silicon dioxide layer or a dielectric material layer situated on the conformal silicon nitride layer).

[0029] HEMT 200 further includes source / drain terminals 232 located on channel layer 203 and gate terminals 235 laterally located on barrier layer 204 between source / drain terminals 232. HEMT 200 may include a barrier layer 204 located above and immediately adjacent to a III-V semiconductor surface 203t at the top of the stack. Barrier layer 204 may be another III-V semiconductor, different from channel layer 203, and having a wider bandgap than channel layer 203. Those skilled in the art will recognize that the channel and barrier III-V semiconductor materials can be selected to form a heterojunction at the interface between the two layers, resulting in the formation of a two-dimensional electron gas (2DEG) in channel layer 203. This 2DEG in channel layer 203 can provide a conduction path for charge drift between source / drain terminals. In the case of E-mode HEMT, the minimum voltage amplitude at gate terminal 235 used to generate 2DEG in channel layer 203 is also referred to as the "threshold voltage". The barrier layer 204 may be a layer of aluminum gallium nitride, aluminum nitride, or any other III-V semiconductor material suitable for use as a barrier layer (e.g., depending on the III-V semiconductor material of the channel layer 203). In any case, the aforementioned layer may be epitaxially grown by metal-organic chemical vapor deposition (MOCVD) or any other suitable technique (e.g., molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), etc.). For illustrative purposes, the above figures and description depict the barrier layer 204 as comprising a single layer of III-V semiconductor material. However, it should be understood that the figures and description are not intended to be limiting, and alternatively, the barrier layer 204 may comprise two or more sublayers of III-V semiconductor material. A first DM layer 251 (which, as described above, may be a silicon nitride layer) may be located above and immediately adjacent to the top surface of the barrier layer 204.

[0030] HEMT 200 can be configured as an enhancement-mode (E-mode) HEMT. Those skilled in the art will recognize that an E-mode HEMT refers to a HEMT that remains in an "off" (i.e., non-conductive) state when no voltage is applied to its gate. In this case, HEMT 200 may require a threshold voltage (e.g., from trigger circuit 112 as discussed herein) to be applied to gate terminal 235. Figure 1 The trigger voltage (VTRIG) is used to operate the device to the on state (i.e., to become conductive). In the case of an E-mode HEMT, the HEMT 200 includes a P-type III-V semiconductor layer 236 stacked in a gate terminal 235 between a barrier layer 204 and a gate conductor material 237. The P-type III-V semiconductor layer 236 may be, for example, a III-V semiconductor (e.g., gallium nitride), which is epitaxially grown on the barrier layer 204 and doped (e.g., with magnesium) to have P-type conductivity. In these embodiments of the HEMT 200, the gate conductor material 237 may include a metal gate conductor material such that the gate terminal 235 is a Schottky contact gate terminal.

[0031] Now for reference Figure 4 Another schematic diagram of structure 100 is shown, featuring example sub-components for implementing trigger circuit 112 and discharge circuit 114. In some embodiments, discharge circuit 114 may simply include HEMT 200, which is coupled from drain to source from second node B to third node C, and at its gate to the source terminal at one end of transistor 302 series coupled within trigger circuit 112. As discussed herein, HEMT 200 may be an E-mode HEMT, such that current flows only from second node B to third node C while a trigger voltage is applied to the gate of HEMT 200. In various alternative configurations, discharge circuit 114 may include multiple interconnected HEMTs 200, for example, an array of interconnected HEMTs configured to serve as a larger transistor according to any now-known or later-developed "macro transistor" configuration, and / or other groups of interconnected transistors configured to approximate the functionality of HEMT 200.

[0032] In contrast to the discharge circuit 114, the trigger circuit 112 may include a number of conventional (e.g., non-HEMT) transistors interconnected as a plurality of diode-connected transistors 302. A diode-connected transistor is a transistor configuration in which the control terminal of the transistor is directly coupled to one of its input-output terminals, thus converting the transistor into a two-terminal diode structure. In the case of a metal-oxide-semiconductor field-effect transistor (MOSFET), the diode-connected transistor may have a drain (or alternatively, source) terminal connected to its gate. According to one example, the trigger circuit 112 may include: a first diode-connected transistor 302, whose connected gate and drain terminals are coupled to a first node A and a pad 101; a last diode-connected transistor, coupled to a terminal of an additional resistor 304; and a plurality of intermediate diode-connected transistors 302 (e.g., two shown) connected in series from drain to source between the first and last diode-connected transistors 302. Multiple diode-connected transistors 302 can be implemented in the trigger circuit 112 instead of a single transistor, for example, to reduce current leakage through the trigger circuit 112 when the discharge circuit 114 is not operating (i.e., when a high-voltage scenario (e.g., an ESD event) at the predetermined operating voltage does not occur).

[0033] The junction between the source of a diode-connected transistor 302 and a terminal of an additional resistor 304 can be connected to the control terminal of the discharge circuit 114 (e.g., the gate terminal of a HEMT 200), such that the operating state of the diode-connected transistor 302 determines whether a trigger voltage is applied to the discharge circuit 114. Therefore, the additional resistor 304 in the trigger circuit 112 prevents the control terminal of the discharge circuit 114 from being at terminal V. SSGrounding is achieved at the point of contact. In an alternative configuration, the control terminal of the discharge circuit can be coupled to another node within the trigger circuit 112, for example, where a different circuit configuration is used to perform a similar function. The diode-connected transistor 302 can have a sufficiently high threshold voltage such that the trigger circuit 112 does not operate until a predetermined high voltage amplitude is applied to the structure 100 at pad 101. The threshold voltage of the diode-connected transistor 302 in the trigger circuit 112 can be at least equal to the desired voltage during an ESD event or a similar event with an undesirably high voltage amplitude. Because a resistor 116 is included between the first node A and the second node B, the voltage used to activate the trigger circuit 112 is greater than the actual voltage applied to the gate of the device 110 and discharged from it through the HEMT 200 in the discharge circuit 114. The combination of trigger circuit 112 (configured to trigger at a pad voltage amplitude higher than the breakdown voltage of device 110) and resistor 116 (configured to reduce the pad voltage to an amplitude lower than the breakdown voltage of device 110) allows structure 100 to release the high voltage amplitude via discharge circuit 114 without overwhelming the control terminals of device 110.

[0034] Let's refer to each other. Figure 1 and Figure 5 The technical advantages of structure 100 over conventional protection circuit structures are discussed in further detail. Figure 5 A comparative voltage diagram and corresponding current diagram are provided for different resistance values ​​of resistor 116 within structure 100. The left Y-axis indicates the total current through structure 100, and the right Y-axis indicates the voltage applied to device 110, i.e., the voltage at the second node B. The X-axis indicates the input voltage applied at pad 101. Therefore, Figure 5 The example diagram illustrates how a change in the pad voltage applied at the first node A will affect the control terminal voltage of device 110 at node B and the subsequent current through discharge circuit 114 when trigger circuit 112 is activated. In a conventional ESD protection device without resistor 116 or similar resistive elements, there is essentially no resistance between nodes A and B; therefore, the conventional circuit (indicated by dashed lines) has a resistance "R" value of zero ohms (Ω).

[0035] In the example embodiment of structure 100 (indicated by solid lines), resistor 116 has a resistance of approximately 4Ω. In the conventional case (V... con Under these conditions, the rising pad voltage at the first node A causes the voltage at the second node B to rise linearly and in the same manner. This linearity is because, since there are no resistive elements between nodes A and B, the voltage applied to device 110 remains the same as the input voltage at pad 101. Therefore, the voltage at the second node B will reach the breakdown voltage (V1) at an amplitude of V1. BDThis amplitude V1 is only slightly higher than the trigger voltage (VTRIG) of the trigger circuit 112. Even when the breakdown voltage is reached, a short circuit is established at ESD component 120 to the terminal V... SS In the case of grounding, the breakdown voltage will also negatively affect device 110. For example, the corresponding current diagram (I) for components without resistors... CON As indicated by the resistor 116, the output from the trigger circuit 112 to the discharge circuit 114 is the same. As the voltage applied from the pad 101 increases (e.g., above 8V), the voltage (VTRIG) output from the trigger circuit 112 also increases. However, without the resistor, the input pad voltage can only rise to 15V (V1) before the device 110 reaches its breakdown voltage; therefore, the discharge current (I) through the discharge device 114 is also limited. CON It reaches its maximum value at only about 0.5A.

[0036] For the trend line indicating the working distribution of the structure 100 with resistor 116, when a predetermined voltage (V) is reached... Trigger After that, at the breakdown voltage V BD The risk of operation is significantly lower below the trigger voltage V. Trigger There is no substantial difference during operation at the specified voltage. When the voltage at the first node A is lower than the predetermined voltage used to activate the trigger circuit 112, the same linear relationship of voltage exists because no voltage drop occurs across resistor 116 (i.e., the second node B is only connected to the gate or control terminal of device 110). However, when the voltage at the first node A reaches V... Trigger The voltage activates the trigger circuit 112, and thus activates the discharge circuit 114, causing a voltage drop across the resistor 116. After the discharge circuit 114 becomes active, the voltage relationship between nodes A and B can become piecewise defined. Initially, as Figure 5 As shown, this will cause a slight voltage tilt between nodes A and B, exceeding a predetermined voltage, due to the parallel circuit path of transistor 302 connected across the diode. With resistor 116 present and having a resistance greater than zero (e.g., 4Ω), the voltage at pad 101 (determined by line V) before device 110 fails... RES The voltage (indicator) can be increased to 23V (V2). Therefore, in this configuration, the discharge current (I) through the discharge circuit 114 is... RES It can achieve much higher levels (e.g., in...) Figure 5 In the example, 2 amperes). Therefore, as shown, structure 100 is operable to apply an intermediate voltage at the second node B, which is less than the higher voltage amplitude at the first node A used to activate the trigger circuit 112.

[0037] Let's refer to it together now. Figure 1 , 5 In accordance with embodiments 6, this disclosure provides a method of operating structure 100 such that during an ESD event or other high-voltage operation, device 110 has an intermediate voltage at a second node B that is less than the voltage at a first node A used to activate trigger circuit 112. Process P1 in this method may include coupling resistor 116 between pad 101 (at first node A) and device 110 (at second node B) in structure 100. When trigger circuit 112 activates discharge circuit 114, it connects pad 101 and ground (at terminal V) through resistor 116. SS When a current path is established between nodes A and B, the resistor 116 at that location can operate to generate a voltage drop from the first node A to the second node B without disconnecting device 110 from pad 101. Therefore, in process P1, the coupling of resistor 116 between nodes A and B can produce structure 100 as discussed herein.

[0038] An ESD event or other high-voltage operation can generate a sufficiently high voltage at the first node A to activate the trigger circuit 112, thereby opening a current path to the third node C through the discharge circuit 114. Process P2 in the method of this disclosure may include, for example, detecting a predetermined operating voltage at the first node A by activating the trigger circuit 112 in response to applying at least a predetermined voltage amplitude from the input pad 101. Therefore, the detection in process P2 can simply include any process of applying a sufficient voltage to activate the trigger circuit 112, for example, to the diode-connected transistor 302 within the trigger circuit 112. Figure 4 Apply at least the threshold voltage.

[0039] Individual activation of trigger circuit 112 will not establish a connection from pad 101 to output pad V via structure 100. SS The electrical path. In the method of this disclosure, process P3 may include causing the trigger circuit 112 to output a trigger voltage VTRIG to the control node of the discharge circuit 114. The discharge circuit 114 includes one or more HEMT 200 ( Figure 3 , 4In the case of a discharge circuit 114, process P3 can simply involve outputting a trigger voltage from the discharge circuit 114 to the gate terminal of the E-mode HEMT 200 with an amplitude equal to or greater than the threshold voltage. Therefore, process P4 can include transferring the trigger voltage VTRIG to the discharge circuit 114 in structure 100. As discussed herein, applying the trigger voltage VTRIG to the discharge circuit 114 (e.g., at its HEMT 200) will allow current to flow from the drain to the source from the second node B (connected to the gate or control terminal of device 110) to the third node C. Due to the presence of a resistor 116 between the first node A and the second node B, the voltage drop across resistor 116 will give device 110 an intermediate voltage at the second node B that is less than the voltage at pad 101 (e.g., less than the high voltage generated during an ESD event), thus avoiding negative impact on device 110. When implemented, these processes can protect device 110 and other circuitry of the device from high-voltage events, while preventing device 110 from operating above its breakdown voltage due to the presence of resistor 116. In embodiments where the discharge circuit 114 includes the HEMT 200 but the trigger circuit 112 does not include any HEMT device, these technical benefits and related advantages may be more apparent.

[0040] The embodiments of this disclosure can provide several technical and commercial advantages, some of which are discussed herein by way of example. Embodiments of structure 100, for example, provide a structure capable of responding to ESD events with a conventional trigger voltage amplitude without applying a voltage close to its breakdown voltage to device 110. Due to the inclusion of resistor 116, device 110 can remain coupled to pad 101 during such events and have an intermediate voltage applied thereto. Furthermore, embodiments of this disclosure avoid the conventional penalties to size and performance associated with forming resistors in ESD protection circuitry by using a HEMT or similar architecture to provide a discharge path. These advantages, in turn, can provide lower leakage current regardless of the operating state of structure 100 and can provide greater protection against high-voltage events by accommodating a wider voltage range before the intermediate voltage approaches the breakdown voltage of device 110.

[0041] The description of various embodiments in this disclosure is presented for illustrative purposes and is not intended to be exhaustive and / or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art within the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, and / or technical improvements relative to technologies found in the market, and / or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: A resistor having a first end connected to a pad and a second end opposite to the first end; A trigger circuit is connected between the pad and ground; as well as A discharge circuit is connected between the second terminal of the resistor and ground, wherein the discharge circuit is connected to the output node of the trigger circuit.

2. The structure according to claim 1, wherein, The trigger circuit is configured to output a trigger voltage in response to detecting a pad voltage higher than a predetermined operating voltage.

3. The structure according to claim 2, wherein, The resistor reduces the pad voltage received from the pad at the first end to an intermediate voltage output from the second end, and wherein the discharge circuit is configured to receive the trigger voltage from the trigger circuit and release the intermediate voltage in response to the trigger voltage.

4. The structure according to claim 3, wherein, The discharge circuit includes an enhancement-mode high electron mobility transistor (HEMT) having a gate coupled to the trigger circuit, a first source / drain S / D terminal coupled to the second end of the resistor, and a second S / D terminal coupled to the ground pad.

5. The structure according to claim 2, wherein, The trigger circuit includes: Multiple diode-connected field-effect transistors are connected in series between the pad and the output node; and An additional resistor is connected between the output node and the ground pad, wherein the trigger voltage is generated and output at the output node.

6. The structure according to claim 1, wherein, The discharge circuit includes a high electron mobility transistor (HEMT), and the trigger circuit does not have a HEMT.

7. The structure according to claim 1, wherein, The predetermined operating voltage is greater than the trigger voltage.

8. A structure comprising: A resistor having a first end coupled to an input / output I / O pad and a second end coupled to a device, wherein the resistor reduces a pad voltage received from the I / O pad at the first end to an intermediate voltage output from the second end; A trigger circuit, coupled between the I / O pad and the ground pad, is configured to output a trigger voltage in response to detecting that the pad voltage on the I / O pad is higher than a predetermined operating voltage; and A discharge circuit, coupled between the second terminal of the resistor and the ground pad, is configured to receive the trigger voltage from the trigger circuit and release the intermediate voltage in response to the trigger voltage.

9. The structure according to claim 8, wherein, Reducing the pad voltage to the intermediate voltage can simultaneously increase the trigger voltage output from the trigger circuit, prevent damage to the device, and increase the drive current of the discharge circuit.

10. The structure according to claim 9, wherein, The discharge circuit includes a high electron mobility transistor (HEMT) having a gate coupled to the trigger circuit, a first source / drain S / D terminal coupled to the second end of the resistor, and a second S / D terminal coupled to the ground pad.

11. The structure according to claim 10, wherein, The HEMT mentioned is an enhanced mode HEMT.

12. The structure according to claim 8, wherein, The trigger circuit includes: Output node; Multiple diode-connected field-effect transistors are connected in series between the I / O pad and the output node; and An additional resistor is connected between the output node and the ground pad, wherein the trigger voltage is generated and output at the output node.

13. The structure according to claim 8, wherein, The discharge circuit includes a high electron mobility transistor (HEMT), and the trigger circuit does not have a HEMT.

14. The structure according to claim 8, wherein, The predetermined operating voltage is greater than the trigger voltage.

15. A method comprising: The resistor reduces the pad voltage received from the input / output I / O pad at the first terminal and outputs an intermediate voltage lower than the pad voltage at the second terminal, wherein the second terminal of the resistor is coupled to the device. In response to a trigger circuit coupled between the I / O pad and the ground pad detecting that the pad voltage on the I / O pad is higher than a predetermined operating voltage, a trigger voltage is output through the trigger circuit. The trigger voltage is received from the trigger circuit through a discharge circuit coupled between the second terminal of the resistor and the grounding pad; and The intermediate voltage is released through the discharge circuit.

16. The method according to claim 15, wherein, Reducing the pad voltage to the intermediate voltage can simultaneously increase the trigger voltage output from the trigger circuit, prevent damage to the device, and increase the drive current of the discharge circuit.

17. The method according to claim 16, wherein, The discharge circuit includes a high electron mobility transistor (HEMT) having a gate coupled to the trigger circuit, a first source / drain S / D terminal coupled to the second end of the resistor, and a second S / D terminal coupled to the ground pad.

18. The method according to claim 17, wherein, The HEMT mentioned is an enhanced mode HEMT.

19. The method according to claim 18, wherein, The trigger circuit does not have a HEMT.

20. The method of claim 15, wherein, The predetermined operating voltage is greater than the trigger voltage.

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