A solar cell and a method of manufacturing the same

Abstract

The application discloses a solar cell and a preparation method thereof, and belongs to the technical field of solar cells. The preparation of the solar cell comprises the following steps: depositing an insulating layer on the surface of a transparent conductive layer of a photovoltaic cell substrate, then performing grid line area and non-grid line area division, protecting the non-grid line area by using a mask, performing laser grooving on the grid line area, and obtaining grooves; performing electrochemical polishing on the grooves, and obtaining electroplating grooves; simultaneously depositing a seed layer and a protective layer on the electroplating grooves and on the side of the insulating layer surface facing the electroplating grooves in sequence; then performing copper electroplating, then performing plasma etching to remove the insulating layer of the non-grid line area; and removing the excessive seed layer and the protective layer. The method can make the copper grid line and the substrate have excellent bonding force on the basis of having low damage to the transparent conductive layer, can effectively reduce the line resistance, and can obtain better grid line quality. The obtained solar cell has better photoelectric conversion performance.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a solar cell and its fabrication method. Background Technology

[0002] The preparation of the insulating layer grooves for photovoltaic copper grid lines is the core step that determines the quality of electroplating. The grooves are required to have high verticality (close to 90°), low surface roughness (Ra<1nm) and low damage compatibility with the TCO layer.

[0003] However, in existing technologies, etching the photovoltaic insulating layer (SiN) x When using Al2O3, surface charge accumulation leads to sidewall tilting (e.g., verticality of only 85°±2°), resulting in high surface roughness Ra (e.g., reaching 10nm~15nm) and easy over-etching, leading to a copper plating fill rate of <92%. Furthermore, traditional electrochemical polishing is only applicable to conductive substrates (metals, silicon) and cannot be directly applied to insulating layers; strong acid electrolytes easily corrode photovoltaic insulating layers, and excessive dissolution or dimensional deviations are prone to occur during micro-nano scale groove trimming, resulting in less than ideal photovoltaic conversion efficiency of the final solar cell.

[0004] In view of this, the present invention is proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a solar cell and its preparation method to solve or improve the above-mentioned technical problems.

[0006] This invention can be implemented as follows: In a first aspect, the present invention provides a method for preparing a solar cell, comprising the following steps: An insulating layer is deposited on the surface of the transparent conductive layer of a photovoltaic cell substrate to obtain a first intermediate cell panel; The first intermediate solar panel is divided into grid line area and non-grid line area. The non-grid line area is protected by a mask, and the grid line area is laser-grooved to obtain grooves. The groove is electrochemically polished to obtain an electroplated groove. A seed layer and a protective layer are deposited sequentially in the electroplating groove and on the side of the insulating layer facing the electroplating groove to obtain a second intermediate solar panel; The second intermediate solar panel is electroplated with copper to obtain a third intermediate solar panel with copper grid lines. Plasma etching is performed on the third intermediate solar panel to remove the insulating layer in the non-gateline area; Remove excess seed and protective layers.

[0007] In an optional embodiment, the insulating layer is prepared by plasma-enhanced chemical vapor deposition.

[0008] In an optional embodiment, the thickness of the insulating layer is 200nm~300nm.

[0009] In an alternative embodiment, after depositing the insulating layer, hydroxyl groups are introduced onto the surface of the insulating layer to obtain a first intermediate battery plate with a hydroxyl layer.

[0010] In an optional embodiment, hydroxyl groups are introduced by plasma treatment, wherein the plasma treatment conditions include: a power of 80W to 120W; and the plasma being argon and oxygen in a volume ratio of 1:1.5 to 1:2.5.

[0011] In an optional implementation, the conditions for laser grooving include: using an ultraviolet nanosecond laser or an ultraviolet picosecond laser; a laser frequency of 1500kHz to 2500kHz; a single pulse energy of 0.3μJ to 0.8μJ; a power of 10% to 40% of the rated power; and a spot diameter of 30μm to 70μm.

[0012] In an alternative embodiment, the groove penetrates the insulating layer to expose the surface of the photovoltaic cell substrate.

[0013] In an optional implementation, the groove is a trapezoidal groove.

[0014] In an optional embodiment, the groove is a trapezoidal groove that is narrower at the top and wider at the bottom.

[0015] In an optional embodiment, the top width of the trapezoidal groove is 10μm~20μm, and the bottom width is 20μm~30μm.

[0016] In an optional embodiment, the conditions for electrochemical polishing of the groove include: a pulse current frequency of 150Hz~250Hz, a duty cycle of 30%~50%, and a current density of 0.8A / dm³. 2 ~1.5A / dm 2 Polishing time is 30s~60s.

[0017] In an optional embodiment, the electrolyte used for electrochemical polishing includes a main component, a solubilizer, and an insulating layer protectant; wherein the main component includes phosphoric acid and ethylene glycol in a volume ratio of 2:8 to 4:6, the mass of the solubilizer is 0.3% to 0.5% of the mass of the main component, and the mass of the insulating layer protectant is 0.5% to 1% of the mass of the main component.

[0018] In an optional implementation, the pH of the electrolyte is 4 to 6.

[0019] In an optional embodiment, after electrochemical polishing, the verticality of the sidewalls of the electroplating groove is 89.5°~90.5°, and the surface roughness is ≤0.5nm.

[0020] In an optional embodiment, the sidewalls of the electroplating groove are formed with a micro-arc transition of 0.1μm to 0.2μm.

[0021] In an optional embodiment, the total thickness of the seed layer and the protective layer is 1 / 3 to 1 / 2 of the depth of the electroplating groove; And / or, the width of the seed layer deposited on the side of the insulating layer facing the electroplating groove is d1, the top width of the electroplating groove is d1, the bottom width of the electroplating groove is d3, and d1+d2=d3.

[0022] In an optional implementation, the thickness of the seed layer is 50 nm to 100 nm.

[0023] In an optional implementation, the thickness of the protective layer is 5nm to 10nm.

[0024] In an optional implementation, the sheet resistance of the seed layer is <10Ω / □.

[0025] In an optional implementation, the hardness of the protective layer is not less than 25 GPa.

[0026] In an optional embodiment, copper electroplating includes at least one of the following features: Feature 1: The electroplating solution includes 180g / L~220g / L of copper sulfate and 40g / L~60g / L of sulfuric acid; preferably, the electroplating solution also includes a leveling agent; Feature 2: Current density is 1 A / dm 2 ~3A / dm 2 ; Feature 3: The deposition temperature is 25℃~30℃ and the deposition time is 10min~15min.

[0027] In an optional embodiment, during the copper electroplating process, copper is first filled into the gradient grooves, and then grown upwards along the seed layer until the copper layer is 0.5 μm to 1 μm higher than the insulating layer.

[0028] In an optional embodiment, after copper electroplating, a low-temperature annealing process is also included.

[0029] In an optional embodiment, the conditions for low-temperature annealing include: holding at a temperature of 200°C to 300°C for 25 to 35 minutes under a protective atmosphere.

[0030] In an optional implementation, the plasma etching of the third intermediate solar panel includes initial etching and fine etching; The initial etching conditions include: a power of 200W~250W, and a plasma consisting of carbon tetrafluoride and oxygen in a volume ratio of 3.5:1 to 4.5:1; the fine etching conditions include: a power of 100W~150W, and a plasma consisting of trifluoromethane and oxygen in a volume ratio of 3:1.5 to 3:2.5.

[0031] In an optional implementation, the initial etching depth is 94% to 96% of the preset etching depth. After the initial etching, an initial groove is formed in the non-gateline area. And / or, after fine etching, the sidewall verticality of the initial groove in the non-gate area is 87°~89°, and the surface roughness is 8nm~10nm.

[0032] In an optional implementation, the excess seed layer is removed by etching, and the etching conditions include at least one of the following characteristics: Feature 4: The etching solution consists of hydrochloric acid and hydrogen peroxide in a volume ratio of 2.5:1 to 3.5:1; Feature 5: Etching is performed at room temperature for 1 to 2 minutes; And / or, the excess protective layer is removed by etching, wherein the etching conditions include at least one of the following characteristics: Feature 6: The etching solution comprises hydrofluoric acid and citric acid in a volume ratio of 1:4.5 to 1:5.5; Feature 7: Etching is performed at room temperature for 1 to 2 minutes.

[0033] In an alternative implementation, ultrasonic oscillation is used as an auxiliary process during etching.

[0034] In an optional implementation, after removing the excess seed layer and protective layer, the copper grid lines are further subjected to electrochemical polishing.

[0035] In an optional embodiment, electrochemical polishing of the copper grid lines includes at least one of the following features: Feature 8: The electrolyte system used for electrochemical polishing consists of phosphoric acid, sulfuric acid, and water in a volume ratio of 6.5:2.5:1 to 7.5:1.5:1; Feature 9: The current density for electrochemical polishing is 0.4 A / dm². 2 ~0.6A / dm 2 ; Feature 10: The electrochemical polishing time is 1 min to 2 min.

[0036] Secondly, the present invention provides a solar cell prepared by the above-described preparation method.

[0037] The beneficial effects of this invention include: The method provided by this invention involves forming grooves in the gate line region, followed by electrochemical polishing of the grooves to obtain electroplated grooves. A seed layer and a protective layer are then sequentially deposited within the electroplated grooves and on the side of the insulating layer facing the grooves, resulting in a second intermediate solar panel. The seed layer provides the conductive path required for subsequent fabrication processes, while the protective layer prevents etching gases from corroding the seed layer and disperses charge accumulation during etching. The second intermediate solar panel is then subjected to copper electroplating and plasma etching to remove the insulating layer in the non-gate line regions. Excess seed and protective layers are then removed, allowing the bottom of the copper layer to directly contact and conduct with the silicon substrate. The sidewalls of the copper gate lines are tightly bonded to the insulating layer without gaps, thus optimizing the performance of the copper gate lines.

[0038] The method provided by this invention can produce insulating layer grooves with high verticality, low surface roughness, and good morphological preservation. It can also achieve excellent bonding between copper grid lines and substrate with minimal damage to the transparent conductive layer, effectively reducing line resistance and obtaining better grid line quality. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the product structure corresponding to step S1 in the method for preparing a solar cell provided by the present invention. Figure 2 A schematic diagram of the product structure corresponding to step S2 in the method for preparing a solar cell provided by the present invention; Figure 3 A schematic diagram of the product structure corresponding to step S4 in the method for preparing a solar cell provided by the present invention; Figure 4 A schematic diagram of the product structure corresponding to step S5 in the method for preparing a solar cell provided by the present invention; Figure 5 This is a schematic diagram of the product structure corresponding to step S6 in the method for preparing a solar cell provided by the present invention. Figure 6 This is a schematic diagram of the product structure corresponding to step S7 in the method for preparing a solar cell provided by the present invention.

[0041] Icons: 10-Photovoltaic cell substrate; 20-Insulating layer; 21-Trapezoidal groove; 30-Seed layer; 40-Protective layer; 50-Copper grid line. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0043] The solar cell and its preparation method provided by the present invention will be described in detail below.

[0044] This invention provides a method for preparing a solar cell, comprising the following steps: S1: An insulating layer 20 is deposited on the surface of the transparent conductive layer of the photovoltaic cell substrate 10 to obtain the first intermediate cell panel (e.g., ...). Figure 1 (As shown).

[0045] In some alternative embodiments, the insulating layer 20 may be prepared using plasma-enhanced chemical vapor deposition. The insulating layer 20 may, for example, include SiN. x The insulating layer 20 can be an Al2O3 layer. The thickness of the insulating layer 20 can be 200nm~300nm, such as 200nm, 250nm or 300nm, or other values ​​in the range of 200nm~300nm.

[0046] In some preferred embodiments, after depositing the insulating layer 20, hydroxyl groups can be introduced onto the surface of the insulating layer 20 to obtain a first intermediate battery panel with a hydroxyl layer.

[0047] In some alternative embodiments, hydroxyl groups may be introduced by plasma treatment. The conditions for plasma treatment may include: a power of 80W to 120W (e.g., 80W, 90W, 100W, 110W, or 120W); the plasma may be argon and oxygen in a volume ratio of 1:1.5 to 1:2.5 (e.g., 1:1.5, 1:2, or 1:2.5).

[0048] By introducing hydroxyl groups onto the surface of the insulating layer 20, the adhesion of subsequent auxiliary layers (such as seed layer 30 and protective layer 40) can be improved.

[0049] S2: Divide the first intermediate solar panel into grid line area and non-grid line area. The non-grid line area is protected by a mask. The grid line area is laser-grooved to obtain a groove.

[0050] For example, laser scribing can be used to divide the grid area into grid-lined and non-grid-lined areas.

[0051] In some alternative implementations, the conditions for laser grooving may include: using an ultraviolet nanosecond laser or an ultraviolet picosecond laser; a laser frequency of 1500kHz to 2500kHz (e.g., 1500kHz, 1800kHz, 2000kHz, 2200kHz, or 2500kHz); a single pulse energy of 0.3μJ to 0.8μJ (e.g., 0.3μJ, 0.4μJ, 0.5μJ, 0.6μJ, 0.7μJ, or 0.8μJ); a power of 10% to 40% of the rated power (e.g., 10%, 20%, 30%, or 40%); and a spot diameter of 30μm to 70μm (e.g., 30μm, 40μm, 50μm, 60μm, or 70μm).

[0052] The groove penetrates the insulating layer 20 and protrudes from the surface of the photovoltaic cell substrate 10.

[0053] In some alternative embodiments, the groove is a trapezoidal groove, preferably a trapezoidal groove 21 that is narrower at the top and wider at the bottom (e.g., Figure 2 (As shown).

[0054] In some optional embodiments, the top width of the trapezoidal groove 21 can be 10μm~20μm (e.g., 10μm, 12μm, 15μm, 18μm or 20μm, etc.), and the bottom width can be 20μm~30μm (e.g., 20μm, 22μm, 25μm, 28μm or 30μm, etc.).

[0055] S3: Electrochemical polishing is performed on the groove to obtain an electroplated groove.

[0056] In some alternative embodiments, the conditions for electrochemical polishing of the groove include: using a pre-defined grid region substrate as the anode, a platinum sheet as the cathode, and a pulsed current.

[0057] The pulse current frequency can be 150Hz~250Hz (e.g., 150Hz, 180Hz, 200Hz, 220Hz, or 250Hz), the duty cycle can be 30%~50% (e.g., 30%, 35%, 40%, 45%, or 50%), and the current density can be 0.8A / dm³. 2 ~1.5A / dm 2 (e.g., 0.8A / dm) 2 1A / dm 2 1.2A / dm 2 Or 1.5A / dm 2 Polishing time can be 30s~60s (e.g., 30s, 40s, 50s or 60s).

[0058] The electrolyte used in the aforementioned electrochemical polishing comprises a main component, a solubility modifier, and an insulating layer protectant. The main component consists of phosphoric acid and ethylene glycol in a volume ratio of 2:8 to 4:6 (e.g., 2:8, 2.5:7.5, 3:7, 3.5:6.5, or 4:6, etc.). The solubility modifier comprises 0.3% to 0.5% (e.g., 0.3%, 0.4%, or 0.5%, etc.) of the main component's mass, and the insulating layer protectant comprises 0.5% to 1% (e.g., 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, or 1%, etc.) of the main component's mass. The solubility modifier may include fluoroborate, and the insulating layer protectant may include a silane coupling agent.

[0059] Preferably, the pH value of the electrolyte is 4 to 6, such as 4, 4.5, 5, 5.5 or 6, or other values ​​within the range of 4 to 6.

[0060] The duty cycle is automatically adjusted based on the height of the etched electroplating groove protrusions. When the protrusion height is greater than 20 nm, the duty cycle is increased to 50%; if the protrusion height is less than 10 nm, the duty cycle is reduced to 30%, ensuring that only the sidewall protrusions and bottom burrs are dissolved without changing the overall size of the electroplating groove. The aforementioned "groove protrusion height" can be detected by an online optical profilometer with an accuracy of ±0.01 μm. The overall polishing intensity can be determined by the detection data of the non-grid area, ensuring consistent polishing results.

[0061] Preferably, after electrochemical polishing, the verticality of the sidewall of the electroplating groove is increased to 89.5°~90.5°, the surface roughness is ≤0.5nm, and the sidewall forms a micro-arc transition of 0.1μm~0.2μm.

[0062] S4: Seed layer 30 and protective layer 40 are simultaneously deposited sequentially in the electroplating groove and on the side of the insulating layer 20 facing the electroplating groove to obtain the second intermediate solar panel (e.g., Figure 3 (As shown).

[0063] Both the seed layer 30 and the protective layer 40 can be deposited by magnetron sputtering.

[0064] In some optional embodiments, the total thickness of the seed layer 30 and the protective layer 40 is 1 / 3 to 1 / 2 of the depth of the electroplating groove. The thickness of the seed layer 30 can be 50 nm to 100 nm, such as 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, or other values ​​within the range of 50 nm to 100 nm. The thickness of the protective layer 40 (e.g., a TiN layer) can be 5 nm to 10 nm, such as 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm, or other values ​​within the range of 5 nm to 10 nm.

[0065] In some alternative implementations, the sheet resistance of the seed layer 30 is <10Ω / □.

[0066] In some alternative implementations, the hardness of the protective layer 40 is not less than 25 GPa.

[0067] The seed layer 30 is used to provide the conductive path required for subsequent fabrication processes, and the protective layer 40 is used to prevent etching gas from corroding the seed layer 30, while also dispersing the charge accumulation during etching.

[0068] In some alternative embodiments, the width of the seed layer 30 deposited on the surface of the insulating layer 20 facing the electroplating groove is d1, the top width of the electroplating groove is d2, the bottom width of the electroplating groove is d3, and d1+d2=d3.

[0069] That is, during deposition, selective deposition is performed on the bottom and sidewalls of the electroplating groove, and a small area is deposited laterally along the insulating layer 20 on the top of the electroplating groove as a basis for the subsequent upward growth of the electroplated gate lines.

[0070] Non-groove areas retain the complete insulating layer 20 to prevent non-target areas from becoming conductive.

[0071] S5: The second intermediate solar panel is electroplated with copper to obtain a third intermediate solar panel with copper grid lines 50 (e.g., Figure 4 (As shown).

[0072] In some alternative implementations, during copper electroplating, the substrate can be used as the cathode to be negatively charged, and the high-purity copper plate can be used as the anode to be positively charged. The two electrodes are placed vertically, and the direction of the electric field is perpendicular to the surface of the substrate.

[0073] The electroplating solution used for copper electroplating may include 180 g / L to 220 g / L (such as 180 g / L, 190 g / L, 200 g / L, 210 g / L, or 220 g / L) of copper sulfate and 40 g / L to 60 g / L (such as 40 g / L, 50 g / L, or 60 g / L). Furthermore, the above-mentioned electroplating solution may also include a leveling agent.

[0074] The current density for copper electroplating can be 1 A / dm³ 2 ~3A / dm 2 , such as 1A / dm 2 1.5A / dm 2 2A / dm 2 2.5A / dm 2 or 3A / dm 2 etc., can also be 1A / dm 2 ~3A / dm 2 Other values ​​within the range.

[0075] The deposition temperature for copper electroplating can be 25℃~30℃; the deposition time can be 10min~15min, such as 10min, 12min or 15min, or other values ​​within the range of 10min~15min.

[0076] Preferably, in the above-mentioned copper electroplating process, copper (Cu) is first... 2+ The gradient groove is filled and contacted with the battery substrate, and then grown upward along the seed layer 30 until the copper layer is 0.5μm~1μm higher than the insulating layer 20, thus obtaining the grid line morphology embedded in the insulating layer 20.

[0077] Furthermore, after copper electroplating, a low-temperature annealing process can be performed.

[0078] In some alternative embodiments, the conditions for low-temperature annealing include: holding at a temperature of 200°C to 300°C (e.g., 200°C, 250°C, or 300°C) for 25 min to 35 min (e.g., 25 min, 30 min, or 35 min) under a protective atmosphere (e.g., nitrogen or argon).

[0079] The aforementioned low-temperature annealing treatment enhances the adhesion between the copper layer and the silicon substrate, eliminating electroplating stress. The annealing temperature setting prevents excessive copper atom diffusion. The solution provided by this invention enables the formation of a Cu-Si alloy layer between the copper layer and the silicon substrate, significantly improving the adhesion between the gate line and the silicon substrate, and also reducing the resistivity of the copper gate line 50.

[0080] S6: Perform plasma etching on the third intermediate solar panel to remove the insulating layer 20 in the non-gateline region (e.g., Figure 5 (As shown).

[0081] In some alternative embodiments, the plasma etching of the third intermediate solar panel includes initial etching and fine etching. Both processes can be performed using reactive ion etching (RIE) equipment, with a polishing allowance left after etching.

[0082] The initial etching conditions may include: a power of 200W~250W (e.g., 200W, 210W, 220W, 230W, 240W, or 250W), and plasma comprising carbon tetrafluoride and oxygen in a volume ratio of 3.5:1 to 4.5:1 (e.g., 3.5:1, 4:1, or 4.5:1). The initial etching depth is 94%~96% (e.g., 94%, 95%, or 96%) of the preset etching depth. For example, if the preset etching depth is 150nm, the initial etching depth can be 142.5nm. After the initial etching, a preliminary groove shape for the non-gateline region (i.e., the initial groove for the non-gateline region) is rapidly formed to reduce the height of the insulating layer 20 in the non-gateline region and smooth the surface.

[0083] Fine etching conditions may include: a power of 100W~150W (such as 100W, 110W, 120W, 130W, 140W or 150W, etc.), and plasma consisting of trifluoromethane and oxygen in a volume ratio of 3:1.5 to 3:2.5 (such as 3:1.5, 3:2 or 3:2.5, etc.).

[0084] Fine etching involves etching the remaining thickness at a predetermined etching depth, a process that disperses charge accumulation. Preferably, after fine etching, the sidewall perpendicularity of the initial groove in the non-gate area can be 87°~89° (e.g., 87°, 88°, or 89°), and the surface roughness can be 8nm~10nm (e.g., 8nm, 9nm, or 10nm), forming smooth insulating sidewalls.

[0085] S7: Remove excess seed layer 30 and protective layer 40 (e.g.) Figure 6 (As shown).

[0086] This process removes redundant layers, allowing the bottom of the copper layer to directly contact and conduct with the silicon substrate, and the sidewalls of the copper gate line 50 to be tightly bonded to the insulating layer 20 without gaps, thereby optimizing the overall performance of the copper gate line 50.

[0087] In some alternative embodiments, the excess seed layer 30 may be removed by etching. The etching solution used in this process may include hydrochloric acid and hydrogen peroxide in a volume ratio of 2.5:1 to 3.5:1 (e.g., 2.5:1, 3:1, or 3.5:1). The etching process may be performed at room temperature for 1 to 2 minutes (e.g., 1 minute, 1.5 minutes, or 2 minutes).

[0088] In some alternative embodiments, the excess protective layer 40 may be removed by etching. The etching solution used in this process may include hydrofluoric acid and citric acid in a volume ratio of 1:4.5 to 1:5.5 (e.g., 1:4.5, 1:5, or 1:5.5). The etching process may be performed at room temperature for 1 to 2 minutes (e.g., 1 minute, 1.5 minutes, or 2 minutes).

[0089] Preferably, ultrasonic oscillation can be used as an auxiliary process during the etching process. The power of the ultrasonic oscillation can be, for example, 50W to 80W (such as 50W, 60W, 70W or 80W).

[0090] During the etching process described above, a nonionic surfactant may be added, and the amount added may be 0.05wt% to 0.2wt% of the etching solution.

[0091] S8: Electrochemical polishing of copper grid line 50.

[0092] In some alternative embodiments, the electrochemical polishing process uses copper grid line 50 as the anode, and the electrolyte system used may include phosphoric acid, sulfuric acid and water in a volume ratio of 6.5:2.5:1 to 7.5:1.5:1 (such as 6.5:2.5:1, 7:2:1 or 7.5:1.5:1, etc.).

[0093] The current density for electrochemical polishing can be 0.4 A / dm³. 2 ~0.6A / dm 2 , such as 0.4A / dm 2 0.5A / dm 2 or 0.6A / dm 2 Etc., can also be 0.4A / dm 2 ~0.6A / dm 2 Other values ​​within the range.

[0094] The electrochemical polishing time can be 1 min to 2 min, such as 1 min, 1.5 min or 2 min.

[0095] In this electrochemical polishing process, the height of the insulating layer 20 in the non-gate region is used as a reference, and only the part of the copper layer that is too high is polished. The polishing time is controlled to avoid over-polishing that would cause the gate line to be thinned.

[0096] The above polishing process can remove electroplating burrs, reduce surface roughness (the surface roughness Ra of copper grid line 50 is <0.1nm), and improve conductivity (conductivity can be improved by about 5% compared to existing solar cells).

[0097] S9: Clean and dry the product after electrochemical polishing to remove residual etching solution and polishing solution and prevent surface oxidation.

[0098] In some alternative implementations, cleaning can be performed using deionized water and ultrasonic cleaning for 2 to 4 minutes. After cleaning, isopropanol can be used for dehydration, followed by nitrogen drying, and prolonged exposure to air should be avoided.

[0099] In conclusion, the method provided by this invention can produce insulating layer grooves with high verticality, low surface roughness, and good morphological preservation. It can also achieve excellent bonding between the copper grid line 50 and the substrate with minimal damage to the transparent conductive layer, effectively reducing line resistance and obtaining better grid line quality.

[0100] Accordingly, the present invention also provides a solar cell prepared by the above-described method. This solar cell exhibits superior photoelectric conversion performance.

[0101] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0102] Example 1 This embodiment provides a solar cell, the preparation method of which includes: S1: An insulating layer 20 is deposited on the surface of the transparent conductive layer of the photovoltaic cell substrate 10, and hydroxyl groups are introduced on the surface of the insulating layer 20 to obtain a first intermediate cell plate with a hydroxyl layer.

[0103] The insulating layer 20 was prepared using plasma-enhanced chemical vapor deposition. The insulating layer 20 is made of SiN. x The thickness is 250 nm. Hydroxyl groups were introduced using plasma treatment, with the following conditions: power of 100 W; plasma consisting of argon and oxygen in a volume ratio of 1:2.

[0104] S2: Divide the first intermediate solar panel into grid line area and non-grid line area. The non-grid line area is protected by a mask. The grid line area is laser-grooved to form a trapezoidal groove 21 that is narrow at the top and wide at the bottom.

[0105] Among them, laser scribing is used to divide the grid area and the non-grid area.

[0106] The conditions for laser grooving include: using an ultraviolet nanosecond laser; laser frequency of 2000kHz; single pulse energy of 0.5μJ; power of 25% of rated power; and spot diameter of 50μm.

[0107] The trapezoidal groove 21 has a top width of 15 μm and a bottom width of 25 μm. The trapezoidal groove 21 penetrates the insulating layer 20 and protrudes from the surface of the photovoltaic cell substrate 10.

[0108] S3: Electrochemical polishing is performed on the trapezoidal groove 21 to obtain the electroplated groove.

[0109] The electrochemical polishing conditions included: using a pre-defined grid region substrate as the anode and a platinum sheet as the cathode, and employing pulsed current. The pulsed current frequency was 200 Hz, and the current density was 1 A / dm³. 2 The polishing time is 45 seconds. The duty cycle is automatically adjusted according to the height of the etched electroplating groove protrusions. When the protrusion height is >20nm, the duty cycle is increased to 50%; when the protrusion height is <10nm, the duty cycle is reduced to 30%.

[0110] The electrolyte used in the aforementioned electrochemical polishing comprises a main component, a solubility regulator, and an insulating layer 20 protective agent. The main component consists of phosphoric acid and ethylene glycol in a volume ratio of 3:7. The solubility regulator (fluoroborate) accounts for 0.4% of the main component's mass, and the insulating layer 20 protective agent (silane coupling agent) accounts for 0.8% of the main component's mass.

[0111] After electrochemical polishing, the verticality of the sidewalls of the electroplating grooves is increased to 90°, the surface roughness is ≤0.5nm, and a micro-arc transition of 0.1μm~0.2μm is formed on the sidewalls.

[0112] S4: Seed layer 30 and protective layer 40 are deposited sequentially in the electroplating groove and on the side of the insulating layer 20 facing the electroplating groove to obtain the second intermediate battery panel.

[0113] Both the seed layer 30 and the protective layer 40 are deposited using magnetron sputtering. During deposition, selective deposition is performed on the bottom and sidewalls of the electroplating groove, and a small area is deposited laterally along the insulating layer 20 on the top of the electroplating groove as a basis for the subsequent upward growth of the electroplated gate lines.

[0114] The total thickness of the seed layer 30 and the protective layer 40 is 1 / 3 of the depth of the electroplating groove. Specifically, the seed layer 30 has a thickness of 75 nm and a sheet resistance of <10 Ω / □; the protective layer 40 (TiN layer) has a thickness of 7.5 nm and a hardness of not less than 25 GPa. The width of the seed layer 30 deposited on the side of the insulating layer 20 facing the electroplating groove is d1, the top width of the electroplating groove is d2, and the bottom width of the electroplating groove is d3, where d1 + d2 = d3.

[0115] S5: The second intermediate solar panel is electroplated with copper to obtain a third intermediate solar panel with copper grid lines 50.

[0116] In copper electroplating, the substrate is used as the cathode (negatively charged), and the high-purity copper plate is used as the anode (positively charged). The two electrodes are placed vertically, with the electric field direction perpendicular to the substrate surface. The electroplating solution includes 200 g / L copper sulfate, 50 g / L sulfuric acid, and a small amount of leveling agent. The current density for copper electroplating is 2 A / dm³. 2 The deposition temperature was 25℃, and the deposition time was 15 minutes. In the above copper electroplating process, copper (Cu) was first... 2+ The gradient groove is filled and contacted with the battery substrate, and then grown upward along the seed layer 30 until the copper layer is 200.5 μm higher than the insulating layer, thus obtaining the gate line morphology embedded in the insulating layer 20.

[0117] After copper electroplating, the copper is subjected to low-temperature annealing at 250°C for 30 minutes under a protective atmosphere (such as nitrogen or argon).

[0118] S6: Perform plasma etching on the third intermediate solar panel to remove the insulating layer 20 in the non-gate area.

[0119] The plasma etching of the third intermediate solar panel using reactive ion etching (RIE) equipment includes initial etching and fine etching. The initial etching conditions are: power of 220W, and plasma consisting of carbon tetrafluoride and oxygen in a volume ratio of 4:1. The initial etching depth is 95% of the preset etching depth. After initial etching, a preliminary groove shape in the non-gateline region (i.e., the initial groove in the non-gateline region) is rapidly formed. The fine etching conditions are: power of 120W, and plasma consisting of trifluoromethane and oxygen in a volume ratio of 3:2. After fine etching, the sidewall perpendicularity of the initial groove in the non-gateline region is 88°, and the surface roughness is 8nm~10nm.

[0120] S7: Remove excess seed layer 30 and protective layer 40.

[0121] Excess seed layer 30 is removed by etching. The etching solution used in this process consists of hydrochloric acid and hydrogen peroxide in a volume ratio of 3:1. This etching process is carried out at room temperature for 1.5 minutes. Excess protective layer 40 is removed by etching. The etching solution used in this process consists of hydrofluoric acid and citric acid in a volume ratio of 1:5. This etching process is carried out at room temperature for 1.5 minutes.

[0122] During the etching process described above, auxiliary ultrasonic oscillation was also performed, with a power of 65W; 0.1wt% of nonionic surfactant was also added during the etching process described above.

[0123] S8: Electrochemical polishing of copper grid line 50.

[0124] The electrochemical polishing process uses copper grid wire 50 as the anode, and the electrolyte system can include phosphoric acid, sulfuric acid, and water in a volume ratio of 7:2:1. The current density for electrochemical polishing is 0.5 A / dm³. 2 The electrochemical polishing time was 1.5 min. During this electrochemical polishing process, based on the height of the insulating layer 20 in the non-gate area, only the portion of the copper layer that protrudes was polished. Through the above polishing treatment, the surface roughness Ra of the copper gate line 50 was less than 0.1 nm.

[0125] S9: The product after electrochemical polishing is ultrasonically cleaned with deionized water for 3 minutes, then dehydrated with isopropanol and dried with nitrogen.

[0126] Example 2 This embodiment provides a solar cell, the preparation method of which includes: S1: An insulating layer 20 is deposited on the surface of the transparent conductive layer of the photovoltaic cell substrate 10, and hydroxyl groups are introduced on the surface of the insulating layer 20 to obtain a first intermediate cell plate with a hydroxyl layer.

[0127] The insulating layer 20 was prepared using plasma-enhanced chemical vapor deposition. The insulating layer 20 is made of SiN.x The thickness is 200 nm. Hydroxyl groups were introduced using plasma treatment, with the following conditions: power of 80 W; plasma consisting of argon and oxygen in a volume ratio of 1:1.5.

[0128] S2: Divide the first intermediate solar panel into grid line area and non-grid line area. The non-grid line area is protected by a mask. The grid line area is laser-grooved to form a trapezoidal groove 21 that is narrow at the top and wide at the bottom.

[0129] Among them, laser scribing is used to divide the grid area and the non-grid area.

[0130] The conditions for laser grooving include: using an ultraviolet nanosecond laser; laser frequency of 1500kHz; single pulse energy of 0.3μJ; power of 10% of rated power; and spot diameter of 30μm.

[0131] The trapezoidal groove 21 has a top width of 10 μm and a bottom width of 20 μm. The trapezoidal groove 21 penetrates the insulating layer 20 and protrudes from the surface of the photovoltaic cell substrate 10.

[0132] S3: Electrochemical polishing is performed on the trapezoidal groove 21 to obtain the electroplated groove.

[0133] The electrochemical polishing conditions included: using a pre-defined grid region substrate as the anode and a platinum sheet as the cathode, and employing pulsed current. The pulsed current frequency was 150 Hz, and the current density was 0.8 A / dm³. 2 The polishing time is 60 seconds. The duty cycle is automatically adjusted according to the height of the etched electroplating groove protrusions. When the protrusion height is >20nm, the duty cycle is increased to 50%; when the protrusion height is <10nm, the duty cycle is reduced to 30%.

[0134] The electrolyte used in the aforementioned electrochemical polishing comprises a main component, a solubility regulator, and an insulating layer 20 protective agent. The main component consists of phosphoric acid and ethylene glycol in a volume ratio of 2:8. The solubility regulator (fluoroborate) accounts for 0.3% of the main component's mass, and the insulating layer 20 protective agent (silane coupling agent) accounts for 0.5% of the main component's mass.

[0135] After electrochemical polishing, the verticality of the sidewalls of the electroplated grooves is increased to 89.5°, the surface roughness is ≤0.5nm, and a micro-arc transition of 0.1μm~0.2μm is formed on the sidewalls.

[0136] S4: Seed layer 30 and protective layer 40 are deposited sequentially in the electroplating groove and on the side of the insulating layer 20 facing the electroplating groove to obtain the second intermediate battery panel.

[0137] Both the seed layer 30 and the protective layer 40 are deposited using magnetron sputtering. During deposition, selective deposition is performed on the bottom and sidewalls of the electroplating groove, and a small area is deposited laterally along the insulating layer 20 on the top of the electroplating groove as a basis for the subsequent upward growth of the electroplated gate lines.

[0138] The total thickness of the seed layer 30 and the protective layer 40 is half the depth of the electroplating groove. Specifically, the seed layer 30 has a thickness of 50 nm and a sheet resistance of <10 Ω / □; the protective layer 40 (TiN layer) has a thickness of 5 nm and a hardness of not less than 25 GPa. The width of the seed layer 30 deposited on the side of the insulating layer 20 facing the electroplating groove is d1, the top width of the electroplating groove is d2, and the bottom width of the electroplating groove is d3, where d1 + d2 = d3.

[0139] S5: The second intermediate solar panel is electroplated with copper to obtain a third intermediate solar panel with copper grid lines 50.

[0140] In copper electroplating, the substrate is used as the cathode (negatively charged), and the high-purity copper plate is used as the anode (positively charged). The two electrodes are placed vertically, with the electric field direction perpendicular to the substrate surface. The electroplating solution includes 180 g / L copper sulfate, 40 g / L sulfuric acid, and a small amount of leveling agent. The current density for copper electroplating is 1 A / dm³. 2 The deposition temperature was 30℃, and the deposition time was 15 minutes. In the above copper electroplating process, copper (Cu) was first... 2+ The gradient groove is filled and contacted with the battery substrate, and then grown upward along the seed layer 30 until the copper layer is 1 μm higher than the insulating layer 20, thus obtaining the gate line morphology embedded in the insulating layer 20.

[0141] After copper electroplating, the copper is subjected to low-temperature annealing at 200°C for 35 minutes under a protective atmosphere (such as nitrogen or argon).

[0142] S6: Perform plasma etching on the third intermediate solar panel to remove the insulating layer 20 in the non-gate area.

[0143] The plasma etching of the third intermediate solar panel using reactive ion etching (RIE) equipment includes initial etching and fine etching. The initial etching conditions are: power of 200W, and plasma consisting of carbon tetrafluoride and oxygen in a volume ratio of 3.5:1. The initial etching depth is 94% of the preset etching depth. After initial etching, a preliminary groove shape in the non-gateline region (i.e., the initial groove in the non-gateline region) is rapidly formed. The fine etching conditions are: power of 100W, and plasma consisting of trifluoromethane and oxygen in a volume ratio of 3:1.5. After fine etching, the sidewall perpendicularity of the initial groove in the non-gateline region is 87°, and the surface roughness is 8nm~10nm.

[0144] S7: Remove excess seed layer 30 and protective layer 40.

[0145] Excess seed layer 30 is removed by etching. The etching solution used in this process includes hydrochloric acid and hydrogen peroxide in a volume ratio of 2.5:1. This etching process is carried out at room temperature for 2 minutes. Excess protective layer 40 is removed by etching. The etching solution used in this process includes hydrofluoric acid and citric acid in a volume ratio of 1:4.5. This etching process is carried out at room temperature for 2 minutes.

[0146] During the etching process described above, auxiliary ultrasonic oscillation was also performed, with a power of 50W; during the etching process described above, 0.05wt% of nonionic surfactant was also added.

[0147] S8: Electrochemical polishing of copper grid line 50.

[0148] The electrochemical polishing process uses copper grid wire 50 as the anode, and the electrolyte system can include phosphoric acid, sulfuric acid, and water in a volume ratio of 6.5:2.5:1. The current density for electrochemical polishing is 0.4 A / dm³. 2 The electrochemical polishing time was 2 minutes. During this electrochemical polishing process, based on the height of the insulating layer 20 in the non-gate area, only the portion of the copper layer that protrudes was removed. Through the above polishing treatment, the surface roughness Ra of the copper gate line 50 was less than 0.1 nm.

[0149] S9: The product after electrochemical polishing is ultrasonically cleaned with deionized water for 2 minutes, then dehydrated with isopropanol and dried with nitrogen.

[0150] Example 3 This embodiment provides a solar cell, the preparation method of which includes: S1: An insulating layer 20 is deposited on the surface of the transparent conductive layer of the photovoltaic cell substrate 10, and hydroxyl groups are introduced on the surface of the insulating layer 20 to obtain a first intermediate cell plate with a hydroxyl layer.

[0151] The insulating layer 20 was prepared using plasma-enhanced chemical vapor deposition. The insulating layer 20 is made of SiN. x The thickness is 300 nm. Hydroxyl groups were introduced using plasma treatment, with the following conditions: power of 120 W; plasma consisting of argon and oxygen in a volume ratio of 1:2.5.

[0152] S2: Divide the first intermediate solar panel into grid line area and non-grid line area. The non-grid line area is protected by a mask. The grid line area is laser-grooved to form a trapezoidal groove 21 that is narrow at the top and wide at the bottom.

[0153] Among them, laser scribing is used to divide the grid area and the non-grid area.

[0154] The conditions for laser grooving include: using an ultraviolet nanosecond laser; laser frequency of 2500kHz; single pulse energy of 0.8μJ; power of 40% of rated power; and spot diameter of 70μm.

[0155] The trapezoidal groove 21 has a top width of 20 μm and a bottom width of 30 μm. The trapezoidal groove 21 penetrates the insulating layer 20 and protrudes from the surface of the photovoltaic cell substrate 10.

[0156] S3: Electrochemical polishing is performed on the trapezoidal groove 21 to obtain the electroplated groove.

[0157] The electrochemical polishing conditions included: using a pre-defined grid region substrate as the anode and a platinum sheet as the cathode, and employing pulsed current. The pulsed current frequency was 250 Hz, and the current density was 1.5 A / dm³. 2 The polishing time is 30 seconds. The duty cycle is automatically adjusted according to the height of the etched electroplating groove protrusions. When the protrusion height is >20nm, the duty cycle is increased to 50%; when the protrusion height is <10nm, the duty cycle is reduced to 30%.

[0158] The electrolyte used in the electrochemical polishing process includes a main component, a solubility regulator, and an insulating layer 20 protective agent. The main component comprises phosphoric acid and ethylene glycol in a volume ratio of 4:6. The solubility regulator (fluoroborate) accounts for 0.5% of the main component's mass, and the insulating layer 20 protective agent (silane coupling agent) accounts for 1% of the main component's mass.

[0159] After electrochemical polishing, the verticality of the sidewalls of the electroplating grooves is increased to 90.5°, the surface roughness is ≤0.5nm, and a micro-arc transition of 0.1μm~0.2μm is formed on the sidewalls.

[0160] S4: Seed layer 30 and protective layer 40 are deposited sequentially in the electroplating groove and on the side of the insulating layer 20 facing the electroplating groove to obtain the second intermediate battery panel.

[0161] Both the seed layer 30 and the protective layer 40 are deposited using magnetron sputtering. During deposition, selective deposition is performed on the bottom and sidewalls of the electroplating groove, and a small area is deposited laterally along the insulating layer 20 on the top of the electroplating groove as a basis for the subsequent upward growth of the electroplated gate lines.

[0162] The total thickness of the seed layer 30 and the protective layer 40 is 1 / 3 of the depth of the electroplating groove. Specifically, the seed layer 30 has a thickness of 100 nm and a sheet resistance of <10 Ω / □; the protective layer 40 (TiN layer) has a thickness of 10 nm and a hardness of not less than 25 GPa. The width of the seed layer 30 deposited on the side of the insulating layer 20 facing the electroplating groove is d1, the top width of the electroplating groove is d2, and the bottom width of the electroplating groove is d3, where d1 + d2 = d3.

[0163] S5: The second intermediate solar panel is electroplated with copper to obtain a third intermediate solar panel with copper grid lines 50.

[0164] In copper electroplating, the substrate is used as the cathode (negatively charged), and the high-purity copper plate is used as the anode (positively charged). The two electrodes are placed vertically, with the electric field direction perpendicular to the substrate surface. The electroplating solution includes 220 g / L copper sulfate, 60 g / L sulfuric acid, and a small amount of leveling agent. The current density for copper electroplating is 3 A / dm³. 2 The deposition temperature was 25℃, and the deposition time was 10 minutes. In the above copper electroplating process, copper (Cu) was first... 2+ The gradient groove is filled and contacted with the battery substrate, and then grown upward along the seed layer 30 until the copper layer is 200.5 μm higher than the insulating layer, thus obtaining the gate line morphology embedded in the insulating layer 20.

[0165] After copper electroplating, the copper is subjected to low-temperature annealing at 300°C for 25 minutes under a protective atmosphere (such as nitrogen or argon).

[0166] S6: Perform plasma etching on the third intermediate solar panel to remove the insulating layer 20 in the non-gate area.

[0167] The plasma etching of the third intermediate solar panel using reactive ion etching (RIE) equipment includes initial etching and fine etching. The initial etching conditions are: power of 250W, and plasma consisting of carbon tetrafluoride and oxygen in a volume ratio of 4.5:1. The initial etching depth is 96% of the preset etching depth. After initial etching, a preliminary groove shape in the non-gateline region (i.e., the initial groove in the non-gateline region) is rapidly formed. The fine etching conditions are: power of 150W, and plasma consisting of trifluoromethane and oxygen in a volume ratio of 3:2.5. After fine etching, the sidewall perpendicularity of the initial groove in the non-gateline region is 89°, and the surface roughness is 8nm~10nm.

[0168] S7: Remove excess seed layer 30 and protective layer 40.

[0169] Excess seed layer 30 is removed by etching. The etching solution used in this process includes hydrochloric acid and hydrogen peroxide in a volume ratio of 3.5:1. This etching process is performed at room temperature for 1 minute. Excess protective layer 40 is removed by etching. The etching solution used in this process includes hydrofluoric acid and citric acid in a volume ratio of 1:5.5. This etching process is performed at room temperature for 1 minute.

[0170] During the etching process described above, auxiliary ultrasonic oscillation was also performed, with a power of 80W; 0.2wt% of nonionic surfactant was also added during the etching process described above.

[0171] S8: Electrochemical polishing of copper grid line 50.

[0172] The electrochemical polishing process uses copper grid wire 50 as the anode, and the electrolyte system can include phosphoric acid, sulfuric acid, and water in a volume ratio of 7.5:1.5:1. The current density for electrochemical polishing is 0.6 A / dm³. 2 The electrochemical polishing time was 1 minute. During this electrochemical polishing process, based on the height of the insulating layer 20 in the non-gate area, only the portion of the copper layer that protrudes was polished. Through the above polishing treatment, the surface roughness Ra of the copper gate line 50 was less than 0.1 nm.

[0173] S9: The product after electrochemical polishing is ultrasonically cleaned with deionized water for 4 minutes, then dehydrated with isopropanol and dried with nitrogen.

[0174] Experimental Example 1 The solar cells prepared in Examples 1-3 were subjected to performance tests, and the results are shown in Table 1. The line resistance was measured using a TLM analyzer, and the photoelectric conversion efficiency was measured using an IV analyzer.

[0175] Table 1 Test Results

[0176] As can be seen from Table 1, the solar cells prepared in Examples 1-3 have low line resistance and high photoelectric conversion efficiency.

[0177] In summary, the method provided by this invention can produce insulating layer grooves with high perpendicularity, low surface roughness, and good morphological preservation. It can also achieve excellent bonding between copper gate lines and substrate with minimal damage to the transparent conductive layer, effectively reducing line resistance and obtaining better gate line quality.

[0178] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a solar cell, characterized in that, Includes the following steps: An insulating layer is deposited on the surface of the transparent conductive layer of a photovoltaic cell substrate to obtain a first intermediate cell panel; The first intermediate solar panel is divided into a grid line area and a non-grid line area. The non-grid line area is protected by a mask. The grid line area is laser-grooved to obtain a groove. The groove is electrochemically polished to obtain an electroplated groove; A seed layer and a protective layer are deposited sequentially in the electroplating groove and on the side of the insulating layer facing the electroplating groove to obtain a second intermediate battery panel; The second intermediate battery panel is electroplated with copper to obtain a third intermediate battery panel with copper grid lines. The third intermediate solar panel is subjected to plasma etching to remove the insulating layer in the non-gateline region; Remove excess seed and protective layers.

2. The preparation method according to claim 1, characterized in that, The insulating layer was prepared by plasma-enhanced chemical vapor deposition. Preferably, the thickness of the insulating layer is 200nm~300nm; Preferably, after depositing the insulating layer, hydroxyl groups are introduced onto the surface of the insulating layer to obtain the first intermediate battery panel having a hydroxyl layer; Preferably, the hydroxyl group is introduced by plasma treatment, wherein the plasma treatment conditions include: a power of 80W to 120W; and the plasma being argon and oxygen in a volume ratio of 1:1.5 to 1:2.

5.

3. The preparation method according to claim 1, characterized in that, The conditions for laser grooving include: using an ultraviolet nanosecond laser or an ultraviolet picosecond laser; laser frequency of 1500kHz~2500kHz; single pulse energy of 0.3μJ~0.8μJ; power of 10%~40% of rated power; and spot diameter of 30μm~70μm. Preferably, the groove penetrates the insulating layer to expose the surface of the photovoltaic cell substrate; Preferably, the groove is a trapezoidal groove, and more preferably a trapezoidal groove that is narrower at the top and wider at the bottom; Preferably, the top width of the trapezoidal groove is 10μm~20μm, and the bottom width is 20μm~30μm.

4. The preparation method according to claim 1, characterized in that, The conditions for electrochemical polishing of the groove include: a pulse current frequency of 150Hz~250Hz, a duty cycle of 30%~50%, and a current density of 0.8A / dm³. 2 ~1.5A / dm 2 Polishing time is 30s~60s; Preferably, the electrolyte used for electrochemical polishing includes a main component, a solubility regulator, and an insulating layer protectant; wherein the main component includes phosphoric acid and ethylene glycol in a volume ratio of 2:8 to 4:6, the solubility regulator is 0.3% to 0.5% of the mass of the main component, and the insulating layer protectant is 0.5% to 1% of the mass of the main component. Preferably, the pH value of the electrolyte is 4-6; Preferably, after electrochemical polishing, the verticality of the sidewalls of the electroplating groove is 89.5°~90.5°, and the surface roughness is ≤0.5nm; Preferably, the sidewall of the electroplating groove has a micro-arc transition of 0.1μm to 0.2μm.

5. The preparation method according to claim 1, characterized in that, The total thickness of the seed layer and the protective layer is 1 / 3 to 1 / 2 of the depth of the electroplating groove; And / or, the width of the seed layer deposited on the surface of the insulating layer facing the electroplating groove is d1, the top width of the electroplating groove is d1, the bottom width of the electroplating groove is d3, and d1+d2=d3; Preferably, the thickness of the seed layer is 50 nm to 100 nm; Preferably, the thickness of the protective layer is 5nm~10nm; Preferably, the sheet resistance of the seed layer is <10Ω / □; Preferably, the hardness of the protective layer is not less than 25 GPa.

6. The preparation method according to claim 1, characterized in that, Copper electroplating includes at least one of the following characteristics: Feature 1: The electroplating solution includes 180g / L~220g / L of copper sulfate and 40g / L~60g / L of sulfuric acid; preferably, the electroplating solution also includes a leveling agent; Feature 2: Current density is 1 A / dm 2 ~3A / dm 2 ; Feature 3: Deposition temperature is 25℃~30℃, and deposition time is 10min~15min; Preferably, during the copper electroplating process, copper is first used to fill the gradient grooves, and then grows upward along the seed layer until the copper layer is 0.5 μm to 1 μm higher than the insulating layer. Preferably, after copper electroplating, a low-temperature annealing treatment is also performed; Preferably, the conditions for low-temperature annealing include: holding at a temperature of 200°C to 300°C for 25 to 35 minutes under a protective atmosphere.

7. The preparation method according to claim 1, characterized in that, The plasma etching performed on the third intermediate solar panel includes initial etching and fine etching; The initial etching conditions include: a power of 200W~250W, and a plasma consisting of carbon tetrafluoride and oxygen in a volume ratio of 3.5:1 to 4.5:1; the fine etching conditions include: a power of 100W~150W, and a plasma consisting of trifluoromethane and oxygen in a volume ratio of 3:1.5 to 3:2.

5. Preferably, the initial etching depth is 94% to 96% of the preset etching depth. After the initial etching, an initial groove is formed in the non-gateline area. And / or, after fine etching, the sidewall verticality of the initial groove in the non-gate area is 87°~89°, and the surface roughness is 8nm~10nm.

8. The preparation method according to claim 1, characterized in that, The excess seed layer is removed by etching, and the etching conditions include at least one of the following characteristics: Feature 4: The etching solution consists of hydrochloric acid and hydrogen peroxide in a volume ratio of 2.5:1 to 3.5:1; Feature 5: Etching is performed at room temperature for 1 to 2 minutes; And / or, the excess protective layer is removed by etching, wherein the etching conditions include at least one of the following characteristics: Feature 6: The etching solution comprises hydrofluoric acid and citric acid in a volume ratio of 1:4.5 to 1:5.5; Feature 7: Etching is performed at room temperature for 1 to 2 minutes; Preferably, ultrasonic oscillation is used as an auxiliary process during etching.

9. The preparation method according to claim 8, characterized in that, After removing excess seed and protective layers, the process also includes electrochemical polishing of the copper grid lines; Preferably, electrochemical polishing of the copper grid lines includes at least one of the following features: Feature 8: The electrolyte system used for electrochemical polishing consists of phosphoric acid, sulfuric acid, and water in a volume ratio of 6.5:2.5:1 to 7.5:1.5:1; Feature 9: The current density for electrochemical polishing is 0.4 A / dm². 2 ~0.6A / dm 2 ; Feature 10: The electrochemical polishing time is 1 min to 2 min.

10. A solar cell, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 9.

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