A dual-window layer transverse structure cadmium telluride photovoltaic cell and a preparation method thereof

Abstract

This invention relates to the field of thin-film photovoltaic cell technology, specifically to a dual-window layer inverted cadmium telluride photovoltaic cell and its preparation method. This invention aims to solve the problems of poor adaptability to flexible application scenarios, low compatibility of stacked integration, and the contradiction between environmental protection and efficiency in existing cadmium telluride photovoltaic cells. The photovoltaic cell of this invention, from back electrode to top electrode, comprises: an Ag / Mo composite metal back electrode, a ZnTe:Cu / ZnTe:Ag composite back contact layer, an Sb-doped p-type CdTe absorber layer, an n-type dual-window layer, an ITO transparent top electrode, and an optional SiO2 / MgF2 anti-reflection layer; wherein the n-type dual-window layer is a bilayer structure consisting of a ZnS bottom layer and a ZnSnO3 top layer. This invention achieves a balance between environmental protection and high efficiency through the synergistic design of the dual-window layer and the composite back contact layer, combined with inverted structure optimization.

Description

Technical Field

[0001] This invention relates to the field of thin-film photovoltaic cell technology, specifically to a dual-window layer inverse structure cadmium telluride photovoltaic cell and its preparation method. Background Technology

[0002] Cadmium telluride (CdTe) photovoltaic cells are characterized by their high light absorption coefficient, ≥10⁵ cm⁻¹. -1 With its advantages such as visible light band, low material consumption, film thickness of only 2μm~5μm, and low manufacturing cost (cost per watt <0.3 USD), it has become the mainstream technology in the global thin-film photovoltaic market.

[0003] Current industrialized CdTe cells mainly use a formal structure: glass / transparent conductive oxide (TCO) / window layer / CdTe / back contact / metal electrode, but this has limitations: Low compatibility of stacked integration: The back contact is located below the CdTe layer and cannot be effectively matched with the intermediate connection layer of the stacked cell, such as the tunnel junction, which limits the improvement of stacked efficiency. The existing stacked efficiency is mostly <20%.

[0004] The conflict between environmental protection and efficiency: Relying on a CdS window layer not only poses a risk of cadmium ion leakage and fails to meet the EU RoHS 2.0 standard, but also results in severe absorption of short-wavelength visible light (λ < 520nm) by CdS, with a light transmission loss > 15%, limiting the short-circuit current density J. sc promote.

[0005] To address the aforementioned issues, the industry has gradually begun developing inverted CdTe solar cells, encompassing substrate / back electrode / back contact / CdTe / window layer / TCO. However, existing technologies still have limitations: 1. Back contact barrier problem: The work function matching degree between a single ZnTe:Cu back contact layer and p-type CdTe is low.

[0006] 2. Window layer interface diffusion: During CdCl2 annealing, a single ZnS window layer easily interdiffused with CdTe to form CdS. x Te 1-x Phase, interface state density > 10¹⁵ cm⁻¹ -2 eV -1 The carrier recombination rate is increased by more than 30%. Summary of the Invention

[0007] To address the shortcomings of the existing technologies, the present invention aims to provide an inverted cadmium telluride photovoltaic cell and its fabrication method. This invention introduces a cadmium-free dual-window layer, achieving a synergistic effect of environmental friendliness and light transmittance. The composite back contact layer achieves precise work function matching, effectively reducing contact resistance. Simultaneously, the dual-window layer exhibits a lower interface state density, significantly reducing carrier coincidence rate. The introduction of the dual-window layer optimizes the window layer thickness and electrical properties through interfacial interdiffusion, improving interface contact quality and effectively mitigating performance losses caused by interface issues. Furthermore, it effectively solves the high-temperature tolerance and metal diffusion problems of flexible substrates. The optimized inverted structure can also more effectively prepare tandem cells with perovskites.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A reverse-structure cadmium telluride photovoltaic cell, comprising, from bottom to top, the following layers from the substrate to the top electrode: a substrate; a composite back electrode comprising, from bottom to top, an Ag layer and a Mo layer; a composite back contact layer comprising, from bottom to top, a ZnTe:Cu layer and a ZnTe:Ag layer; an Sb-doped p-type CdTe absorber layer; an n-type dual-window layer comprising, from bottom to top, a ZnS bottom layer and a ZnSnO3 top layer; and a transparent top electrode ITO layer.

[0009] In a preferred embodiment of the present invention, in the n-type dual-window layer, the thickness of the ZnS bottom layer is 8nm~10nm, the thickness of the ZnSnO3 top layer is 40nm~50nm, and the molar ratio of Sn to Zn is 0.8~1.2:1.

[0010] In a preferred embodiment of the present invention, an anti-reflection layer is further provided, which is deposited on the upper surface of the transparent top electrode ITO layer; the anti-reflection layer includes a SiO2 layer and a MgF2 layer; the method for preparing the anti-reflection layer is electron beam evaporation deposition of the SiO2 layer and the MgF2 layer.

[0011] In a preferred embodiment of the present invention, the SiO2 layer has a thickness of 90nm~100nm, the MgF2 layer has a thickness of 50nm~60nm, and the reflectivity in the 400nm~800nm ​​band is <5%.

[0012] In a preferred embodiment of the present invention, in the composite back contact layer, the ZnTe:Cu layer has a thickness of 60nm~80nm and a Cu doping concentration of 1at%~3at%; the ZnTe:Ag layer has a thickness of 30nm~40nm and an Ag doping concentration of 0.5at%~1.5at%; the Sb-doped p-type CdTe absorber layer has a thickness of 2μm~3μm and an Sb doping concentration of 5×10⁻⁶. 16 ~2×10 17 cm -3 .

[0013] In a preferred embodiment of the present invention, the ITO layer has a thickness of 180nm~200nm, a Sn doping concentration of 5at%-8at, and a sheet resistance of <15Ω / □.

[0014] In a preferred embodiment of the present invention, the SiO2 layer has a thickness of 90nm~100nm, the MgF2 layer has a thickness of 50nm~60nm, and the reflectivity in the 400nm~800nm ​​band is <5%.

[0015] The method for preparing the dual-window layer inverse structure cadmium telluride photovoltaic cell of the present invention includes the following steps: Substrate pretreatment: Rigid Mo substrate: ultrasonically cleaned with acetone and ethanol for 15 min to 20 min in sequence, dried with nitrogen, and annealed at 300℃ to 350℃ for 30 min in Ar atmosphere.

[0016] Flexible PI substrate: SiO2 sol is coated on the surface of PI film, dried at 150℃~200℃, and then annealed at 300℃ for 1 hour to form an insulating layer.

[0017] Composite back electrode deposition: On the pretreated substrate, an Ag layer is deposited by DC magnetron sputtering with an Ar flow rate of 20-30 sccm, a deposition pressure of 0.5 Pa to 1 Pa, and a deposition temperature of room temperature; a Mo layer is then deposited with the same process parameters as the Ag layer to ensure no pinhole defects.

[0018] Composite back contact layer deposition: ZnTe:Cu layer was deposited by radio frequency magnetron sputtering with ZnTe-Cu target material, Cu content of 1wt%~3wt%, Ar flow rate of 15sccm~25sccm, deposition pressure of 0.3Pa~0.8Pa, and deposition temperature of 150℃~200℃.

[0019] The ZnTe:Ag layer was deposited by radio frequency magnetron sputtering with ZnTe-Ag as the target material and Ag content of 0.5wt%~1.5wt%. The process parameters were the same as those for the ZnTe:Cu layer.

[0020] p-type CdTe absorber layer deposition: Near-space sublimation equipment was used, with CdTe:Sb as the source material, Sb content 0.1wt%~0.3wt%, sublimation temperature 580℃-620℃, substrate temperature 500℃~550℃, deposition time 10min~15min, and Ar flow rate 80sccm~100sccm atmosphere protection.

[0021] The PI flexible substrate was deposited using a dual-source co-evaporation unit (DSCU) to deposit CdTe:Sb layers with a thickness of 1.0 μm-3.0 μm. The substrate temperature was 180℃~250℃, the CdTe source temperature was 580℃~680℃, and the Sb source temperature was 380℃~480℃. Simultaneously, a radio frequency plasma source was activated with a power of 50W~150W, an Ar / H2 content of Ar+5%H2, and a pressure of 0.1Pa~1.0Pa.

[0022] CdCl2 annealing treatment: A two-step annealing process is adopted: the first step is to hold at 300℃~320℃ for 10min to promote the initial growth of grains; the second step is to hold at 380℃~420℃ for 20min to activate Sb doping. The annealing atmosphere is a mixture of Ar+5%O2 gas and the pressure is 1atm.

[0023] Dual-window layer deposition: Atomic layer deposition of ZnS layer was used, with diethylzinc Zn(C2H5)2 and hydrogen sulfide H2S as precursors. The deposition temperature was 150℃~200℃, the pulse time was 0.1s~0.2s, and the number of cycles was 50~200. Radio frequency magnetron sputtering was used to deposit ZnSnO3 layer, with ZnSnO3 target material, Zn:Sn=1:1, Ar+5%O2 mixed gas, flow rate 20sccm~30sccm, deposition pressure 0.5Pa~1Pa, and deposition temperature room temperature.

[0024] Transparent top electrode deposition: ITO layer is deposited by magnetron sputtering with In2O3-SnO2 target material, SnO2 content of 5wt%~8wt%, Ar+10%O2 mixed gas, flow rate of 25sccm~35sccm, deposition pressure of 0.8Pa~1.2Pa, and deposition temperature of 200℃-250℃.

[0025] Anti-reflection layer deposition: SiO2 layer was deposited by electron beam evaporation at a deposition rate of 0.5 nm / s to 1 nm / s and a deposition temperature of room temperature; MgF2 layer was then deposited with the same process parameters as the SiO2 layer.

[0026] Encapsulation: The encapsulation structure adopts glass / POE adhesive / battery / POE adhesive / backplane, with a lamination temperature of 130℃~150℃ and a lamination time of 15min~20min.

[0027] In a preferred embodiment of the present invention, during the deposition of the CdTe absorber layer, the rigid substrate is subjected to near-space sublimation at a deposition temperature of 580°C to 620°C; the flexible substrate is subjected to dual-source co-evaporation at a substrate temperature of 180°C to 300°C, with the radio frequency plasma source being turned on simultaneously.

[0028] Compared with the prior art, the beneficial effects of the present invention are: 1. The dual-window layer inverse cadmium telluride photovoltaic cell of the present invention comprises, from substrate to top electrode, the following layers: substrate; composite back electrode, including Ag layer and Mo layer; composite back contact layer, including ZnTe:Cu layer and ZnTe:Ag layer; Sb-doped p-type CdTe absorber layer; n-type dual-window layer, including ZnS bottom layer and ZnSnO3 top layer; transparent top electrode ITO layer; and optional anti-reflection layer, including SiO2 layer and MgF2 layer. This design synergistically improves environmental friendliness and light transmittance. The dual-window layer is completely cadmium-free, complying with RoHS 2.0 standards. The composite back contact layer achieves precise work function matching, effectively reducing contact resistance. Simultaneously, the dual-window layer has a lower interface state density and significantly reduced carrier coincidence. The introduction of the dual-window layer optimizes the window layer thickness and electrical properties through interfacial interdiffusion, improving interface contact quality and effectively mitigating performance losses caused by interface problems.

[0029] 2. This invention solves the environmental pollution and short-wavelength light transmission loss problems of CdS window layers, achieving cadmium-free window layers with high light transmittance (λ=400nm~550nm, transmittance>90%); it also solves the work function mismatch problem between the back contact and CdTe, reducing the contact resistance to <5×10⁻⁶. -4 Ω・cm 2 The efficiency (FF) is increased to >70%; the diffusion problem at the interface between the window layer and the CdTe layer during CdCl2 annealing is solved; the high temperature resistance and metal diffusion problems of the flexible substrate are solved, so that the efficiency decay rate after 1000h damp heat aging is ≤5%.

[0030] 3. The flexible substrate solution can withstand high-temperature deposition below 300℃. The SiO2 sol is coated on the PI film surface, so that the substrate and the back electrode have an insulating layer directly. After 1000h of damp heat aging, the efficiency decay rate is ≤5%, which is 10 to 12 percentage points higher than the existing flexible CdTe cells. The inverted structure can be directly used as the intermediate cell of the stack. After integration with the perovskite top cell, the stack efficiency can reach 24%-26%.

[0031] 4. The rigid substrate battery of the present invention can achieve a conversion efficiency of 12.5%~15.5% and the flexible substrate battery can achieve a conversion efficiency of 12.0%~14.0%, which is 1.5 to 2.5 percentage points higher than the existing inverse structure CdTe battery. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the inverse CdTe thin-film photovoltaic cell structure of the present invention.

[0033] Figure 2 This is a comparison chart of the JV curves of the inverse CdTe thin-film photovoltaic cells with ZnS / ZnSnO3 composite window layer / ZnS window layer / ZnSnO3 window layer according to the present invention.

[0034] Figure 3 This is a comparison chart of the JV curves of the inverse CdTe thin-film photovoltaic cells of the ZnTe:Ag / ZnTe:Cu composite back contact layer / ZnTe:Ag back contact layer / ZnTe:Cu back contact layer of the present invention.

[0035] Explanation of reference numerals in the attached figures: 1. Substrate, 2. Ag layer, 3. Mo layer, 4. ZnTe:Cu layer, 5. ZnTe:Ag layer, 6. Sb-doped p-type CdTe absorber layer, 7. ZnS bottom layer, 8. ZnSnO3 top layer, 9. Transparent top electrode ITO layer, 10. SiO2 layer, 11. MgF2 layer. Detailed Implementation

[0036] The following detailed description, in conjunction with embodiments of the present invention and accompanying drawings, provides a clear and complete illustration of the technical solutions in these embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0037] It should be noted that all technical terms used in this invention are for the purpose of describing specific embodiments only and are not intended to limit the scope of protection of this invention. Unless otherwise specified, all raw materials, reagents, instruments and equipment used in the following embodiments of this invention can be purchased from the market or prepared by existing methods.

[0038] Example 1: Rigid substrate photovoltaic cell, polished Mo plate (1) Substrate pretreatment: 0.5mm thick polished Mo plate was selected, ultrasonically cleaned with acetone and ethanol for 20min each, dried with nitrogen, and annealed at 320℃ for 30min in Ar atmosphere, with surface roughness Ra=0.08μm.

[0039] (2) Deposition of composite back electrode: DC magnetron sputtering deposition of Ag layer thickness 150nm, power 120W, Ar flow rate 25sccm, pressure 0.8Pa, room temperature, redeposition of Mo layer thickness 80nm, power 100W, other parameters are the same as Ag layer.

[0040] (3) Deposition of composite back contact layer: RF magnetron sputtering deposition of ZnTe:Cu layer with Cu doping of 2at%, thickness of 80nm, power of 100W, Ar flow rate of 20sccm, pressure of 0.5Pa, 180℃, and then deposition of ZnTe:Ag layer with Ag doping of 1at%, thickness of 40nm, with the same parameters as ZnTe:Cu layer.

[0041] (4) CdTe absorption layer deposition: CSS deposition of CdTe:Sb layer, Sb doping 0.2wt%, thickness 3μm, sublimation temperature 600℃, substrate temperature 520℃, Ar atmosphere, deposition time 12min, grain size 1.2μm.

[0042] (5) CdCl2 annealing: two-step annealing, with conditions of 310℃×10min, 400℃×20min, Ar+5%O2 atmosphere, and pressure of 1atm.

[0043] (6) Dual-window layer deposition: ALD deposition of ZnS layer thickness 10nm, 180℃, diethylzinc and hydrogen sulfide pulse time 0.15s, 100 cycles, RF magnetron sputtering deposition of ZnSnO3 layer thickness 50nm, power 100W, Ar+5%O2 flow rate 25sccm, pressure 0.8Pa, room temperature.

[0044] (7) ITO top electrode deposition: ITO layer was deposited by magnetron sputtering with Sn doping of 6 at%, thickness of 200 nm, power of 180 W, flow rate of Ar+10%O2 of 30 sccm, pressure of 1.0 Pa, temperature of 220 °C, and sheet resistance of 12 Ω / □.

[0045] (8) Anti-reflection layer deposition: SiO2 layer with a thickness of 100 nm and a velocity of 0.8 nm / s is deposited by electron beam evaporation, and MgF2 layer with a thickness of 60 nm and a velocity of 0.8 nm / s is deposited. The reflectivity in the 400-800 nm band is 4.2%.

[0046] Performance testing: Conversion efficiency 14.9%, Voc=0.79V, Jsc=25.8mA / cm 2 FF=73.5%, efficiency after 1000h damp heat aging is 14.3%, and decay rate is 3.7%.

[0047] Example 2: Flexible substrate photovoltaic cell, PI film (1) Substrate pretreatment: A 75μm thick PI film was selected, coated with SiO2 sol and dried at 180℃, and annealed at 300℃ for 1h to form an 80nm thick SiO2 insulating layer with a temperature resistance of 320℃.

[0048] (2) Composite back electrode deposition: DC magnetron sputtering deposition of Ag layer thickness 120nm, power 100W, Ar flow rate 20sccm, pressure 0.6Pa, room temperature, redeposit Mo layer thickness 60nm, power 80W, other parameters are the same as Ag layer.

[0049] (3) Deposition of composite back contact layer: Same as in Example 1, ZnTe:Cu layer, Cu doped 1.5at%, thickness 60nm, ZnTe:Ag layer, Ag doped 0.8at%, thickness 35nm.

[0050] (4) CdTe absorption layer deposition: CdTe was deposited in a dual-source co-evaporation equipment (DSCU): Sb layer thickness 2.5 μm, CdTe source temperature 590℃, Sb source temperature 400℃, substrate temperature 250℃, deposition time 10 min, radio frequency plasma source was turned on simultaneously, power 50-150W, Ar / H2, where Ar+5%H2, pressure 1.0 Pa; after evaporation, it was annealed in the same atmosphere for 10 minutes and then naturally cooled to 80℃.

[0051] (5) Subsequent steps: Same as in Example 1, with double window layer ZnS=8nm, ZnSnO3=40nm; ITO=180nm; anti-reflection layer SiO2=90nm, MgF2=55nm.

[0052] (6) Performance test: Conversion efficiency 13.1%, Voc=0.76V, Jsc=24.7mA / cm 2 FF=70.2%, efficiency after 1000h damp heat aging is 12.5%, and decay rate is 4.1%.

[0053] Example 3: Stacked intermediate cell, integrated with perovskite top cell (1) Battery preparation: Same as in Example 1, except for the removal of the anti-reflection layer. The ITO layer thickness is 200 nm and the sheet resistance is 10 Ω / □.

[0054] (2) Stacked integration: A CsPbI3 perovskite top cell with a thickness of 500 nm was fabricated on an ITO layer, using a Sprio-OMeTAD hole transport layer and an ITO top electrode.

[0055] (3) Performance testing: The conversion efficiency of the tandem cell was 22.9%, and for the top cell, the perovskite Voc was 1.17V and Jsc was 16.9mA / cm. 2 FF=81.0%; bottom cell cadmium telluride Voc=0.78V, Jsc=12.5mA / cm 2 FF=70.8%, 1000h light aging, under AM1.5G conditions, efficiency 21.8% after 50℃, attenuation rate 4.7%.

[0056] Example 4: Rigid substrate photovoltaic cell, polished Mo plate The implementation method is the same as in Example 1, with the composite back electrode having Ag=135nm and Mo=70nm; the composite back contact layer having ZnTe:Cu=70nm and ZnTe:Ag=30nm; the absorption layer having CdTe:Sb=2μm; and the dual-window layer having ZnS=9nm and ZnSnO. 3= 45nm; ITO top electrode = 190nm; anti-reflective layer SiO 2= 95nm, MgF 2= 50nm.

[0057] Performance testing: Conversion efficiency 14.1%, Voc=0.76V, Jsc=25.3mA / cm 2 FF=73.4%, efficiency after 1000h damp heat aging is 13.5%, and decay rate is 3.8%.

[0058] Comparative Example 1: Rigid substrate photovoltaic cell, polished Mo plate / ZnS window layer The implementation method is the same as in Example 1, except that only a ZnS layer is prepared for the window layer.

[0059] Performance testing: Conversion efficiency 13.7%, Voc=0.73V, Jsc=25.6mA / cm 2 FF=70.1%, efficiency after 1000h damp heat aging is 13.2%, and decay rate is 4.2%.

[0060] Comparative Example 2: Polished Mo plate / ZnSnO3 window layer for rigid substrate photovoltaic cells The implementation method is the same as in Example 1, except that only a ZnSnO3 layer is prepared for the window layer.

[0061] Performance testing: Conversion efficiency 13.3%, Voc=0.75V, Jsc=25.3mA / cm 2 FF=69.9%, efficiency after 1000h damp heat aging is 12.6%, and decay rate is 5.0%.

[0062] Based on the data analysis of Comparative Example 1, Comparative Example 2, and Example 1, the ZnS single-window layer possesses extremely high optical transmittance and a wide bandgap, which can effectively improve JSC. However, its performance is limited by the quality of the ZnS / CdTe interface and bandgap matching. The performance of the ZnSnO3 single-window layer is highly dependent on its bandgap matching with CdTe. Poor matching can easily lead to severe S-shaped IV curves and efficiency losses.

[0063] Through material combination and interface engineering, the ZnS / ZnSnO3 dual-window layer can simultaneously achieve high JSC, leveraging the optical advantages, high VOC, and high FF of ZnS, and the bandgap modulation and recombination suppression of ZnSnO3, thereby comprehensively improving the conversion efficiency of CdTe cells.

[0064] Comparative Example 3: Rigid substrate photovoltaic cell, polished Mo plate / ZnTe:Cu back contact layer The implementation method is the same as in Example 1, except that only a ZnTe:Cu layer is prepared for the back contact layer.

[0065] Performance testing: Conversion efficiency 13.6%, Voc=0.73V, Jsc=25.7mA / cm 2FF=72.8%, efficiency after 1000h damp heat aging is 13.0%, and decay rate is 4.9%.

[0066] Comparative Example 4: Rigid substrate photovoltaic cell, polished Mo / ZnTe:Ag back contact layer The implementation method is the same as in Example 1, except that only a ZnTe:Ag layer is prepared for the back contact layer.

[0067] Performance testing: Conversion efficiency 13.7%, Voc=0.75V, Jsc=25.3mA / cm 2 FF=72.24%, efficiency after 1000h damp heat aging is 13.1%, and decay rate is 4.5%.

[0068] Based on the data analysis of Comparative Examples 3 and 4 and Example 1: ZnTe:Cu back contact technology: low contact resistance and high fill factor. Cu doping can simultaneously achieve p-type doping on the CdTe back surface, enhancing the built-in electric field. However, at high temperatures or during long-term use, Cu diffuses into the CdTe / window layer, forming deep-level defects, leading to performance degradation. Furthermore, the interface passivation effect is limited, resulting in significant non-radiative recombination losses; insufficient electron reflection capability means some electrons reach the back electrode and recombine.

[0069] ZnTe:Ag back contact technology: No Cu diffusion, excellent long-term stability. The Ag2Te phase has a large band gap of 2.2 eV, strong electron blocking ability, and higher Voc; it is stable at the CdTe interface with no significant interdiffusion. However, the contact resistance is relatively high, the fill factor is slightly low, the Ag doping efficiency is low, and the p-type conductivity is not as good as Cu doping.

[0070] ZnTe:Cu / ZnTe:Ag composite back contact technology: The Ag layer passivates the interface and improves Voc, the Cu layer enhances conductivity and improves FF, and Jsc is improved due to enhanced electron reflection, which can maximize the performance of the battery.

[0071] The Ag layer forms a physical barrier layer, inhibiting Cu diffusion into CdTe and reducing the attenuation rate by 60%, thus achieving a breakthrough in stability.

[0072] The Cu layer is in direct contact with the metal substrate, and the Ag layer is in direct contact with CdTe, perfectly matching the electric field distribution of the inverted structure. This structural optimization method can greatly improve the conversion efficiency of inverted cadmium telluride solar cells.

[0073] Results Analysis Figure 1This is a schematic diagram of the inverted CdTe thin-film photovoltaic cell structure of the present invention. As can be seen from the figure, light enters from one side of the MgF2 layer, passes through the anti-reflection layer, the ITO top electrode, and the double window layer, and enters the p-type CdTe absorption layer, realizing light absorption and carrier separation. Electrons are output through the double window layer and the ITO top electrode, and holes are output through the Ag layer and the Mo layer, completing the photoelectric conversion process.

[0074] Figure 2 The graph shows a comparison of the JV curves of the inverse CdTe thin-film photovoltaic cells with ZnS / ZnSnO3 composite window layer / ZnS window layer / ZnSnO3 window layer of the present invention. It can be seen from the graph that the photovoltaic device of Example 1 has significantly better performance, followed by Comparative Example 1, and Comparative Example 2 is the worst. This indicates that the material / structure design of Example 1 more effectively suppresses charge recombination and improves the device performance.

[0075] Figure 3 This is a comparison chart of the JV curves of the inverse CdTe thin-film photovoltaic cells of the ZnTe:Cu / ZnTe:Ag composite back contact layer / ZnTe:Ag back contact layer / ZnTe:Cu back contact layer of the present invention. It can be seen from the figure that the photovoltaic device of Example 1 has significantly better performance, followed by Comparative Example 4, and Comparative Example 3 is the worst. This indicates that the material / structure design of Example 1 more effectively suppresses charge recombination and improves device performance.

[0076] In summary, compared with existing technologies, this invention has the following significant advantages: it improves light transmittance of the window layer while also being environmentally friendly; it achieves precise work function matching through double doping of the composite back contact layer, further optimizing carrier transport performance; its unique structural and material design greatly enhances adaptability in flexible and stacked applications; thus effectively improving the performance of inverted CdTe photovoltaic cells, with a conversion efficiency of 12.5%~14.9% for rigid substrates and 11.0%~13.1% for flexible substrates.

[0077] It should be noted that when numerical ranges are involved in this invention, it should be understood that both endpoints of each numerical range and any value between the two endpoints can be selected. Since the steps and methods used are the same as in the embodiments, preferred embodiments are described here to avoid redundancy. Although preferred embodiments of the invention have been described, those skilled in the art, once they understand the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this invention.

[0078] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A dual-window layer inverted cadmium telluride photovoltaic cell, characterized in that, From the substrate to the top electrode, from bottom to top, the following are included: Base (1); The composite back electrode consists of an Ag layer (2) and a Mo layer (3) from bottom to top. The composite back contact layer includes, from bottom to top, a ZnTe:Cu layer (4) and a ZnTe:Ag layer (5); Sb-doped p-type CdTe absorber layer (6); The n-type double window layer includes a bottom ZnS layer (7) and a top ZnSnO3 layer (8) from bottom to top. Transparent top electrode ITO layer (9).

2. The dual-window layer inverted cadmium telluride photovoltaic cell according to claim 1, characterized in that, In the n-type double window layer, the thickness of the bottom ZnS layer (7) is 8nm~10nm, the thickness of the top ZnSnO3 layer (8) is 40nm~50nm, and the molar ratio of Sn to Zn is 0.8~1.2:

1.

3. The dual-window layer inverted cadmium telluride photovoltaic cell according to claim 1, characterized in that, An anti-reflection layer is also provided, which is deposited on the upper surface of the transparent top electrode ITO layer (9); the anti-reflection layer includes a SiO2 layer (10) and a MgF2 layer (11); the method for preparing the anti-reflection layer is electron beam evaporation deposition of the SiO2 layer and the MgF2 layer.

4. The cadmium telluride photovoltaic cell with a dual-window layer inverted structure according to claim 3, characterized in that, In the anti-reflection layer, the SiO2 layer (10) has a thickness of 90nm~100nm, the MgF2 layer (11) has a thickness of 50nm~60nm, and the reflectivity in the 400nm~800nm ​​band is <5%.

5. The dual-window layer inverted cadmium telluride photovoltaic cell according to claim 1, characterized in that, In the composite back contact layer, the ZnTe:Cu layer (4) has a thickness of 60nm~80nm and a Cu doping concentration of 1at%-3at%; the ZnTe:Ag layer (5) has a thickness of 30nm~40nm and an Ag doping concentration of 0.5at%~1.5at%; the Sb-doped p-type CdTe absorber layer (6) has a thickness of 2μm~3μm and an Sb doping concentration of 5×10⁻⁶. 16 ~2×10 17 cm -3 .

6. The dual-window layer inverted cadmium telluride photovoltaic cell according to claim 1, characterized in that, The substrate (1) is a rigid Mo plate or a flexible polyimide PI film; the surface of the flexible PI film is provided with a SiO2 insulating layer with a thickness of 50nm~100nm.

7. The dual-window layer inverted cadmium telluride photovoltaic cell according to claim 1, characterized in that, In the composite back electrode, the thickness of the Ag layer (2) is 120nm~150nm, and the thickness of the Mo layer (3) is 60nm~80nm.

8. The dual-window layer inverted cadmium telluride photovoltaic cell according to claim 1, characterized in that, The ITO layer (9) has a thickness of 180nm~200nm, a Sn doping concentration of 5at%~8at%, and a sheet resistance of <15Ω / □.

9. A method for preparing a dual-window layer inverse structure cadmium telluride photovoltaic cell according to any one of claims 1-8, characterized in that, Includes the following steps: Substrate pretreatment: Cleaning the substrate; Deposition of composite back electrode: Sequentially depositing Ag and Mo layers by DC magnetron sputtering; Deposition of composite back contact layer: sequentially depositing ZnTe:Cu layer and ZnTe:Ag layer by radio frequency magnetron sputtering; Deposited CdTe absorber layer: Sb-doped CdTe layer is deposited by near-space sublimation or dual-source co-evaporation; CdCl2 annealing: a two-step annealing process that activates doping and promotes grain growth; Deposition of dual-window layers: ALD deposition of ZnS layer, followed by RF magnetron sputtering deposition of ZnSnO3 layer on ZnS layer; ITO top electrode deposition: ITO layer deposited by magnetron sputtering; Encapsulation: Glass / POE adhesive / battery / POE adhesive / backplane structure laminate encapsulation.

10. The method for preparing a dual-window layer inverse structure cadmium telluride photovoltaic cell according to claim 9, characterized in that, The substrate pretreatment method is as follows: when the substrate is a rigid Mo substrate, the substrate is directly cleaned; when the substrate is a flexible PI substrate, SiO2 sol is coated on the PI film surface to form an insulating layer; in the CdTe absorber layer deposition, the rigid substrate adopts near-space sublimation, and the deposition temperature is 580℃~620℃. The flexible substrate is coated with dual-source co-evaporation, with a substrate temperature of 180℃~300℃ and the radio frequency plasma source is turned on simultaneously.

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