An intrinsic sub-nanopore confinement-based two-dimensional material memristor device and a preparation method thereof

Abstract

This invention relates to a two-dimensional material memristor device based on intrinsic sub-nanometer channel confinement and its fabrication method, belonging to the field of semiconductor device technology. From bottom to top, it comprises a bottom electrode layer, a porous two-dimensional material resistive switching layer, an active metal layer, and a top electrode layer. The porous two-dimensional material resistive switching layer has sub-nanometer intrinsic channels within its crystal structure. The core innovation of this invention lies in the fact that the resistive switching layer is composed of a two-dimensional material with sub-nanometer channels. This porous two-dimensional material layer not only provides a confined, fast channel for the migration of metal cations, but its inherent sub-nanometer channels can also effectively guide and constrain the formation path of conductive filaments. Compared to traditional memristors, this invention utilizes defined ion migration channels instead of random paths, thus possessing advantages such as low settling voltage and low power consumption. The memristor fabricated by this invention has broad application prospects in high-density non-volatile memory and neuromorphic computing systems.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a two-dimensional memristor device based on intrinsic sub-nanometer channel confinement and its fabrication method. Background Technology

[0002] Memristors are a new type of electronic device that can remember historical current states. Their resistance value can dynamically change according to voltage signals and retain its final resistance state after power is off. This characteristic makes them an ideal core component for building in-memory computing architectures. Furthermore, memristors offer advantages such as high response speed, low power consumption, and ease of high-density integration, making them a research hotspot for next-generation neuromorphic computing systems. The diverse resistive switching mechanisms of memristors provide a rich physical foundation for disruptive technologies such as in-memory computing and neuromorphic chips, making them a promising candidate for core devices in the post-Moore's Law era. The resistive switching mechanism is a key focus of memristor research, and differences in its mechanisms are usually due to variations in the materials and structures used to fabricate memristors. Currently, materials used to fabricate memristors include metal oxides, organic materials, ferroelectric materials, and two-dimensional materials.

[0003] The resistive switching mechanism of memristors is generally classified into the following categories: valence state change mechanism (VCM), electrochemical metallization mechanism (ECM), and phase transition mechanism (PCM). Among these, the mechanism based on metal cations (such as Ag) is the most common. + Cu + The electrochemical metallization mechanism of ion migration, with its significant advantages of low operating voltage and high on / off ratio, has become the dominant working mechanism of memristors. However, in traditional memristor materials (such as transition metal oxides), the migration path of metal ions is highly random due to the distribution of internal defects (such as vacancies and grain boundaries), making it difficult to precisely control the spatial growth position, thickness, and morphology of conductive filaments. This inherent randomness further manifests as poor device uniformity, such as large deviations in switching voltage and significant differences in resistance between high and low resistance states, greatly limiting the application potential of memristors in large-scale array integration and the construction of high-reliability neuromorphic computing chips. Therefore, how to achieve precise control of ion migration paths through material design and structural optimization, and thus fabricate memristors with stable performance and high uniformity, has become a key problem that urgently needs to be solved in this field.

[0004] To overcome this challenge, researchers have focused their attention on two-dimensional (2D) materials. 2D materials, with their atomically flat surfaces, absence of dangling bonds, and excellent electrical tunability, provide an ideal platform for constructing high-performance memristors. However, even with a perfectly porous crystal structure, intrinsic 2D materials inevitably rely on randomly generated defect sites (such as edge defects and lattice vacancies) for ion migration, and their in-plane migration paths remain random. This fundamentally limits further improvements in device performance uniformity. Therefore, exploring novel 2D materials with intrinsic ion channels to pre-define low-energy pathways for ion migration has become a highly forward-looking research direction in this field. Summary of the Invention

[0005] This invention employs a porous two-dimensional material with sub-nanometer intrinsic channels within its crystal structure as the resistive switching layer material. The inherent sub-nanometer channels (long-range order, atomic-level natural channels) and van der Waals gaps in the material's lattice provide a natural directional path for silver ion migration. This structural characteristic makes it naturally suitable for vertical memristor architectures: the channels effectively confine the ion migration direction, suppressing random nucleation of conductive filaments, thereby helping to reduce the switching voltage and significantly reduce the power consumption of the memristor. This solves the technical problem in existing technologies where memristor ion migration inevitably relies on randomly generated defect sites, and its in-plane migration path still possesses randomness.

[0006] According to a first aspect of the present invention, a two-dimensional material memristor device based on intrinsic sub-nanometer channel confinement is provided, comprising, from bottom to top, a bottom electrode layer, a porous two-dimensional material resistive switching layer, an active metal layer, and a top electrode layer, wherein the crystal structure of the porous two-dimensional material resistive switching layer has sub-nanometer intrinsic channels.

[0007] Preferably, the porous two-dimensional resistive switching layer is V2P4S. 13 or Nb2PS 10 .

[0008] Preferably, the thickness of the porous two-dimensional material resistive switching layer is 5-100 nm.

[0009] Preferably, the active metal layer is one of Ag, Cu, Ni, Zn, Al or Ti, or the active metal layer is an alloy containing at least two of Ag, Cu, Ni, Zn, Al and Ti; the thickness of the active metal layer is 20-200 nm.

[0010] Preferably, the bottom electrode layer is Au, Pt, or graphene, with the thickness of the Au or Pt bottom electrode layer being 5-50 nm and the thickness of the graphite bottom electrode layer being 0.3-30 nm.

[0011] Preferably, the top electrode layer is Au or Pt, and the thickness of the top electrode layer is 20-200 nm.

[0012] According to another aspect of the present invention, a method for fabricating the aforementioned two-dimensional material memristor device based on intrinsic sub-nanometer channel confinement is provided, comprising the following steps: (1) Deposit a bottom electrode layer on the substrate, or form a bottom electrode layer on the substrate by mechanically exfoliating graphene; (2) A resistive switching layer is prepared on the bottom electrode by mechanically exfoliating a two-dimensional porous material with sub-nanometer intrinsic channels inside the crystal structure; (3) An active metal element or an alloy containing an active metal is deposited on the resistive switching layer to form an active metal layer, and a top electrode layer is deposited on the active metal layer to obtain a two-dimensional material memristor device based on intrinsic sub-nano pore confinement.

[0013] Preferably, in step (1), the bottom electrode layer is obtained by depositing an Au thin film or a Pt thin film on the substrate using thermal evaporation deposition, electron beam evaporation deposition or magnetron sputtering deposition.

[0014] Preferably, in step (2), a mechanical peeling method is used to peel off V2P4S using adhesive tape. 13 or Nb2PS 10 The material is exfoliated onto polydimethylsiloxane, and then the porous two-dimensional material on the polydimethylsiloxane is transferred to the bottom electrode through a two-dimensional material transfer platform to form a resistive switching layer on the bottom electrode layer.

[0015] Preferably, in step (3), thermal evaporation deposition, electron beam evaporation deposition, or magnetron sputtering deposition are used to sequentially deposit an active metal material and a top electrode layer on the resistive switching layer.

[0016] Overall, the technical solutions conceived in this invention, compared with the prior art, can achieve at least the following beneficial effects.

[0017] (1) Material Innovation and Application: This invention is the first to apply a two-dimensional material with sub-nanometer intrinsic channels as a resistive switching layer in a memristor. The natural sub-nanometer channels and van der Waals gaps in the lattice of this material provide directional pathways for the migration of active metal ions, thereby effectively suppressing the random nucleation and growth of conductive filaments. This provides a new material basis for solving the bottleneck problems of uncontrollable ion migration paths and poor device uniformity in traditional memristors.

[0018] (2) Device performance and advantages: Memristors based on intrinsic sub-nanometer channel confinement two-dimensional materials exhibit excellent electrochemical metallization resistive switching behavior, with low operating voltage, low power consumption, high on / off ratio and good cycle stability. Its structural design is conducive to realizing spatial confinement of ion migration direction, significantly improving the consistency of high and low resistance states and device reliability, and is suitable for the application requirements of high-density integration and neuromorphic computing chips.

[0019] (3) The preparation method is simple and feasible: The present invention uses mechanical exfoliation to prepare porous two-dimensional material thin layers. The process is simple and highly repeatable, and can effectively maintain the crystal structure and intrinsic pore characteristics of the material. It is easy to be compatible with existing micro-nano processing technology and provides a feasible technical path for subsequent large-scale device integration and performance optimization. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the memristor structure in Example 1.

[0021] Figure 2 This is the IV characteristic diagram of the memristor in Example 1.

[0022] Figure 3 The curves show the multiconductance control characteristics of the memristor in Example 1.

[0023] Figure 4 The image shows the It characteristic diagram of the memristor in Example 1.

[0024] Figure 5 This is a diagram showing the operation speed of non-volatile electrical pulse writing to the memristor in Example 1.

[0025] Figure 6 This is a diagram showing the operating speed of the non-volatile electrical pulse eraser for the memristor in Example 1. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0027] The present invention discloses a two-dimensional material memristor device based on intrinsic sub-nanometer channel confinement, comprising: a bottom electrode layer, a porous two-dimensional material resistive switching layer, an active metal layer and a top electrode layer arranged sequentially from bottom to top, wherein the porous two-dimensional material resistive switching layer has sub-nanometer intrinsic channels inside its crystal structure. In some embodiments, a substrate and an encapsulation layer are also included, with the substrate located below the bottom electrode and the top electrode located above the active metal layer, and the encapsulation layer used to prevent water and oxygen molecules from reacting with the underlying material.

[0028] In some embodiments, the bottom electrode layer comprises one of Au, Pt, or graphene, wherein the thickness of the Au or Pt bottom electrode layer is 5-50 nm, and the thickness of the graphite bottom electrode layer is 0.3-30 nm.

[0029] In some embodiments, the porous two-dimensional material includes V2P4S. 13 Nb2PS 10 One of the following, wherein the thickness of the resistive switching layer is 5-100 nm.

[0030] In some embodiments, the active metal layer includes one of Ag, Cu, Ni, Zn, Al or Ti, the alloy contains two or more of the above active metals, the number of any one dopant (Ag, Cu, Ni, Zn, Al or Ti) atoms is greater than 5%, and the thickness of the active metal layer is 20-200 nm.

[0031] In some embodiments, the top electrode layer includes one of Au and Pt, and the thickness of the top electrode layer is 20-200 nm.

[0032] In some embodiments, the encapsulation layer comprises one of h-BN, Sb2O3, or Ga2O3, and the thickness of the encapsulation layer is 2-50 nm.

[0033] This invention relates to a method for fabricating memristor devices based on intrinsically sub-nanometer channel-confined two-dimensional materials, comprising the following steps: (1) Deposit a bottom electrode layer on a substrate, or form a bottom electrode layer by mechanically peeling off few layers of graphene; (2) A resistive switching layer is prepared on the bottom electrode by mechanically exfoliating a two-dimensional porous material; (3) An active metal layer is formed by depositing an active metal element or an alloy containing an active metal on the resistive switching layer, and a top electrode layer is deposited on the active metal layer.

[0034] Preferably, an encapsulation layer is formed on the top electrode by mechanical stripping of h-BN or thermal evaporation deposition of Sb2O3.

[0035] In some embodiments, in step (1), the bottom electrode layer is obtained by depositing an Au thin film or a Pt thin film on the substrate using thermal evaporation deposition, electron beam evaporation deposition, or magnetron sputtering deposition.

[0036] In some embodiments, in step (2), a mechanical peeling method is used to remove V2P4S using adhesive tape. 13 Nb2PS10 The material is exfoliated onto polydimethylsiloxane (PDMS), and then the porous two-dimensional material on PDMS is transferred to the bottom electrode through a two-dimensional material transfer platform to form a resistive switching layer on the bottom electrode layer.

[0037] In some embodiments, the active metal layer and the top electrode layer in step (3) are obtained by sequentially depositing an active metal material and one of Au and Pt on the resistive switching layer using thermal evaporation deposition, electron beam evaporation deposition, or magnetron sputtering deposition.

[0038] In some embodiments, the encapsulation layer is prepared by mechanical peeling to create a few-layer h-BN and then covering it onto the memristor device using a two-dimensional material transfer platform, or by thermal evaporation deposition of an Sb2O3 thin film.

[0039] This invention relates to the application of memristor devices based on intrinsic sub-nanometer channel confined two-dimensional materials. The invention is characterized by its application in fields where energy consumption is less than 100 pJ. The energy consumption is E, which is calculated as E = V × I × t (where V is the device set voltage, I is the device operating current, and t is the device response time).

[0040] The following are specific examples.

[0041] Example 1 This embodiment 1 provides a memristor device, the structure of which is as follows: Figure 1 As shown, the resistive switching layer is V2P4S. 13 film.

[0042] The fabrication method of the memristor device in this embodiment 1 includes the following steps: (1) A clean silicon wafer was used as the substrate, and an Au thin film with a thickness of 10 nm was deposited on the substrate as the bottom electrode by thermal evaporation. The process conditions were: Au as the evaporation source, nitrogen as the evaporation atmosphere, evaporation rate of 0.15 Å / s, and chamber pressure less than 8 × 10⁻⁶. -4 Pa.

[0043] (2) V2P4S was prepared on the bottom electrode by mechanical stripping. 13 The thin film serves as a resistive switching layer, V2P4S 13 The film thickness is 10 nm. The process conditions are: V2P4S is removed by mechanical exfoliation. 13 The thin film was adhered to the PDMS surface with tape, and then the material was transferred to the bottom electrode surface using a two-dimensional material transfer platform.

[0044] (3) Using electron beam lithography on V2P4S 13Top electrode patterns were fabricated on the thin film. The photoresist used was polymethyl methacrylate (PMMA), which was spin-coated and then baked at 150 °C for 5 minutes. After exposure, the sample was immersed in the developer for 5-10 seconds, followed by immersion in the fixer for 10 seconds and then dried with a nitrogen gun.

[0045] (4) An Ag film with a thickness of 20 nm was deposited on the pattern created in step (3) using electron beam evaporation. The process conditions were: Ag as the evaporation source, nitrogen as the evaporation atmosphere, evaporation rate of 0.1 Å / s, and chamber pressure less than 8 × 10⁻⁶. -4 Pa.

[0046] (5) An Au layer was deposited on the Ag film as the top electrode using electron beam evaporation. The thickness of the Au film was 100 nm. The process conditions were: Au as the evaporation source, nitrogen as the evaporation atmosphere, evaporation rate of 0.2 Å / s, and chamber pressure less than 8 × 10⁻⁶. -4 Pa. The sample with the top electrode deposited was placed in acetone and heated to 60-70 °C. After soaking for 20 min, the gold was removed, and the memristor device was obtained.

[0047] (6) An h-BN film is prepared on the device surface as an encapsulation layer by mechanical peeling. The thickness of the h-BN film is 5-10 nm. The process conditions are as follows: the tape with the h-BN film is attached to the PDMS surface by mechanical peeling, and then the material is transferred to the surface of the memristor device by a two-dimensional material transfer platform to cover the resistive switching layer material.

[0048] Results analysis: In this embodiment 1, the two-dimensional material V2P4S based on intrinsic sub-nanopore confinement is used. 13 The IV characteristic curve of the memristor is as follows Figure 2 As shown. Figure 2 The green area represents the set process (voltage changes from 0 to 0.2V and then scans back); the red area represents the reset process (voltage changes from 0 to -0.2V and then scans back). Under a current limit of 100 uA, the device exhibits typical threshold-type non-volatile resistive switching characteristics. During the forward voltage scan, when the voltage reaches approximately 0.078 V, the device current undergoes a sudden change, completing the set process from a high-resistance state to a low-resistance state. During the reverse voltage scan, a current sudden change occurs at approximately -0.046 V, realizing the reset process from a low-resistance state to a high-resistance state. The device's on / off ratio (R0) is... on / R off Approximately 10 4 The high and low impedance states are clearly distinguishable. In particular, the device has an extremely low set voltage, demonstrating excellent low power consumption potential.

[0049] In this embodiment 1, the two-dimensional material V2P4S based on intrinsic sub-nanopore confinement is used. 13 The multiconductance control characteristic curve of the memristor is as follows: Figure 3 As shown, by setting different current limits, the device can be controllably set to 256 discrete and stable resistive states. Subsequent IV testing results show that each set state exhibits a unique IV curve, with excellent linearity and discriminability between each state. This characteristic indicates that the device can achieve multi-bit data storage through simple DC voltage operation and can directly simulate the continuous changes in weights in biological synapses, providing a core device foundation for building high-density memories and high-precision neuromorphic computing systems.

[0050] In this embodiment 1, the two-dimensional material V2P4S based on intrinsic sub-nanopore confinement is used. 13 The It retention curve of the memristor is as follows Figure 4 As shown. The test employed a combination of DC voltage operation and a fixed readout voltage: first, a DC set voltage was applied to switch the device to a low-resistance state, and then the current change over time was monitored under a constant readout voltage of 20 mV. The test results show that the low-resistance current of the device exceeds 10 mV. 4 The device remained stable for 10 seconds during the test, with no significant decay observed. Subsequently, a DC reset voltage was applied to restore it to its high-resistivity state, and monitoring was performed at the same 20 mV readout voltage; its high-resistivity current remained at 10 mV. 4 It exhibits excellent hold-up characteristics within seconds. Both high and low resistive currents exceed 10. 4 The ability to maintain a stable state for seconds fully demonstrates the non-volatility of the memristor state.

[0051] In this embodiment 1, the two-dimensional material V2P4S based on intrinsic sub-nanopore confinement is used. 13 The operation speed diagram of non-volatile electrical pulse writing of memristors is shown in Figure 1. Figure 5 As shown. Figure 5 In the diagram, red and blue correspond to the left and right coordinate axes, respectively. Red represents voltage changes, and blue represents current changes. The colors are the same as the coordinate axes. First, a 20 mV read pulse is applied to the device, placing it in a high-impedance state. Then, a 2 V set pulse is applied, followed by a 20 mV read of the device current. The observed current is higher than the initial read current, indicating that the device has successfully set to a low-impedance state with a response time of 160 ns and an energy consumption of 35.8 pJ (E). SET = V SET × I SET × t SET This fully demonstrates the application potential of deionized devices in the field of low-power memristors.

[0052] In this embodiment 1, the two-dimensional material V2P4S based on intrinsic sub-nanopore confinement is used. 13 The non-volatile electrical pulse erase operation speed diagram of the memristor is shown below. Figure 6 As shown. Figure 6 In the diagram, red and blue correspond to the left and right coordinate axes, respectively. Red represents voltage changes, and blue represents current changes. The colors are the same as the coordinate axes. First, a 20 mV read pulse is applied to the device, placing it in a low-resistivity state. Then, a -4 V reset pulse is applied, followed by a 20 mV read of the device current. The observed current is lower than the initial read current, indicating that the device has successfully reset to a high-resistivity state with a response time of 80 ns and an energy consumption of 15.3 pJ (E). RESET = V RESET × I RESET × t RESET This fully demonstrates the application potential of deionized devices in the field of low-power memristors.

[0053] Example 2 This embodiment 2 uses the same steps as embodiment 1 to prepare a memristor device. The difference from embodiment 1 is that the resistive switching layer material is Nb2PS. 10 .

[0054] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A two-dimensional material memristor device based on intrinsic sub-nanometer channel confinement, characterized in that, From bottom to top, it includes a bottom electrode layer, a porous two-dimensional material resistive switching layer, an active metal layer, and a top electrode layer. The porous two-dimensional material resistive switching layer has sub-nanometer intrinsic channels inside its crystal structure.

2. The two-dimensional material memristor device based on intrinsic sub-nanometer channel confinement as described in claim 1, characterized in that, The porous two-dimensional resistive switching layer is V2P4S. 13 or Nb2PS 10 .

3. The two-dimensional material memristor device based on intrinsic sub-nanometer channel confinement as described in claim 1 or 2, characterized in that, The thickness of the porous two-dimensional resistive switching layer is 5-100 nm.

4. The two-dimensional memristor device based on intrinsic sub-nanometer channel confinement as described in claim 1, characterized in that, The active metal layer is one of Ag, Cu, Ni, Zn, Al or Ti, or the active metal layer is an alloy containing at least two of Ag, Cu, Ni, Zn, Al and Ti; the thickness of the active metal layer is 20-200 nm.

5. The two-dimensional memristor device based on intrinsic sub-nanometer channel confinement as described in claim 1, characterized in that, The bottom electrode layer is Au, Pt, or graphene, with the thickness of the Au or Pt bottom electrode layer being 5-50 nm and the thickness of the graphite bottom electrode layer being 0.3-30 nm.

6. The two-dimensional memristor device based on intrinsic sub-nanometer channel confinement as described in claim 1, characterized in that, The top electrode layer is Au or Pt, and the thickness of the top electrode layer is 20-200 nm.

7. The method for fabricating a two-dimensional memristor device based on intrinsic sub-nanometer channel confinement as described in any one of claims 1-6, characterized in that, Includes the following steps: (1) Deposit a bottom electrode layer on the substrate, or form a bottom electrode layer on the substrate by mechanically exfoliating graphene; (2) A resistive switching layer is prepared on the bottom electrode by mechanically exfoliating a two-dimensional porous material with sub-nanometer intrinsic channels inside the crystal structure; (3) An active metal element or an alloy containing an active metal is deposited on the resistive switching layer to form an active metal layer, and a top electrode layer is deposited on the active metal layer to obtain a two-dimensional material memristor device based on intrinsic sub-nano pore confinement.

8. The method for fabricating a two-dimensional memristor device based on intrinsic sub-nanometer channel confinement as described in claim 7, characterized in that, In step (1), the bottom electrode layer is obtained by depositing an Au thin film or a Pt thin film on the substrate using thermal evaporation deposition, electron beam evaporation deposition or magnetron sputtering deposition.

9. The method for fabricating a two-dimensional memristor device based on intrinsic sub-nanometer channel confinement as described in claim 7, characterized in that, In step (2), a mechanical peeling method is used to peel off V2P4S using adhesive tape. 13 or Nb2PS 10 The material is exfoliated onto polydimethylsiloxane, and then the porous two-dimensional material on the polydimethylsiloxane is transferred to the bottom electrode through a two-dimensional material transfer platform to form a resistive switching layer on the bottom electrode layer.

10. The method for fabricating a two-dimensional memristor device based on intrinsic sub-nanometer channel confinement as described in claim 7, characterized in that, In step (3), active metal material and top electrode layer are deposited sequentially on the resistive switching layer by thermal evaporation deposition, electron beam evaporation deposition or magnetron sputtering deposition.

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