Heat flow control phase change material device with sidewall liner and method for forming the same

Abstract

A method for forming a heat flow controlled phase change material device with sidewall liners includes forming bottom electrodes and heater elements in a dielectric material layer; forming a layer stack of a respective bottom liner, a respective phase change material portion, and a respective top electrode; and forming sidewall liners on the layer stack, wherein each respective combination of a respective one of the bottom electrodes, a respective one of the heater elements, a respective one of the layer stack, and a respective sidewall liner selected from the sidewall liners forms a phase change memory cell, by which a plurality of phase change memory cells is formed. A first subset of the plurality of phase change memory cells is configured to generate a first temperature gradient along a first lateral direction. The disclosure also provides a heat flow controlled phase change material device with sidewall liners formed by the above method.

Description

Technical Field

[0001] This disclosure relates to a method for forming an apparatus structure and an apparatus structure. In particular, this disclosure relates to a method for forming a heat flow controlled phase change material apparatus with sidewall linings and a heat flow controlled phase change material apparatus with sidewall linings. Background Technology

[0002] Phase change material (PCM) devices are suitable for memory-based computing applications due to their scalability and electrical independence. Thermal crosstalk between PCM cells impairs performance and scalability, especially with advancements in device miniaturization. Furthermore, stress-induced reliability issues arising from thermal and mechanical stresses during operation limit the long-term stability of PCM devices. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method for forming a heat flow-controlled phase change material device having sidewall liners is provided, comprising: forming a bottom electrode and a heater element within a dielectric material layer; forming a stack of layers comprising a corresponding bottom liner, a corresponding phase change material portion, and a corresponding top electrode; and forming sidewall liners on the stack of layers, wherein: a corresponding bottom electrode, a corresponding heater element, a corresponding layer in the stack of layers, and each connected combination of the corresponding sidewall liners selected from the sidewall liners constitutes a phase change memory cell. The plurality of phase-change memory cells are configured to form a first temperature gradient along a first lateral direction, wherein the first lateral direction is rotated clockwise by a first azimuth angle from a first horizontal direction at a top-down perspective; and a second subset of the plurality of phase-change memory cells is configured to generate a second temperature gradient along a second lateral direction, wherein the second lateral direction is rotated clockwise by a second azimuth angle from the first horizontal direction at the top-down perspective, the second azimuth angle being different from the first azimuth angle.

[0004] According to some embodiments of this disclosure, a method is provided for forming a heat flow controlled phase change material device having sidewall liners, comprising: forming a bottom electrode and a heater element within a dielectric material layer; forming a processing layer stack comprising a corresponding processing bottom liner, a corresponding processing phase change material portion, and a corresponding processing top electrode; forming a processing sidewall liner on the processing layer stack; and patterning the processing layer stack and the processing sidewall liner, wherein: the patterned portion of the processing layer stack comprises the layer stack; the patterned portion of the processing sidewall liner comprises a sidewall liner; and the phase change material portion within a first subset of the layer stack comprises a corresponding sidewall facing a first outward surface normal direction having an azimuth angle relative to a first horizontal direction measured along a clockwise direction, and further comprising a corresponding additional sidewall facing a horizontal direction and substantially exposed to an surrounding gaseous environment, the horizontal direction being different from the first outward surface normal direction.

[0005] According to some embodiments of this disclosure, an apparatus for forming a heat flow-controlled phase change material with sidewall linings is provided, comprising: phase change memory units, wherein: each of the phase change memory units includes a corresponding layer stack including a bottom lining, a phase change material portion including a phase change material, and a top electrode; a first subset of the phase change memory units is configured to generate a first temperature gradient along a first lateral direction, the first lateral direction being rotated clockwise by a first azimuth angle from a first horizontal direction at a top-down perspective; and a second subset of the plurality of phase change memory units is configured to generate a second temperature gradient along a second lateral direction, the second lateral direction being rotated clockwise by a second azimuth angle from the first horizontal direction at the top-down perspective, the second azimuth angle being different from the first azimuth angle. Attached Figure Description

[0006] The nature of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. For clarity of explanation, the dimensions of the various features may be increased or decreased arbitrarily.

[0007] Figure 1 This is a vertical cross-sectional view of an intermediate embodiment structure after the formation of a field-effect transistor, a metal interconnect structure, and a dielectric material layer, according to one embodiment of the present disclosure.

[0008] Figure 2 This is a vertical cross-sectional view of an intermediate embodiment structure after forming a through-hole cavity through a dielectric material layer, according to one embodiment of the present disclosure.

[0009] Figure 3This is a vertical cross-sectional view of an intermediate embodiment structure after the metal through-hole structure has been formed, according to one embodiment of the present disclosure.

[0010] Figure 4 This is a vertical cross-sectional view of an intermediate embodiment structure after the bottom electrode and heater cavity have been formed, according to one embodiment of the present disclosure.

[0011] Figure 5 This is a vertical cross-sectional view of an intermediate embodiment structure after lateral expansion of the heater cavity, according to one embodiment of the present disclosure.

[0012] Figure 6 This is a vertical cross-sectional view of an intermediate embodiment structure after the heater element has been formed, according to one embodiment of the present disclosure.

[0013] Figure 7 This is a vertical cross-sectional view of an intermediate embodiment structure after forming a continuous layer stack according to one embodiment of the present disclosure. The continuous layer stack includes a bottom liner layer, a phase change material layer containing a phase change material, and a top electrode material layer.

[0014] Figure 8 As an embodiment of the present disclosure, a vertical cross-sectional view is provided of an intermediate embodiment structure after a continuous layer stack is patterned into a processing layer stack, each of the processing layer stacks including a processing bottom liner, a processing phase change material portion, and a processing top electrode.

[0015] Figure 9 This is a vertical cross-sectional view of an intermediate embodiment structure after the formation of a sidewall lining layer, according to one embodiment of the present disclosure.

[0016] Figure 10 This is a vertical cross-sectional view of an intermediate embodiment structure after forming a processing sidewall liner, according to one embodiment of the present disclosure.

[0017] Figure 11 This is a vertical cross-sectional view of an intermediate embodiment structure after the processing layer stack is patterned into a layer stack and the processing sidewall liner is patterned into a sidewall liner, according to one embodiment of the present disclosure. Each layer stack includes a bottom liner, a phase change material portion and a top electrode.

[0018] Figure 12 This is a vertical cross-sectional view of the embodiment structure after removing a patterned etched mask layer, according to one embodiment of the present disclosure.

[0019] Figure 13A – 13C example in Figure 10– During the processing steps of step 12, a sequential top-to-bottom view of a region of a first configuration of the embodiment structure.

[0020] Figure 14A – 14C example in Figure 10 – During the processing steps of step 12, a sequential top-to-bottom view of a region of a second configuration of the embodiment structure.

[0021] Figure 15A – 15C example in Figure 10 – During the processing steps of step 12, a top-to-bottom view of a region of a third configuration of the embodiment structure.

[0022] Figure 16 Example in Figure 10 After the processing steps, a top-down view of a region of a fourth configuration of the embodiment structure.

[0023] Figure 17A – 17C example in Figure 10 – During the processing steps of step 12, the sequential top-to-bottom views of the fifth, sixth, seventh, and eighth configurations of the embodiment structure.

[0024] Figure 18A – 18C example in Figure 10 – During the processing steps of step 12, the top-to-bottom view of the ninth, tenth, eleventh and twelfth configurations of the embodiment structure.

[0025] Figure 19A , 19B 19C and 19D are Figure 12 The horizontal cross-sectional views of the thirteenth, fourteenth, fifteenth and sixteenth configurations of the embodiment structure after the processing steps.

[0026] Figure 20 This is a vertical cross-sectional view of an embodiment of the present disclosure after forming an encapsulated dielectric layer and additional metal interconnect structure.

[0027] Figure 21A – 21D represents an embodiment of this disclosure, showing various configurations of a phase change material portion in various programmed resistance states.

[0028] Figure 22A The following is an example of a sequential vertical cross-sectional view of a phase-change memory cell during programming into a low-resistance state.

[0029] Figure 22B The following is an example of a sequential vertical cross-sectional view of a phase-change memory cell during programming into a first intermediate resistance state.

[0030] Figure 22C The following is an example of a sequential vertical cross-sectional view of a phase-change memory cell during programming into a second intermediate resistance state.

[0031] Figure 22D The following is an example of a sequential vertical cross-sectional view of a phase-change memory cell during programming into a high-resistance state.

[0032] Figure 23 The following is an example of a pair of horizontal and vertical cross-sectional views of eight configurations of a phase-change memory cell according to an embodiment of the present disclosure.

[0033] Figure 24 A diagram showing the unit cell area size for comparing various configurations of the phase-change memory cells disclosed herein.

[0034] Figure 25 This is a vertical cross-sectional view of a first alternative configuration of the embodiment structure after the heater element has been formed, according to an embodiment of the present disclosure.

[0035] Figure 26 This is a vertical cross-sectional view of a first alternative configuration of the embodiment structure after forming the encapsulated dielectric layer and additional metal interconnect structure, according to an embodiment of the present disclosure.

[0036] Figure 27 This is a vertical cross-sectional view of a second alternative configuration of the embodiment structure after the heater element has been formed, according to one embodiment of the present disclosure.

[0037] Figure 28 This is a vertical cross-sectional view of a second alternative configuration of the embodiment structure after forming the encapsulated dielectric layer and additional metal interconnect structure, according to an embodiment of the present disclosure.

[0038] Figure 29 A first flowchart illustrating the general processing steps for manufacturing an apparatus structure, as shown in an embodiment of the present disclosure.

[0039] Figure 30 A second flowchart illustrating the general processing steps for manufacturing an apparatus structure, as shown in an embodiment of the present disclosure.

[0040] Figure 31 A third flowchart illustrating the general processing steps for manufacturing an apparatus structure, as shown in an embodiment of the present disclosure. Detailed Implementation

[0041] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to illustrate this disclosure. These are merely examples and not limitations. The drawings are not to scale. Elements with the same reference numerals refer to the same elements and are assumed to have the same material composition and the same thickness range, unless explicitly indicated otherwise. Unless explicitly disclosed otherwise, all features of an original embodiment are assumed to exist in any derived embodiments. Therefore, features illustrated with reference to relevant embodiments in the drawings and / or this specification support features in an embodiment. Embodiments that repeat multiple instances of any illustrated element are expressly contemplated unless explicitly stated otherwise. Embodiments that omit non-essential elements are expressly contemplated, even if such embodiments are not explicitly disclosed but are known in the art.

[0042] Additionally, for ease of explanation, spatial relative terms such as “under,” “below,” “below,” “above,” “on top,” and similar terms may be used to describe the geometric characteristics of the elements illustrated in the accompanying drawings. Besides the orientations shown in the drawings, these spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly. Unless explicitly indicated otherwise, elements having the same element symbol are assumed to have the same material composition and thickness within the same thickness range.

[0043] Phase-change memory (PCM) devices hold great promise for computation-in-memory (CIM) applications, but also face challenges such as resistance variations, drift between low and high resistance states, and scalability and efficiency limitations due to large cell size, narrow memory windows, and high write power. The various embodiments disclosed in this application address these challenges by incorporating at least one sidewall liner and a bottom liner into the PCM cell design. The sidewall liner can be formed on the sidewalls of the phase-change material portion to control the resistance in the high-resistance state, while the bottom liner can be positioned below the phase-change material and above the heater element. These sidewall and bottom liners can interact with the amorphous volume of the phase-change material to stabilize resistance drift, thereby enabling accurate and reliable weight representation in CIM operations. Additionally, the resistance range can be extended by adjusting the resistivity of the sidewall liner, such as by incorporating nitrogen or carbon atoms into its metallic composition. The designs of the various embodiments disclosed in this case can reduce power consumption, reduce unit size and improve reliability, while providing enhanced performance and efficiency for modern CIM applications.

[0044] The embodiments of this disclosure relate to configurations of phase-change memory (PCM) cells to reduce thermal crosstalk and thermal stress. These embodiments can be used to enhance the reliability and scalability of memory arrays. In one example, the PCM cells of this disclosure reduce thermal crosstalk between adjacent PCM cells. Thermal isolation regions, also known as kick-out zones (KOZs), are used to control heat flow generated during memory cell operation. The thermal isolation regions prevent thermal interference between adjacent PCM cells, thereby improving data integrity and operational reliability.

[0045] Embodiments of this disclosure can be used to provide an adaptive memory cell architecture supporting multi-level memory functionality. Coherent resistance control for the programmed state of a phase-change memory cell can be provided through the directional distribution of heat generated during programmed operation. Phase-change memory cells with different geometries and / or different heat flow directions can be provided in multiple phase-change memory arrays to minimize thermal stress at a single grain level and extend the lifetime of the phase-change memory device. Phase-change memory cells with different heat flow characteristics can be manufactured using the same set of processing steps by modifying the mask pattern used during patterning of the phase-change memory cell. Various embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0046] Reference Figure 1 This illustration depicts an intermediate embodiment structure according to the present disclosure. The intermediate embodiment structure includes a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9 at at least an upper portion of the substrate. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate, or it may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single-crystal semiconductor material, such as single-crystal silicon. In one embodiment, the substrate 8 may include a single-crystal silicon substrate comprising a single-crystal silicon material.

[0047] A shallow trench isolation structure 720, comprising a dielectric material such as silicon oxide, may be formed in an upper portion of the semiconductor material layer 9. Suitable doped semiconductor wells, such as p-type and n-type wells, may be formed in various regions laterally enclosed by a portion of the shallow trench isolation structure 720.

[0048] Semiconductor device 700 may be formed on semiconductor material layer 9. Semiconductor device 700 may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitor structures, etc.). Semiconductor device 700 may include programmable transistors 701 formed in a memory array region 100 and peripheral transistors 702 formed in a peripheral region 300. Each field-effect transistor (701, 702) may include a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. In one embodiment, the channel region may include a portion of semiconductor material layer 9 and may include a single-crystal semiconductor material. Each of the programmable transistors 701 may be configured to provide a set of programmable pulses for a corresponding phase-change memory cell to be subsequently formed. Peripheral transistors 702 may form a component of a peripheral circuit that controls the operation of programmable transistors 701 and interfaces with an input / output (I / O) circuit (not illustrated).

[0049] In one embodiment, substrate 8 may include a monocrystalline silicon substrate, and field-effect transistors (701, 702) may include a corresponding portion of the monocrystalline silicon substrate as a semiconducting channel. As used herein, a "semiconductor" device refers to a device having a 1.0 x 10⁻⁶ ohm diameter. -6 S / cm to 1.0 x 10 5 A component having a conductivity in the range of S / cm. In this context, a "semiconductor material" refers to a component having a conductivity in the range of 1.0 x 10⁻⁶ S / cm when free of electrical dopants. -6 S / cm to 1.0 x 10 5 Conductivity in the range of S / cm, and capable of achieving conductivity from 1.0 S / cm to 1.0 x 10⁻⁶ when appropriately doped with an electrical dopant. 5 A material with a conductivity in the range of S / cm is a doped material.

[0050] Various metal interconnect structures embedded within the dielectric material layer may then be formed over the substrate 8 and the semiconductor device. In one exemplary example, the dielectric material layer may include, for example, a first dielectric material layer 601, which may be a layer surrounding contact structures connected to the source and drain (sometimes referred to as a contact-level dielectric material layer 601); a first interconnect-level dielectric material layer 610; a second interconnect-level dielectric material layer 620; a third interconnect-level dielectric material layer 630; and a fourth interconnect-level dielectric material layer 640. The metal interconnect structure may include a device contact via structure 612 formed in a first dielectric layer 601 and contacting a corresponding component of the semiconductor device 700, a first metal line structure 618 formed in a first interconnect layer dielectric layer 610, a first metal via structure 622 formed in a lower portion of a second interconnect layer dielectric layer 620, a second metal line structure 628 formed in an upper portion of a second interconnect layer dielectric layer 620, a second metal via structure 632 formed in a lower portion of a third interconnect layer dielectric layer 630, and a third metal line structure 638 formed in an upper portion of a third interconnect layer dielectric layer 630. An additional dielectric layer, referred to herein as a lower fourth interconnect layer dielectric layer 641, may be formed above the third interconnect layer dielectric layer 630.

[0051] Each of the dielectric material layers (601, 610, 620, 630, 641) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorinated carbon, or a combination thereof with varying porosity. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638) may include at least one conductive material, which may be a combination of a metal liner (such as a metal nitride or a metal carbide) and a metal filler. The respective metal liners may include TiN, TaN, WN, TiC, TaC, and WC, and the respective metal filler portions may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, their alloys, and / or combinations thereof. In one embodiment, the first metal via structure 622 and the second metal circuit structure 628 may be formed as an integrated circuit and via structure by a dual damascene process. Generally speaking, any combination of a metal circuit structure (628, 638) and at least one underlying metal via structure (622, 632) can form an integrated circuit and via structure.

[0052] Generally, a semiconductor device (such as a field-effect transistor (701, 702)) may be formed on a substrate 8, and metal interconnect structures (612, 618, 622, 628, 632, 638) and dielectric material layers (601, 610, 620, 630, 641) may be formed in the dielectric material layers (601, 610, 620, 630, 641) and may be electrically connected to the semiconductor device.

[0053] In summary, the programmed transistor 701 can be formed on a substrate 8. Metal interconnect structures (612, 618, 622, 628, 632, 638) formed within interconnect-level dielectric material layers (601, 610, 620, 630, 641) can be formed above the programmed transistor 701. The metal interconnect structures (612, 618, 622, 628, 632, 638) can be assembled to electrically connect to the heater elements of the subsequently formed phase-change memory cell.

[0054] According to one aspect of this disclosure, programmable transistors 701 can be configured to program a corresponding phase-change memory cell into at least two different resistance states, more preferably at least three different resistance states, and even more preferably at least four different resistance states. Programming each phase-change memory cell into different resistance states can be achieved by selecting a pulse pattern from a set of pre-programmed pulse patterns applicable to each programmable transistor 701. Pulse patterns can differ from each other by the duration of a pulse pattern and the peak voltage of the pulse pattern. In one embodiment, the total number of resistance states that a phase-change memory cell can be programmed into can range from 2 to 64, such as from 3 to 16 and / or from 4 to 8, although a greater number of resistance states can be programmed by changing the pulse patterns generated by each programmable transistor 701 as needed.

[0055] Reference Figure 2Via cavities 41 can be formed through a dielectric material layer (such as the lower fourth interconnect layer dielectric material layer 641). Each via cavity 41 can be formed above a corresponding one in the underlying metal interconnect structure (such as a subset of the third metal circuit structure 638), thereby exposing the top surface segment of the underlying metal interconnect structure. The dielectric material layer through which the via cavities 41 are formed comprises a heat-resistant dielectric material, such as undoped silicate glass or doped silicate glass. The thickness of the dielectric material layer can range from 200 nm to 1,000 nm, although smaller or larger thicknesses can also be used. The lateral dimensions (such as diameter) of each via cavity 41 can range from 30 nm to 300 nm, although smaller or larger lateral dimensions can also be used. Peripheral via cavities 6411 can be formed through a dielectric material layer in the peripheral region 300.

[0056] Reference Figure 3 A metallic filler material with high electrical conductivity, such as copper or tungsten, may be deposited in the via cavity 41 and the peripheral via cavity 6411. A metallic liner material, such as a conductive metal nitride material, may be optionally deposited as a thin liner prior to the deposition of the metallic filler material. Excess portions of the metallic filler material may be removed above a horizontal plane including the top surface of a dielectric layer (such as the lower fourth interconnect layer dielectric layer 641) by performing a planarization process, which may include a recess etching process and / or a chemical mechanical polishing process. The optional metallic liner material filling a corresponding via cavity 41 and the respective remaining portions of the metallic filler material constitute an in-process bottom electrode 42', which is subsequently modified to become a bottom electrode of a corresponding phase-change memory cell. As used in this application, an "in-process" element refers to an element that is subsequently modified in structure or composition. The remaining portions of the optional metal lining material and the metal filler material that fill a peripheral through-hole cavity 6411 constitute the lower peripheral through-hole structure 6421.

[0057] Reference Figure 4A masking layer 57, such as a patterned photoresist layer, may be formed over a dielectric material layer (such as a lower fourth interconnect layer dielectric material layer 641) to cover the peripheral region 300 but not the memory array region 100. A recessed etching process may be performed to selectively and vertically recess the bottom electrode 42' under processing relative to the material of the dielectric material layer, i.e., without removing the material of the dielectric material layer. The recessed etching process may include a wet etching process or a reactive ion etching process. The upper portion of the bottom electrode 42' under processing may be removed by the recessed etching process. The remaining portion of the bottom electrode 42' under processing constitutes the bottom electrode 42 of the phase change memory cell to be subsequently formed. A heater cavity 47 may be formed in the volume in which the upper portion of the bottom electrode 42' under processing can be removed. The height of the bottom electrode 42 may be from 100 nm to 800 nm, such as in the range of 200 nm to 400 nm, although smaller or larger heights may also be used. The depth of the heater cavity 47 can be from 100 nm to 800 nm, such as in the range of 200 nm to 400 nm, although smaller or larger depths can also be used.

[0058] Reference Figure 5 An isotropic recess etching process can be performed to isotropically recess the solid exposed surface of the dielectric material layer, including the sidewall surfaces of the heater cavity 47 and a planar top surface of the dielectric material layer. For example, in embodiments where the dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) comprises a silicate glass, the isotropic recess etching process may include a wet etching process using diluted hydrofluoric acid. The duration of the isotropic recess etching process can be selected such that the recess distance of the dielectric material layer is between 1 nm and 100 nm, such as in the range of 5 nm to 50 nm, although smaller or larger recess distances may also be used. In this embodiment, the top surface of the dielectric material layer may have a step between the memory array region 100 and the peripheral region 300. In embodiments performing the isotropic recess etching process, the heater cavity 47 may extend laterally. Generally, a metal material subsequently deposited in the heater cavity 47 has a higher resistivity than the metal filler material of the bottom electrode 42. The lateral expansion of heater cavity 47 can be advantageously used to optimize the resistance of the heater element subsequently formed in heater cavity 47. Masking layer 57 can then be removed, for example by ashing.

[0059] Reference Figure 6A metal heater material having a higher conductivity than the metal filler material of the bottom electrode 42 can be deposited in the heater cavity 47. The metal heater material may comprise at least one metal nitride material and / or be substantially composed of it, such as TiN, TaN, WN, and / or MoN. Other suitable metal heater materials are within the scope of this disclosure. The metal heater material can be deposited by chemical vapor deposition or physical vapor deposition. In one embodiment, the metal heater material may comprise a stoichiometric or near-stoichiometric metal nitride material, such as a stoichiometric or near-stoichiometric TiN, TaN, WN, and / or MoN. If the heater cavity 47 has an aspect ratio greater than 1 (i.e., the height-to-width ratio), a conformal deposition process, such as a chemical vapor deposition process, can be used to deposit the metal heater material.

[0060] A planarization process can be performed to remove a portion of the metal heater material deposited above the top surface of the dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) of the embedded bottom electrode 42. The planarization process may include a selective recess etching process that selectively etches the metal heater material relative to the dielectric material of the dielectric material layer. The remaining portions of the metal heater material filling the respective heater cavities 47 constitute a heater element 48. In one embodiment, the top surface of the heater element 48 may be coplanar or substantially coplanar with a portion of the top surface of the dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) located in the memory array region 100.

[0061] For each phase-change memory cell to be formed subsequently, a bottom electrode 42 and a heater element 48 may be formed within a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641). The heater element 48 is electrically connected to an electrical node (i.e., an output node) of a corresponding one of the programmable transistors 701. In one embodiment, a two-dimensional array of a stack of bottom electrodes 42 and heater elements 48 may be formed in the memory array region 100.

[0062] Reference Figure 7 A continuous stack of layers (52L, 54L, 56L) can be sequentially deposited above the top surface of the dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) of the embedded bottom electrode 42 and heater element 48. The stack includes a bottom liner layer 52L, a phase change material layer 54L containing a phase change material, and a top electrode material layer 56L.

[0063] The bottom liner layer 52L comprises a first metal nitride material, which may be a stoichiometric or near-stoichiometric metal nitride material. For example, the bottom liner layer 52L may comprise TaN, TiN, WN, and / or MoN. In one embodiment, the electrical conductivity of the metal material in the bottom liner layer 52L may be from 1.0 x 10⁻⁶. 3 S / cm to 1.0 x 10 5 The thickness of the bottom liner layer 52L is selected such that the patterned portions of the heater liner layer 52L can provide resistance during operation of the subsequently formed phase change memory cell. For example, the thickness of the bottom liner layer 52L can range from 1 nm to 20 nm, such as from 2 nm to 4 nm, although smaller or larger thicknesses can also be used. The bottom liner layer 52L can be deposited by chemical vapor deposition or physical vapor deposition.

[0064] The phase change material layer 54L comprises and / or is substantially composed of a phase change material. As used herein, a “phase change material” refers to a material having at least two distinct phases providing different resistivities. A phase change material (PCM) can be used to store information as a resistivity state of a material, which may be in different resistivity states corresponding to different phases of the material. Different phases may include an amorphous state with high resistivity and a crystalline state with low resistivity (i.e., a lower resistivity than the amorphous state). After an electrical pulse causing the phase change material to become amorphous is applied in a first part of a programmed procedure, the transition between the amorphous and crystalline states can be induced by controlling the cooling rate. A second part of the programmed procedure includes controlling the cooling rate of the phase change material. In embodiments where rapid quenching occurs, the phase change material may be cooled to an amorphous, high-resistivity state. In embodiments where slow cooling occurs, the phase change material may be cooled to a crystalline, low-resistivity state.

[0065] Exemplary phase change materials include, but are not limited to, germanium antimony telluride (GST) compounds such as Ge2Sb2Te5 or GeSb2Te4, germanium antimony compounds, indium germanium telluride compounds, aluminum selenide telluride compounds, indium selenide telluride compounds, and aluminum indium selenide telluride compounds. In one embodiment, the phase change material of the phase change material layer 54L may comprise a doped GST compound, such as N-doped GST, Si-doped GST, C-doped GST, Ge-doped GST, Ru-doped GST, or Al-doped GST, or a doped GeTe compound, such as N-doped GeTe, Si-doped GeTe, C-doped GeTe, or Ge-doped GeTe. The phase change material layer 54L may be deposited by physical vapor deposition. The thickness of the phase change material layer 54L may be in the range from 30 nm to 200 nm, such as from 50 nm to 90 nm, although smaller and larger thicknesses may also be used. In one embodiment, the phase change material of the phase change material layer may be selected such that the conductivity of the amorphous phase of the phase change material is in the range of 1.0 x 10⁻⁶. -8 S / cm to 1.0 x 10 -3 The conductivity of the crystalline phase of the phase change material is in the range of S / cm, while the conductivity of the crystalline phase is in the range of 1.0 x 10⁻⁶. -1 S / cm to 1.0 x 10 3 Range of S / cm.

[0066] The top electrode material layer 56L comprises a metallic material, such as W, Ta, Ti, Mo, WN, TiN, WN, or MoN. The top electrode material layer 56L may have a thickness ranging from 100 nm to 200 nm, although smaller and larger thicknesses are also possible. The top electrode material layer 56L may be deposited by chemical vapor deposition or physical vapor deposition.

[0067] Figure 8 – 19D together illustrate various configurations of phase change memory cells that can be formed on the same substrate 8. Figure 8 , 9 Examples 10, 11, and 12 illustrate phase-change memory cells 50 that can be used to form the contents of this disclosure (see also...). Figure 12 The sequence of processing steps. Figure 13A – 19D illustrates various configurations of phase change memory cells 50 that can be formed on substrate 8. Figure 13A – 19D illustrates sixteen configurations of the phase-change memory cell 50 of this disclosure. According to one embodiment of this disclosure, the structure of this disclosure includes… Figure 13A – At least one of the sixteen configurations illustrated in 19D, and preferably including Figure 13A At least two of the sixteen configurations illustrated in –19D.

[0068] Therefore, the various configurations of the phase-change memory cell 50 disclosed herein do not constitute discrete species that must be manufactured separately, but can be manufactured simultaneously on the same substrate 8. Preferably, two or more of the sixteen configurations of the phase-change memory cell 50 disclosed herein can be manufactured on the same substrate 8 within a single semiconductor die, and the benefits of multiple configurations of the phase-change memory cell 50 can be fully utilized by manufacturing multiple configurations of the phase-change memory cell 50 on the same substrate 8. To reiterate, each configuration selected from the sixteen configurations of the phase-change memory cell 50 may or may not be formed on a substrate 8, provided that at least one configuration of the phase-change memory cell 50 is formed on the substrate 8. Therefore, it is clearly envisioned that a total of 2 16 - One possibility is that each of the sixteen configurations of the phase-change memory cell 50 covering the present disclosure may or may not exist, minus the possibility that none of the sixteen configurations exist. Preferably, embodiments of two or more of the sixteen configurations of the phase-change memory cell 50 are preferred. The number of such instances is 2. 16 – 1 – 16, which is equivalent to the total combination of the presence or absence of each of the 16 configurations, minus the configurations where none of the 16 configurations exist, minus the instances where only a single configuration exists. In an exemplary example, an embodiment of a phase-change memory array is explicitly envisioned, comprising 16 types of phase-change memory arrays, each of which includes a corresponding configuration of phase-change memory cells, wherein each of the 16 configurations of the phase-change memory cells exists within a corresponding cell in the phase-change memory array.

[0069] Figure 13A – 13C example in Figure 10 – During the processing steps of step 12, a sequential top-to-bottom view of a region of a first configuration of the embodiment structure. Figure 14A – 14C example in Figure 10 – During the processing steps of step 12, a sequential top-to-bottom view of a region of a second configuration of the embodiment structure. Figure 15A – 15C example in Figure 10 – During the processing steps of step 12, a top-to-bottom view of a region of a third configuration of the embodiment structure. Figure 16 Example in Figure 10 Following the processing steps, a top-down view of a region of a fourth configuration of the embodiment structure. The fourth configuration can be achieved by etching a second patterned mask layer 79 (which will be referenced later). Figure 11 (Note: This is an example of obtaining the fourth configuration of phase-change memory cell 50 by covering the entire device area.) Figure 17A – 17C example in Figure 10– During the processing steps of step 12, the sequential top-to-bottom views of the fifth, sixth, seventh, and eighth configurations of the embodiment structure. Figure 18A – 18C example in Figure 10 – During the processing steps of step 12, the top-to-bottom view of the ninth, tenth, eleventh and twelfth configurations of the embodiment structure. Figure 19A , 19B 19C and 19D are Figure 12 The horizontal cross-sectional views of the thirteenth, fourteenth, fifteenth and sixteenth configurations of the embodiment structure after the processing steps.

[0070] Reference Figure 8 A first patterning process can be performed to pattern the continuous layer stack (52L, 54L, 56L) into a processing layer stack (52', 54', 56'). Specifically, a first patterned etch mask layer 77 can be formed over the continuous layer stack (52L, 54L, 56L). For example, the first patterned etch mask layer 77 can be formed by applying a photoresist layer over the continuous layer stack (52L, 54L, 56L) and photolithographically patterning the photoresist layer into an array of discrete patterned photoresist material portions. In one embodiment, the first patterned etch mask layer 77 can comprise a two-dimensional array, such as a two-dimensional rectangular periodic array, of patterned photoresist material layer portions located in the memory array region 100. In one embodiment, each patterned photoresist material portion can have a rectangular horizontal cross-sectional shape. In one embodiment, the lateral dimensions of each patterned photoresist material portion can be selected to provide patterning of at least two phase-change memory cells in subsequent processing steps. Alternatively, the lateral dimensions of each patterned photoresist portion can be selected to provide patterning of a single phase-change memory cell in subsequent processing steps.

[0071] A first anisotropic etching process can be performed to etch portions of the continuous layer stack (52L, 54L, 56L) not masked by the first patterned etch mask layer 77. The first anisotropic etching process has an etching chemistry method that selectively etches the material of the continuous layer stack (52L, 54L, 56L) relative to the material of the dielectric material layer of the embedded heater element 48 (such as the lower fourth interconnect level dielectric material layer 641). The continuous layer stack (52L, 54L, 56L) is patterned into an in-process layer stack (52', 54', 56'), each including an in-process bottom liner 52', an in-process phase change material portion 54', and an in-process top electrode 56'. As used herein, an "in-process" element refers to an element whose structure and / or composition are modified in a subsequent processing step. Each in-process bottom liner 52' ​​is a patterned portion of the bottom liner layer 52L. Each processing phase change material portion 54' is a patterned portion of the phase change material layer 54L. Each processing top electrode 56' is a patterned portion of the top electrode material layer 56L. For each processing layer stack (52', 54', 56'), the sidewall of the processing bottom liner 52' ​​may be perpendicularly coincident with the sidewall of the processing phase change material portion 54' and the sidewall of the processing top electrode 56'. In this application, a first surface and a second surface are "perpendicularly coincident," wherein the second surface covers or unders the first surface, and wherein the first surface and the second surface are located in the same vertical plane, which may be planar or curved in a horizontal cross-sectional view. The first patterned etch mask layer 77 may subsequently be removed, for example by ashing or dissolution.

[0072] Reference Figure 9 According to one embodiment of this disclosure, a sidewall liner layer 58L may be deposited on the solid exposed surface of the mid-layer stack (52', 54', 56') and on the solid exposed top surface of the dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641) of the embedded bottom electrode 42 and heater element 48. In one embodiment, the sidewall liner layer 58L may comprise a metal nitride material layer, which is deposited by a conformal deposition process such as a chemical vapor deposition process. In one embodiment, the sidewall liner layer 58L may comprise a second metal nitride material, which may comprise TiN, TaN, WN and / or MoN and / or may be substantially composed of therein. The thickness of the sidewall liner layer 58L may be in the range from 1 nm to 20 nm, such as from 2 nm to 4 nm, although smaller or larger thicknesses may also be used.

[0073] According to one aspect of this disclosure, the electrical conductivity of the second metal nitride material can be reduced by incorporating carbon or nitrogen atoms into the metal nitride material layer through in-situ or out-of-situ doping, i.e., during or after the deposition of the sidewall liner layer 58L. For example, the carbon or nitrogen atoms can be provided by a reactive carbon-containing gas (such as acetylene or ethylene) or a reactive nitrogen-containing gas (such as ammonia) during a chemical vapor deposition of the sidewall liner layer 58L. Alternatively, the sidewall liner layer 58L can be exposed to an environment containing reactive carbon-containing or reactive nitrogen-containing species at a high temperature after the deposition process of the sidewall liner layer 58L. Furthermore, an ion implantation process or a plasma doping process can be performed after the deposition process of the sidewall liner layer 58L.

[0074] Carbon or nitrogen atoms are incorporated into the second metal nitride material of the sidewall liner layer 58L at an atomic concentration such that the conductivity of the doped metal nitride material of the sidewall liner layer 58L after the incorporation of carbon or nitrogen atoms is less than one-third of the conductivity of the second metal nitride material before the incorporation of carbon or nitrogen atoms. In an exemplary example, the conductivity of the sidewall liner layer 58L after the incorporation of carbon or nitrogen atoms can be from 1.0 x 10⁻⁶ 1 S / cm to 1.0 x 10 5 Range of S / cm.

[0075] Generally, in a stoichiometric metal compound MN, where M is Ta, Ti, Mo, or W, the ratio of metal atoms to nitrogen atoms is 1:1. In embodiments using nitrogen doping, when the sidewall liner layer 58L of this disclosure is formed by doping a stoichiometric metal compound with nitrogen atoms, the ratio of metal atoms to nitrogen atoms in the sidewall liner layer 58L can range from 1:1.02 to 1:1.05. In embodiments using carbon doping, when the sidewall liner layer 58L of this disclosure is formed by doping a stoichiometric metal compound with carbon atoms, the ratio of metal atoms to nitrogen atoms to carbon atoms in the sidewall liner layer 58L can range from 1:1:0.02 to 1:1:0.05. Generally, the atomic concentration of added nitrogen atoms in a nitrogen-doped metal nitride material can range from 0.02 times to 0.05 times the atomic concentration of metal atoms. Similarly, the atomic concentration of carbon atoms in carbon-doped metal nitride materials can range from 0.02 times to 0.05 times the atomic concentration of metal atoms.

[0076] In one embodiment, the second metal nitride material of the sidewall liner layer 58L after the doping process may have a conductivity less than 1 / 3, preferably less than 1 / 10, of the conductivity of the first metal nitride material of the bottom liner 52' ​​during processing. In other words, the bottom liner 52' ​​during processing comprises a material having a conductivity at least 3 times, preferably at least 10 times, that of the sidewall liner material of the sidewall liner layer 58L.

[0077] Generally, the first metal nitride material of the bottom liner layer 52L (and the bottom liner 52' ​​under processing) and the second metal nitride material of the sidewall liner layer 58L (which is a doped metal nitride material) are selected such that the resistance of a bottom liner patterned from a bottom liner 52' ​​under processing and the resistance of a sidewall liner patterned from the sidewall liner layer 58L dominate the resistance of the phase change memory cell in a state with high resistance, including a high resistance state and an intermediate resistance state with relatively high resistance. In this embodiment, the resistance of the amorphous volume of a phase change material portion does not determine the resistance of the phase change memory cell in a high resistance state. Therefore, the phase change memory cell can operate without significant degradation caused by any resistance drift of the phase change material.

[0078] Reference Figure 10 An anisotropic etching process can be performed to remove the horizontal extensions of the sidewall liner layer 58L. The anisotropic etching process can selectively target the material of a dielectric layer (such as a lower fourth interconnect layer dielectric layer 641) having a heater element 48 formed therein. The remaining vertical extensions of the sidewall liner layer 58L constitute a processing sidewall liner 58' that laterally surrounds a corresponding processing layer stack (52', 54', 56'). Each processing sidewall liner 58' contacts the processing bottom liner 52', the processing phase change material portion 54', and the processing top electrode 56' of a corresponding processing layer stack (52', 54', 56'). In one embodiment, an upper surface segment of each sidewall of the processing top electrode 56' may be solidly exposed. Generally, a processing sidewall liner 58' can be formed by conformal deposition and anisotropic etching of a layer of sidewall liner material to form a stack around each processing layer (52', 54', 56').

[0079] Reference Figure 11A second patterning process can be performed to pattern the in-process stack (52', 54', 56') and the in-process sidewall liner 58'. A second patterned etch mask layer 79 is formed over the in-process stack (52', 54', 56') and the in-process sidewall liner 58' in a manner that covers a first region of the in-process stack (52', 54', 56') and the in-process sidewall liner 58' but does not cover a second region of the in-process stack (52', 54', 56') and the in-process sidewall liner 58'. For example, a photoresist layer (not shown) can be applied over the in-process stack (52', 54', 56') and the in-process sidewall liner 58' and can be photolithographically patterned into a two-dimensional array of patterned photoresist material portions, such as a rectangular array. In one embodiment, the second patterned etch mask layer 79 may cover at least two discrete regions of each of the processed layer stacks (52', 54', 56') that are not interconnected, i.e., they are separated by a gap not covered by the second patterned etch mask layer 79.

[0080] A second anisotropic etching process can be performed to etch unmasked portions of the intermediate layer stack (52', 54', 56') and the intermediate sidewall liner 58', specifically, to etch portions of the intermediate layer stack (52', 54', 56') and the intermediate sidewall liner 58' that are not masked by the second patterned etch mask layer 79. The second anisotropic etching process has an etching chemistry method that selectively etches the material of the intermediate layer stack (52', 54', 56') and the intermediate sidewall liner 58' relative to the material of the dielectric material layer of the embedded heater element 48 (such as the lower fourth interconnect level dielectric material layer 641).

[0081] In one embodiment, a second patterning process can pattern each connected combination of a processing layer stack (52', 54', 56') and a processing sidewall liner 58' into multiple discrete material portions that are not adjacent to each other. In one embodiment, each patterned portion of a processing layer stack (52', 54', 56') includes a corresponding layer stack comprising a bottom liner 52, a phase change material portion 54, and a top electrode 56. According to one embodiment of this disclosure, each patterned portion of the processing sidewall liner 58' constitutes a sidewall liner 58. A processing layer stack (52', 54', 56') can be patterned into multiple layer stacks (52, 54, 56). A processing sidewall liner 58' can be patterned into multiple sidewall liners 58. For each layer stack (52, 54, 56), the lateral distance between one sidewall of the layer stack (52, 54, 56) and a proximal sidewall of the underlying heater element 48 can be in the range of 30 nm to 200 nm, such as from 50 nm to 150 nm, although smaller or larger lateral distances may also be used.

[0082] Generally, at least one sidewall liner 58 can be formed on a sidewall of each layer stack (52, 54, 56) by depositing and patterning a sidewall liner material, which is a patterned portion of a continuous layer stack (52L, 54L, 56L). The sidewall liner material of at least one sidewall liner 58 comprises a material having a conductivity higher than that of an amorphous phase of the phase change material. The sidewall liner material may comprise a metal nitride material formed by incorporating carbon or nitrogen atoms therein, such that the metal nitride material has a lower conductivity than a stoichiometric metal nitride material. Therefore, in embodiments where a phase change material and an amorphous phase portion of one sidewall liner 58 provide two parallel conductive paths, the sidewall liner 58 provides a lower resistance path and primarily determines the total resistance of the two parallel conductive paths during operation of the phase change memory cell of this disclosure. This state is particularly useful for the operation of phase change memory cells used in computation-in-memory (CIM) applications because the resistivity drift effect of the phase change material is suppressed during the operation of the phase change memory cell.

[0083] Reference Figure 12 The second patterned etched mask layer 79 can be removed, for example, by ashing. A bottom electrode 42, a heater element 48, a bottom liner 52, a phase change material portion 54, a top electrode 56, and at least one sidewall liner 58, in a connected combination, constitute a phase change memory cell 50. A two-dimensional array of phase change memory cells 50 may be provided.

[0084] As discussed above, refer to Figure 8 The first patterning procedure and reference are explained. Figure 11 The second patterning procedure described herein can use various combinations of patterns to provide an array of phase change memory cells 50 with different configurations. Figure 13A –13C is exemplified in Figure 10 – During the processing steps of step 12, a sequential top-to-bottom view of a region of a first configuration of the embodiment structure. Figure 14A – 14C example in Figure 10 – During the processing steps of step 12, a sequential top-to-bottom view of a region of a second configuration of the embodiment structure. Figure 15A – 15C example in Figure 10 – During the processing steps of step 12, a top-to-bottom view of a region of a third configuration of the embodiment structure. Figure 16 A top-down view of a region in a fourth configuration of an illustrative embodiment structure. Figure 17A – 17C example in Figure 10– During the processing steps of step 12, the sequential top-to-bottom views of the fifth, sixth, seventh, and eighth configurations of the embodiment structure. Figure 18A – 18C example in Figure 10 – During the processing steps of step 12, the top-to-bottom view of the ninth, tenth, eleventh and twelfth configurations of the embodiment structure. Figure 19A , 19B 19C and 19D are Figure 12 The horizontal cross-sectional views of the thirteenth, fourteenth, fifteenth and sixteenth configurations of the embodiment structure after the processing steps. Figure 13A – The various configurations illustrated in 19D are merely illustrative of specific configurations and do not limit the scope of this disclosure.

[0085] Common reference Figure 1 – 19D, the bottom electrode 42 and the heater element 48 are formed within a dielectric material layer (such as the lower fourth interconnect level dielectric material layer 641), and an in-process stack (52', 54', 56') of a corresponding in-process bottom liner 52', a corresponding in-process phase change material portion 54', and a corresponding in-process top electrode 56' is formed above the heater element 48. An in-process sidewall liner 58' is formed on the in-process stack (52', 54', 56'), and the in-process stack (52', 54', 56') and the in-process sidewall liner 58' are patterned. The patterned portion of the in-process stack (52', 54', 56') includes a stack (52, 54, 56) of a corresponding bottom liner 52, a corresponding phase change material portion 54, and a corresponding top electrode 56. The patterned portion of the sidewall liner 58' during processing includes the sidewall liner 58. The sidewall liner 58 is formed on the layer stack (52, 54, 56). Each connected combination of a corresponding one of the bottom electrodes 42, a corresponding one of the heater elements, a corresponding one of the layer stack (52, 54, 56), and a corresponding sidewall liner 58 selected from the sidewall liner 58 constitutes a phase change memory cell 50. A plurality of phase change memory cells 50 are formed, which can be configured into a phase change memory array with a corresponding configuration of the phase change memory cells 50 disclosed herein, and a corresponding periodic arrangement.

[0086] Reference Figure 13A ,exist Figure 10A processing step illustrates a region of a first configuration of an embodiment structure including a processing layer stack (52', 54', 56') and a processing sidewall liner 58'. The first configuration may be located within a first device region R1 within the embodiment structure. The processing layer stack (52', 54', 56') may include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2. The second horizontal direction hd2 may be orthogonal to the first horizontal direction hd1.

[0087] Reference Figure 13B This illustrates a region of a first configuration of an embodiment structure after the formation of the second patterned etch mask layer 79 and before the execution of the second anisotropic etching process. The second patterned etch mask layer 79 may comprise a two-dimensional array, such as a 2 x N array, of patterned discrete etch mask material portions (e.g., patterned photoresist material portions) covering 2N segments of the first sidewalls of the processing layer stack (52', 54', 56'). In the illustrated example, the integer N is 4. Generally, the integer N can be any positive integer. As discussed above, the processing layer stack (52', 54', 56') may comprise a first sidewall extending laterally along a first horizontal direction hd1 and a second sidewall extending laterally along a second horizontal direction hd2. The mask material portions of the second patterned etch mask layer 79 extend laterally along the second horizontal direction hd2 and may be laterally spaced from each other along the first horizontal direction hd1.

[0088] Reference Figure 13C For reference Figure 11 The description describes the execution of a second anisotropic etching process. This second anisotropic etching process removes unmasked portions of the processed in-layer stacks (52', 54', 56') not covered by the second patterned etch mask layer 79. Each patterned portion of the processed in-layer stacks (52', 54', 56') comprises a single in-layer stack (52, 54, 56) including a corresponding bottom liner 52, a corresponding phase change material portion 54, and a corresponding top electrode 56. Generally, the plurality of patterned portions of each processed in-layer stack (52', 54', 56') may include at least one row of patterned portions arranged along the first horizontal direction hd1. Figure 13C In the illustrated first configuration, at least one patterned row may comprise two patterned rows of the processing intermediate layer stacks (52', 54', 56'), i.e., two rows of layer stacks (52, 54, 56) constituting a 2 x N array of layer stacks (52, 54, 56). Generally, a P x Q array of the processing intermediate layer stacks (52', 54', 56') can be used, and can be achieved by using... Figure 13A – The first configuration illustrated in 13C is used to form a 2P x QN array of phase change memory cells 50.

[0089] Generally, at least one sidewall liner 58 may be formed on each layer stack (52, 54, 56) within each phase change memory cell 50. In a first configuration, at least one sidewall liner 58 within each phase change memory cell 50 may consist of a single sidewall liner 58 formed directly on one sidewall of the layer stack (52, 54, 56) of the phase change memory cell 50, which is a patterned portion of a continuous layer stack (52L, 54L, 56L).

[0090] Reference Figure 14A ,exist Figure 10 The processing steps illustrate a region of a second configuration of an embodiment structure including two processing layer stacks (52', 54', 56') and two processing sidewall liners 58'. The second configuration may be located within a second device region R2 within the embodiment structure. Each processing layer stack (52', 54', 56') may include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2. The second horizontal direction hd2 may be orthogonal to the first horizontal direction hd1.

[0091] Reference Figure 14B This illustrates a second configuration of the region of the embodiment structure after the formation of the second patterned etch mask layer 79 and before the execution of the second anisotropic etching process. The second patterned etch mask layer 79 may comprise a 1 x N array of patterned discrete etch mask material portions (such as patterned photoresist material portions) covering 2N segments of the first sidewalls of the respective in-process stacks (52', 54', 56'). Each patterned discrete etch mask material portion may comprise a photoresist strip extending laterally along a second horizontal direction hd2 and having a uniform width along a first horizontal direction hd1. In the illustrated example, the integer N is 4. Generally, the integer N can be any positive integer. As discussed above, each in-process stack (52', 54', 56') comprises a first sidewall extending laterally along the first horizontal direction hd1 and a second sidewall extending laterally along the second horizontal direction hd2. The masking material portion of the second patterned etched mask layer 79 extends laterally along the second horizontal direction hd2 and can be laterally spaced from each other along the first horizontal direction hd1.

[0092] Reference Figure 14C For reference Figure 11The description describes the execution of a second anisotropic etching process. This second anisotropic etching process removes unmasked portions of the processed in-layer stacks (52', 54', 56') not covered by the second patterned etch mask layer 79. Each patterned portion of the processed in-layer stacks (52', 54', 56') comprises a single in-layer stack (52, 54, 56) including a corresponding bottom liner 52, a corresponding phase change material portion 54, and a corresponding top electrode 56. Generally, the plurality of patterned portions of each processed in-layer stack (52', 54', 56') may include at least one row of patterned portions arranged along the first horizontal direction hd1. Figure 14C In the illustrated second configuration, at least one patterned row may include a patterned row of the processing intermediate layer stacks (52', 54', 56'), that is, a row of layer stacks (52, 54, 56) constituting a 1 x N array of layer stacks (52, 54, 56). Generally, a P x Q array of the processing intermediate layer stacks (52', 54', 56') can be used, and it can be achieved by using... Figure 14A – The second configuration illustrated in 14C is used to form a P x QN array of phase change memory cells 50.

[0093] Generally, at least one sidewall liner 58 may be formed on each layer stack (52, 54, 56) within each phase change memory cell 50. In a second configuration, at least one sidewall liner 58 within each phase change memory cell 50 may comprise two sidewall liners 58 formed directly on a pair of sidewalls of the layer stack (52, 54, 56) of the phase change memory cell 50, which is a patterned portion of a continuous layer stack (52L, 54L, 56L). The pair of sidewalls may be parallel to each other, and the two sidewall liners 58 are laterally spaced from each other along a horizontal direction such as a second horizontal direction hd2.

[0094] Reference Figure 15A ,exist Figure 10 The processing steps illustrate a region of a third configuration of the embodiment structure, including processing intermediate layer stacks (52', 54', 56') and processing intermediate sidewall liners 58'. This third configuration may be located within a third device region R3 of the embodiment structure. Each processing intermediate layer stack (52', 54', 56') may include a first sidewall parallel to a first horizontal direction hd1 and a second sidewall parallel to a second horizontal direction hd2. The second horizontal direction hd2 may be orthogonal to the first horizontal direction hd1.

[0095] Reference Figure 15BThis illustrates a third configuration of the embodiment structure after the formation of the second patterned etch mask layer 79 and before the execution of the second anisotropic etching process. The second patterned etch mask layer 79 may include a pair of patterned discrete etch mask material portions (such as patterned photoresist material portions) that cover all the second sidewalls of the processing layer stacks (52', 54', 56') and the segments of each first sidewall adjacent to a corresponding second sidewall of the processing layer stacks (52', 54', 56'). Each first sidewall of the processing layer stacks (52', 54', 56') includes a central segment not covered by the second patterned etch mask layer 79. As discussed above, each processing layer stack (52', 54', 56') includes a first sidewall extending laterally along a first horizontal direction hd1 and a second sidewall extending laterally along a second horizontal direction hd2. The two masking material portions of the second patterned etch mask layer 79 extend laterally along the second horizontal direction hd2 and are laterally spaced from each other along the first horizontal direction hd1, so that the central segments of the respective first sidewalls of the processing layer stack (52', 54', 56') are not covered by the second patterned etch mask layer 79.

[0096] Reference Figure 15C For reference Figure 11 The description describes the execution of a second anisotropic etching process. This second anisotropic etching process removes unmasked portions of the processed in-layer stacks (52', 54', 56') not covered by the second patterned etch mask layer 79. Each patterned portion of the processed in-layer stacks (52', 54', 56') comprises a single in-layer stack (52, 54, 56) including a corresponding bottom liner 52, a corresponding phase change material portion 54, and a corresponding top electrode 56. Generally, the plurality of patterned portions of each processed in-layer stack (52', 54', 56') may include at least one row of patterned portions arranged along the first horizontal direction hd1. Figure 15C In the third configuration illustrated, at least one row of the patterned portion may include one row of two patterned portions of the processing layer stacks (52', 54', 56'), that is, one row of the layer stacks (52, 54, 56) constituting a 1 x 2 array of the layer stacks (52, 54, 56). Generally, a P x Q array of the processing layer stacks (52', 54', 56') can be used, and it can be achieved by using... Figure 15A – The third configuration illustrated in 15C is used to form a P x 2Q array of phase change memory cells 50.

[0097] Generally, at least one sidewall liner 58 may be formed on each layer stack (52, 54, 56) within each phase change memory cell 50. In a third configuration, at least one sidewall liner 58 within each phase change memory cell 50 may consist of a single sidewall liner 58 formed directly on the three sidewalls of the layer stack (52, 54, 56) of the phase change memory cell 50, which is a patterned portion of a continuous layer stack (52L, 54L, 56L).

[0098] Reference Figure 16 Examples are shown in Figure 10 The fourth configuration is a fourth configuration of the embodiment structure after the processing steps. The fourth configuration may be located within the fourth device region R4 of the embodiment structure. In the fourth configuration, it is used for... Figure 8 The masking pattern of the first patterned etch mask layer 77 in the processing step is modified so that the pattern of the first patterned etch mask layer 77 is the same as the target pattern of an array of layer stacks (52, 54, 56) for an array of phase-change memory cells 50. In this embodiment, reference is made to... Figure 8 The described first anisotropic etching process directly patterns the continuous stacked layers (52L, 54L, 56L) into an array of stacked layers (52, 54, 56). Additionally, during the execution of the reference... Figure 9 and 10 During the described processing steps, the sidewall lining layer 58L can be directly patterned into the sidewall lining 58. The fourth configuration area of ​​the embodiment structure can be... Figure 11 During the processing steps, the second patterned etch mask layer 79 is completely covered, so that... Figure 11 and 12 During the processing steps, the fourth configuration of the embodiment structure does not change.

[0099] Generally, at least one sidewall liner 58 can be formed on each layer stack (52, 54, 56) within each phase change memory cell 50. In the fourth configuration, at least one sidewall liner 58 within each phase change memory cell 50 can have a ring configuration. In other words, at least one sidewall liner 58 within each phase change memory cell 50 can consist of a single sidewall liner 58 topologically homeomorphic to a ring, i.e., continuously deformable without forming a new hole and without eliminating any pre-existing holes to form a ring. A single sidewall liner 58 can be directly formed on each sidewall of a corresponding layer stack (52, 54, 56), which is a patterned portion of a continuous layer stack (52L, 54L, 56L).

[0100] According to one embodiment of this disclosure, a phase change material portion 54 within a first subset of the stacked layers (52, 54, 56) includes a corresponding sidewall facing a first outward surface normal direction (which may be parallel, antiparallel, or orthogonal to a first horizontal direction hd1 or a second horizontal direction hd2), the first outward surface normal direction having an azimuth angle relative to a first horizontal direction hd1 measured in a clockwise direction, and further includes a corresponding additional sidewall facing a horizontal direction different from the first outward surface normal direction (which may be parallel, antiparallel, or orthogonal to the first horizontal direction hd1 or the second horizontal direction hd2) and the solid being exposed to an surrounding gaseous environment. Examples of such configurations are illustrated in Figure 17A – 17C and 18A – 18C.

[0101] Reference Figure 17A – 17C and 18A – 18C, listed sequentially in Figure 10 – During the processing steps of step 12, the regions of the fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth configurations of the embodiment structure are described. As discussed above, in the same embodiment structure, multiple configurations of the phase-change memory unit 50 can be provided in different device regions. In the exemplary example, Figure 17A – The fifth configuration of the embodiment structure illustrated in 17C can be formed in the fifth device region R5 of the embodiment structure; Figure 17A – The sixth configuration of the embodiment structure illustrated in 17C can be formed in the sixth device region R6 of the embodiment structure; Figure 17A – The seventh configuration of the embodiment structure illustrated in 17C can be formed in the seventh device region R7 of the embodiment structure; and Figure 17A – The eighth configuration of the embodiment structure illustrated in 17C can be formed in the eighth device region R8 of the embodiment structure. Additionally, Figure 18A – The ninth configuration of the embodiment structure illustrated in 18C can be formed in the ninth device region R9 of the embodiment structure; Figure 18A – The tenth configuration of the embodiment structure illustrated in 18C can be formed in the tenth device region R10 of the embodiment structure; Figure 18A – The eleventh configuration of the embodiment structure illustrated in 18C can be formed in the eleventh device region R11 of the embodiment structure; and Figure 18A – The twelfth configuration of the embodiment structure illustrated in 18C can be formed in the twelfth device region R12 of the embodiment structure.

[0102] Figure 17A and 18A Corresponding to reference Figure 10 The processing steps described. Figure 17B and 18B Corresponding to reference Figure 11 The processing steps described. Figure 17C and 18C Corresponding to reference Figure 12 The processing steps described.

[0103] Generally speaking, Figure 17C and 18C The phase-change memory cell 50 illustrated herein is configured to generate a temperature gradient TG along a lateral direction. In this context, a temperature gradient refers to a non-zero rate of temperature change along a specific direction, relating to spatial location. In the context of this disclosure, a temperature gradient along a lateral direction represents the temperature change per unit distance measured along that lateral direction. The direction of the temperature gradient is defined as the direction in which the magnitude of the spatial temperature change is not positive.

[0104] In one embodiment, in Figure 11 After the anisotropic etching process is completed at the processing step, each phase change material portion 54 can be patterned by fully exposing at least one sidewall to the surrounding gaseous or vacuum environment. Asymmetry in thermal conductivity inherently exists between the side of each phase change material portion 54 that is in direct contact with the sidewall liner 58 and the other side of each phase change material portion 54 that has a solidly exposed sidewall. The temperature gradient TG generated by the phase change memory cell 50 generally runs from the sidewall with a solidly exposed sidewall to the sidewall with the sidewall liner 58. If more than one sidewall of the phase change material portion 54 is solidly exposed and / or if more than one sidewall of the phase change material portion 54 is in contact with a sidewall liner 58, the direction of the temperature gradient TG depends on the geometry and can generally be oriented from a first lateral direction without the sidewall liner 58 to a second lateral direction with the sidewall liner 58.

[0105] In one embodiment, a first subset of phase change memory cells 50 is configured to generate a first temperature gradient TG along a first lateral direction. In one embodiment, the first lateral direction is rotated clockwise by a first azimuth angle α1 from a first horizontal direction hd1 at a top-down perspective. As discussed above, the first horizontal direction hd1 may be parallel to a subset of the sidewalls of the phase change material portion 54 and / or along a periodic direction of the phase change memory cells 50. In one embodiment, a second subset of phase change memory cells 50 is configured to generate a second temperature gradient TG along a second lateral direction, which is rotated clockwise by a second azimuth angle α2 from the first horizontal direction hd1 at a top-down perspective, the second azimuth angle α2 being different from the first azimuth angle α1.

[0106] exist Figure 17C and 18CIn the example illustrated, phase-change memory (PCM) units 50 in the fifth device region R5, a subset of PCM units 50 in the ninth device region R9, and a subset of PCM units 50 in the tenth device region R10 are configured to generate a first temperature gradient TG along a first lateral direction, which is rotated clockwise by a first azimuth angle α1 from the first horizontal direction hd1 from a top-down perspective. PCM units 50 in the sixth device region R6, a subset of PCM units 50 in the ninth device region R9, and a subset of PCM units 50 in the twelfth device region R12 are configured to generate a second temperature gradient TG along a second lateral direction, which is rotated clockwise by a second azimuth angle α2 from the first horizontal direction hd1 from a top-down perspective. Phase change memory (PCM) units 50 in the seventh device region R7, a subset of PCM units 50 in the eleventh device region R11, and a subset of PCM units 50 in the twelfth device region R12 are configured to generate a second temperature gradient TG along a third lateral direction, which is rotated clockwise by a third azimuth angle α3 from the first horizontal direction hd1 from a top-down perspective. Phase change memory (PCM) units 50 in the eighth device region R8, a subset of PCM units 50 in the tenth device region R10, and a subset of PCM units 50 in the eleventh device region R11 are configured to generate a fourth temperature gradient TG along a fourth lateral direction, which is rotated clockwise by a fourth azimuth angle α4 from the first horizontal direction hd1 from a top-down perspective. In one embodiment, the second horizontal direction hd2 is orthogonal to the first horizontal direction hd1, and the first lateral direction, the second lateral direction, the third lateral direction, and the fourth lateral direction are not parallel to or orthogonal to any of the first horizontal direction hd1 and the second horizontal direction hd2.

[0107] In one embodiment, the phase change material portion 54 within a first subset of the layer stacks (52, 54, 56) includes a corresponding sidewall facing a first outward surface normal direction (which may be parallel, antiparallel, or orthogonal to a first horizontal direction hd1 or a second horizontal direction hd2), the first outward surface normal direction having a third azimuth angle relative to the first horizontal direction hd1 measured in a clockwise direction. In this embodiment, the phase change material portion 54 within a second subset of the layer stacks (52, 54, 56) includes a corresponding sidewall facing a second outward surface normal direction, the second outward surface normal direction having a fourth azimuth angle relative to the first horizontal direction hd1 measured in the clockwise direction, and does not include any sidewall facing a third horizontal direction. As used herein, the "outward surface normal direction" of a surface refers to a direction that is normal (i.e., orthogonal) to the surface and points outward.

[0108] In one embodiment, each sidewall liner 58 in a first subset of the phase-change memory cells 50 has a first horizontal cross-sectional shape; and each sidewall liner 58 in a second subset of the phase-change memory cells 50 has a second horizontal cross-sectional shape that is not translationally identical to the first horizontal cross-sectional shape. In this application, if the first two-dimensional shape can be positioned to provide a periphery identical to that of the second two-dimensional shape solely by translation—that is, without rotation, reflection, or any scaling—then the first two-dimensional shape is translationally identical to the second two-dimensional shape. In cases where the first two-dimensional shape cannot be positioned to provide a periphery identical to that of the second two-dimensional shape solely by translation, the first two-dimensional shape is not translationally identical to the second two-dimensional shape.

[0109] In the illustrated example, the sidewall liner 58 in the fifth device region R5 is not translationally identical to any of the sidewall liners 58 in the sixth device region R6, the seventh device region R7, or the eighth device region R8. Furthermore, each of the ninth device region R9, the tenth device region R10, the eleventh device region R11, and the twelfth device region R12 contains a corresponding first-type sidewall liner 58, which is not translationally identical to the corresponding second-type sidewall liner 58.

[0110] In one embodiment, each of the phase-change memory cells 50 includes a corresponding phase-change material portion 54 formed with a sidewall parallel to the first horizontal direction hd1. In one embodiment, the second horizontal cross-sectional shape is mirror-symmetrical with respect to a vertical plane parallel to or orthogonal to the first horizontal direction hd1. In this application, the first two-dimensional shape is mirror-symmetrical to a second two-dimensional shape if the second two-dimensional shape is a mirror image of any shape derived from the translation of the first two-dimensional shape without any rotation or scaling of the first two-dimensional shape. For example, each of the ninth device region R9 and the tenth device region R10 includes a first-type sidewall liner 58 having a corresponding first horizontal cross-sectional shape, and a second-type sidewall liner 58 having a corresponding second horizontal cross-sectional shape mirror-symmetrical to the first horizontal cross-sectional shape.

[0111] In one embodiment, when rotated relative to a vertical direction, the second horizontal cross-sectional shape is rotationally identical to the first horizontal cross-sectional shape. In this application, if the second two-dimensional shape can be obtained by translating and rotating the first two-dimensional shape, then the first two-dimensional shape and the second two-dimensional shape are rotationally identical without any mirroring or scaling. For example, each of the eleventh device region R11 and the twelfth device region R12 includes a first-type sidewall liner 58 having a corresponding first horizontal cross-sectional shape, and a second-type sidewall liner 58 having a corresponding second horizontal cross-sectional shape that is rotationally identical to the first horizontal cross-sectional shape.

[0112] In one embodiment, a first subset of phase-change memory cells 50 comprises rows of first-type phase-change memory cells 50. Each row of the first-type phase-change memory cells 50 comprises a corresponding subset of first-type phase-change memory cells 50 configured along a second horizontal direction hd2, different from the first horizontal direction hd1. In one embodiment, a second subset of phase-change memory cells 50 comprises rows of second-type phase-change memory cells 50. Each row of the second-type phase-change memory cells 50 comprises a corresponding subset of second-type phase-change memory cells 50 configured along the second horizontal direction hd2. The rows of first-type and second-type phase-change memory cells 50 are staggered along the first horizontal direction hd1, as shown below. Figure 18C Examples are given in the ninth zone R9, tenth zone R10, eleventh zone R11, and twelfth zone R12.

[0113] In one embodiment, the phase change material portion 54 within a first subset of the layer stacks (52, 54, 56) includes a corresponding sidewall facing a first outward surface normal direction (which may be parallel or antiparallel to a first horizontal direction or parallel or antiparallel to a second horizontal direction), the first outward surface normal direction having an azimuth angle relative to a first horizontal direction hd1 measured in a clockwise direction (which may be an integer multiple of π / 2, e.g., 0, π / 2, π, or 3π / 2). In one embodiment, the phase change material portion 54 within the first subset of the layer stacks (52, 54, 56) further includes a horizontally oriented portion substantially exposed to a gaseous surrounding environment, i.e., in reference... Figure 12 The described processing steps include a corresponding additional sidewall that does not directly contact any solid material portion, and this horizontal direction differs from the normal direction of the first outward surface. All such exposed surfaces of the solid are in direct contact with an encapsulated dielectric layer that will subsequently be deposited.

[0114] In one embodiment, an additional phase change material portion 54 within a second subset of the layer stack (52, 54, 56) includes a corresponding sidewall facing a second outward surface normal direction (which may be parallel or antiparallel to a first horizontal direction or parallel or antiparallel to a second horizontal direction), the second outward surface normal direction having an additional azimuth angle relative to a first horizontal direction hd1 measured in a clockwise direction, and not including any sidewall facing the horizontal direction of the first horizontal sidewall.

[0115] In one exemplary example, the phase change material portion 54 within the first subset of phase change memory cells 50 in the ninth device region R9 may include a corresponding sidewall facing the second horizontal direction hd2 (which is the first outward surface normal direction), and an additional phase change material portion 54 within the second subset of phase change memory cells in the ninth device region R9 may include a corresponding sidewall facing the opposite direction (which is the second outward surface normal direction) of the second horizontal direction hd2. In another exemplary example, the phase change material portion 54 within the first subset of phase change memory cells 50 in the tenth device region R10 may include a corresponding sidewall facing the first horizontal direction hd1 (which is the first outward surface normal direction), and an additional phase change material portion 54 within the second subset of phase change memory cells in the tenth device region R10 may include a corresponding sidewall facing the opposite direction (which is the second outward surface normal direction) of the first horizontal direction hd1.

[0116] In one embodiment, a first subset of the stacked layers (52, 54, 56) is configured to generate a first temperature gradient TG along a first lateral direction, the first lateral direction being rotated clockwise by a first azimuth angle α1 from a top-down perspective from a first horizontal direction hd1; and a second subset of the stacked layers (52, 54, 56) is configured to generate a second temperature gradient TG along a second lateral direction, the second lateral direction being rotated clockwise by a second azimuth angle α2 from the first horizontal direction hd1 from a top-down perspective, the second azimuth angle α2 being different from the first azimuth angle α1.

[0117] In one embodiment, each sidewall liner 58 in a first subset of the layer stacks (52, 54, 56) has a first horizontal cross-sectional shape; and each sidewall liner 58 in a second subset of the layer stacks (52, 54, 56) has a second horizontal cross-sectional shape that is not translated identically to the first horizontal cross-sectional shape.

[0118] Figure 19A , 19B 19C and 19D are Figure 12 The horizontal cross-sectional views are shown for the thirteenth, fourteenth, fifteenth, and sixteenth configurations of the embodiment structure after the processing steps. The horizontal cross-sectional views are obtained at the layer level of the phase change material portion 54. Thus, the sidewall liner 58 of the phase change memory cell 50 is also illustrated. The keep-out zone (KOZ) is also illustrated, referring to the area where the heater element 48 and bottom electrode 42 are excluded. In other words, the heater element 48 and bottom electrode 42 are not present in the keep-out zone. The direction of heat flow during programmed operation is indicated by arrows, with the head of the arrow pointing in the direction of heat flow (outward and away from the sidewall liner 58). Each phase change material portion 54 includes a contact area 59, which is a surface portion of the phase change material portion 54 that directly contacts the sidewall liner 58.

[0119] Reference Figure 19A Example: A thirteenth device region R13 includes an array of phase change memory cells 50 having a thirteenth configuration. The thirteenth device region R13 may be one of the regions within the structure of the embodiments disclosed herein. In the thirteenth configuration, a single sidewall liner 58 laterally encapsulates a corresponding phase change material portion 54. In this embodiment, 100% of the overall sidewall of each phase change material portion 54 is contacted by a sidewall liner 58.

[0120] Reference Figure 19B Example: A fourteenth device region R14, which includes an array of phase change memory cells 50 having a fourteenth configuration. The fourteenth device region R14 may be one of the regions within the structure of the embodiments disclosed herein. In the fourteenth configuration, no sidewall liner 58 is provided. Therefore, 0% of the overall sidewall of each phase change material portion 54 is contacted by a sidewall liner.

[0121] Reference Figure 19C Example: A fifteenth device region R15, comprising an array of phase change memory cells 50 having a fifteenth configuration. The fifteenth device region R15 may be one of the regions within the structure of the embodiments disclosed herein. In the fifteenth configuration, two sidewall liners 58 may be formed on the sidewalls of a phase change material portion 54. Heat flow may primarily occur along a first horizontal direction hd1 orthogonal to the interface between the phase change material portion 54 and the sidewall liners 58. The ratio of the total contact area between each phase change material portion 54 and the sidewall liners 58 to the total area of ​​the sidewalls of the phase change material portion 54 may range from 0.2 to 0.9, although smaller or larger fractions may also be used.

[0122] Reference Figure 19D Example: A sixteenth device region R16 includes an array of phase change memory cells 50 having a sixteenth configuration. The sixteenth device region R16 may be one of the regions within the structure of the embodiments disclosed herein. In the sixteenth configuration, a sidewall liner 58 may be formed on a sidewall of a phase change material portion 54. Heat flow may be unidirectional and may be parallel or antiparallel to a first horizontal direction hd1, which is orthogonal to the interface between the phase change material portion 54 and the sidewall liner 58. The ratio of the total contact area between each phase change material portion 54 and a sidewall liner 58 to the total area of ​​the sidewall of the phase change material portion 54 may range from 0.1 to 0.45, although smaller or larger fractions may also be used.

[0123] Common reference Figure 1– 19D, an in-process stack (52', 54', 56') of a corresponding in-process bottom liner 52', a corresponding in-process phase change material portion 54', and a corresponding in-process top electrode 56' may be formed above a dielectric material layer, and an in-process sidewall liner 58' may be formed on the in-process stack (52', 54', 56'). The in-process stack (52', 54', 56') and the in-process sidewall liner 58' are patterned to form a phase change memory cell 50. The patterned portion of the in-process stack (52', 54', 56') includes the stack (52, 54, 56). The patterned portion of the in-process sidewall liner 58' includes the sidewall liner 58. A phase change memory cell 50 is formed, comprising a connected combination of one corresponding portion of the stack (52, 54, 56) and a corresponding subset of the sidewall liner 58. Each of the phase change memory cells 50 includes a corresponding layer stack (52, 54, 56) comprising a bottom liner 52, a phase change material portion 54 containing a phase change material, and a top electrode 56, with at least one sidewall liner 58 located on at least one sidewall of the layer stack (52, 54, 56). In one embodiment, for each phase change memory cell 50 within a first subset of the phase change memory cells 50, the ratio of the total contact area between the phase change material portion 54 and at least one sidewall liner 58 to the total sidewall area of ​​the phase change material portion 54 has a first fraction; and for each phase change memory cell 50 within a second subset of the phase change memory cells 50, the ratio of the total contact area between the phase change material portion 54 and at least one sidewall liner 58 to the total sidewall area of ​​the phase change material portion 54 has a second fraction, which differs from the first fraction. The stress direction caused by the heat flow is the same as the heat flow direction and the same as the temperature gradient caused by the heat flow.

[0124] Reference Figure 20An encapsulated dielectric layer 643 and additional metal interconnect structures (62, 6422, 648) may be formed above the phase-change memory cell 50. The encapsulated dielectric layer 643 includes at least one interlayer dielectric material, such as silicon oxide, silicon nitride, and / or silicon carbide nitride. The additional metal interconnect structures (62, 6422, 648) may include a top contact via structure 62 that contacts a top surface of a corresponding one of the top electrodes 56; an upper peripheral via structure 6422 formed on a lower peripheral via structure 6421; and a fourth metal circuit structure 648 formed on the top contact via structure 62 and the upper peripheral via structure 6422. The top surface of the fourth metal circuit structure 648 may be coplanar with the horizontal top surface of the encapsulated dielectric layer 643. The encapsulated dielectric layer 643 constitutes an upper fourth interconnect level dielectric material layer. The combination of the lower fourth interconnect dielectric layer 641 and the encapsulating dielectric layer 643 constitutes a fourth interconnect dielectric layer 640. Additional dielectric layers (not shown) and additional metal interconnect structures can be formed to provide electrical connections between the top electrode 56 of the phase-change memory cell 50 and various semiconductor devices 700 covered by the dielectric layers (601, 610, 620, 630, 640).

[0125] Generally, a programmable transistor 701 may be disposed on a substrate 8. Metal interconnect structures (612, 618, 622, 628, 632, 638, 42, 6421) embedded within interconnect-level dielectric layers (601, 610, 620, 630, 641) may be formed above the programmable transistor 701. A bottom electrode 42 and a heater element 48 may be formed within a dielectric layer, such as a lower fourth interconnect-level dielectric layer 641. Each heater element 48 is electrically connected to an electrical node of the corresponding programmable transistor 701, such as an output node. A continuous stack of layers (52L, 54L, 56L) comprising a bottom liner layer 52L, a phase change material layer 54L including a phase change material, and a top electrode material layer 56L can be deposited and patterned to form a stack of layers (52, 54, 56) comprising a bottom liner 52, a phase change material portion 54, and a top electrode 56. A sidewall liner layer 58L can be formed and patterned to form a sidewall liner 58. At least one sidewall liner 58 can be formed on at least one sidewall of each stack of layers (52, 54, 56).

[0126] Each sidewall liner 58 comprises a material having an electrical conductivity of an amorphous phase of the phase change material higher than that of the phase change material portion 54. For each phase change memory cell 50, an encapsulating dielectric layer 643 may be directly deposited on at least one sidewall of the layer stack (52, 54, 56) (which is a patterned portion of a continuous layer stack (52L, 54L, 56L)), directly deposited on an outer sidewall of each of the at least one sidewall liners 58, and directly deposited on a top surface of the layer stack (52, 54, 56). Thus, for each phase change memory cell 50, the encapsulating dielectric layer 643 is in contact with at least one sidewall of the layer stack, an outer sidewall of each of the at least one sidewall liners 58, and a top surface of the layer stack (52, 54, 56).

[0127] For each phase change memory cell 50 electrically connected to a programmable transistor 701, the programmable transistor 701 is configured to program the phase change memory cell 50 into at least three different resistance states by applying at least three different programmable pulse patterns to the heater element 48. Figure 18A – 18D represents an embodiment of the present disclosure, showing various configurations of a phase change material portion 54 in various programmed resistance states.

[0128] Reference Figure 21A An example is illustrated of a phase change memory cell 50 in a low-resistance state. In this embodiment, at least 99% of the entire volume of the phase change material portion 54 is in a polycrystalline phase. In one embodiment, the entire phase change material portion 54 may be a crystalline phase change material portion 54C comprising a polycrystalline phase change material. The conductivity of the crystalline phase change material is higher than that of the materials of the bottom liner 52 and at least one sidewall liner 58. Therefore, the main conductive path extends vertically between the heater element 48 and the top electrode 56.

[0129] Reference Figure 21B An example is a phase change memory cell 50 in a first intermediate state. In this embodiment, the phase change material portion 54 includes a first volume having an amorphous phase and a second volume having a crystalline phase. The first volume includes an amorphous phase change material portion 54A, and the second volume includes a crystalline phase change material portion 54C. The first volume is not in direct contact with at least one sidewall liner 58. The conductivity of the amorphous phase change material is lower than that of the materials of the bottom liner 52 and at least one sidewall liner 58. Therefore, the main conductive path extends laterally into the bottom liner 52 beneath the amorphous phase change material portion 54A and extends at an angle relative to the vertical direction through the crystalline phase change material portion 54C between the peripheral portion of the bottom liner 52 and the top electrode 56.

[0130] Reference Figure 21CAn example is a phase change memory cell 50 in a second intermediate state providing a higher resistance than the first intermediate state. In this embodiment, the phase change material portion 54 includes a first volume having an amorphous phase and a second volume having a crystalline phase. The first volume includes an amorphous phase change material portion 54A, and the second volume includes a crystalline phase change material portion 54C. The first volume is in direct contact with at least one sidewall liner 58 but not with the top electrode 56. The conductivity of the amorphous phase change material is lower than that of the materials of the bottom liner 52 and at least one sidewall liner 58. Therefore, the main conductive path extends laterally inside the bottom liner 52 beneath the amorphous phase change material portion 54A, extends vertically through a lower portion of each sidewall liner 58, and extends at an angle relative to the vertical direction through the crystalline phase change material portion 54C between an intermediate portion of each sidewall liner 58 and the top electrode 56.

[0131] Reference Figure 21D Example: A phase change memory cell 50 is shown in a high-resistivity state. In this embodiment, at least 99% of the entire volume of the phase change material portion 54 is in an amorphous phase.

[0132] although Figure 21A – 21D illustrates four resistance states of a phase change memory cell 50, but the pulse pattern of a programmed pulse from a programmed transistor 701 can be preprogrammed to self-store multiple programmed pulse pattern selections in a programmable circuit for the phase change memory cell 50. The total number of preprogrammed pulse patterns can range from 2 to 210, such as from 3 to 28 and / or from 4 to 26. The total number of programmable resistance states in each phase change memory cell 50 can be the same as the total number of preprogrammed pulse patterns. In one embodiment, each programmed transistor 701 can be configured to apply at least four different programmed pulse patterns to a corresponding heater element 48. The programmed pulse may have a corresponding duration and / or voltage ramp-down rate to provide a controlled cooling rate for a molten region of a phase change material portion 54. The duration of programmed pulses can range from 10 nanoseconds to 500 nanoseconds, with longer programmed pulses generally corresponding to the formation of large crystalline regions in the phase change material portion 54.

[0133] Figure 22AThe diagram illustrates sequential vertical cross-sectional views of a phase change memory cell 50 during programming into a low resistance state (LRS). In this illustrative example, an initial state of a phase change memory cell 50 may be a low resistance state, wherein the phase change material portion 54 is composed of a crystalline phase change material portion 54C. A programming pulse PP_S may be applied to convert the entire phase change material portion 54 into a molten phase change material portion 54M. The programming pulse PP_S slopes slowly (e.g., with a pulse slope time in the range of 10 nanoseconds to 1 microsecond) to induce crystallization of the molten phase change material portion 54M. When the programming operation is complete, the entire molten phase change material portion 54M is converted into a crystalline phase change material portion 54C.

[0134] Figure 22B The diagram illustrates sequential vertical cross-sectional views of a phase change memory cell 50 during programming into a first intermediate resistance state (IRS1). In this illustrative example, an initial state of a phase change memory cell 50 may be a low resistance state, wherein the phase change material portion 54 consists of a crystalline phase change material portion 54C. A first intermediate programming pulse PP_I1 may be applied to convert a small portion of the phase change material portion 54 into a molten phase change material portion 54M. The magnitude of the first intermediate programming pulse (i.e., current and / or voltage) may be selected to limit the volume of the phase change material portion 54 converted into the molten phase change material portion 54M. The first intermediate programming pulse PP_I1 terminates rapidly (e.g., with a pulse ramp time of less than 1 ns) to induce rapid quenching of the molten phase change material portion 54M. When the programming operation is complete, the molten phase change material portion 54M is converted into a small amorphous phase change material portion 54A. The phase change material portion 54 comprises a combination of a small amorphous phase change material portion 54A and a residual crystalline phase change material portion 54C.

[0135] Figure 22CThe illustration shows sequential vertical cross-sectional views of a phase change memory cell 50 during programming into a second intermediate resistance state (IRS2). In this illustrative example, an initial state of a phase change memory cell 50 may be a low resistance state, wherein the phase change material portion 54 consists of a crystalline phase change material portion 54C. A second intermediate programming pulse PP_I2 may be applied to convert a large portion of the phase change material portion 54 into a molten phase change material portion 54M. The magnitude of the second intermediate programming pulse (i.e., current and / or voltage) may be selected to increase the volume of the phase change material portion 54 converted into the molten phase change material portion 54M, relative to the volume of the molten phase change material portion 54M formed after the application of the second intermediate programming pulse PP_I2. The second intermediate programming pulse PP_I2 terminates rapidly (e.g., with a pulse ramp time of less than 1 ns) to induce rapid quenching of the molten phase change material portion 54M. When the programmed operation is complete, the molten phase change material portion 54M is converted into a large amorphous phase change material portion 54A. The phase change material portion 54M comprises a combination of the large amorphous phase change material portion 54A and a residual crystalline phase change material portion 54C.

[0136] Figure 22D The diagram illustrates sequential vertical cross-sectional views of a phase change memory cell 50 during programming into a high resistance state (HRS). In this illustrative example, an initial state of a phase change memory cell 50 may be a low resistance state, wherein the phase change material portion 54 consists of a crystalline phase change material portion 54C. A reset programming pulse PP_R may be applied to convert the entire phase change material portion 54 into a molten phase change material portion 54M. The reset programming pulse PP_R is rapidly terminated (e.g., with a pulse ramp time of less than 1 ns) to induce rapid quenching of the molten phase change material portion 54M. The molten phase change material portion 54M is converted into an amorphous phase change material portion 54A, which constitutes the entire phase change material portion 54.

[0137] Reference Figure 23 Various configurations of a phase-change memory cell (a), (b), (c), (d), (e), (f), (g), and (h) are illustrated using pairs of horizontal and vertical cross-sectional views. Each vertical cross-sectional view is taken along a vertical plane V – V' shown in the corresponding horizontal cross-sectional view. Each horizontal cross-sectional view is taken along a horizontal plane H – H' shown in the corresponding vertical cross-sectional view. Each of the phase-change memory cells 50 can function as a repeating unit in a two-dimensional periodic array of phase-change memory cells 50. A unit cell UC that functions as a repeating unit in such a two-dimensional periodic array is illustrated for each configuration. Additionally, an exclusion zone (KOZ) is also illustrated for each configuration. Arrows indicate the direction of heat flow during a programmed operation.

[0138] Reference Figure 24 A comparison in one picture Figure 24 The unit cell region sizes of various configurations of the phase-change memory cell 50 illustrated herein are shown. The unit cell region may be equal to the sum of a first region A_LS, a second region A_KOZ, and a third region A_B. The first region A_LS is a combination of a single-layer stack (52, 54, 56) and at least one sidewall liner 58. The second region A_KOZ is the exclusion region. The third region A_B is a buffer region adjacent to the exclusion region. Additional metal structures (such as metal via structures) are permitted in the buffer region. Generally, a compact design layout with a small buffer region tends to exhibit high thermal stress while providing a high device density, while a relaxed design layout with a larger buffer region reduces thermal stress while providing a low device density.

[0139] See Figure 25 A first alternative configuration of the embodiment structure is illustrated after the formation of heater element 48. In the first alternative configuration, references may be omitted. Figure 5 The described processing steps. In this embodiment, each heater element 48 may have the same lateral dimensions as the corresponding underlying bottom electrode 42. The sidewall of each heater element 48 may be perpendicularly coincident with the sidewall of the corresponding underlying bottom electrode 42, that is, may be located in the same vertical plane as the sidewall of the corresponding underlying bottom electrode 42.

[0140] Reference Figure 26 , refer to Figure 7 – The processing steps described in 20 can be performed on a first alternative configuration of the embodiment structure to provide an array of phase change memory cells 50.

[0141] Reference Figure 27 This illustrates a second alternative configuration of the embodiment structure, which can be derived from this by using a chemical mechanical polishing process to remove a portion of the metal filler material overlying the dielectric material layer of the embedded bottom electrode 42. Figure 6 The illustrated embodiment structure. In this embodiment, the entire top surface of the dielectric material layer of the embedded bottom electrode 42 can be formed in a horizontal plane. In other words, the top surface of the dielectric material layer can be formed without any steps. The top surface of the heater element 48 can be formed in the same horizontal plane as the top surface of the dielectric material layer of the embedded heater element 48.

[0142] Reference Figure 28 , refer to Figure 7 – The processing steps described in 17 can be performed on a second alternative configuration of the embodiment structure to provide an array of phase change memory cells 50.

[0143] Integrated reference Figure 1– 28. According to various embodiments of the present disclosure, an apparatus structure is provided that includes phase change memory units 50, wherein: each of the phase change memory units 50 includes a corresponding layer stack (52, 54, 56) including a bottom liner 52, a phase change material portion 54 including a phase change material and a top electrode 56; and a first subset of the phase change memory units 50 is configured to generate a first temperature gradient TG along a first lateral direction.

[0144] In one embodiment, a first lateral direction is rotated clockwise by a first azimuth angle α1 from a top-down perspective from a first horizontal direction hd1; and a second subset of phase change memory units 50 is configured to generate a second temperature gradient TG along a second lateral direction, the second lateral direction being rotated clockwise by a second azimuth angle α2 from the first horizontal direction hd1 from a top-down perspective, the second azimuth angle α2 being different from the first azimuth angle α1.

[0145] In one embodiment, a phase change material portion 54 within a first subset of the stacked layers (52, 54, 56) of the phase change memory cell 50 includes a corresponding first sidewall facing a first outward surface normal direction (which may be parallel, antiparallel, or orthogonal to a first horizontal direction hd1 or a second horizontal direction hd2), the first outward surface normal direction having a third azimuth angle relative to the first horizontal direction hd1 measured in a clockwise direction; and a phase change material portion 54 within a second subset of the stacked layers (52, 54, 56) of the phase change memory cell 50 includes a corresponding second sidewall facing a second outward surface normal direction, the second outward surface normal direction having a fourth azimuth angle relative to the first horizontal direction hd1 measured in a clockwise direction, and does not include any sidewall facing a third horizontal direction.

[0146] In one embodiment, a corresponding first sidewall contacts a corresponding first sidewall liner 58; the corresponding second sidewall contacts a corresponding second sidewall liner 58; the bottom liner 52 of the phase change material unit 50 includes a first conductive material having a first conductivity; and the first sidewall liner 58 and the second sidewall liner 58 of the phase change material unit 50 include a second conductive material having a second conductivity less than the first conductivity.

[0147] In one embodiment, each sidewall liner 58 in a first subset of the phase change memory cells 50 has a first horizontal cross-sectional shape; and each sidewall liner 58 in a second subset of the phase change material cells 50 has a second horizontal cross-sectional shape that is not translationally congruent to the first horizontal cross-sectional shape. In other words, the second horizontal cross-sectional shape may not be matched to the first horizontal cross-sectional shape by any type of linear translation only along any horizontal direction. The second horizontal cross-sectional shape may or may not be rotationally congruent to the first horizontal cross-sectional shape. The second horizontal cross-sectional shape may or may not be mirror-symmetrical with respect to the first horizontal cross-sectional shape. The second horizontal cross-sectional shape may have the same area as the first horizontal cross-sectional shape or may have a different area.

[0148] In some embodiments, a subset of the phase-change memory cells 50 may be formed without any sidewall linings 58, for example, as in Figure 23 The configuration illustrated in (b) is shown. In this case, the net temperature gradient generated from such phase change memory cells 50 can be zero. In other words, such phase change memory cells 50 may not have any horizontal direction along which a net flow of heat can be generated. Such a subset of phase change memory cells 50 that do not generate any net horizontal heat flow can be formed in the same device structure as at least one set of phase change memory cells 50 that each generate a corresponding horizontal heat flow along a corresponding horizontal direction.

[0149] In one embodiment, the device structure disclosed herein includes: a bottom electrode 42 and a heater element 48 embedded in a dielectric material layer; a layer stack (52, 54, 56) including a bottom liner 52, a phase change material portion 54 comprising a phase change material and a top electrode 56; and at least one sidewall liner 58 located on at least one sidewall of the layer stack and comprising a material having a conductivity higher than that of an amorphous phase of the phase change material.

[0150] In one embodiment, the electrical conductivity of the amorphous phase of the phase change material is in the range of 1.0 x 10⁻⁸ S / cm to 1.0 x 10⁻³ S / cm; and the electrical conductivity of the sidewall liner 58 material is in the range of 1.0 x 10¹ S / cm to 1.0 x 10⁵ S / cm. In one embodiment, the bottom liner layer 52L comprises a material having a conductivity at least three times that of the sidewall liner material. In one embodiment, the device structure comprises an encapsulated dielectric layer 643 in contact with at least one sidewall of the layer stack, an outer sidewall of each of the at least one sidewall liners 58, and a top surface of the layer stack (52, 54, 56).

[0151] According to another embodiment of this disclosure, a device structure is provided, comprising: a programmable transistor 701 located on a substrate 8; a bottom electrode 42 and a heater element 48 embedded in a dielectric material layer, wherein the heater element 48 is electrically connected to an electrical node of the programmable transistor 701; and a phase-change memory cell 50 comprising a volumetric stack including a bottom liner 52, a phase-change material portion 54 comprising a phase-change material and a top electrode 56, and further comprising at least one sidewall liner 58 located on at least one sidewall of the volumetric stack, wherein the programmable transistor 701 is configured to program the phase-change memory cell 50 into at least three different resistance states by applying at least three different programmable pulse patterns to the heater element 48.

[0152] In one embodiment, the at least three different resistance states include: a high-resistance state in which at least 99% of the entire volume of the phase change material portion 54 is in an amorphous phase; a low-resistance state in which at least 99% of the entire volume of the phase change material portion 54 is in a polycrystalline phase; and a first intermediate state in which the phase change material portion 54 includes a first volume having an amorphous phase and a second volume having a crystalline phase, the first volume not being in direct contact with the at least one sidewall liner 58 and having a higher resistance than the low-resistance state. In one embodiment, the at least three different resistance states further include a second intermediate state containing an amorphous volume having an amorphous phase and contacting the bottom liner 52 and at least one sidewall liner 58 but not contacting the top electrode 56; and programmed transistors 701 are configured to apply at least four different programmed pulse patterns to the heater element 48.

[0153] In one embodiment, the bottom liner 52 comprises a first metal nitride material; and at least one sidewall liner 58 comprises a second metal nitride material having a conductivity less than 1 / 3 of that of the first metal nitride material.

[0154] Reference Figure 29 A first flowchart illustrating an apparatus structure for forming the contents of this disclosure is shown.

[0155] Refer to step 2910 and Figure 1 – 6. The bottom electrode 42 and the heater element 48 are formed within a dielectric material layer.

[0156] Refer to step 2920 and Figure 7 – 28, forming a layer stack (52, 54, 56) of a corresponding bottom liner 52, a corresponding phase change material portion 54 and a corresponding top electrode 56.

[0157] Refer to step 2930 and Figure 9– 28, Sidewall liners 58 are formed on the layer stack (52, 54, 56). A corresponding combination of one of the bottom electrodes 42, one of the heater elements, one of the layer stack (52, 54, 56), and a corresponding sidewall liner 58 selected from the sidewall liners 58 constitutes a phase change memory cell 50, thereby forming a plurality of phase change memory cells 50. A first subset of the phase change memory cells 50 is arranged to generate a first temperature gradient TG along a first lateral direction.

[0158] In an embodiment, the first lateral direction can be a first azimuth angle rotated clockwise from a first horizontal direction by a top-down perspective; and a second subset of a plurality of phase change memory units 50 can be configured to generate a second temperature gradient along a second lateral direction, the second lateral direction being a second azimuth angle rotated clockwise from the first horizontal direction by the top-down perspective, the second azimuth angle being different from the first azimuth angle.

[0159] Reference Figure 30 A second flowchart illustrates an apparatus structure used to form the contents of this disclosure.

[0160] Refer to step 3010 and Figure 1 – 6. The bottom electrode 42 and the heater element 48 are formed within a dielectric material layer.

[0161] Refer to step 3020 and Figure 7 and 8 This forms a processing layer stack (52', 54', 56') consisting of a corresponding processing bottom liner 52', a corresponding processing phase change material portion 54', and a corresponding processing top electrode 56'.

[0162] Refer to step 3030 and Figure 9 and 10 The sidewall lining 58' is formed on the processing layer stack (52', 54', 56').

[0163] Refer to step 3040 and Figure 11– 28, Pattern the intermediate layer stacks (52', 54', 56') and the intermediate sidewall liner 58'. The patterned portion of the intermediate layer stacks (52', 54', 56') includes the layer stacks (52, 54, 56). The patterned portion of the intermediate sidewall liner 58' includes the sidewall liner 58. The phase change material portion 54 within a first subset of the stacked layers (52, 54, 56) includes a corresponding sidewall facing a first outward surface normal direction (which may be parallel, antiparallel, or orthogonal to a first horizontal direction hd1 or a second horizontal direction hd2), the first outward surface normal direction having an azimuth angle relative to a first horizontal direction hd1 measured in a clockwise direction, and further includes a corresponding additional sidewall facing a horizontal direction different from the first outward surface normal direction (which may be parallel, antiparallel, or orthogonal to the first horizontal direction hd1 or the second horizontal direction hd2) and the solid being exposed to a surrounding gaseous environment.

[0164] Reference Figure 31 A third flowchart illustrates an apparatus structure used to form the contents of this disclosure.

[0165] Refer to step 3110 and Figure 1 – 8, A corresponding processing bottom liner 52', a corresponding processing phase change material portion 54' and a corresponding processing top electrode 56' are stacked in processing layers (52', 54', 56') on top of a dielectric material layer.

[0166] Refer to step 3120 and Figure 9 and 10 The sidewall lining 58' is formed on the processing layer stack (52', 54', 56').

[0167] Refer to step 3130 and Figure 11– 28, The in-process layer stacks (52', 54', 56') and the in-process sidewall liners 58' are patterned. The patterned portion of the in-process layer stacks (52', 54', 56') includes the layer stacks (52, 54, 56). The patterned portion of the in-process sidewall liners 58' includes the sidewall liners 58. A phase change memory cell 50 is formed, which includes a connected combination of a corresponding one of the layer stacks (52, 54, 56) and a corresponding subset of the sidewall liners 58. Each of the phase change memory cells 50 includes a corresponding layer stack (52, 54, 56) which includes a bottom liner 52, a phase change material portion 54 including a phase change material, and a top electrode 56, and at least one sidewall liner 58 is located on at least one sidewall of the layer stack (52, 54, 56). For each phase change memory cell 50 within a first subset of phase change memory cells 50, the ratio of the total contact area between the phase change material portion 54 and at least one sidewall liner 58 to the total sidewall area of ​​the phase change material portion 54 has a first fraction. For each phase change memory cell 50 within a second subset of phase change memory cells 50, the ratio of the total contact area between the phase change material portion 54 and at least one sidewall liner 58 to the total sidewall area of ​​the phase change material portion 54 has a second fraction, which is different from the first fraction.

[0168] The embodiments of this disclosure reduce thermal crosstalk and thermal stress in phase-change memory cells 50 while enhancing scalability, efficiency, and reliability. By incorporating sidewall liners 58 for directional heat dissipation, the embodiments of this disclosure effectively stabilize resistance in various programmed resistance states and suppress resistance drift. Stability of programmed resistance levels allows for accurate representation of programmed states in computational memory applications. Furthermore, the ability to implement multiple geometries of phase-change memory cells on a single substrate 8 provides thermal management flexibility at the array level. For example, multiple phase-change memory arrays may include different configurations for phase-change memory cells 50 such that heat flows in different directions, for example, toward a nearest-end periphery of a semiconductor die. The use of materials with custom conductivity, such as carbon- or nitrogen-doped metal nitrides, in the sidewall liners 58 further ensures that the resistance of the sidewall liners 58 primarily determines the resistance in high-resistance states, thereby minimizing the impact on the inherent resistance variations of the phase-change material. Embodiments of this disclosure can facilitate different local temperature gradient directions across multiple memory configurations, thereby enabling directional heat dissipation and extended device reliability. The various features of embodiments of this disclosure collectively provide advantages for modern memory applications, including reduced power consumption, improved reliability, and enhanced scalability.

[0169] In a non-limiting exemplary embodiment, a method for forming a device structure is provided, comprising: forming a bottom electrode and a heater element within a dielectric material layer; forming a stack of layers comprising a corresponding bottom liner, a corresponding phase change material portion, and a corresponding top electrode; and forming sidewall liners on the stack of layers, wherein: each of the corresponding bottom electrode, the corresponding heater element, the corresponding layer stack, and a corresponding sidewall liner selected from the sidewall liners are connected together to form a phase change memory cell, thereby forming a plurality of phase changes. The memory cells; and a first subset of the plurality of phase-change memory cells are configured to generate a first temperature gradient along a first lateral direction, wherein: the first lateral direction is rotated clockwise by a first azimuth angle from a first horizontal direction at a top-down perspective; and a second subset of the plurality of phase-change memory cells are configured to generate a second temperature gradient along a second lateral direction, wherein the second lateral direction is rotated clockwise by a second azimuth angle from the first horizontal direction at the top-down perspective, the second azimuth angle being different from the first azimuth angle.

[0170] In a non-limiting exemplary embodiment, the phase change material portion within a first subset of the layer stack includes a corresponding sidewall facing a first outward surface normal direction having a third azimuth angle relative to the first horizontal direction, measured along the clockwise direction.

[0171] In a non-limiting exemplary embodiment, the phase change material portion within a second subset of the layer stack includes a corresponding sidewall facing a second outward surface normal direction having a fourth azimuth angle relative to the first horizontal direction measured along the clockwise direction, and does not include any sidewall facing a third horizontal direction.

[0172] In a non-limiting exemplary embodiment, the method further includes: forming a processing layer stack on the heater element, wherein each of the processing layer stacks includes a corresponding processing bottom liner, a corresponding processing phase change material portion, and a corresponding processing top electrode; and patterning the processing layer stack, wherein the patterned portion of the processing layer stack includes the layer stack.

[0173] In a non-limiting exemplary embodiment, the method further includes: forming an in-process sidewall liner, wherein each of the in-process sidewall liners is formed to surround a corresponding one in the in-process layer stack; and patterning the in-process sidewall liner, wherein the patterned portion of the in-process sidewall liner includes the sidewall liner.

[0174] In a non-limiting exemplary embodiment, the method further includes: forming a patterned etch mask layer over the processing layer stack and the processing sidewall liner; and anisotropically etching the portions of the processing layer stack and the processing sidewall liner not covered by the patterned etch mask layer, wherein the remaining portion of the processing layer stack includes the layer stack, and the remaining portion of the processing sidewall liner includes the sidewall liner.

[0175] In a non-limiting exemplary embodiment, the sidewall liner within the plurality of phase-change memory cells is formed by: depositing a sidewall liner layer on the processing layer stack; anisotropically etching the sidewall liner layer, wherein the remaining portion of the sidewall liner layer comprises the processing sidewall liner; and patterning the processing sidewall liner into the sidewall liner.

[0176] In a non-limiting exemplary embodiment, the method further includes performing an anisotropic etching process using an etch mask layer that partially covers the processing layer stack and the processing sidewall liner as an etch mask, wherein each of the layer stacks includes a patterned portion of a corresponding one of the processing layer stacks and includes a corresponding phase change material portion having at least one sidewall fully and substantially exposed to an surrounding gaseous or vacuum environment after the anisotropic etching process is completed.

[0177] In a non-limiting exemplary embodiment, each sidewall liner in a first subset of the plurality of phase-change memory cells has a first horizontal cross-sectional shape; and each sidewall liner in a second subset of the plurality of phase-change memory cells has a second horizontal cross-sectional shape, which is not translated identically to the first horizontal cross-sectional shape.

[0178] In a non-limiting exemplary embodiment, each of the plurality of phase change memory cells includes a corresponding phase change material portion having a sidewall formed parallel to a first horizontal direction; and the second horizontal cross-sectional shape is mirror-symmetrical with respect to a vertical plane parallel to or orthogonal to the first horizontal direction.

[0179] In a non-limiting exemplary embodiment, the second horizontal cross-sectional shape is rotationally identical to the first horizontal cross-sectional shape when rotated relative to a vertical direction.

[0180] In a non-limiting exemplary embodiment, the first subset of the plurality of phase-change memory cells includes rows of first-type phase-change memory cells, wherein each row of the first-type phase-change memory cells includes a corresponding subset of the first-type phase-change memory cells arranged along a second horizontal direction different from the first horizontal direction; the second subset of the plurality of phase-change memory cells includes rows of second-type phase-change memory cells, wherein each row of the second-type phase-change memory cells includes a corresponding subset of the second-type phase-change memory cells arranged along the second horizontal direction; and the rows of the first-type phase-change memory cells and the rows of the second-type memory cells are staggered along the first horizontal direction.

[0181] In a non-limiting exemplary embodiment, a method of forming a device structure is provided, comprising: forming a bottom electrode and a heater element within a dielectric material layer; forming a processing layer stack comprising a corresponding processing bottom liner, a corresponding processing phase change material portion, and a corresponding processing top electrode; forming a processing sidewall liner on the processing layer stack; and patterning the processing layer stack and the processing sidewall liner, wherein: the patterned portion of the processing layer stack comprises the layer stack; the patterned portion of the processing sidewall liner comprises a sidewall liner; and the phase change material portion within a first subset of the layer stack comprises a corresponding sidewall facing a first outward surface normal direction having an azimuth angle relative to a first horizontal direction measured along a clockwise direction, and further comprising a corresponding additional sidewall facing a horizontal direction and substantially exposed to an surrounding gaseous environment, the horizontal direction being different from the first outward surface normal direction.

[0182] In a non-limiting exemplary embodiment, an additional phase change material portion within a second subset of the layer stack includes a corresponding sidewall facing a second outward surface normal direction having an additional azimuth angle relative to the first horizontal direction measured along the clockwise direction, and does not include any sidewall facing the horizontal direction of the first horizontal sidewall.

[0183] In a non-limiting exemplary embodiment, the first subset of the stacked layers is configured to generate a first temperature gradient along a first lateral direction, the first lateral direction being rotated by a first azimuth angle from a first horizontal direction in a clockwise direction from a top-down perspective; and the second subset of the stacked layers is configured to generate a second temperature gradient along a second lateral direction, the second lateral direction being rotated by a second azimuth angle from the first horizontal direction in a clockwise direction from a top-down perspective, the second azimuth angle being different from the first azimuth angle.

[0184] In a non-limiting exemplary embodiment, each sidewall liner in the first subset of the stacked layers has a first horizontal cross-sectional shape; and each sidewall liner in the second subset of the stacked layers has a second horizontal cross-sectional shape that is not translated identically to the first horizontal cross-sectional shape.

[0185] In a non-limiting exemplary embodiment, a device structure is provided, comprising: phase change memory units, wherein: each of the phase change memory units includes a corresponding layer stack, which includes a bottom liner, a phase change material portion comprising a phase change material, and a top electrode; a first subset of the phase change memory units is configured to generate a first temperature gradient along a first lateral direction, the first lateral direction being rotated clockwise by a first azimuth angle from a first horizontal direction at a top-down perspective; and a second subset of the plurality of phase change memory units is configured to generate a second temperature gradient along a second lateral direction, the second lateral direction being rotated clockwise by a second azimuth angle from the first horizontal direction at the top-down perspective, the second azimuth angle being different from the first azimuth angle.

[0186] In a non-limiting exemplary embodiment, each phase change material portion within the first subset of the stacked layers of the phase change memory cell includes a corresponding first sidewall facing a first outward surface normal direction having a third azimuth angle relative to the first horizontal direction measured along the clockwise direction; and each phase change material portion within the second subset of the stacked layers of the phase change memory cell includes a corresponding second sidewall facing a second outward surface normal direction having a fourth azimuth angle relative to the first horizontal direction measured along the clockwise direction, and does not include any sidewall facing a third horizontal direction.

[0187] In a non-limiting exemplary embodiment, the corresponding first sidewall is in contact with a corresponding first sidewall liner; the corresponding second sidewall is in contact with a corresponding second sidewall liner; the bottom liner of the phase change memory cell includes a first conductive material having a first conductivity; and the first sidewall liner and the second sidewall liner of the phase change material cell include a second conductive material having a second conductivity less than the first conductivity.

[0188] In a non-limiting exemplary embodiment, each of the first sidewall linings in the first subset of the phase-change memory cells has a first horizontal cross-sectional shape; and each of the second sidewall linings in the second subset of the phase-change memory cells has a second horizontal cross-sectional shape that is not translated identically to the first horizontal cross-sectional shape.

[0189] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. The use of the term "comprising" in the description of various embodiments inherently discloses that the term "comprising" may be replaced in some embodiments with "substantially consisting of" or "consisting of," unless otherwise explicitly disclosed herein. Whenever two or more elements are listed in the same paragraph or in different paragraphs as an alternative, a Markush group comprising a list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb "may" is used in this disclosure to describe the formation of an element or the performance of a processing step, it also explicitly covers embodiments in which this element or processing step is not performed, provided that the resulting apparatus or device provides an equivalent result. Thus, when applied to the formation of an element or the performance of a processing step, the auxiliary verb "may" is also interpreted as "may" or "may or may not," and whenever omitting the formation of this element or processing step can provide the same or equivalent result, the equivalent result includes a slightly superior result and a slightly inferior result. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other programs and structures to achieve the same purposes and / or advantages as the embodiments described in this case. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations to this case without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a heat flow-controlled phase change material device with sidewall linings, characterized in that: Include: A bottom electrode and heater element are formed within a dielectric material layer; Forming a layered stack of a corresponding bottom liner, a corresponding phase change material portion, and a corresponding top electrode; and A sidewall lining is formed on the stacked layers, wherein: The corresponding one of the bottom electrodes, the corresponding one of the heater elements, the corresponding one of the layer stack, and each interconnected combination of the corresponding sidewall liner selected from the sidewall liner constitutes a phase change memory unit, thereby forming a plurality of phase change memory units; and The first subset of the plurality of phase-change memory cells is arranged to generate a first temperature gradient along a first lateral direction. in: The first lateral direction is rotated clockwise from the first horizontal direction by a top-down perspective; and The second subset of the plurality of phase change memory cells are arranged to generate a second temperature gradient along a second lateral direction, the second lateral direction being rotated clockwise from the first horizontal direction by a second azimuth angle from the top-down perspective, the second azimuth angle being different from the first azimuth angle.

2. The method for forming a heat flow-controlled phase change material device with sidewall lining as described in claim 1, characterized in that: The phase change material portion within the first subset of the stacked layers includes a corresponding sidewall facing a first outward surface normal direction, the first outward surface normal direction having a third azimuth angle relative to the first horizontal direction, measured along the clockwise direction.

3. The method for forming a heat flow-controlled phase change material device with sidewall lining as described in claim 1, characterized in that: It also includes: A processing layer stack is formed on the heater element, wherein each of the processing layer stacks includes a corresponding processing bottom liner, a corresponding processing phase change material portion, and a corresponding processing top electrode; and The processing layer stack is patterned, wherein the patterned portion of the processing layer stack includes the layer stack.

4. A method for forming a heat flow-controlled phase change material device with sidewall linings, characterized in that: Include: A bottom electrode and heater element are formed within a dielectric material layer; The corresponding processing bottom lining, the corresponding processing phase change material part and the corresponding processing top electrode are stacked in the processing layer; A processing sidewall liner is formed on the processing layer stack; and The processing layer stack and the processing sidewall lining are patterned, wherein: The patterned portion of the layer stack during processing includes the layer stack; The patterned portion of the sidewall lining during processing includes the sidewall lining; and The phase change material portion within the first subset of the stacked layers includes a corresponding sidewall facing a first outward surface normal direction having an azimuth angle relative to a first horizontal direction measured in a clockwise direction, and further includes a corresponding additional sidewall facing a horizontal direction and exposed to the surrounding gaseous environment, which is different from the first outward surface normal direction.

5. The method for forming a heat flow controlled phase change material device with sidewall lining as described in claim 4, characterized in that: The additional phase change material portion within the second subset of the layer stack includes a corresponding sidewall facing a second outward surface normal direction, which has an additional azimuth angle relative to the first horizontal direction measured along the clockwise direction, and does not include any sidewall facing the horizontal direction of the first horizontal sidewall.

6. The method for forming a heat flow-controlled phase change material device with sidewall lining as described in claim 5, characterized in that: The first subset of the stacked layers is configured to generate a first temperature gradient along a first lateral direction, the first lateral direction being rotated by a first azimuth angle from the first horizontal direction in the clockwise direction from a top-down perspective. as well as The second subset of the stacked layers is configured to generate a second temperature gradient along a second lateral direction, which is a second azimuth angle rotated clockwise from the first horizontal direction from a top-down perspective, and the second azimuth angle is different from the first azimuth angle.

7. A heat flow controlled phase change material device with sidewall lining, characterized in that: Include: Phase-change memory cell, wherein: Each of the phase change memory cells comprises a corresponding stack of layers, which includes a bottom liner, a phase change material portion containing phase change material, and a top electrode. A first subset of the phase-change memory cells is configured to generate a first temperature gradient along a first lateral direction, the first lateral direction being rotated clockwise from a first horizontal direction by a top-down perspective; and The second subset of the plurality of phase change memory cells are arranged to generate a second temperature gradient along a second lateral direction, the second lateral direction being rotated clockwise from the first horizontal direction by a second azimuth angle from the top-down perspective, the second azimuth angle being different from the first azimuth angle.

8. The heat flow controlled phase change material device with sidewall lining as described in claim 7, characterized in that: Each phase change material portion within the first subset of the stacked layers of the phase change memory cell includes a corresponding first sidewall facing a first outward surface normal direction, the first outward surface normal direction having a third azimuth angle relative to the first horizontal direction measured along the clockwise direction. as well as Each phase change material portion within the second subset of the stacked layers of the phase change memory cell includes a corresponding second sidewall facing a second outward surface normal direction having a fourth azimuth angle relative to the first horizontal direction measured along the clockwise direction, and does not include any sidewall facing a third horizontal direction.

9. The heat flow controlled phase change material device with sidewall lining as claimed in claim 8, characterized in that: The corresponding first sidewall is in contact with the corresponding first sidewall lining; The corresponding second sidewall is in contact with the corresponding second sidewall lining; The bottom liner of the phase change memory cell contains a first conductive material having a first conductivity. as well as The first sidewall liner and the second sidewall liner of the phase change material unit contain a second conductive material having a second conductivity that is less than the first conductivity.

10. The heat flow controlled phase change material device with sidewall lining as claimed in claim 9, characterized in that: Each of the first sidewall linings in the first subset of the phase-change memory cells has a first horizontal cross-sectional shape; and Each of the second sidewall linings in the second subset of the phase-change memory cell has a second horizontal cross-sectional shape that is not translated identically to the first horizontal cross-sectional shape.

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