Package for embedded semiconductor devices and method of forming the same

Abstract

A semiconductor device package, a package for embedded semiconductor devices, and a method of forming a semiconductor device package are provided. The semiconductor device package includes a semiconductor device having a first side and a second side opposite the first side. A first metallization layer is disposed on the first side, and a first metal layer is formed on the first metallization layer. The first metal layer includes a first pattern defined by first spaces, the first spaces including a first non-conductive material formed on the first metallization layer. A second metallization layer is disposed on the second side, and a second metal layer is formed on the second metallization layer. A second pattern can be formed in the second metal layer and can be based on the first pattern to provide mechanical stress relief for the semiconductor device.

Description

Technical Field

[0001] This specification relates to semiconductor device packaging, and more particularly to semiconductor device packages, packages for embedded semiconductor devices, and methods for forming semiconductor device packages. Background Technology

[0002] Semiconductor device packaging typically involves encasing one or more semiconductor devices in a protective housing that provides electrical connectivity, heat dissipation, mechanical support, and / or electrical isolation. Many different types of semiconductor device packages exist, offering varying degrees of packaging parameters. These packaging parameters may include, but are not limited to, performance (e.g., speed or power handling) parameters, cost parameters, and / or size parameters.

[0003] Semiconductor device packages, including embedded device packages, are typically manufactured through collaborations between semiconductor device manufacturers and suppliers of substrates and other packaging components (e.g., printed circuit boards, PCBs). For example, semiconductor device manufacturers typically design and manufacture semiconductor dies, providing detailed specifications regarding die layout, electrical requirements, and thermal characteristics. PCB suppliers, for instance, ensure that the relevant PCB design is compatible with the relevant semiconductor die, including layers designed for wiring, power delivery, and thermal management. For embedded device packages where the semiconductor die is directly embedded into PCB layers, the PCB supplier is responsible for ensuring that the embedding process does not damage the die and that electrical connections are reliable. Summary of the Invention

[0004] According to one general aspect, a semiconductor device package includes: a semiconductor device having a first side and a second side opposite to the first side; a first metallization layer disposed on the first side; and a first metal layer formed on the first metallization layer, the first metal layer including a first pattern defined by a first space, the first space including a first non-conductive material formed on the first metallization layer. The semiconductor device package further includes a second metallization layer disposed on the second side, and a second metal layer formed on the second metallization layer.

[0005] According to another general aspect, a package for an embedded semiconductor device includes a substrate and a semiconductor device disposed on the substrate, the semiconductor device having a first side and a second side opposite to the first side. The package further includes: a first metallization layer disposed on the first side; and a first metal layer formed on the first metallization layer and including a first stress-relief pattern defined by a first metal layer portion and a second metal layer portion, having a first space between the first metal layer portion and the second metal layer portion, the first space including a first non-conductive material formed on the first metallization layer. The package further includes: a second metallization layer disposed on the second side; a second metal layer formed on the second metallization layer; and a sealant that secures the semiconductor device, the first metal layer, and the second metal layer to the substrate.

[0006] According to another general aspect, a method of forming a semiconductor device package includes: forming a first metallization layer on a first side of the semiconductor device; forming a second metallization layer on a second side of the semiconductor device opposite to the first side; and forming a first metal layer on the first metallization layer, the first metal layer including a first pattern defined by a first space. The method further includes: forming a first non-conductive material in the first space and on the first metallization layer; and forming a second metal layer on the second metallization layer.

[0007] Details of one or more specific embodiments are set forth in the accompanying drawings and the following description. Other features will be apparent from the specification and drawings, as well as from the claims. Attached Figure Description

[0008] Figure 1A This is a side view of a semiconductor device with double-sided patterned electroplating.

[0009] Figure 1B This is a top view of a semiconductor device that can be patterned on both sides.

[0010] Figure 1C It is a bottom view of a semiconductor device with double-sided patterned electroplating.

[0011] Figure 2 It is a side view of a multi-device semiconductor device with double-sided patterned electroplating.

[0012] Figure 3 It includes Figure 1A The first example of a semiconductor device is a side view of a semiconductor device package.

[0013] Figure 4 It includes Figure 1A A second example of a semiconductor device is shown in the side view of a semiconductor device package.

[0014] Figure 5A An example first operation for forming a semiconductor device with double-sided patterned electroplating is illustrated.

[0015] Figure 5B An example second operation for forming a semiconductor device with double-sided patterned electroplating is illustrated.

[0016] Figure 5C An example third operation for forming a semiconductor device with double-sided patterned electroplating is illustrated.

[0017] Figure 6A An example fourth operation is illustrated for forming a semiconductor device with double-sided patterned electroplating.

[0018] Figure 6B An example fifth operation is illustrated for forming a semiconductor device with double-sided patterned electroplating.

[0019] Figure 6C An example sixth operation is illustrated for forming a semiconductor device with double-sided patterned electroplating.

[0020] Figure 7A An example alternative to the fourth operation is illustrated for forming a semiconductor device with double-sided patterned electroplating.

[0021] Figure 7B An example of an alternative fifth operation is illustrated for forming a semiconductor device with double-sided patterned electroplating.

[0022] Figure 7C An example alternative to the sixth operation is illustrated for forming a semiconductor device with double-sided patterned electroplating and sidewall protection.

[0023] Figure 8 Examples Figure 7C Examples of the results of the alternative sixth operation are grinding and dicing, which include single-chip packages with sidewall protection and multi-chip packages with sidewall protection.

[0024] Figure 9A An example alternative to the fourth operation is illustrated for forming a semiconductor device with double-sided patterned electroplating.

[0025] Figure 9B An example of an alternative fifth operation is illustrated for forming a semiconductor device with double-sided patterned electroplating.

[0026] Figure 9C An example alternative to the sixth operation is illustrated for forming a semiconductor device with double-sided patterned electroplating.

[0027] Figure 10AAn example eighth operation is illustrated for forming a semiconductor device with double-sided plating and sidewall protection in the case of a fan-out layer.

[0028] Figure 10B Example ninth operation is illustrated for forming a semiconductor device with double-sided plating and sidewall protection in the case of a fan-out layer.

[0029] Figure 10C Example tenth operation is illustrated for forming a semiconductor device with double-sided plating and sidewall protection in the case of a fan-out layer.

[0030] Figure 11 This is an example used to form Figures 1A to 10C A flowchart illustrating an example operation of a semiconductor device.

[0031] Figure 12 This is an example of a multi-chip semiconductor device with double-sided plating and sidewall protection in the case of a fan-out layer.

[0032] Figure 13 This is a first example semiconductor device package for use with a semiconductor device having double-sided plating and sidewall protection in the presence of a fan-out layer.

[0033] Figure 14 This is a second example semiconductor device package for use with a semiconductor device having double-sided plating and sidewall protection in the presence of a fan-out layer.

[0034] Figure 15 This is a third example of a semiconductor device package for use in semiconductor devices with double-sided plating and sidewall protection in the presence of a fan-out layer. Detailed Implementation

[0035] The described techniques and embodiments provide improved semiconductor device packaging, including facilitating assembly, increasing safety margins, and enhancing encapsulation. For example, semiconductor dies can be manufactured with patterned metal plating on one or both sides of each semiconductor die. Patterned metal plating reduces warpage and breakage during, for example, subsequent die processing and via formation.

[0036] As mentioned above, packaging suppliers and semiconductor die manufacturers often have a symbiotic relationship, with each relying on the other's expertise to successfully realize the final product (such as embedded semiconductor device packages). For example, semiconductor die manufacturers depend on packaging suppliers for efficient integration and manufacturing capabilities, while packaging suppliers require detailed semiconductor specifications to design boards that meet performance, size, and cost requirements. This collaboration has enabled the development of fields such as mobile devices, automotive electronics, IoT, high-performance computing, and other increasingly popular technology areas like embedded systems.

[0037] However, in some cases, packaging suppliers (e.g., substrate or PCB suppliers) may not have the necessary tools to process the received semiconductor dies reliably, efficiently, and cost-effectively. For example, manufactured semiconductor dies are often very thin and prone to warping or breaking. Semiconductor manufacturers may possess the best available tools to handle such dies, even though they may experience some degree of die damage. However, packaging suppliers may be less likely to have such die handling tools and may be forced to use tools that are prone to damaging the semiconductor dies during the embedding process.

[0038] Various known techniques can be used to enhance the structure of semiconductor dies, including, for example, providing a reinforcing metal layer on the semiconductor die. Such layers can reduce damage during tooling at the package supplier, but if they are too thick, they can cause associated die warping due to the mechanical stress applied to the die.

[0039] Furthermore, it may be necessary to drill through such metal layers to form vias used to provide external connections for the semiconductor die. For example, a suitable laser can be used to provide such drilling. However, in many cases, such lasers or other drilling tools may be prone to over-drilling the metal layers, resulting in overshoot that damages the underlying die. Using thicker metal layers can reduce the frequency of such damage, but as mentioned above, such thicker metal layers impose more mechanical stress on the die and are therefore more likely to cause warping. The frequency of such damage can also be reduced by using slower and / or more expensive lasers or other drilling techniques, but these techniques increase the time and cost for package suppliers.

[0040] In contrast, the described technique provides patterned metal layers on the semiconductor die, which can be formed to a desired thickness level without causing warping of the associated die. Utilizing such thicker metal layers reduces the risk of drill overshoot and allows for faster / cheaper drilling techniques.

[0041] For example, double-sided patterned metal layers can be formed on both the top and bottom of a semiconductor die. Such double-sided patterned metal layers compensate for the mechanical stresses they cause to each other, thereby reducing the net mechanical stress applied to the die and correspondingly reducing the likelihood of warpage.

[0042] For example, the patterning of the top-side metal layer can be determined or influenced by the pattern of the metal contacts (e.g., source contacts and gate contacts) formed on the top side of the semiconductor die. In some embodiments, a bottom-side metal layer may subsequently be provided on the entire or nearly entire bottom side of the semiconductor die.

[0043] In other implementations, the bottom metal layer can be patterned. For example, such patterning of the bottom metal layer can be chosen to reduce or compensate for mechanical stress and warping that may be caused by the top metal layer.

[0044] In some examples, simulation tools can be used to determine top-side and / or bottom-side metal patterning. For instance, top-side patterning may be determined at least in part by the layout of the top-side contact pads of the semiconductor die, and may be input into the simulation tool along with a request for a corresponding bottom-side patterning that minimizes die warpage. In other examples, both top-side and bottom-side patterning may be output based on various factors, including, for example, top-side contacts, die thickness or other parameters, the thickness of the patterned metal layer, and / or the permissible degree of warpage. In other words, warpage may be used as a simulation parameter to be minimized when simulating potential top-side and / or bottom-side patterning.

[0045] In some implementations, various masking and plating techniques can be used to provide patterned metal. For example, a mask can be provided on the top and / or bottom side of a semiconductor die to define a desired pattern. Copper plating can then be applied simultaneously on both the top and bottom sides of the semiconductor die in a single process.

[0046] In some implementations, the molded part can be provided within any recess or other space defined by the metal pattern, for example, for further stabilization and / or for electrical isolation. Grinding can then be performed to reduce the thickness of the patterned metal and the molded part, thereby achieving the desired thickness of the metal plating. Such grinding can also be used to ensure a uniform and consistent height of the metal and the molded part on the surface of the semiconductor die.

[0047] In some implementations, embedded sidewalls may be located on one or more sides of the semiconductor die. Such sidewalls provide enhanced stability and make the semiconductor die less likely to experience damage when embedded in, for example, a PCB or other substrate.

[0048] Furthermore, some embedded packaging technologies are prone to difficulties caused by conductive anode filaments (CAFs), which are, for example, copper or other metal ions that migrate through non-conductive materials under the influence of an electric field. For instance, prepreg materials used in embedded packaging technologies are susceptible to CAF growth. Such CAF growth can lead to short circuits or other failure mechanisms. Adding the described epoxy molding compound (EMC) sidewalls prevents CAF growth, thereby increasing the reliability and stability of embedded packages.

[0049] In some implementations, the fan-out layer may be provided in combination with a patterned metal layer. Such a fan-out layer can be used, for example, to facilitate or enhance external connections to a semiconductor die.

[0050] Using the described technology, the metal thickness on the top side of a semiconductor die can be increased to, for example, a range of 10 micrometers to 200 micrometers or greater. Due to the use of the described technology, warpage or other damage to semiconductor devices can be reduced, and vias for semiconductor devices can be formed quickly, inexpensively, and reliably. Therefore, semiconductor manufacturers can achieve higher yields of embedded packages from packaging suppliers, and packaging suppliers can obtain simplified and efficient processes for providing embedded packages.

[0051] Figure 1A This is a side view of a semiconductor device 100a with double-sided electroplating. Figure 1A In the example, semiconductor die 102 is illustrated as having a first side or top side in the upper portion of the figure and a second side or bottom side in the lower portion of the figure. On the top side of semiconductor die 102, a sintered layer 106 is used to attach a metallization layer 108 to semiconductor die 102. A passivation layer 104 is disposed between portions of the sintered layer 106 and the metallization layer 108, as described in more detail below.

[0052] A top-side patterned metal 110, also referred to as a first-side patterned metal, is provided using a patterned top-side metal plating layer, as mentioned above. The pattern formed in or using the top-side patterned metal 110 may be referred to as a stress-relieving pattern. Figure 1A In the example, a first portion of the top-side patterned metal 110 is disposed on a portion of the metallization layer 108 connected to the source portion of the semiconductor die 102. The source portion of the semiconductor die 102, the source portion of the metallization layer 108, and the corresponding portion of the top-side patterned metal 110 are collectively referred to as the source 112. A second portion of the top-side patterned metal 110 is disposed on a portion of the metallization layer 108 connected to the gate portion of the semiconductor die 102; these three portions are collectively referred to as the gate 114.

[0053] A passivation layer 113 (e.g., a polyimide passivation layer) is disposed in the space or opening 111 of the top-side patterned metal 110. See below for example regarding... Figure 5B As described, the passivation layer 113 may have been used as part of a mask for forming the top-side patterned metal 110 together with the passivation layer 104.

[0054] Further in Figure 1A In this design, sealant 115 is illustrated as surrounding and encapsulating the top-side patterned metal 110. As shown, sealant 115 is also disposed within the opening 111 of the top-side patterned metal 110. Sealant 115 may represent any suitable molding material, such as resin or epoxy resin.

[0055] The similar description given above regarding the top or first side of semiconductor die 102 applies to the opposite side of semiconductor die 102, which is referred to as the second or bottom side of semiconductor die 102. Specifically, on the bottom side of semiconductor die 102, a sintered layer 116 is used to attach a metallization layer 118 to semiconductor die 102.

[0056] The bottom-side patterned metal 120 (also referred to as the second-side patterned metal) provides a patterned bottom-side metal plating, as mentioned above. Similarly, as described above, the pattern formed in or using the bottom-side patterned metal 120 can be referred to as a stress-relieving pattern. Figure 1A In the example, the bottom-side patterned metal 120 is disposed on the metallization layer 118, which is itself connected to the drain portion of the semiconductor die 102. The bottom-side patterned metal, the metallization layer, and the drain portion are collectively referred to as the drain 126.

[0057] A passivation layer 122 is disposed in the space or opening 125 of the bottom patterned metal 120. (See below for example regarding...) Figure 5B As described, the passivation layer 122 may have been used as part of a mask for forming the bottom-side patterned metal 120. As further illustrated, a sealant 124 is disposed within the opening 125.

[0058] therefore, Figure 1A The term "patterned metal" is illustrated as referring to a metal layer (e.g., an electroplated metal layer) in which openings or gaps are formed, such that the metal layer exhibits a pattern defined by these openings. That is, the top-side patterned metal 110 exhibits a pattern defined by opening 111 (and by the gap between source 112 and gate 114), while the bottom-side patterned metal 120 exhibits a pattern defined by opening 125.

[0059] Therefore, the patterned metals 110 and 120 provide relief of mechanical stress on the semiconductor die 102, making it less likely to warp or break, for example, when handled by a PCB supplier during the embedding process. For example, the total amount or mass of the top-side patterned metal 110 and the bottom-side patterned metal 120 may be the same or nearly the same, thereby providing a balance relative to the forces applied to the semiconductor device 100a during processing. Specifically, as mentioned above and described in more detail below, both the top-side patterned metal 110 (and sealant 115) and the bottom-side patterned metal 120 (and sealant 124) may be exposed to a polishing process that reduces the height of both the top-side patterned metal 110 and the bottom-side patterned metal 120 to a desired height. Such a polishing process further ensures a uniform height across the entire top-side patterned metal 110 and bottom-side patterned metal 120.

[0060] Due to the balance of relative forces exerted by the top-side patterned metal 110 and the bottom-side patterned metal 120 during wafer processing, the thickness of the patterned metals 110, 120 can be increased relative to existing metal layers formed on the semiconductor die without increasing the likelihood of cracking or warping. For example, the thickness of the metal layers 110, 120 can be 10 micrometers, 50 micrometers, 100 micrometers, or greater. Therefore, and as illustrated in more detail below, through-holes can be drilled through the patterned metal layers 110, 120 to form electrical connections quickly and economically without concern that over-drilling may damage the semiconductor die 102.

[0061] exist Figure 1A In the example, semiconductor device 100a represents a transistor, which can be any suitable transistor made of any suitable material, such as a silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) transistor. Of course, these are just examples and can include various types of semiconductor devices, such as diodes, or combinations of devices (e.g., transistors, diodes).

[0062] For example, semiconductor device 100a can represent various types of power transistors, such as insulated-gate bipolar transistors (IGBTs), power metal-oxide-semiconductor field-effect transistors (MOSFETs), etc. Electrical interconnects within the high-power semiconductor device package may include, for example, bonding wires, conductive spacers, metal and insulating building blocks, and conductive clamps.

[0063] Although sintered materials, such as Ag sintered materials, have been mentioned above, other die-attachment materials or techniques, such as solder, may be used. Any suitable metal may be used for the metallization layer, such as alloys of titanium, nickel, and / or silver. Copper plating provides an example of materials and techniques that may be used to form the top-side patterned metal 110 and the bottom-side patterned metal 120, but other suitable materials and techniques may also be used.

[0064] Figure 1B It is usable as about Figure 1A A top view of the double-sided electroplated semiconductor device 127 as described. Figure 1B In the example, semiconductor device 127 is illustrated as including source contact 128 and additional contacts 130, 132, 134, which may represent, for example, gate contacts, Kelvin sensor contacts or other contacts. Figure 1B It does not limit any type of semiconductor device that can benefit from the described technology. Instead, Figure 1B The semiconductor device 127 is only intended to illustrate examples of contacts that can be formed on the top side of the semiconductor device in order to describe example aspects of top-side patterned metal that can be formed relative to such contacts.

[0065] For example, from Figure 1A As will be understood from the description, top-side patterned metal 110 may be formed on or relative to contacts 128, 130, 132, 134 to provide the various benefits and advantages described above. For example, top-side patterned metal may be formed over some or all of each of contacts 128, 130, 132, 134. Top-side patterned metal 110 may also extend beyond the perimeter of one or more of contacts 128, 130, 132, 134. (See also: Regarding...) Figure 1A As described, suitable molding material may be provided within any recesses (including between various contacts 128, 130, 132, 134) of the top-side patterned metal 110 disposed on the semiconductor device 127 to provide mechanical stress relief and electrical isolation. The patterning of any such top-side patterned metal and associated recesses may be determined, for example, using suitable simulation tools capable of determining metal patterns that reduce warpage or otherwise alleviate mechanical stresses that would otherwise be applied to the semiconductor device 127.

[0066] Figure 1C This is a bottom view of a semiconductor device 135 with double-sided electroplating. Figure 1C In this example, bottom-patterned metal 136 is formed on semiconductor device 135. Spaces 138 are formed between portions of the bottom-patterned metal 136 and may be filled with suitable passivation layers and / or sealants. Figure 1C (Not shown separately in the text).

[0067] Will understand, Figure 1C It should not be interpreted as necessarily corresponding to Figure 1B A top view of example semiconductor device 127. Conversely... Figure 1C The examples illustrate virtually any desired pattern that can define the patterned metal and associated spacing, and such patterns can be selected to compensate for the mechanical forces exerted by the corresponding top-side metal pattern selected for implementation on the top side of the corresponding semiconductor device. Such compensation can depend on several factors, such as, for example, the material of the underlying semiconductor die, the size of the semiconductor die, the thickness of the semiconductor die, and / or the nature of the individual devices (e.g., transistors, diodes) formed within the semiconductor die.

[0068] therefore, Figures 1A to 1CAn example of a semiconductor device is generally illustrated, having a first side and a second side opposite to the first side, a first metallization layer disposed on the first side, and a first metal layer formed on the first metallization layer. The first metal layer includes a first pattern defined by a first space, the first space containing a first non-conductive material formed on the first metallization layer. A second metallization layer is disposed on the second side, and a second metal layer is formed on the second metallization layer. The second metal layer includes a second pattern defined by a second space, the second space containing a second non-conductive material formed on the second metallization layer. A first sealant may be disposed in the first space, located on the first non-conductive material, and a second sealant may be disposed in the second space, located on the second non-conductive material. The first sealant and the first metal layer may be ground to a first uniform height, and the second sealant and the second metal layer may be ground to a second uniform height, wherein the first uniform height and the second uniform height may be equal. The first space of the first metal layer may include a plurality of first spaces defining a first stress relief line, and the second space may include defining a second stress relief line (e.g., Figure 1C Multiple second spaces of the stress relief line 138.

[0069] The second pattern can be based on the first pattern to provide mechanical stress relief for the semiconductor device. For example, simulation tools can be used to model the first and second patterns relative to the underlying contact pads and relative to each other, and optimize the first and second patterns to minimize the warpage of the underlying semiconductor die.

[0070] Figure 2 This is a side view of a multi-device semiconductor device 200 with double-sided electroplating. Figure 2 In the example, with Figure 1A As in the figure, semiconductor die 202 is illustrated as having a first side or top side in the upper portion of the figure and a second side or bottom side in the lower portion of the figure. On the top side of semiconductor die 202, a sintered layer 206 is used to attach a metallization layer 208 to semiconductor die 202. A passivation layer 204 is disposed between portions of the sintered layer 206 and the metallization layer 208, as described in more detail below.

[0071] A top-side patterned metal 210 is provided using a patterned top-side metal plating layer, which is also referred to as the first-side patterned metal, as in... Figure 1AIn the example, a first portion of the top-side patterned metal 210 is disposed on a portion of the metallization layer 208 connected to the first source portion of the semiconductor die 202. The first source portion of the semiconductor die 202, the first source portion of the metallization layer 208, and the corresponding portion of the top-side patterned metal 210 are collectively referred to as the first source 212a. A second portion of the top-side patterned metal 210 is disposed on a portion of the metallization layer 208 connected to the first gate portion of the semiconductor die 202; these three portions are collectively referred to as the first gate 214a.

[0072] A third portion of the top-side patterned metal 210 is disposed on a portion of the second source portion of the metallization layer 208 connected to the semiconductor die 202. The second source portion of the semiconductor die 202, the second source portion of the metallization layer 208, and the corresponding portion of the top-side patterned metal 210 are collectively referred to as the second source 212b. A fourth portion of the top-side patterned metal 210 is disposed on a portion of the second gate portion of the metallization layer 208 connected to the semiconductor die 202; these three portions are collectively referred to as the second gate 214b.

[0073] A passivation layer 213 (e.g., a polyimide passivation layer) is disposed in the space or opening 211 of the top-side patterned metal 210. See below for example regarding... Figure 5B As described, the passivation layer 213 may have been used as part of a mask for forming the top-side patterned metal 210 together with the passivation layer 204.

[0074] Further in Figure 2 In this design, sealant 215 is illustrated as surrounding and encapsulating the top-side patterned metal 210. As shown, sealant 215 is also disposed within the opening 211 of the top-side patterned metal 210. Sealant 215 can represent any suitable molding material, such as resin or epoxy resin.

[0075] The similar description given above regarding the top or first side of semiconductor die 202 applies to the opposite side of semiconductor die 202, which is referred to as the second or bottom side of semiconductor die 202. Specifically, on the bottom side of semiconductor die 202, a sintered layer 216 is used to attach a metallization layer 218 to semiconductor die 202.

[0076] The bottom-side patterned metal 220 (also referred to as the second-side patterned metal) provides a patterned bottom-side metal plating, as mentioned above. Figure 2 In the example, the bottom-side patterned metal 220 is disposed on the metallization layer 218, which is itself connected to the drain portion of the semiconductor die 202. The bottom-side patterned metal, the metallization layer, and the drain portion are collectively referred to as the drain 226.

[0077] A passivation layer 222 is disposed in the space or opening 225 of the bottom patterned metal 220. (See example below for details.) Figure 5B As described, the passivation layer 222 may have been used as part of a mask for forming the bottom-side patterned metal 220. As further illustrated, a sealant 224 is disposed within the opening 225.

[0078] therefore, Figure 2 Examples illustrate how multiple devices and / or multiple chips can be included in a single larger semiconductor device. Figure 2 It is not restrictive and may include more than two devices / chips. Figure 2 Share about Figure 1A Many or all of the advantages and features described. For example, patterned metals 210 and 220 provide relief of mechanical stress on semiconductor die 202, making semiconductor die 202 less likely to warp or break. Both the top-side patterned metal 210 (and sealant 215) and the bottom-side patterned metal 220 (and sealant 224) are exposed to a polishing process that reduces the height of both the top-side and bottom-side patterned metals 210 to a desired height. Such a polishing process further ensures a uniform height across the entire top-side and bottom-side patterned metals 210 and 220.

[0079] Figure 3 It includes Figure 1A A side view of a first example semiconductor device package. Figure 3 In this process, semiconductor device 100a is attached to substrate 302 via a bonding layer 304 (e.g., a sintered layer). Sealant 306 is disposed around semiconductor device 100a and provides, for example, protection and isolation while securing semiconductor device 100a to substrate 302.

[0080] The substrate 302 may represent any suitable mounting surface or mounting member in which the semiconductor device 100a may be positioned. For example, the substrate 302 may represent a lead frame, such as a metal lead frame (e.g., a copper lead frame).

[0081] Figure 3 The simplified example illustrates substrate 302 as a single material, but substrate 302 may also be composed of multiple materials. For example, substrate 302 may include multiple layers in a direct-bonded metal (DBM) or direct-bonded copper (DBC) structure, wherein a dielectric material is placed between two metal materials (e.g., copper or aluminum). Substrate 302 may be part of a larger printed circuit board (PCB) and panel assembly.

[0082] The substrate 302 may be implemented as or combined with a leadframe for providing external electrical connections to the high-power semiconductor device 100a. For example, some of the high-power components described herein operate at voltages ranging from about 200 V to about 800 V. Such high-power chip assemblies, encapsulated as embedded semiconductor device modules, can be used in a variety of applications, including electric vehicles (EVs), hybrid electric vehicles (HEVs), and industrial applications.

[0083] Figure 4 It includes Figure 1A A side view of a second example semiconductor device package. Figure 4 In the device package, semiconductor device 400a and semiconductor device 400b typically correspond to Figure 1A Semiconductor device 100a. This mainly concerns the connection to semiconductor device 400a and the packaging of this semiconductor device. Figure 4 Further description of the device package is provided, but it will be understood that similar descriptions also apply to semiconductor device 400b and its corresponding connections and packages.

[0084] As shown in the figure, the source region of semiconductor device 400a is attached to a plurality of source contacts 405 established using source vias 404 via a portion of sintered layer 402, thereby defining a source connection 406. Similarly, the gate region of semiconductor device 400a is attached to a plurality of gate contacts 409 established using gate vias 408 via a portion of sintered layer 402, thereby defining a gate connection 410.

[0085] On the opposite side of semiconductor device 400a, semiconductor device 400a is attached to drain contact 414 via sintered layer 412. Figure 4 In the example, semiconductor devices 400a and 400b are connected to drain connector 422 via a drain via 420, in which a drain contact 421 is provided. Other techniques for establishing the drain connection may also be used.

[0086] Further in Figure 4 In this process, semiconductor devices 400a and 400b are disposed and encapsulated within a core layer 401. The core layer 401 may comprise any suitable material or composite material, such as that used for semiconductor packaging. For example, the core layer 401 may be formed of FR-4 (flame retardant 4), a composite material of woven glass fiber impregnated with epoxy resin or other reinforcing materials. The core layer 401 may be provided with notches in which the semiconductor devices 400a and 400b are placed, and a metal connector 418 provides both mechanical and electrical connections for stability. Figure 4The entire semiconductor package. A thermal prepreg layer 416 is positioned across the core layer 401 and the bottom of the semiconductor devices 400a and 400b. The prepreg layer 416 typically refers to a reinforcing material, such as glass fiber or other fabric, impregnated with a partially cured resin (such as epoxy resin), which provides thermal and mechanical stability.

[0087] Figures 5A to 5C An example operation for forming a semiconductor device with double-sided electroplating is illustrated. Figure 11 (1102 in the middle). Figure 5A In this embodiment, semiconductor die 502 is illustrated with a sintered layer 506 disposed on its top side for attaching a metallization layer 508 to semiconductor die 502. A passivation layer 504 is disposed between portions of the sintered layer 106 and the metallization layer 108 to delineate and define future source and gate contact regions. On the opposite (bottom) side of semiconductor die 502, a sintered layer 510 is used for attaching a metallization layer 512 to semiconductor die 502.

[0088] exist Figure 5B In this process, a polyimide layer mask 514 is disposed on the first surface or top surface of the semiconductor die 502. A polyimide layer mask 516 is disposed on the second surface or bottom surface of the semiconductor die 502.

[0089] exist Figure 5C In this configuration, a top-side patterned metal 518 is formed on the first or top surface of the semiconductor die 502, for example, on the metallization layer 508, where the polyimide layer mask 514 is absent. Therefore, and as mentioned above and described in more detail below (e.g., regarding...), Figures 6A to 6C The source contact portion 520 and gate contact portion 522 can be defined for a single transistor device. In addition, a bottom-side patterned metal 524 is formed on the second surface or bottom surface of the semiconductor die 502, for example, on the metallization layer 512, where there is no polyimide layer mask 516 providing a drain contact portion for the transistor device.

[0090] For example, the patterned metals 518 and 524 can be formed using electroplating techniques (e.g., Cu electroplating). Electroplating can be performed using either electroless or current-based electroplating techniques. Electroplating can be performed simultaneously on both surfaces (top and bottom) of the semiconductor die 502, such that the patterned metals 518 and 524 are formed at approximately the same rate and have approximately the same thickness.

[0091] Figures 6A to 6C Further example operations for forming a semiconductor device with double-sided electroplating are illustrated. Figure 11 (1104 in the middle). Figure 6AIn this process, a top-side sealant 602 is provided above and around the entire top surface, and a bottom-side sealant 604 is provided above and around the entire bottom surface. Figure 6B In the process, top and bottom grinding operations are performed to produce a top layer 606 and a bottom layer 608, in which all patterned metal and surrounding sealant material are ground to a consistent, uniform height.

[0092] Then, in Figure 6C In this process, segmentation or dicing is performed to provide three separate, segmented devices 610, 612, and 614. Figure 6C In the example, splitting is performed to provide something similar to Figure 1A Devices 610, 612, and 614 are single-chip devices. In other examples, partitioning can be performed to provide... Figure 2 Multi-chip devices (e.g., dividing device 610 into single-chip devices and leaving the remaining devices 612 and 614 as multi-chip devices).

[0093] Figures 7A to 7C An example alternative operation for forming a semiconductor device with double-sided electroplating is illustrated. Figure 11 (1106 in the text). More specifically, Figures 7A to 7C follow Figures 5A to 5C The operation, and provides Figures 6A to 6C Alternative operations to the operations that provide the resulting chip with, for example, sidewall protection from the conductive anode wire (CAF).

[0094] exist Figure 7A In Figure 5C Following this operation, a partitioning process is performed to define devices 702, 704, and 706. Figure 7B In this process, the segmented components are placed within cavity 707 of the EMC core 708. As shown, cavity 707 is sized to provide sufficient clearance to accommodate the sealant. Then, in Figure 7C In this process, sealant 710 is disposed around the device within the EMC core 708 and is disposed on the core 708.

[0095] The EMC core 708 can be provided as a waffle tray, within which various cavities are defined to receive diced devices. For example, the original wafer may have a specific size and shape, such as a six-inch circular wafer. When diced and deposited into a core such as the core 708, a new panel size and shape determined by the core's size / shape can be effectively defined. In this way, a molded panel is provided.

[0096] Figure 8 Examples Figure 7C Examples of the results of the operation: grinding and cutting ( Figure 11 (1108, 1110 in the middle). Figure 8 In the middle, grinding Figure 7C The encapsulated device and EMC core 708 produce similar results Figure 6B The structure is 800, but the sidewalls 802, 804, 806, and 808 are remaining from the EMC core 708.

[0097] For example Figure 8 As illustrated, subsequent dicing (e.g., slicing or sawing) can be performed to obtain a single-chip package 810 and / or a multi-chip package 812. As shown, the single-chip package 810 is similar to... Figure 1A The single-chip package 812 has sawn / splittered sidewalls 814 and 816. The multi-chip package 812 is similar to... Figure 2 A multi-chip package, but with sawed / splittered sidewalls 818, 820 and the remaining sidewall (core portion) 806.

[0098] Figures 9A to 9C Examples of alternatives to the fourth, fifth, and sixth operations are illustrated for forming semiconductor devices with double-sided electroplating. Figure 11 (1112 in the middle). Figure 9A In, with Figure 7A Similarly, segmentation is performed to obtain semiconductor devices 904, 906, and 908. However, in Figure 9A In the illustration, semiconductor devices 904, 906, and 908 are shown positioned on wafer transfer strip 902.

[0099] Wafer transfer tape 902 is typically used to provide support during transport and processing operations. For example, wafer transfer tape 902 may be UV sensitive, such that exposure to ultraviolet light reduces the adhesion of wafer transfer tape 902 for subsequent processing (e.g., pick-up and placement) of each individual semiconductor die / device on wafer transfer tape 902.

[0100] exist Figure 9B As shown in the figure, matrix expansion is implemented to form spaces 910 and 912 between the individual semiconductor devices 904, 906, and 908. Generally, such matrix expansion refers to the process in which these increased spacings are formed to facilitate easier handling and prevent die damage during further processing. For example, an expansion machine can be used to uniformly expand the transfer band in both the X and Y directions, which separates the mounted dies. Such methods, for example, reduce the risk of die edge breakage or cracking and make die splitting and pick-and-place operations more reliable.

[0101] exist Figure 9C In the middle, add sealant 914. Subsequently, after removing transfer belt 902, grinding and further division can be performed, as per [reference needed]. Figure 8 The shown and described ( Figure 11 (1108 and 1110 in the middle).

[0102] Figures 10A to 10C An example operation is illustrated for forming a semiconductor device with double-sided plating and sidewall protection in the presence of a fan-out layer. Figure 11 (1114 in the middle). Figure 10A middle, Figure 8 Structure 800 undergoes further electroplating to add a top fan-out plating layer 1002 and a bottom fan-out plating layer 1004.

[0103] exist Figure 10B In this process, photolithography and etching operations can be performed to define individual source contacts 1006, 1010, 1014 and gate contacts 1008, 1012, 1016. Figure 10C In the process, the partitioning is performed to provide individual devices 1018, 1020, and 1022.

[0104] As shown in the figure, each segmented device includes protective EMC core sidewalls 1024 and 1026. As mentioned above, these sidewalls provide additional stability and reliability during processing, while also preventing CAF that could lead to short circuits or other device failures.

[0105] As can be further observed with respect to device 1018, fan-out layers 1006 and 1008 provide easy and reliable source and gate connections, respectively, while space 1028, together with fan-out layers 1006 and 1008, provides the aforementioned... Figure 1A The type of top-side patterned metal layer described.

[0106] exist Figure 10C In this embodiment, the bottom-side metal layer 1030, which provides easy and reliable drain connections, is illustrated as a uniform fan-out layer. That is, the bottom-side metal layer 1030 is not patterned, but rather uniform. However, the bottom-side metal layer 1030 can provide, for example, the aforementioned... Figure 1A Furthermore, it incorporates the stability types and anti-warping / crack prevention described in the top-side patterned metals 1006 and 1008. In an alternative embodiment, the bottom-side fan-out metal layer 1030 may be configured as described, for example, regarding... Figure 1A and / or Figure 1C The described method is similar to the way of patterning.

[0107] Figure 12 This is an example of a multi-chip semiconductor device 1200 with double-sided plating and sidewall protection, featuring a fan-out layer. Device 120 can be... Figure 10B It is formed after the operation. Device 1200 is conceptually similar to Figure 8 The multi-chip device 812, but including a fan-out layer. Device 1200 is also conceptually similar. Figure 2 The device 200, but with sidewall protection and fan-out layer.

[0108] More specifically, as shown in the figure, device 1200 includes, as about Figure 8 The sidewalls 806, 818, and 820 are described. Device 1200 also includes source electrodes 1202 and 1206 with fan-out layers, and corresponding gate electrodes 1204 and 1208, also with fan-out layers. Drain 1210 provides a common drain with a fan-out layer for the device (similar to...). Figure 10C (Public drain 1018).

[0109] Figure 13 This is a first example semiconductor device package for use with a semiconductor device having double-sided plating and sidewall protection in the presence of a fan-out layer. Specifically, Figure 13 It is about Figure 10C The example device 1018 is used for description.

[0110] exist Figure 13 In this configuration, semiconductor device 1018 is attached to substrate 1302 via interconnect layer 1304 (e.g., sintered layer). Sealant 1306 is disposed around semiconductor device 1018 and provides, for example, protection and isolation.

[0111] The substrate 1302 may represent any suitable mounting surface or mounting member in which the semiconductor device 1018 may be positioned. For example, the substrate 1302 may represent a lead frame, such as a metal lead frame (e.g., a copper lead frame).

[0112] Figure 13 The simplified example illustrates substrate 1302 as a single material, but substrate 1302 may also be composed of multiple materials. For example, substrate 1302 may include multiple layers in a DBM (e.g., DBC) structure. Substrate 1302 may be part of a larger printed circuit board (PCB) and panel assembly. Substrate 1302 may be implemented as or combined with a leadframe for providing external electrical connections to the high-power semiconductor device 1018.

[0113] Figure 14 This is a second example semiconductor device package for use with double-sided plating and sidewall protection in the case of a semiconductor device having a fan-out layer. Figure 14 In the device package, semiconductor device 1018a and semiconductor device 1018b typically correspond to Figure 10C Semiconductor device 1018. This mainly concerns the connections to semiconductor device 1018a and the packaging of this semiconductor device. Figure 14 Further description of the device package is provided, but it will be understood that similar descriptions also apply to semiconductor device 1018b and its corresponding connections and packages.

[0114] As shown in the figure, the source region of semiconductor device 1018a is attached to a plurality of source contacts 1405 established using source vias 1404 via a portion of sintered layer 1402, thereby defining a source connection 1406. Similarly, the gate region of semiconductor device 1018a is attached to a plurality of gate contacts 1409 established using gate vias 1408 via a portion of sintered layer 1402, thereby defining a gate connection 1410.

[0115] On the opposite side of semiconductor device 1018a, semiconductor device 1018a is attached to drain contact 1414 via sintered layer 1412. Figure 14 In the example, semiconductor devices 1018a and 1018b are connected to drain connector 1422 via a drain via 1420, in which a drain contact 1421 is provided. Other techniques for establishing the drain connection may also be used.

[0116] Further in Figure 14 In this process, semiconductor devices 1018a and 1018b are disposed and encapsulated within a core layer 1401. The core layer 1401 may comprise any suitable material or composite material, such as that used for semiconductor packaging. For example, the core layer 1401 may be formed of FR-4. The core layer 1401 may be provided with notches in which the semiconductor devices 1018a and 1018b are placed, and a metal connector 1418 provides both mechanical and electrical connections for stability. Figure 14 The entire semiconductor package. The thermal prepreg layer 1416 is positioned across the core layer 1401 and the bottom of the semiconductor devices 1018a and 1018b.

[0117] Figure 15 This is a third example of a semiconductor device package for use in semiconductor devices with double-sided plating and sidewall protection, featuring a fan-out layer. Similar to... Figure 14 , Figure 15 Provided corresponding Figure 10C Examples of packaged devices 1018a and 1018b of device 1018.

[0118] exist Figure 15 In this configuration, sintered layers 1502a and 1502b attach devices 1018a and 1018b to lead frames 1504a and 1504b, respectively. Lead frames 1504a and 1504b also provide drain connections for devices 1018a and 1018b, respectively. Device 1018a has a gate connection 1506a, and device 1018b has a gate connection 1506b. Device 1018a has a source connection 1508a, and device 1018b has a source connection 1508b.

[0119] Further in Figure 15In this process, semiconductor devices 1018a and 1018b are disposed and encapsulated within a core layer 1501. The core layer 1501 may comprise any suitable material or composite material, such as that used for semiconductor packaging. For example, the core layer 1501 may be formed of FR-4. A thermal prepreg layer 1516 is positioned across the core layer 1501 and the bottom of the semiconductor devices 1018a and 1018b, and is disposed on a metal layer 1510.

[0120] In some specific implementations, soldering can be or may include a process of joining two surfaces (e.g., metal surfaces) together using a molten filler metal that may be referred to as solder (e.g., metal alloys, tin (Sn), lead (Pb), silver (Ag), copper (Cu)).

[0121] In some embodiments, sintering can be, or may include, a process of fusing particles together into a solid substance using, for example, a combination of pressure and / or heat without melting the material. In some embodiments, sintering may include agglomerating a material (e.g., a powdered material) into a solid or porous substance by heating the material and typically also compressing it without liquefying it. In some embodiments, materials that can be used for sintering may include metals such as silver (Ag), copper (Cu), and / or metal alloys. In some embodiments, sintered joints may have desired electrical and / or thermal conductivity, durability, and a relatively high melting temperature.

[0122] In some specific implementations, materials such as solder, sintered (e.g., silver, copper) and / or other metal-to-metal bonding materials may be used to couple one or more components of the components described herein.

[0123] In some embodiments, a DBM substrate can be formed by bonding one or more metal layers (e.g., a first metal layer, a second metal layer) to an insulating layer. In some embodiments, one or more metal layers can be bonded to an insulating layer using, for example, a high-temperature process.

[0124] In some embodiments, the DBM substrate may include an insulating layer disposed between the first metal layer and the second metal layer. The insulating layer may be, for example, a ceramic layer. In some embodiments, the insulating layer may be, or may include, a ceramic material such as alumina (Al2O3) or aluminum nitride (AlN).

[0125] In some embodiments, one or more metal layers may be, or can be used as, a heat sink. In some embodiments, the one or more metal layers may be coupled to a heat sink. In some embodiments, at least a portion of the one or more metal layers may be exposed by a molding material.

[0126] In some embodiments, the one or more metal layers may be or may include patterned metal layers, which include one or more conductive traces. In some embodiments, the one or more metal layers may be or may include patterned layers configured to form one or more circuits and / or one or more conductive blind vias and / or vias, etc.

[0127] In some embodiments, the DBM substrate may be or may include a direct-bonded copper (DBC) substrate. In some embodiments, such as in a DBC substrate embodiment, the metal layer of the DBC may be or may include a copper layer.

[0128] In some embodiments, one or more semiconductor dies (e.g., one or more semiconductor components) may be or may include power semiconductor dies. In some embodiments, one or more semiconductor dies may be one or more of the following (e.g., may be part of one or more of the following) or may include one or more of the following: metal-oxide-semiconductor field-effect transistor (MOSFET) devices, insulated-gate bipolar transistors (IGBTs), integrated circuits (ICs), inverters, power conversion circuits, bridge circuits, fast recovery diodes (FRDs), and / or diodes, etc. In some embodiments, one or more semiconductor dies may be components for electric vehicles (EVs) (e.g., may be part of such components) or may include such components.

[0129] The specific embodiments described herein may include more than one semiconductor die. In some embodiments, different semiconductor substrates (e.g., silicon carbide (SiC substrate, silicon (Si) substrate, gallium nitride (GaN) substrate) may be used to fabricate different semiconductor dies (when more than one semiconductor die is included in some of these embodiments). In other words, different semiconductor dies may be fabricated, for example, on different semiconductor wafers or materials. This may be referred to as a hybrid die configuration. For example, a first semiconductor die may be formed using a SiC substrate, and a second semiconductor die (separate from the first semiconductor die) may be formed using a silicon substrate. As another example, an IGBT may be fabricated using a SiC substrate, while a controller may be fabricated using a silicon substrate.

[0130] In a specific embodiment of the example, the first semiconductor die may be connected to the second die, for example, via an electrical connection (e.g., a wire bond, an electrical clamp) extending directly from the first die into the second die, or via a trace formed in a first conductive layer (e.g., a metal layer) of the electronic power substrate. The first semiconductor die among a plurality of semiconductor dies may also be connected to leadframe posts via electrical connections (such as wire bonds or clamps).

[0131] In some exemplary embodiments, the package (e.g., a power module) may be a hybrid device package comprising one or more semiconductor dies integrated onto a unified electronic power substrate (e.g., a ceramic substrate, a DBM or DBC substrate, an AMB substrate, an elastomer substrate, an organic substrate, a phenolic substrate, or a PCB / FR-4 substrate). In some embodiments, multiple semiconductor devices may be fabricated, for example, on the same substrate (such as a SiC substrate) suitable for high-power applications.

[0132] Although referred to by way of example as a lead frame in at least some parts of this specific embodiment, the lead frame may include any type of conductive portion of the package (e.g., conductive portion, conductive terminal) that provides an external connection point from the package. Therefore, the lead frame may be referred to as a conductive portion of the package.

[0133] In some implementations, one or more portions of the leadframe may be coupled to pads (e.g., bonding pads) on at least a portion of the DBM substrate.

[0134] In some specific implementations, the molding material (e.g., molding material or compound, encapsulating material) may be or may include a non-conductive layer / material.

[0135] One or more wire bonds, which may be included in at least some of the embodiments described herein, may be replaced by conductive components. For example, in some embodiments, one or more wire bonds may be replaced by conductive clamps. Conductive clamps may be coupled to another component (e.g., attachment pads, lead frames, semiconductor dies, etc.) using, for example, solder (e.g., soldering process), sintered coupling (e.g., sintering process), welding, etc. In some embodiments, one or more wire bonds and / or clamps may serve as input and / or output power terminals, signal terminals, power terminals, etc.

[0136] In some implementations, one or more semiconductor dies may be embedded within a layer (rather than surface mounted). For example, one or more semiconductor dies may be disposed in a recess (or cavity) of a layer (e.g., a substrate, printed circuit board, conductive layer, insulating layer).

[0137] In some implementations, a module (e.g., a package including a semiconductor device) may be included within another module. A module may be referred to as a package. For example, one or more modules may be one or more sub-modules included within another module. In other words, a first module may be included as a sub-module within a second module.

[0138] It should be understood that in the foregoing description, when an element such as a layer, region, substrate, or component is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, no intermediate elements or layers are present. Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the specific embodiments, elements shown as being directly on, directly connected to, or directly coupled to an element can be referred to in this manner. The claims of this application, if any, may be amended to describe the exemplary relationships described in the specification or shown in the drawings.

[0139] As used in this specification and claims, the singular form may include the plural form unless the context clearly indicates otherwise. In addition to the orientations shown in the figures, spatially relative terms (e.g., above, on, above, below, under, beneath, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may respectively include vertically above and vertically below. In some embodiments, term proximity may include lateral proximity or horizontal proximity.

[0140] Some specific implementations can be achieved using various semiconductor processing and / or packaging technologies. Some specific implementations can be achieved using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0141] While certain features of the described embodiments have been exemplified as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail are possible. Any parts of the apparatus and / or method described herein can be combined in any way, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

[0142] While certain features of the specific embodiments described herein have been exemplified, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the embodiments.

Claims

1. A semiconductor device package, characterized in that, The semiconductor device package includes: A semiconductor device having a first side and a second side opposite to the first side; A first metallization layer is disposed on the first side; A first metal layer is formed on the first metallization layer, the first metal layer includes a first pattern defined by a first space, the first space including a first non-conductive material formed on the first metallization layer; A second metallization layer is disposed on the second side; and A second metal layer is formed on the second metallization layer.

2. The semiconductor device package of claim 1, wherein the second metal layer includes a second pattern defined by a second space, the second space including a second non-conductive material formed on the second metallization layer.

3. The semiconductor device package according to claim 2, wherein the semiconductor device package further comprises a first sealant disposed in the first space and located on the first non-conductive material, and a second sealant disposed in the second space and located on the second non-conductive material.

4. The semiconductor device package of claim 3, wherein the first sealant and the first metal layer are ground to a first uniform height, and the second sealant and the second metal layer are ground to a second uniform height.

5. The semiconductor device package of claim 4, wherein the first uniform height and the second uniform height are equal.

6. The semiconductor device package of claim 2, wherein the first space includes a plurality of first spaces defining a first stress relief line, and the second space includes a plurality of second spaces defining a second stress relief line.

7. The semiconductor device package of claim 2, wherein the second pattern is based on the first pattern to provide mechanical stress relief for the semiconductor device.

8. The semiconductor device package of claim 1, wherein the first space comprises a sealant, and the first metal layer and the sealant are ground to a uniform height.

9. The semiconductor device package of claim 1, wherein the semiconductor device package further comprises: An insulating sidewall is disposed on one side of the semiconductor device and extends from the first metal layer to the second metal layer.

10. The semiconductor device package of claim 1, wherein the semiconductor device package further comprises: A fan-out layer is disposed on the first metal layer and extends above the first space, and contacts the first metal layer on both sides of the first space.

11. A package for embedded semiconductor devices, characterized in that, The package includes: substrate; A semiconductor device disposed on the substrate, the semiconductor device having a first side and a second side opposite to the first side; A first metallization layer is disposed on the first side; A first metal layer is formed on the first metallization layer and includes a first stress relief pattern defined by a first metal layer portion and a second metal layer portion, having a first space between the first metal layer portion and the second metal layer portion, the first space including a first non-conductive material formed on the first metallization layer. A second metallization layer is disposed on the second side; A second metal layer is formed on the second metallization layer; and A sealant that secures the semiconductor device, the first metal layer, and the second metal layer to the substrate.

12. The package of claim 11, wherein the second metal layer includes a second stress-relief pattern defined by a second space, the second space including a second non-conductive material formed on the second metallization layer.

13. The package of claim 12, wherein the second pattern is based on the first stress-relief pattern to provide mechanical stress relief for the semiconductor device.

14. The package of claim 12, wherein the first space includes a plurality of first spaces defining a first stress relief line, and the second space includes a plurality of second spaces defining a second stress relief line.

15. The package of claim 11, wherein the package further comprises: An insulating sidewall is disposed on one side of the semiconductor device and extends from the first metal layer to the second metal layer.

16. A method for forming a semiconductor device package, characterized in that, The method includes: A first metallization layer is formed on a first side of the semiconductor device; A second metallization layer is formed on the second side of the semiconductor device opposite to the first side; A first metal layer is formed on the first metallization layer, the first metal layer including a first pattern defined by a first space; A first non-conductive material is formed in the first space and on the first metallization layer; and A second metal layer is formed on the second metallization layer.

17. The method of claim 16, wherein the method further comprises: A second metal layer is formed having a second pattern defined by a second space, the second space including a second non-conductive material formed on the second metallization layer.

18. The method of claim 17, wherein the method further comprises: The second pattern is formed based on the first pattern to provide mechanical stress relief for the semiconductor device.

19. The method of claim 17, wherein the method further comprises: A first sealant is formed in the first space and located on the first non-conductive material, and a second sealant is formed in the second space and located on the second non-conductive material.

20. The method of claim 16, wherein the method further comprises: An insulating sidewall is formed, which is disposed on one side of the semiconductor device and extends from the first metal layer to the second metal layer.

Images