Chip and method for writing data to a flash memory
By introducing a FLASH controller and a DMA controller during the data writing process of the FLASH memory, automatic data transfer and writing are achieved, solving the problem of excessive processing time caused by CPU intervention, improving the chip's responsiveness and execution efficiency, while maintaining economic efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN HANGSHUN CHIP TECH DEV CO LTD
- Filing Date
- 2026-05-29
- Publication Date
- 2026-08-04
AI Technical Summary
In the traditional process of writing data to FLASH memory, the CPU needs to intervene throughout the entire process, which consumes a lot of processing time and affects the chip's responsiveness and execution efficiency.
It adopts a chip structure that includes a CPU, a FLASH controller, a DMA controller, and an SRAM memory. It triggers DMA requests through error flags to realize the automatic transfer and writing of data from FLASH memory to SRAM memory, avoiding CPU intervention.
It reduces CPU processing time, improves chip responsiveness and execution efficiency, and does not increase chip cost, making it economical.
Smart Images
Figure CN122284931B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, specifically to a chip and a method for writing data to a FLASH memory. Background Technology
[0002] Flash memory, as a non-volatile storage medium, is widely used in various electronic devices to store program code, user data, and other information. The physical characteristics of flash memory dictate that an erase operation is typically performed on a sector-by-sector basis before a write operation can be performed. When only a small amount of data in a sector needs to be modified (such as a byte, a half-word, or a word), the traditional software-driven write process follows the basic paradigm of "read-modify-write back".
[0003] Specifically, traditional solutions rely on the central processing unit (CPU) for full control and intervention. When application software needs to update the content stored at a certain address in FLASH, the CPU performs the following steps: First, the CPU reads all the data in the entire sector containing the target address from FLASH and moves it to the cache of Static Random Access Memory (SRAM); second, the CPU locates the data to be modified in the SRAM cache and writes the new target data to that location, completing the data update; subsequently, the CPU controls the erasure of the target sector in FLASH; finally, the CPU moves the updated data of the entire sector in the SRAM cache back to the erased FLASH sector.
[0004] In the process of writing data to the FLASH memory, each step requires the CPU to issue an instruction and wait for completion, which can easily consume a lot of CPU processing time, increase the system's operating burden, and affect the responsiveness and execution efficiency of the corresponding chip. Summary of the Invention
[0005] In view of this, this application provides a chip and a method for writing data to a FLASH memory, so as to reduce the burden on the CPU when writing data to the FLASH memory.
[0006] This application provides a chip, which includes a CPU, a FLASH controller, a FLASH memory, a DMA controller, and an SRAM memory; The FLASH controller is used to receive FLASH write requests sent by the CPU and write target data to the first target address of the FLASH memory; The FLASH memory is used to trigger an error flag when the data in the first target address is not preset data; The FLASH controller is also used to respond to the error flag by sending a DMA request to the DMA controller; The DMA controller is also configured to respond to the DMA request by configuring the DMA source address as the starting address of the FLASH sector to be written, configuring the second target address as the starting address of the SRAM cache, and sending a first transfer instruction to the FLASH controller. The FLASH controller is also configured to respond to the first transfer command by reading data from the FLASH sector and transmitting the read data to the DMA controller; The DMA controller is also configured to write received data to the SRAM memory according to the configured DMA source address and the second target address, so as to move the data of the FLASH sector from the FLASH memory to the SRAM memory; The FLASH controller is also used to erase the contents of the FLASH sector after the data transfer is completed; The DMA controller is also used to exchange the DMA source address and the second target address, and to write the target data to the SRAM memory according to the first target address; The DMA controller is also used to move data between the DMA source address and the second target address to the FLASH memory.
[0007] Optionally, the FLASH controller is further configured to determine that data writing is complete when the data in the first target address of the FLASH memory is preset data.
[0008] Optionally, the DMA controller is further configured to transmit data between the DMA source address and the second target address to the FLASH controller; the FLASH controller is further configured to write the received data to the FLASH sector.
[0009] Optionally, the DMA controller includes a register and an address switching module; the register is used to cache data transmitted by the FLASH controller and / or to the FLASH controller; the address switching module is used to exchange the DMA source address and the second target address.
[0010] Optionally, the CPU is configured to receive a data write instruction to send the FLASH write request and the target data to the FLASH controller.
[0011] This application also provides a method for writing data to a FLASH memory, including: The FLASH controller receives the FLASH write request sent by the CPU and writes the target data to the first target address of the FLASH memory; If the data in the first target address in the FLASH memory is not the preset data, an error flag is triggered so that the FLASH controller receives the error flag and sends a DMA request to the DMA controller. The DMA controller responds to the DMA request by configuring the DMA source address as the starting address of the FLASH sector to be written, configuring the second target address as the starting address of the SRAM cache, and sending a first transfer instruction to the FLASH controller. The FLASH controller responds to the first transfer command by reading data from the FLASH sector and transmitting the read data to the DMA controller; The DMA controller writes the received data to the SRAM memory according to the configured DMA source address and the second target address, so as to move the data of the FLASH sector from the FLASH memory to the SRAM memory; After the data migration is completed, the FLASH controller erases the contents of the FLASH sector; The DMA controller exchanges the DMA source address and the second target address, and writes the target data into the SRAM memory according to the first target address; The DMA controller moves the data between the DMA source address and the second target address to the FLASH memory.
[0012] Optionally, the method for writing data to the FLASH memory further includes: if the data at the target address in the FLASH memory is preset data, then the data writing is determined to be complete.
[0013] Optionally, the DMA controller moves the data between the DMA source address and the second target address to the FLASH memory, including: the DMA controller transmitting the data between the DMA source address and the second target address to the FLASH controller; and the FLASH controller writing the received data to the FLASH sector.
[0014] Optionally, the method for writing data to the FLASH memory further includes: the CPU receiving a data write instruction and sending the FLASH write request and the target data to the FLASH controller.
[0015] The chip and method for writing data to FLASH memory described in this application can trigger an error flag when the data at the first target address is not preset data. This causes the FLASH controller to respond to the error flag and send a DMA request to the DMA controller. The DMA controller responds to the DMA request by configuring the DMA source address as the starting address of the FLASH sector to be written to and the second target address as the starting address of the SRAM cache. Based on the configured DMA source address and second target address, the data in the FLASH sector is moved from the FLASH memory to the SRAM memory, so that the SRAM memory stores the content to be written to the FLASH sector. The FLASH controller then performs the data transfer... After the migration is complete, the contents of the FLASH sector are erased. The DMA controller swaps the DMA source address and the second target address, and writes the target data to the FLASH memory according to the first target address to write the target data into the corresponding content. The DMA controller then moves the data between the DMA source address and the second target address to the FLASH memory to move the content after the target data is written in the SRAM memory into the FLASH memory. In this way, the corresponding target data is written to the FLASH memory without CPU intervention, which can avoid occupying too much CPU processing time, reduce the chip's operating burden, improve the chip's responsiveness and execution efficiency, and does not increase the chip cost, thus having good economic benefits. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of a chip structure according to an embodiment of this application; Figure 2 This is a schematic diagram of the chip portion structure according to an embodiment of this application; Figure 3 This is a schematic diagram of a chip structure according to another embodiment of this application; Figure 4 This is a schematic diagram of the chip portion structure according to another embodiment of this application; Figure 5 This is a schematic flowchart of a method for writing data to a FLASH memory according to an embodiment of this application. Detailed Implementation
[0018] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.
[0019] The first aspect of this application provides a chip, with reference to... Figure 1 As shown, the chip includes a CPU, a FLASH controller, a FLASH memory, a DMA (Direct Memory Access) controller, and an SRAM memory.
[0020] The CPU can connect to the FLASH controller to issue relevant instructions. The FLASH controller connects to both the FLASH memory and the DMA controller to control data reading and writing in the FLASH memory and to transfer data between the FLASH memory and the DMA controller. The DMA controller also connects to the SRAM memory to control data reading and writing in the SRAM memory. The DMA controller enables high-speed data transfer between the FLASH memory and SRAM memory without CPU intervention, supporting memory-to-memory transfer mode. The FLASH controller is responsible for controlling the erasure, programming, and read operations of the FLASH memory, and automatically initiates a DMA request signal when an error flag (PGERR) is detected.
[0021] Specifically, the CPU can obtain data write instructions from external control terminals and / or user input, extract the FLASH write request and target data from the data write instructions, and send information such as the FLASH write request, the first target address, and the target data to the FLASH controller. The FLASH controller can respond to the FLASH write request and write the target data to the first target address of the FLASH memory. The connection relationship between the FLASH controller, FLASH memory, DMA controller, and SRAM memory can be found in [reference needed]. Figure 2 As shown, the following workflow may be included: The FLASH controller is used to receive FLASH write requests sent by the CPU and write target data to the first target address of the FLASH memory.
[0022] The FLASH memory is used to trigger an error flag when the data at the first target address is not preset data. The preset data may include data such as 0xFFFFFFFF, which indicates that the current state is erased and corresponding data can be directly written to the FLASH memory. Specifically, if the data at the first target address is not the preset data 0xFFFFFFFF, then directly writing the target data to the FLASH memory will trigger an error flag (PGERR). If the data at the first target address is the preset data 0xFFFFFFFF, then the target data can be directly written to the FLASH memory without triggering an error flag.
[0023] The FLASH controller is also used to respond to the error flag by sending a DMA request to the DMA controller. The DMA request is used to request that the contents of the FLASH sector to be written be written to the SRAM memory.
[0024] The DMA controller is also used to respond to the DMA request by configuring the DMA source address as the starting address of the FLASH sector to be written, configuring the second target address as the starting address of the SRAM cache, and sending a first transfer instruction to the FLASH controller. Specifically, the source address register of the DMA controller can be automatically loaded with the base address of the FLASH sector corresponding to the PGERR trigger, the register corresponding to the second target address can be loaded with the preset base address of the SRAM cache, and the transfer length can be automatically configured to the size of the corresponding FLASH sector (such as 128KB, 256KB, or 512KB, etc.) so that the data space between the configured DMA source address and the second target address is consistent with the data space of the corresponding FLASH sector.
[0025] The FLASH controller is also used to respond to the first transfer command, read data from the FLASH sector, and transmit the read data to the DMA controller.
[0026] The DMA controller is also used to write the received data to the SRAM memory according to the configured DMA source address and the second target address, so as to move the data of the FLASH sector from the FLASH memory to the SRAM memory, thereby realizing automatic backup and writing of FLASH sector data without the need to add a dedicated hardware module.
[0027] The FLASH controller is also used to erase the contents of the FLASH sector after the data transfer is completed.
[0028] The DMA controller is also used to exchange the DMA source address and the second target address, and to write the target data to the SRAM memory according to the first target address.
[0029] The DMA controller is also used to move the data between the DMA source address and the second target address in the SRAM memory to the FLASH memory, thereby writing the target data into the FLASH memory.
[0030] In some examples, the FLASH controller is also used to determine that data writing is complete when the data in the first target address of the FLASH memory is preset data.
[0031] The aforementioned chip can trigger an error flag when the data at the first target address is not the preset data. This causes the FLASH controller to respond to the error flag and send a DMA request to the DMA controller. The DMA controller responds to the DMA request by configuring the DMA source address as the starting address of the FLASH sector to be written and the second target address as the starting address of the SRAM cache. Based on the configured DMA source address and second target address, the data of the FLASH sector is moved from the FLASH memory to the SRAM memory so that the SRAM memory can store the content to be written to the FLASH sector. After the data is moved, the FLASH controller erases the content of the FLASH sector. The DMA controller then swaps the DMA source address and the second target address and writes the target data to the FLASH memory according to the first target address to write the target data into the corresponding content. The DMA controller then moves the data between the DMA source address and the second target address to the FLASH memory to move the content after the target data is written in the SRAM memory into the FLASH memory. This process writes the corresponding target data to the FLASH memory without CPU intervention, avoiding excessive CPU processing time, reducing the chip's operating burden, improving the chip's responsiveness and execution efficiency, and without increasing chip cost, thus exhibiting good economic efficiency.
[0032] In some embodiments, the DMA controller is further configured to transmit data between the DMA source address and the second target address to the FLASH controller, so that the FLASH controller writes the received data to the corresponding FLASH sector in the FLASH memory, thereby realizing the writing of the target data into the FLASH memory.
[0033] In some examples, reference Figure 3 As shown, the DMA controller includes registers and an address switching module. The registers may include double-buffered address registers, and the address switching module may be implemented using a logic operation module or logic operation circuit for hardware address switching.
[0034] The register is used to cache the data transmitted by the FLASH controller, so that the DMA controller writes the data cached in the register into the SRAM memory; the register can also be used to cache the data transmitted to the FLASH controller, so that the DMA controller transmits the data cached in the register to the FLASH controller.
[0035] The address switching module is used to exchange the DMA source address and the second target address, enabling the DMA controller to integrate address switching logic. Specifically, when the first data transfer (FLASH memory → SRAM memory) is completed and an interrupt or status flag is generated, the corresponding flag signal can trigger the address switching logic, swapping the contents of the source address register and the target address register (corresponding to the second target address). Simultaneously, after the FLASH controller's erase completion signal, a second DMA request can be automatically triggered, initiating data write-back between the SRAM memory and the FLASH memory.
[0036] Optionally, the DMA controller may also include a DMA hardware trigger input, which can be used to receive relevant signals sent by the FLASH controller. For example, the error output (PGERR signal) of the FLASH controller can be connected to the hardware trigger input of the DMA controller so that the FLASH controller responds to the error flag and sends a DMA request to the DMA controller.
[0037] In some examples, reference Figure 4 As shown, the FLASH controller can be configured with structures such as an error detection module and / or an address management module.
[0038] The error detection module can be used to monitor the write status of the FLASH memory in real time. When an error flag (PGERR) is detected, the FLASH controller will automatically trigger a DMA request to start the data backup process. For example, the error detection module can detect the error flag triggered by the FLASH memory, and make the FLASH controller respond to the error flag and send a DMA request to the DMA controller.
[0039] The address management module is responsible for managing information such as source and destination addresses transmitted between the DMA controller and the DMA controller. During the PGERR triggering phase, the DMA source address is configured to the address corresponding to the FLASH sector, and the second destination address is configured to the SRAM cache address. During the write phase after erasure, the address switching module automatically switches the source / destination addresses, making the SRAM memory the data source and the FLASH memory the target space to be written. For example, the address management module can obtain or manage address information such as the starting address of the FLASH sector, so that the FLASH controller can perform operations such as sending the starting address of the FLASH sector to the DMA controller.
[0040] In some embodiments, the CPU is used to receive data write instructions, such as data write instructions input by an external control terminal and / or a user, extract FLASH write requests and target data from the data write instructions, and send information such as FLASH write requests, a first target address, and target data to the FLASH controller. The first target address refers to a specific address in the FLASH memory, that is, the space address where target data needs to be written to the FLASH memory. For example, if the external control terminal can write target data 0x12345678 to address 0x8000400, then the first target address is 0x8000400.
[0041] The above chips integrate a standard FLASH controller and a general-purpose DMA controller internally. Through the interactive and coordinated control between the two, data can be transferred between FLASH memory and SRAM memory, greatly reducing the CPU load, resulting in high efficiency. Furthermore, it utilizes existing peripherals without increasing chip costs, making it economical. DMA requests can be automatically triggered by the chip's internal structure (i.e., PGERR triggering), avoiding the involvement of complex control programs and achieving true automated writing, avoiding the delays of software polling or interrupt handling. The automatic address switching mechanism further reduces software configuration overhead. Traditional methods require software to configure two DMA transfers (including read and write), while the above chips can automatically complete address switching through their internal structure. The software program loaded by the CPU only needs to monitor the final completion status. Therefore, the above chips have advantages such as low operating burden and cost, high responsiveness, and high execution efficiency.
[0042] A second aspect of this application provides a method for writing data to a FLASH memory, which can be executed by the chip described in any of the above embodiments.
[0043] refer to Figure 5 As shown, the method for writing data to the FLASH memory includes steps S110 to S170.
[0044] S110, the FLASH controller receives the FLASH write request sent by the CPU and writes the target data to the first target address of the FLASH memory.
[0045] S120, if the data in the first target address in the FLASH memory is not preset data, an error flag is triggered so that the FLASH controller receives the error flag and sends a DMA request to the DMA controller.
[0046] S130, the DMA controller responds to the DMA request by configuring the DMA source address as the starting address of the FLASH sector to be written and configuring the second target address as the starting address of the SRAM cache.
[0047] S140, the DMA controller moves the data of the FLASH sector from the FLASH memory to the SRAM memory according to the configured DMA source address and the second target address.
[0048] In some examples, step S140 above, in which the DMA controller moves data from the FLASH memory to the SRAM memory according to the configured DMA source address and the second target address, may include steps S141 to S143.
[0049] S141, the DMA controller sends a first transfer command to the FLASH controller; S142, the FLASH controller responds to the first transfer command, reads data from the FLASH sector, and transmits the read data to the DMA controller; S143, the DMA controller writes the received data (i.e., the data of the FLASH sector) to the SRAM memory according to the configured DMA source address and the second target address, so as to move the data of the FLASH sector from the FLASH memory to the SRAM memory.
[0050] S150, after the data transfer is completed, the FLASH controller erases the contents of the FLASH sector.
[0051] S160, the DMA controller exchanges the DMA source address and the second target address, and writes the target data to the SRAM memory according to the first target address.
[0052] S170, the DMA controller moves the data between the DMA source address and the second target address to the FLASH memory.
[0053] Optionally, the method for writing data to the FLASH memory further includes: S121, if the data in the target address of the FLASH memory is preset data, then an error flag is not triggered, and the data writing is determined to be complete.
[0054] In some embodiments, the DMA controller moves the data between the DMA source address and the second target address to the FLASH memory, including steps S171 to S172.
[0055] S171, the DMA controller reads the data between the DMA source address and the second target address from the SRAM memory, and transmits the data between the DMA source address and the second target address to the FLASH controller; S172, the FLASH controller writes the received data (i.e., the data between the DMA source address and the second target address in the SRAM memory) to the FLASH sector.
[0056] In some embodiments, the method of writing data to the FLASH memory further includes: the CPU receiving a data write instruction and sending the FLASH write request and the target data to the FLASH controller.
[0057] The method for writing data to a FLASH memory provided in this application can be executed by the chip described in any of the above embodiments, and has all the technical effects of the chip described in any of the above embodiments, which will not be repeated here.
[0058] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.
[0059] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.
[0060] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0061] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.
Claims
1. A chip, characterized in that, The chip includes a CPU, a FLASH controller, a FLASH memory, a DMA controller, and an SRAM memory; The FLASH controller is used to receive FLASH write requests sent by the CPU and write target data to the first target address of the FLASH memory; The FLASH memory is used to trigger an error flag when the data in the first target address is not preset data; The FLASH controller is also used to respond to the error flag by sending a DMA request to the DMA controller; The DMA controller is also configured to respond to the DMA request by configuring the DMA source address as the starting address of the FLASH sector to be written, configuring the second target address as the starting address of the SRAM cache, and sending a first transfer instruction to the FLASH controller. The FLASH controller is also configured to respond to the first transfer command by reading data from the FLASH sector and transmitting the read data to the DMA controller; The DMA controller is also configured to write received data to the SRAM memory according to the configured DMA source address and the second target address, so as to move the data of the FLASH sector from the FLASH memory to the SRAM memory; The FLASH controller is also used to erase the contents of the FLASH sector after the data transfer is completed; The DMA controller is also used to exchange the DMA source address and the second target address, and to write the target data to the SRAM memory according to the first target address; The DMA controller is also used to move data between the DMA source address and the second target address to the FLASH memory.
2. The chip according to claim 1, characterized in that, The FLASH controller is also used to determine that the data writing is complete when the data in the first target address of the FLASH memory is preset data.
3. The chip according to claim 1, characterized in that, The DMA controller is also used to transmit data between the DMA source address and the second target address to the FLASH controller; The FLASH controller is also used to write received data to the FLASH sector.
4. The chip according to claim 3, characterized in that, The DMA controller includes registers and an address switching module; The register is used to cache data transmitted by the FLASH controller and / or data transmitted to the FLASH controller; The address switching module is used to exchange the DMA source address and the second target address.
5. The chip according to claim 3, characterized in that, The CPU is used to receive data write instructions to send the FLASH write request and the target data to the FLASH controller.
6. A method for writing data to a FLASH memory, characterized in that, The method for writing data to the FLASH memory includes: The FLASH controller receives the FLASH write request sent by the CPU and writes the target data to the first target address of the FLASH memory; If the data in the first target address in the FLASH memory is not the preset data, an error flag is triggered so that the FLASH controller receives the error flag and sends a DMA request to the DMA controller. The DMA controller responds to the DMA request by configuring the DMA source address as the starting address of the FLASH sector to be written, configuring the second target address as the starting address of the SRAM cache, and sending a first transfer instruction to the FLASH controller. The FLASH controller responds to the first transfer command by reading data from the FLASH sector and transmitting the read data to the DMA controller; The DMA controller writes the received data to the SRAM memory according to the configured DMA source address and the second target address, so as to move the data of the FLASH sector from the FLASH memory to the SRAM memory; After the data migration is completed, the FLASH controller erases the contents of the FLASH sector; The DMA controller exchanges the DMA source address and the second target address, and writes the target data into the SRAM memory according to the first target address; The DMA controller moves the data between the DMA source address and the second target address to the FLASH memory.
7. The method for writing data to a FLASH memory according to claim 6, characterized in that, The method for writing data to the FLASH memory further includes: If the data at the target address in the FLASH memory is the preset data, then the data writing is considered complete.
8. The method for writing data to a FLASH memory according to claim 6, characterized in that, The DMA controller moves the data between the DMA source address and the second target address to the FLASH memory, including: The DMA controller transmits the data between the DMA source address and the second target address to the FLASH controller; The FLASH controller writes the received data to the FLASH sector.
9. The method for writing data to a FLASH memory according to claim 6, characterized in that, The method for writing data to the FLASH memory further includes: The CPU receives a data write instruction and sends the FLASH write request and the target data to the FLASH controller.