Display panel and driving method of pixel circuit

Abstract

This invention relates to the field of display technology and discloses a display panel and a driving method for pixel circuits. The display panel includes multiple sub-pixels, a first power line, a second power line, and a power chip. The power chip provides a first power signal to the multiple sub-pixels through the first and second power lines. Each sub-pixel includes a pixel circuit. The pixel circuit includes a first initialization module for transmitting the first power signal to a first node according to a first scan signal; a threshold compensation module for turning on or off the connection between a second node and a third node according to a second scan signal; a data writing module for transmitting a data signal to the first node according to a third scan signal; a first storage module connected between the first node and the second node; a second storage module connected between the first node and the first power line; and a driving module whose gate is connected to the second node. The above-described display panel uses the first power signal to reset the first node, which improves display uniformity.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a driving method for a display panel and pixel circuits. Background Technology

[0002] In the display process of AMOLED (Active-matrix organic light-emitting diode) display panels, pixel driving circuits drive the light-emitting devices to emit light. As the market demands increasingly higher pixel resolution for display devices, high PPI (Pixels Per Inch) products have become the mainstream products in the market. However, in related technologies, high PPI products suffer from poor uniformity and cannot meet application requirements. Summary of the Invention

[0003] Therefore, it is necessary to provide a driving method for the display panel and pixel circuit to address the problems existing in the current pixel circuit.

[0004] A display panel includes a display area and a non-display area surrounding the display area. The display panel includes a substrate and a plurality of sub-pixels disposed on the substrate and located in the display area. The display panel also includes a first power line, a second power line, and a power chip located in the non-display area. The first power line and the second power line are respectively connected to the power chip and the plurality of sub-pixels. The power chip is used to provide a first power signal to the plurality of sub-pixels through the first power line and the second power line.

[0005] Each of the plurality of sub-pixels includes a pixel circuit, the pixel circuit comprising: The first initialization module is connected to the second power line and the first node respectively, and is used to transmit the first power signal to the first node according to the first scan signal; A threshold compensation module, connected between the second node and the third node, is used to turn on or off the connection between the second node and the third node according to the second scan signal; The data writing module is connected to the first node and is used to transmit data signals to the first node according to the third scan signal; A first storage module is connected between the first node and the second node and is used to store the voltage difference between the first node and the second node; The second storage module is connected between the first node and the first power line and is used to store the voltage difference between the first node and the first power line. A driving module is connected between the first power line and the light-emitting device. The control terminal of the driving module is connected to the second node, and the second terminal of the driving module is connected to the third node. It is used to output a driving signal according to the potential at the second node.

[0006] In one possible implementation, the first power line includes a plurality of first sub-power lines extending along a first direction and a plurality of second sub-power lines extending along a second direction, wherein the plurality of first sub-power lines and the plurality of second sub-power lines are cross-connected to form a first mesh structure, and the second power line includes a plurality of third sub-power lines extending along the first direction and a plurality of fourth sub-power lines extending along the second direction, wherein the plurality of third sub-power lines and the plurality of fourth sub-power lines are cross-connected to form a second mesh structure, wherein the first direction intersects the second direction; In the first direction, the second sub-power line and the fourth sub-power line are arranged alternately, and in the second direction, the first sub-power line and the third sub-power line are arranged alternately.

[0007] In one possible implementation, the first power line further includes a first connection portion located in the non-display area and connected to the power chip, at least a portion of the second sub-power line extends from the display area to the non-display area and is connected to the first connection portion, the second power line further includes a second connection portion located in the non-display area and connected to the power chip, and at least a portion of the fourth sub-power line extends from the display area to the non-display area and is connected to the second connection portion.

[0008] In one possible implementation, the first power line further includes a first extension located in the non-display area, the first extension being connected to the first mesh structure, and the first extension being disposed around at least a portion of the display area; the second power line further includes a second extension located in the non-display area, the second extension being connected to the second mesh structure, and the second extension being disposed around at least a portion of the display area.

[0009] In one possible implementation, in the second direction, the non-display area includes a first sub-non-display area and a second sub-non-display area. Along the second direction, the display area is located between the first sub-non-display area and the second sub-non-display area. The first extension and the second extension are disposed in the first sub-non-display area. The power chip, the first connection portion, and the second connection portion are disposed in the second sub-non-display area. At least a portion of the second sub-power line extends from the display area to the first sub-non-display area and connects to the first extension portion. At least a portion of the fourth sub-power line extends from the display area to the second sub-non-display area and connects to the second extension portion. In one possible implementation, the driving module includes a first transistor. The gate of the first transistor serves as the control terminal of the driving module and is connected to the second node. The first electrode of the first transistor serves as the first terminal of the driving module, and the second electrode of the first transistor serves as the second terminal of the driving module.

[0010] In one possible implementation, the data writing module includes a second transistor, the gate of the second transistor being connected to the third scan signal as the control terminal of the data writing module, the first terminal of the second transistor being connected to the data signal as the first terminal of the data writing module, and the second terminal of the second transistor being connected to the first node as the second terminal of the data writing module.

[0011] In one possible implementation, the threshold compensation module includes a third transistor, the gate of which serves as the control terminal of the threshold compensation module and is connected to the second scan signal, the first terminal of which serves as the first terminal of the threshold compensation module and is connected to the second node, and the second terminal of which serves as the second terminal of the threshold compensation module and is connected to the second terminal of the driving module.

[0012] In one possible implementation, the first initialization module includes a fourth transistor, the gate of which serves as the control terminal of the first initialization module and is connected to the first scan signal, the first electrode of which serves as the first terminal of the first initialization module and is connected to a second power supply line, and the second electrode of which serves as the second terminal of the first initialization module and is connected to the first node.

[0013] In one possible implementation, the fourth transistor is a dual-gate transistor, wherein both the first gate and the second gate of the fourth transistor are connected to the first scan signal.

[0014] In one possible implementation, the first storage module includes a first capacitor, with a first terminal of the first capacitor connected to the first node as a first end of the first storage module, and a second terminal of the first capacitor connected to the second node as a second end of the first storage module.

[0015] In one possible implementation, the second storage module includes a second capacitor, with the first terminal of the second capacitor serving as the first end of the second storage module and connected to the first node, and the second terminal of the second capacitor serving as the second end of the second storage module and connected to the first power line.

[0016] In one possible implementation, the pixel circuit further includes: A light-emitting module, connected between the third node and the third power line, is used to emit light according to the driving signal; the third power line is used to transmit a second power signal. The pixel circuit includes a non-light-emitting stage and a light-emitting stage. The level of the second power supply signal in the non-light-emitting stage is a first level, and the level of the second power supply signal in the light-emitting stage is a second level. The first level is greater than the second level.

[0017] In one possible implementation, the first level is greater than a first preset value, which is determined based on the potential at the third node when the driving module is turned on.

[0018] In one possible implementation, a second initialization module, connected to the third node, is used to transmit a first initialization signal to the third node according to a fourth scan signal.

[0019] In one possible implementation, the second initialization module includes a fifth transistor, the gate of which serves as the control terminal of the second initialization module and is connected to the fourth scan signal, the first terminal of which serves as the first terminal of the second initialization module and is connected to the first initialization signal, and the second terminal of which serves as the second terminal of the second initialization module and is connected to the third node.

[0020] In one possible implementation, the first initialization signal is less than zero.

[0021] In one possible implementation, the pixel circuit further includes: A light-emitting control module is connected between the first end of the driving module and the first power line, and is used to turn on or off the connection between the first end of the driving module and the first power line according to the light-emitting control signal.

[0022] In one possible implementation, the light-emitting control module includes a sixth transistor, the gate of which serves as the control terminal of the light-emitting control module and is connected to the light-emitting control signal, the first electrode of which serves as the first terminal of the light-emitting control module and is connected to the first power line, and the second electrode of which serves as the second terminal of the light-emitting control module and is connected to the first terminal of the driving module.

[0023] In one possible implementation, the pixel circuit further includes: The third initialization module is connected to the first end of the driving module and is used to transmit the second initialization signal to the first end of the driving module according to the fourth scan signal.

[0024] In one possible implementation, the third initialization module includes a seventh transistor, the gate of which serves as the control terminal of the third initialization module and is connected to the fourth scan signal, the first terminal of which serves as the first terminal of the third initialization module and is connected to the second initialization signal, and the second terminal of which serves as the second terminal of the third initialization module and is connected to the first terminal of the driving module.

[0025] In one possible implementation, the second initialization signal is less than a second preset value, which is determined based on the first power signal and the threshold information of the drive module.

[0026] In one possible implementation, the pixel circuit includes an initialization phase in one operating cycle. In the initialization phase, the first initialization module transmits the first power signal to the first node according to the first scan signal, the threshold compensation module connects the second node and the third node according to the second scan signal, the second initialization module transmits the first initialization signal to the third node according to the fourth scan signal, and the third initialization module transmits the second initialization signal to the first terminal of the driving module according to the fourth scan signal; wherein the level of the second power signal is the first level.

[0027] In one possible implementation, a threshold compensation phase is included after the initialization phase. In the threshold compensation phase, the first initialization module transmits the first power signal to the first node according to the first scan signal, the threshold compensation module connects the second node and the third node according to the second scan signal, and the light emission control module connects the first terminal of the driving module to the first power line according to the light emission control signal; wherein, the level of the second power signal is the first level.

[0028] In one possible implementation, a data writing phase is included after the threshold compensation phase, in which the data writing module transmits the data signal to the first node according to the third scan signal; wherein the level of the second power signal is the first level.

[0029] In one possible implementation, a light-emitting stage is included after the data writing stage, in which the light-emitting control module connects the first terminal of the driving module to the first power line according to the light-emitting control signal; wherein the level of the second power signal is a second level, and the first level is greater than the second level.

[0030] A method for driving a pixel circuit, used to drive a pixel circuit in a display panel as described in any of the above embodiments, wherein one working cycle of the pixel circuit includes an initialization phase, a threshold compensation phase, a data writing phase, and a light emission phase, and the driving method includes: During the initialization phase, the level of the first scan signal is controlled to be on, the level of the second scan signal is controlled to be on, and the level of the third scan signal is controlled to be off. During the threshold compensation stage, the level of the first scan signal is controlled to be on, the level of the second scan signal is controlled to be on, and the level of the third scan signal is controlled to be off. During the data writing phase, the level of the first scan signal is controlled to be off, the level of the second scan signal is controlled to be off, and the level of the third scan signal is controlled to be on. During the light emission stage, the level of the first scan signal is controlled to be at the cutoff level, the level of the second scan signal is controlled to be at the cutoff level, and the level of the third scan signal is controlled to be at the cutoff level.

[0031] In one possible implementation, the driving method further includes: During the initialization phase, the level of the fourth scanning signal is controlled to be on, the light emission control signal is controlled to be off, and the level of the second power supply signal is controlled to be the first level. During the threshold compensation stage, the level of the fourth scanning signal is controlled to be cut off, the light emission control signal is controlled to be on, and the level of the second power supply signal is controlled to be the first level. During the data writing phase, the level of the fourth scan signal is controlled to be at the cutoff level, the light emission control signal is controlled to be at the cutoff level, and the level of the second power supply signal is controlled to be at the first level. During the light emission stage, the level of the fourth scanning signal is controlled to be at the cutoff level, the level of the second light emission control signal is controlled to be at the on level, and the level of the second power supply signal is controlled to be at the second level. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of one type of display panel provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of one pixel circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of one type of power trace provided in an embodiment of this application; Figure 4 This is a schematic diagram of another power trace structure provided in an embodiment of this application; Figure 5 A schematic diagram of the circuit structure of the first pixel circuit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the second pixel circuit provided in the embodiments of this application; Figure 7 A schematic diagram of the circuit structure of the second pixel circuit provided in the embodiments of this application; Figure 8 This is a schematic diagram of the structure of the third pixel circuit provided in the embodiments of this application; Figure 9 A schematic diagram of the circuit structure of the third pixel circuit provided in the embodiments of this application; Figure 10 This is a signal timing diagram of one pixel circuit provided in an embodiment of this application; Figure 11 This is a flowchart illustrating the driving method of the pixel circuit in one embodiment of this application. Detailed Implementation

[0034] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0037] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0038] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0039] Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application. In one possible implementation, the display panel can be an organic light-emitting diode (OLED) display panel or a quantum dot (QLED) display panel. The display panel can include a display area AA with display function and a non-display area NA, with the non-display area NA surrounding the display area AA.

[0040] The display area AA of the display panel can be rectangular, square, circular, elliptical, or other shapes. Preferably, the non-display area NA surrounds the entire display area AA and is a ring corresponding to the shape of the display area AA. For example, when the display area AA is rectangular, the non-display area NA is a rectangular ring; when the display area AA is circular, the non-display area NA is a circular ring.

[0041] The display panel may include a substrate and multiple sub-pixels (px) disposed on the substrate, with each sub-pixel (px) located within a display area AA. The multiple sub-pixels (px) may be arranged in an array along the X and Y directions. Each sub-pixel includes a pixel circuit, which may include a light-emitting device. One pixel circuit drives at least one light-emitting device to emit light. For example, the display area AA includes a normal display area and a light-transmitting display area. The light-transmitting display area is the display area corresponding to a sensor and has light-transmitting properties, while the normal display area is the display area not corresponding to a sensor. In the normal display area, one pixel circuit drives one light-emitting device to emit light, and in the light-transmitting display area, one pixel circuit drives one or more light-emitting devices to emit light. The light-emitting devices in different sub-pixels (px) may emit different colors; for example, the light-emitting devices may emit red, green, blue, white, or other colors of light.

[0042] The display panel may further include a first power line 100, a second power line 200, and a power chip 300. The power chip 300 may be a Power IC (Power Management IC), capable of outputting different voltage or current signals as needed. In this embodiment, the power chip 300 may be used to output a first power signal VDD. The first power line 100 and the second power line 200 may each be connected to the power chip 300 and multiple sub-pixels px, respectively, and the first power line 100 and the second power line 200 may be used to transmit the first power signal VDD to different nodes within the sub-pixels px.

[0043] Figure 2 This is a schematic diagram of the structure of a pixel circuit provided in one embodiment of this application. In one possible implementation, the pixel circuit may include a driving module 110, a data writing module 120, a threshold compensation module 130, a first initialization module 140, a first storage module 160, and a second storage module 170.

[0044] The first initialization module 140 can be connected to the first node N1. The first initialization module 140 can be configured to transmit a first power signal VDD to the first node N1 according to a first scan signal S1. In some specific embodiments, the first terminal of the first initialization module 140 can be connected to a second power line, which can transmit the first power signal VDD output by the power chip 300 to the first terminal of the first initialization module 140. The control terminal of the first initialization module 140 can be connected to a first scan line, which can transmit the first scan signal S1 to the control terminal of the first initialization module 140. The second terminal of the first initialization module 140 can be connected to the first node N1, so that the first initialization module 140 can transmit the first power signal VDD to the first node N1 according to the control of the first scan signal S1.

[0045] In existing circuits, the Vref signal is typically used to reset or regulate the potential of certain nodes within the circuit. For example, the Vref signal is used to reset the source or drain of driving transistors, storage capacitors, and the anode of light-emitting devices. However, since the Vref signal is provided by the DDIC (Display Driver Integrated Circuit), and the DDIC's output current is relatively small, this leads to an increased voltage drop within the panel. This large voltage drop not only affects the display quality but also increases power consumption. Therefore, wiring is needed in the AA area and the bezel to reduce the corresponding voltage drop. However, this increases the product size, contradicting the requirement for narrow bezels.

[0046] In the pixel circuit provided in this application, the first power signal VDD is generated by the power chip 300. The power chip 300 provides a larger output current, a more stable signal, and a smaller voltage drop in the display panel. Therefore, compared to the conventional circuit design that uses the Vref signal output by DDIC to stabilize the potential at certain nodes (such as N1) in the circuit, in this embodiment, the first initialization module 140 transmits the first power signal VDD to the first node N1 and uses the first power signal VDD to reset and / or regulate the voltage of the first node N1. This not only provides a stable and continuous voltage to the first node N1, but also reduces the difference in compensation and data writing caused by voltage drop in different rows in the display panel, effectively improving image quality and uniformity, and is also conducive to adapting to the design requirements of narrow bezels.

[0047] A threshold compensation module 130 can be connected between the second node N2 and the third node N3. The threshold compensation module 130 can be configured to turn the connection between the second node N2 and the third node N3 on or off according to a second scan signal S2. In some specific embodiments, the first end of the threshold compensation module 130 can be connected to the second node N2, and the control end of the threshold compensation module 130 can be connected to a second scan line, which can transmit the second scan signal S2 to the control end of the threshold compensation module 130. The second end of the threshold compensation module 130 can be connected to the third node N3, so that the threshold compensation module 130 can control the on / off connection between the second node N2 and the third node N3 according to a first scan signal S1.

[0048] The data writing module 120 is connected to the first node N1 and can be configured to transmit the data signal Vdata to the first node N1 according to the third scan signal S3. In some specific embodiments, the first end of the data writing module 120 can be connected to a data line, which can output the data signal Vdata to the first end of the data writing module 120. The control end of the data writing module 120 can be connected to the third scan line to receive the third scan signal S3, and the second end of the data writing module 120 can be connected to the first node N1, so that the data writing module 120 can transmit the data signal Vdata to the first node N1 according to the control of the third scan signal S3.

[0049] The first storage module 160 can be connected between the first node N1 and the second node N2. The first storage module 160 can be configured to store the voltage difference between the first node N1 and the second node N2. In some specific embodiments, the first terminal of the first storage module 160 can be connected to the data writing module 120 and the first initialization module 140 at the first node N1, and the second terminal of the first storage module 160 can be connected to the driving module 110 and the threshold compensation module 130 at the second node N2.

[0050] The second storage module 170 can be connected between the first node N1 and the first power line 100. The second storage module 170 can be configured to store the voltage difference between the first node N1 and the first power line. The first power line 100 can transmit a first power signal VDD to the second storage module 170. In some specific embodiments, the first end of the second storage module 170 can be connected to the first storage module 160, the data writing module 120, and the first initialization module 140 at the first node N1, and the second end of the first storage module 160 can be connected to the first power line 100.

[0051] The control terminal of the driving module 110 can be connected to the second node N2, and the second terminal of the driving module 110 can be connected to the third node N3. The driving module 110 can be connected between the first power line 100 and the light-emitting module 210. The first power line 100 can provide the first power signal VDD required for the operation of the pixel circuit. The driving module 110 can output a driving signal to the light-emitting module 210 according to the voltage of its control terminal, so as to control the light-emitting module 210 to emit light using the driving signal.

[0052] This application proposes a pixel circuit that can improve display uniformity. The first initialization module 140 transmits the first power signal VDD output by the power chip 300 to the first node N1. The first power signal VDD can be used to reset and / or regulate the voltage of the first node N1, which can not only provide a stable and continuous voltage to the first node N1, but also reduce the differences in compensation and data writing caused by voltage drop in different rows within the display panel, effectively improving image quality and uniformity. Through the cooperation of the driving module 110, data writing module 120, threshold compensation module 130, first initialization module 140, first storage module 160 and second storage module 170, and the timing of various input signals, functions such as resetting the components in the circuit and threshold compensation for the driving module 110 can be realized, thereby effectively improving display uniformity when the pixel circuit is applied to display products.

[0053] In one possible implementation, Figure 3 This is a schematic diagram of a power supply trace provided in one embodiment of this application. The first power line 100 may include multiple first sub-power lines 100a extending along a first direction X and multiple second sub-power lines 100b extending along a second direction Y. The multiple first sub-power lines 100a and multiple second sub-power lines 100b are cross-connected to form a first mesh structure 100c. The second power line 200 may include multiple third sub-power lines 200a extending along the first direction X and multiple fourth sub-power lines 200b extending along the second direction Y. The multiple third sub-power lines 200a and multiple fourth sub-power lines 200b are cross-connected to form a second mesh structure 200c.

[0054] In the first direction X, the second sub-power line 100b and the fourth sub-power line 200b are arranged alternately, and in the second direction Y, the first sub-power line 100a and the third sub-power line 200a are arranged alternately. That is, in this embodiment, the first power line 100 and the second power line 200 are designed as a symmetrical and staggered mesh structure. The first direction X intersects the second direction Y. Preferably, the first direction X is perpendicular to the second direction Y.

[0055] Considering the inherent resistance of power traces, when current flows from the PCB board into the center of the display panel, traditional single-sided or single-side routing can cause a decrease in the actual voltage received by pixels far from the driving end. Since the driving current is proportional to the square of the voltage, even a small voltage difference can cause the center of the screen to be darker than the edges. In this application, the first power signal VDD output by the power chip 300 is transmitted to each sub-pixel inside the display panel through the first power line 100 and the second power line 200, respectively. On the one hand, the current of the output signal of the power chip 300 is relatively large, thus reducing the voltage drop inside the display panel. On the other hand, by designing the first power line 100 and the second power line 200 as follows... Figure 3 The symmetrically distributed mesh structure shown is equivalent to countless parallel current paths. Current no longer needs to be transmitted over long distances; instead, it is supplied to each sub-pixel via the crisscrossing mesh through shorter paths. This significantly reduces the equivalent resistance from the power chip 300 to each sub-pixel, lowers the VDD voltage difference between the panel center and edges, and thus ensures highly consistent brightness across the entire screen.

[0056] In one possible implementation, the first power line 100 may further include a first connection portion 100d located in the non-display area NA and connected to the power chip 300, and at least a portion of the second sub-power line 100b extends from the display area AA to the non-display area NA and is connected to the first connection portion 100d. The second power line 200 may further include a second connection portion 200d located in the non-display area NA and connected to the power chip 300, and at least a portion of the fourth sub-power line 200b extends from the display area AA to the non-display area NA and is connected to the second connection portion 200d. See also... Figure 3 In some embodiments, the display panel may include two power chips 300, both of which output a first power signal VDD. A first connection portion 100d connects the two power chips 300 and is connected to a second sub-power line 100b extending to the non-display area NA, so that the first power signal VDD output by the power chips 300 can be transmitted to the first terminal of the driving module 110 of each pixel circuit through the first power line 100. Similarly, a second connection portion 200d connects the two power chips 300 and is connected to a fourth sub-power line 200b extending to the non-display area NA, so that the first power signal VDD output by the power chips 300 can be transmitted to the first initialization module 140 of each pixel circuit through the second power line 200.

[0057] In one possible implementation, the first power line 100 may further include a first extension 100e located in the non-display area NA, the first extension 100e being connected to the first mesh structure 100c, and the first extension 100e at least surrounding a portion of the display area AA. The second power line 200 may further include a second extension 200e located in the non-display area NA, the second extension 200e being connected to the second mesh structure 200c, and the second extension 200e at least surrounding a portion of the display area AA. See also... Figure 3 The first extension 100e and the second extension 200e can be arranged around the entire display area AA. The first extension 100e and the second extension 200e are rings corresponding to the shape of the display area AA. For example, when the display area AA is rectangular, the shape of the first extension 100e and the second extension 200e is a rectangular ring; when the display area AA is circular, the shape of the first extension 100e and the second extension 200e is a circular ring.

[0058] Compared to solutions where current enters only from one side of the display panel (e.g., the bottom bonding area), requiring current to flow from the bottom to the top and causing significant voltage drops in distant pixels, this embodiment utilizes a first extension 100e and a second extension 200e surrounding the display area AA to provide an entry point for the first power signal VDD around the entire display area AA. This results in a more balanced supply of the first power signal VDD to each row of sub-pixels. Simultaneously, the first extension 100e and the second extension 200e also provide a parallel path to the first network structure 100c and the second network structure 200c, significantly reducing the total resistance of the first power line 100 and the second power line 200. By providing low-impedance paths for the first power line 100 and the second power line 200, the signal stability of the first power signal VDD is further enhanced.

[0059] In one possible implementation, Figure 4 This is a schematic diagram of another power trace structure provided in an embodiment of this application. In the second direction Y, the non-display area NA may include a first sub-non-display area NA1 and a second sub-non-display area NA2. Along the second direction Y, the display area AA is located between the first sub-non-display area NA1 and the second sub-non-display area NA2. The first extension 100e and the second extension 200e may be disposed in the first sub-non-display area NA1, and the power chip 300, the first connection portion 100d, and the second connection portion 200d may be disposed in the second sub-non-display area NA2. At least a portion of the second sub-power line 100b extends from the display area AA to the first sub-non-display area NA1 and is connected to the first extension portion 100e. At least a portion of the fourth sub-power line 200b extends from the display area AA to the second sub-non-display area NA2 and is connected to the second extension portion 200e.

[0060] Because the power chip 300 has a large output current, the voltage drop of the first power signal VDD in the display panel is small. Therefore, the power traces on the left and right bezels can be eliminated, and the first power line 100 and the second power line 200 can be connected in a mesh pattern only on the top and bottom bezels to meet the design requirements of narrow bezels.

[0061] In embodiments of this disclosure, a transistor can refer to a device that includes at least a gate, a drain, and a source. In this disclosure, the first terminal of a transistor can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In embodiments of this disclosure, the first and second terminals of all or some transistors can be interchanged as needed.

[0062] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. Furthermore, the on-level and off-level in the embodiments of this invention are general terms; the on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0063] Figure 5 This is a schematic diagram of the circuit structure of a first pixel circuit provided in an embodiment of this application. In one possible implementation, the driving module 110 may include a first transistor M1. The gate of the first transistor M1 can be connected to the second node N2 as the control terminal of the driving module 110. The first electrode of the first transistor M1 can be used as the first terminal of the driving module 110, and the second electrode of the first transistor M1 can be used as the second terminal of the driving module 110.

[0064] In one possible implementation, the data writing module 120 may include a second transistor M2. The gate of the second transistor M2 may be connected to the third scan line as the control terminal of the data writing module 120 to access the third scan signal S3. The first terminal of the second transistor M2 may be connected to the data line as the first terminal of the data writing module 120 to access the data signal Vdata. The second terminal of the second transistor M2 may be connected to the first node N1 as the second terminal of the data writing module 120.

[0065] In one possible implementation, the threshold compensation module 130 may include a third transistor M3. The gate of the third transistor M3 may be connected to the second scan line as the control terminal of the threshold compensation module 130 to access the second scan signal S2. The first terminal of the third transistor M3 may be connected to the second node N2 and the control terminal of the driving module 110 as the first terminal of the threshold compensation module 130. The second terminal of the third transistor M3 may be connected to the second terminal of the driving module 110 as the second terminal of the threshold compensation module 130.

[0066] In one possible implementation, the first initialization module 140 may include a fourth transistor M4. The gate of the fourth transistor M4 may be connected to the first scan line as the control terminal of the first initialization module 140 to access the first scan signal S1. The first terminal of the fourth transistor M4 may be connected to the second power line as the first terminal of the first initialization module 140 to access the first power signal VDD. The second terminal of the fourth transistor M4 may be connected to the first node N1 as the second terminal of the first initialization module 140.

[0067] In one possible implementation, the fourth transistor M4 can be a dual-gate transistor, with both its first and second gates connected to the first scan signal S1. More specifically, as... Figure 5 As shown, the fourth transistor M4 may include a first sub-transistor M4_1 and a second sub-transistor M4_2 connected in series. The gate of the first sub-transistor M4_1 serves as the first gate of the fourth transistor M4, and the gate of the second sub-transistor M4_2 serves as the second gate of the fourth transistor M4. Both the gates of the first sub-transistor M4_1 and the gate of the second sub-transistor M4_2 are connected to the first scan signal S1. The fourth transistor M4, composed of the first sub-transistor M4_1 and the second sub-transistor M4_2 connected in series, transmits the first power supply signal VDD. The fourth transistor M4 has advantages such as a steeper subthreshold swing SS, lower leakage current, and stronger gate control capability, resulting in a more stable input first power supply signal VDD potential. This allows for better initialization and / or voltage regulation of the first node N1.

[0068] In one possible implementation, the first storage module 160 may include a first capacitor C1. The first terminal of the first capacitor C1 can serve as the first end of the first storage module 160, and the second terminal of the first capacitor C1 can serve as the second end of the first storage module 160. The first terminal of the first capacitor C1 can be connected to a first node N1, and the second terminal of the first capacitor C1 can be connected to a second node N2.

[0069] In one possible implementation, the second storage module 170 may include a second capacitor C2. The first terminal of the second capacitor C2 can serve as the first terminal of the second storage module 170, and the second terminal of the second capacitor C2 can serve as the second terminal of the second storage module 170. The first terminal of the second capacitor C2 can be connected to the first node N1, and the second terminal of the second capacitor C2 can be connected to the first power supply line.

[0070] Figure 6 This is a schematic diagram of the structure of a second pixel circuit provided in an embodiment of this application. In one embodiment, the pixel circuit may further include a light-emitting module 210, a second initialization module 150, and a first light-emitting control module 220.

[0071] The light-emitting module 210 can be connected between the third node N3 and the third power line, and the third power line can provide a second power signal ACVSS to the second end of the light-emitting module 210. Preferably, the second power signal ACVSS is an AC signal.

[0072] In one possible implementation, the pixel circuit may include a non-light-emitting stage and a light-emitting stage. The level of the second power signal ACVSS in the non-light-emitting stage can be a first level VSSH, and the level of the second power signal ACVSS in the light-emitting stage can be a second level VSSL, where the first level VSSH is greater than the second level VSSL. Preferably, the first level VSSH can be a high level greater than a first preset value. The first preset value can be determined based on the potential of the first terminal of the light-emitting module 210 in the non-light-emitting stage, to ensure that the value of the second power signal ACVSS can keep the light-emitting module 210 in a reverse cutoff state in the non-light-emitting stage, thereby preventing the light-emitting module 210 from emitting light in the non-light-emitting stage. Specifically, VSSH > VDD - ΔV (ΔV is the voltage drop value of VDD after passing through the first transistor T1), and the second level VSSL can be a low level. In the light-emitting stage, the light-emitting module 210 can emit light normally according to the potential at its terminals.

[0073] The second initialization module 150 can be connected to the third node N3. The second initialization module 150 can be configured to transmit the first initialization signal Vref1 to the third node N3 according to the fourth scan signal S4. In some specific embodiments, the first terminal of the second initialization module 150 can be connected to a first initialization signal line, which can output the first initialization signal Vref1 to the first terminal of the second initialization module 150. The control terminal of the second initialization module 150 can be connected to a second scan line, which can transmit the second scan signal S2 to the control terminal of the second initialization module 150. The second terminal of the second initialization module 150 can be connected to the third node N3, so that the second initialization module 150 can transmit the first initialization signal Vref1 to the third node N3 according to the control of the second scan signal S2. Preferably, the first initialization signal Vref1 is less than zero.

[0074] As can be seen, when the second scan signal S2 and the fourth scan signal S4 are both on, the first initialization signal Vref1 can be transmitted through the second initialization module 150 and the threshold compensation module 130 to the third node N3, the second terminal of the driving module 110, the second node N2, and the control terminal of the driving module 110, respectively. In the pixel circuit provided by this application, during the initialization phase, the second initialization module 150 and the threshold compensation module 130 are simultaneously turned on, and the first initialization signal Vref1 can simultaneously initialize the third node N3, the second terminal of the driving module 110, the second node N2, and the control terminal of the driving module 110. In addition, during the threshold compensation phase, the threshold compensation module 130 can write the threshold information of the driving module 110 into the second node N2. The data writing module 120 transmits the data signal Vdata to the second node N2 after the third scan signal S3 is turned on during the data writing phase. That is, the threshold compensation operation and the data writing operation in the pixel circuit are executed in different phases to ensure that the threshold voltage of the driving transistor can be fully compensated.

[0075] The light emission control module 220 is connected between the first end of the drive module 110 and the first power line 100. The light emission control module 220 can be configured to turn on or off the connection between the drive module 110 and the first power line 100 according to the light emission control signal EM.

[0076] In some specific embodiments, the first end of the light-emitting control module 220 can be connected to the first power line 100, and the control end of the light-emitting control module 220 can be connected to the light-emitting control signal line, which can transmit the light-emitting control signal EM to the first end of the light-emitting control module 220. The second end of the light-emitting control module 220 can be connected to the first end of the driving module 110, so that the light-emitting control module 220 can turn on or off the connection between the first power line 100 and the first end of the driving module 110 according to the control of the light-emitting control signal EM.

[0077] Figure 7 This is a schematic diagram of the circuit structure of a second pixel circuit provided in an embodiment of this application. In one possible implementation, the second initialization module 150 may include a fifth transistor M5. The gate of the fifth transistor M5 can serve as the control terminal of the second initialization module 150, the first terminal of the fifth transistor M5 can serve as the first terminal of the second initialization module 150, and the second terminal of the fifth transistor M5 can serve as the second terminal of the second initialization module 150. The gate of the fifth transistor M5 can be connected to a fourth scan line to receive a fourth scan signal S4, the first terminal of the fifth transistor M5 can be connected to a first initialization signal line to receive a first initialization signal Vref1, and the second terminal of the fifth transistor M5 can be connected to a third node N3.

[0078] The light-emitting control module 220 may include a sixth transistor M6. The gate of the sixth transistor M6 can serve as the control terminal of the light-emitting control module 220, the first terminal of the sixth transistor M6 can serve as the first terminal of the light-emitting control module 220, and the second terminal of the sixth transistor M6 can serve as the second terminal of the light-emitting control module 220. The gate of the sixth transistor M6 can be connected to a light-emitting control signal line to receive a light-emitting control signal EM. The first terminal of the sixth transistor M6 can be connected to a first power supply line 100, and the second terminal of the sixth transistor M6 can be connected to the first terminal of the driving module 110.

[0079] In one possible implementation, the light-emitting module 210 may include a light-emitting diode (OLED) D1. The OLED may include an anode and a cathode. The anode of OLED D1, serving as the first terminal of the light-emitting module 210, can be connected to a third node N3. The cathode of OLED D1, serving as the second terminal of the light-emitting module 210, can be connected to a third power line to receive a second power signal ACVSS. During the light-emitting phase, the second power signal ACVSS can be a second level VSSL, which is a low level. When the driving signal output by the driving module 110 is transmitted to the OLED D1, the OLED D1 can emit light with a brightness corresponding to the driving signal.

[0080] Figure 8 This is a schematic diagram of the structure of a third pixel circuit provided in an embodiment of this application. In one possible implementation, the pixel circuit may further include a third initialization module 240. The third initialization module 240 may be connected to the first terminal of the driving module 110. The third initialization module 240 may be configured to transmit a second initialization signal Vref2 to the first terminal of the driving module 110 according to a fourth scan signal S4. In some embodiments, the first terminal of the third initialization module 240 may be connected to a second initialization signal line, which may output the second initialization signal Vref2 to the first terminal of the third initialization module 240. The control terminal of the third initialization module 240 may be connected to a third scan line, which may output a third scan signal S3 to the control terminal of the third initialization module 240. The second terminal of the third initialization module 240 may be connected to the first terminal of the driving module 110, so that the third initialization module 240 may transmit the second initialization signal Vref2 to the first terminal of the driving module 110 according to the fourth scan signal S4.

[0081] In one possible implementation, the second initialization signal Vref2 may be less than a second preset value. The second preset value can be determined based on the first initialization signal Vref1 and the threshold information Vth of the driving module, to ensure that the second initialization signal Vref2 can effectively reset the first terminal of the driving module 110. Specifically, Vref2 < Vref1 + Vth.

[0082] Figure 9 This is a schematic diagram of the circuit structure of a third pixel circuit provided in an embodiment of this application. In one possible implementation, the third initialization module 240 may include a seventh transistor M7. The gate of the seventh transistor M7 can serve as the control terminal of the third initialization module 240, the first terminal of the seventh transistor M7 can serve as the first terminal of the third initialization module 240, and the second terminal of the seventh transistor M7 can serve as the second terminal of the third initialization module 240. The gate of the seventh transistor M7 can be connected to a third scan line to receive a fourth scan signal S4, the first terminal of the seventh transistor M7 can be connected to a second initialization signal line to receive a second initialization signal Vref2, and the second terminal of the seventh transistor M7 can be connected to the first terminal of the driving module 110.

[0083] Figure 9 The pixel circuit shown is a 7T2C structure, in which the first transistor M1 is a DTFT (Driver Thin Film Transistor), and the remaining transistors are all STFTs (Switch Thin Film Transistors). All seven transistors can also be P-type transistors.

[0084] The first terminal of the second transistor M2 is connected to the data signal Vdata. The second terminal of the second transistor M2 is connected to the second terminal of the fourth transistor M4, the first terminal of the first capacitor C1, and the first terminal of the second capacitor C2 at the first node N1. The first terminal of the fourth transistor M4 is connected to the second power supply line 200, and the gate of the fourth transistor M4 is connected to the first scan signal S1. The gate of the first transistor M1 is connected to the first terminal of the third transistor M3 and the second terminal of the first capacitor C1 at the second node N2. The first terminal of the first transistor M1 is connected to the second terminals of the sixth transistor M6 and the seventh transistor M7. The second terminal of the first transistor M1 is connected to the second terminals of the third transistor M3, the fifth transistor M5, and the anode of the light-emitting diode D1 at the third node N3. The first terminal of the sixth transistor M6 is connected to the first power supply line 100 and the second terminal of the second capacitor C2. The gate of the sixth transistor M6 is connected to the light-emitting control signal EM. The first terminal of the seventh transistor M7 is connected to the second initialization signal Vref2, and the gates of both the fifth transistor M5 and the seventh transistor M7 are connected to the fourth scan signal S4. The first terminal of the fifth transistor M5 is connected to the first initialization signal Vref1. The cathode of the light-emitting diode D1 is connected to the second power supply line to receive the second power supply signal ACVSS.

[0085] In one possible implementation, the pixel circuit may include an initialization phase t1, a threshold compensation phase t2, a data writing phase t3, and an emission phase t4 in one working cycle.

[0086] Figure 10 This is a signal timing diagram of one pixel circuit provided in an embodiment of the present application, which can be applied to, for example... Figure 9 The pixel circuit shown in this embodiment is combined with Figure 9 and Figure 10 The operation of a pixel circuit provided in one embodiment of this application will be described in detail, but this should not be construed as limiting the scope of the invention. In this embodiment, the transistors in the pixel circuit are all P-type transistors, therefore the on-level is low and the off-level is high.

[0087] During the initialization phase t1, the level of the first scan signal S1 can be on, the level of the second scan signal S2 can be on, and the level of the third scan signal S3 can be off. That is, the first initialization module 140 is turned on according to the first scan signal S1, the threshold compensation module 130 is turned on according to the second scan signal S2, and the data writing module 120 is turned off according to the third scan signal S3. In addition, the level of the fourth scan signal S4 can be on, the level of the light emission control signal EM can be off, the second initialization module 150 and the third initialization module 240 are turned on according to the fourth scan signal S4, the light emission control module 220 is turned off according to the light emission control signal EM, and the level of the second power supply signal ACVSS is the first level VSSH.

[0088] During initialization phase t1, the second transistor M2 is turned off according to the third scan signal S3. After the fourth transistor M4 is turned on according to the first scan signal S1, the first power supply signal VDD is transmitted to the first node N1 through the fourth transistor M4, thus initializing the first node N1. Simultaneously, the fifth transistor M5 and the third transistor M3 are turned on, and the first initialization signal Vref1 is transmitted to the second node N2 sequentially through the fifth transistor M5 and the third transistor M3, simultaneously initializing the anode of the light-emitting diode D1, the drain of the first transistor M1, and the gate of the first transistor M1. That is, the gate G, drain D of the first transistor M1, and the anode of the light-emitting diode D1 are all initialized by the first initialization signal Vref1. The second initialization signal Vref2 is transmitted to the first terminal of the first transistor M1 through the seventh transistor M7 to initialize the first terminal of the first transistor M1. At this time, the gate potential V of the first transistor M1 is... G =Vref1, the potential V at the first terminal of the first transistor M1 S =Vref2. Additionally, since the level of the second power supply signal ACVSS is VSSH, the potential at the cathode of LED D1 is greater than the potential at its anode, causing LED D1 to be reverse-biased and therefore not to emit light.

[0089] In one possible implementation, after initialization phase t1, the pixel circuit may include a threshold compensation phase t2. In threshold compensation phase t2, the level of the first scan signal S1 can be on, the level of the second scan signal S2 can be on, and the level of the third scan signal S3 can be off. That is, the first initialization module 140 is turned on according to the first scan signal S1, the threshold compensation module 130 is turned on according to the second scan signal S2, and the data writing module 120 is turned off according to the third scan signal S3. Additionally, the level of the fourth scan signal S4 is off, the level of the light emission control signal EM can be on, the second initialization module 150 and the third initialization module 240 are turned off according to the fourth scan signal S4, the light emission control module 220 is turned on according to the light emission control signal EM, and the level of the second power supply signal ACVSS is the first level VSSH.

[0090] During the threshold compensation phase t2, the second transistor M2 is turned off according to the third scan signal S3. The fourth transistor M4 is turned on according to the first scan signal S1. That is, the potential at the first node N1 is still VDD. The potential at the first node N1 is stabilized using the first power supply signal VDD. The third transistor M3 is turned on according to the second scan signal S2, and the sixth transistor M6 is turned on according to the light emission control signal EM. At the same time, since the potential at the first transistor M1 is reset to Vref1 and the potential at the first terminal of the first transistor M1 is reset to Vref2 during the initialization phase t1, and Vref2 < Vref1 + Vth, the first transistor M1 meets the turn-on condition and turns on. The first power supply signal VDD transmitted on the first power line 100 can be sequentially written into the gate of the first transistor M1 through the sixth transistor M6, the first transistor M1, and the third transistor M3, and the first power supply signal VDD is used to perform threshold compensation on the first transistor M1. At this time, the potential V at the first transistor M1 is V... G =VDD+Vth. Additionally, since the level of the second power supply signal ACVSS is VSSH, the potential at the cathode of LED D1 is greater than the potential at its anode, causing LED D1 to be reverse-biased and therefore not to emit light.

[0091] In one possible implementation, after the threshold compensation stage t2, the pixel circuit may include a data writing stage t3. In the data writing stage t3, the levels of the first scan signal S1 and the second scan signal S2 may be off levels, and the level of the third scan signal S3 may be on levels. That is, the first initialization module 140 is off according to the first scan signal S1, the threshold compensation module 130 is off according to the second scan signal S2, and the data writing module 120 is on according to the third scan signal S3. Additionally, the level of the fourth scan signal is off, the level of the light emission control signal EM may be off, the second initialization module 150 and the third initialization module 240 are off according to the fourth scan signal S4, the light emission control module 220 is off according to the light emission control signal EM, and the level of the second power supply signal ACVSS is the first level VSSH.

[0092] During the data writing phase t3, the second transistor M2 is turned on according to the third scan signal S3, while all other transistors are turned off. The data signal Vdata is transmitted to the first node N1 through the second transistor M2, resulting in a voltage jump at the first node N1.

[0093] The jump variable at the first node N1 is: ΔV N1 =(c1 / c N1_all ) (Vdata-VDD) Where c1 is the capacitance value of the first capacitor C1, c N1_all This is the total capacitance value coupled to the first plate of the first capacitor C1 in the circuit.

[0094] The voltage jump at the first node N1 will be coupled to the second node N2, i.e., the gate of the first transistor M1, through the first capacitor C1. That is, the voltage jump at the second node N2 is also ΔV. N1 =(c1 / c N1_all ) (Vdata-VDD), and the potential of the second node N2 before the transition is VDD+Vth, therefore the potential of the second node N2 after the transition is V. N2 =VDD+Vth+ (c1 / c N1_all ) (Vdata-VDD), that is, the potential at the gate of the first transistor M1 is V G = VDD + Vth + (c1 / c N1_all ) (Vdata-VDD).

[0095] In addition, since the level of the second power supply signal ACVSS is VSSH, the potential at the cathode of LED D1 is greater than the potential at its anode, LED D1 is reverse biased, and therefore LED D1 does not emit light.

[0096] In one possible implementation, after the data writing stage t3, the write frame may include a light emission stage t4. In the light emission stage t4, the levels of the first scan signal S1, the second scan signal S2, and the third scan signal S3 can be cutoff levels. That is, the first initialization module 140 is cut off according to the first scan signal S1, the threshold compensation module 130 is cut off according to the second scan signal S2, and the data writing module 120 is cut off according to the third scan signal S3. Additionally, the level of the fourth scan signal S4 is a cutoff level, the level of the light emission control signal EM can be a conduction level, the second initialization module 150 and the third initialization module 240 are both cut off according to the fourth scan signal S4, the light emission control module 220 is conduction according to the light emission control signal EM, and the level of the second power signal ACVSS is the second level VSSL.

[0097] During the light-emitting phase t4, the sixth transistor M6 is turned on according to the light-emitting control signal EM. The first transistor M1 outputs a drive signal based on its gate-source voltage. The drive current output by the first transistor M1 can be expressed as: ID=1 / 2 μCOX (W / L)( (c1 / c) N1_all ) (Vdata-VDD)) 2 The gate voltage of the first transistor M1 is V. G = VDD + Vth + (c1 / c N1_all ) (Vdata-VDD), the source voltage of the first transistor M1 is V S =VDD, which is the voltage difference V between the gate and source of the first transistor M1. GS = Vth+(c1 / c N1_all ) (Vdata-VDD), therefore, V GS -Vth= (c1 / c N1_all ) (Vdata-VDD), that is, the drive current is about (c1 / c N1_all ) The function is (Vdata-VDD). This function does not include VSS or Vth, indicating that the drive current output by this pixel circuit is unaffected by differences in VSS and Vth at different locations on the display panel, meaning it provides good compensation for both VSS and Vth.

[0098] The drive current ID output by the first transistor M1 is transmitted to the anode of the light-emitting diode D1, so that the light-emitting diode D1 emits light according to the drive current ID.

[0099] In the initialization phase t1, the pixel circuit described above can simultaneously initialize the gate, drain, and anode of the first transistor M1 and the light-emitting diode D1 using a single circuit consisting of the fifth transistor M5 and the third transistor M3. Furthermore, in the threshold compensation phase t2, the first power supply signal VDD can compensate for the threshold voltage Vth of the first transistor M1, reducing the impact of differences in threshold voltages between different transistors on the driving current and improving display uniformity. Additionally, at the data writing node t3, the data signal Vdata can be quickly written to the gate of the first transistor M1 using the coupling of the first capacitor C1, which is beneficial for meeting market demands for high brightness. Moreover, the pixel circuit provided in this embodiment does not add an additional TFT compared to related technologies, making it more advantageous for layout design.

[0100] This invention also provides a display panel that may include the pixel circuits described in any of the above embodiments. The display panel may include one or more sets of pixel circuits. The pixel circuits may be configured to generate driving signals and use these driving signals to drive the light-emitting units to emit light. This display panel can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0101] This invention also provides a display device, which may include the pixel circuit described in any of the above embodiments. The display device may include one or more sets of pixel circuits. The pixel circuits may be configured to generate driving signals and use these driving signals to drive the light-emitting units to emit light. Similarly, this display device can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0102] The present invention also provides a driving method for driving a pixel circuit as described in any of the above embodiments. The pixel circuit may include an initialization phase t1, a threshold compensation phase t2, a data writing phase t3, and a light emission phase t4 in one working cycle. Figure 11This is a flowchart illustrating a pixel circuit driving method in one embodiment of the present application. In one possible implementation, the pixel circuit driving method may include the following steps S100 to S400.

[0103] Step S100: During the initialization phase, the level of the first scan signal is controlled to be on, the level of the second scan signal is controlled to be on, and the level of the third scan signal is controlled to be off.

[0104] During the initialization phase t1, the level of the first scan signal S1 can be a conducting level, the level of the second scan signal S2 can be a conducting level, and the level of the third scan signal S3 can be a cut-off level. That is, the first initialization module 140 is turned on according to the first scan signal S1, the threshold compensation module 130 is turned on according to the second scan signal S2, and the data writing module 120 is turned off according to the third scan signal S3.

[0105] In one possible implementation, at initialization node t1, the level of the fourth scan signal S4 can be an on level, the level of the light emission control signal EM can be an off level, and the level of the second power supply signal can be the first level VSSH. The second initialization module 150 and the third initialization module 240 can be turned on according to the fourth scan signal S4, and the light emission control module 220 is turned off according to the light emission control signal EM.

[0106] The second transistor M2 is turned off according to the third scan signal S3. After the fourth transistor M4 is turned on according to the first scan signal S1, the first power supply signal VDD is transmitted to the first node N1 through the fourth transistor M4, initializing the first node N1. Simultaneously, the third transistor M3 is turned on according to the second scan signal S2, and the fifth transistor M5 is turned on according to the fourth scan signal S4. The first initialization signal Vref1 is transmitted to the second node N2 sequentially through the fifth transistor M5 and the third transistor M3, simultaneously initializing the anode of the light-emitting diode D1, the drain of the first transistor M1, and the gate of the first transistor M1. That is, the gate G, drain D of the first transistor M1, and the anode of the light-emitting diode D1 are all initialized by the first initialization signal Vref1. The second initialization signal Vref2 is transmitted to the first terminal of the first transistor M1 through the seventh transistor M7 to initialize the first terminal of the first transistor M1. In addition, since the level of the second power supply signal ACVSS is VSSH, the potential at the cathode of LED D1 is greater than the potential at its anode, LED D1 is reverse biased, and therefore LED D1 does not emit light.

[0107] Step S200: During the threshold compensation stage, the level of the first scan signal is controlled to be on, the level of the second scan signal is controlled to be on, and the level of the third scan signal is controlled to be off.

[0108] During the threshold compensation stage t2, the level of the first scan signal S1 can be a conducting level, the level of the second scan signal S2 can be a conducting level, and the level of the third scan signal S3 can be a cut-off level. That is, the first initialization module 140 is turned on according to the first scan signal S1, the threshold compensation module 130 is turned on according to the second scan signal S2, and the data writing module 120 is turned off according to the third scan signal S3.

[0109] In one possible implementation, the level of the fourth scan signal can be a cutoff level, the level of the light emission control signal EM can be a conduction level, the level of the second power supply signal can be the first level VSSH, the second initialization module 150 and the third initialization module 240 can be cut off according to the fourth scan signal S4, and the light emission control module 220 can be turned on according to the light emission control signal EM.

[0110] During the threshold compensation phase t2, the second transistor M2 is turned off according to the third scan signal S3. The fourth transistor M4 is turned on according to the first scan signal S1. That is, the potential at the first node N1 is still VDD. The third transistor M3 is turned on according to the second scan signal S2. The sixth transistor M6 is turned on according to the light emission control signal EM, and at the same time, the first transistor M1 is turned on, so that the first power signal VDD transmitted on the first power line 100 can be written into the gate of the first transistor M1 in sequence through the sixth transistor M6, the first transistor M1, and the third transistor M3. The potential at the first transistor M1 becomes VDD. G =VDD+Vth. Additionally, since the level of the second power supply signal ACVSS is VSSH, the potential at the cathode of LED D1 is greater than the potential at its anode, causing LED D1 to be reverse-biased and therefore not to emit light.

[0111] Step S300: During the data writing stage, the level of the first scan signal is controlled to be cut off, the level of the second scan signal is controlled to be cut off, and the level of the third scan signal is controlled to be on.

[0112] During the data writing phase t3, the levels of the first scan signal S1 and the second scan signal S2 can be at cutoff levels, and the level of the third scan signal S3 can be at on levels. That is, the first initialization module 140 is cut off according to the first scan signal S1, the threshold compensation module 130 is cut off according to the second scan signal S2, and the data writing module 120 is turned on according to the third scan signal S3.

[0113] In one possible implementation, the level of the fourth scan signal can be a cutoff level, the level of the light emission control signal EM can be a cutoff level, the level of the second power supply signal can be the first level VSSH, the second initialization module 150 and the third initialization module 240 can be cut off according to the fourth scan signal S4, and the light emission control module 220 can be cut off according to the light emission control signal EM.

[0114] During the data writing phase t3, the second transistor M2 is turned on according to the third scan signal S3, while all other transistors are turned off. The data signal Vdata is transmitted to the first node N1 through the second transistor M2, resulting in a voltage jump at the first node N1.

[0115] The jump variable at the first node N1 is: ΔV N1 =(c1 / c N1_all ) (Vdata-VDD) Where c1 is the capacitance value of the first capacitor C1, c N1_all This is the total capacitance value coupled to the first plate of the first capacitor C1 in the circuit.

[0116] The voltage jump at the first node N1 will be coupled to the second node N2, i.e., the gate of the first transistor M1, through the first capacitor C1. That is, the voltage jump at the second node N2 is also ΔV. N1 =(c1 / c N1_all ) (Vdata-VDD), and the potential of the second node N2 before the transition is VDD+Vth, therefore the potential of the second node N2 after the transition is V. N2 =VDD+Vth+ (c1 / c N1_all ) (Vdata-VDD), that is, the potential at the gate of the first transistor M1 is V G = VDD + Vth + (c1 / c N1_all ) (Vdata-VDD).

[0117] Step S400: During the light emission stage, the level of the first scan signal is controlled to be at the cutoff level, the level of the second scan signal is controlled to be at the cutoff level, and the level of the third scan signal is controlled to be at the cutoff level.

[0118] During the light emission stage t4, the levels of the first scan signal S1, the second scan signal S2, and the third scan signal S3 can be cutoff levels. That is, the first initialization module 140 is cut off according to the first scan signal S1, the threshold compensation module 130 is cut off according to the second scan signal S2, and the data writing module 120 is cut off according to the third scan signal S3.

[0119] In one possible implementation, the level of the fourth scan signal can be a cutoff level, the level of the first light emission control signal EM can be a conduction level, the level of the second power supply signal can be the second level VSSL, the second initialization module 150 and the third initialization module 240 can be cut off according to the fourth scan signal S4, and the light emission control module 220 can be turned on according to the light emission control signal EM.

[0120] During the luminescence phase t4, The first transistor M1 can output a drive signal based on its gate and source voltages. The drive current output by the first transistor M1 can be expressed as: ID=1 / 2 μCOX (W / L)( (c1 / c) N1_all ) (Vdata-VDD)) 2 The gate voltage of the first transistor M1 is V. G = VDD + Vth + (c1 / c N1_all ) (Vdata-VDD), the source voltage of the first transistor M1 is V S =VDD, which is the voltage difference V between the gate and source of the first transistor M1. GS = Vth+(c1 / c N1_all ) (Vdata-VDD), therefore, V GS -Vth= (c1 / c N1_all ) (Vdata-VDD), that is, the drive current is about (c1 / c N1_all ) The function is (Vdata-VDD). This function does not include VSS or Vth, indicating that the drive current output by this pixel circuit is unaffected by differences in VSS and Vth at different locations on the display panel; that is, it provides good compensation for both VSS and Vth. The drive current ID output by the first transistor M1 is transmitted to the anode of the light-emitting diode D1, causing D1 to emit light according to the drive current ID.

[0121] When the aforementioned pixel circuit driving method is applied to the pixel circuit, during the initialization phase t1, the fifth transistor M5 and the third transistor M3 can be used in a single circuit to simultaneously initialize the gate, drain, and anode of the first transistor M1 and the light-emitting diode D1. A more stable first power supply signal VDD is used to initialize the first node N1. During the threshold compensation phase t2, the first power supply signal VDD is used to stabilize the potential at the first node N1, and simultaneously, it is used to compensate for the threshold voltage Vth of the first transistor M1. This reduces the impact of differences in threshold voltages between different transistors or differences in VDD at different locations on the driving current, improving display uniformity. Furthermore, at the data writing node t3, the data signal Vdata can be quickly written to the gate of the first transistor M1 using the coupling of the first capacitor C1, which is beneficial for meeting market demands for high brightness.

[0122] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0123] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0124] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area surrounding the display area. The display panel includes a substrate and a plurality of sub-pixels disposed on the substrate and located in the display area. The display panel also includes a first power line, a second power line, and a power chip located in the non-display area. The first power line and the second power line are respectively connected to the power chip and the plurality of sub-pixels. The power chip is used to provide a first power signal to the plurality of sub-pixels through the first power line and the second power line. Each of the plurality of sub-pixels includes a pixel circuit, the pixel circuit comprising: The first initialization module is connected to the second power line and the first node respectively, and is used to transmit the first power signal to the first node according to the first scan signal; A threshold compensation module, connected between the second node and the third node, is used to turn the connection between the second node and the third node on or off according to the second scan signal; The data writing module is connected to the first node and is used to transmit data signals to the first node according to the third scan signal; A first storage module is connected between the first node and the second node and is used to store the voltage difference between the first node and the second node; The second storage module is connected between the first node and the first power line and is used to store the voltage difference between the first node and the first power line. A driving module is connected between the first power line and the light-emitting device. The control terminal of the driving module is connected to the second node, and the second terminal of the driving module is connected to the third node. It is used to output a driving signal according to the potential at the second node.

2. The display panel according to claim 1, characterized in that, The first power line includes multiple first sub-power lines extending along a first direction and multiple second sub-power lines extending along a second direction. The multiple first sub-power lines and the multiple second sub-power lines are intersected and connected to form a first mesh structure. The second power line includes multiple third sub-power lines extending along the first direction and multiple fourth sub-power lines extending along the second direction. The multiple third sub-power lines and the multiple fourth sub-power lines are intersected and connected to form a second mesh structure. The first direction intersects with the second direction. In the first direction, the second sub-power line and the fourth sub-power line are arranged alternately, and in the second direction, the first sub-power line and the third sub-power line are arranged alternately. Preferably, the first power line further includes a first connection portion located in the non-display area and connected to the power chip, at least a portion of the second sub-power line extends from the display area to the non-display area and is connected to the first connection portion, the second power line further includes a second connection portion located in the non-display area and connected to the power chip, and at least a portion of the fourth sub-power line extends from the display area to the non-display area and is connected to the second connection portion; Preferably, the first power line further includes a first extension located in the non-display area, the first extension being connected to the first mesh structure, and the first extension at least surrounding a portion of the display area; the second power line further includes a second extension located in the non-display area, the second extension being connected to the second mesh structure, and the second extension at least surrounding a portion of the display area. Preferably, in the second direction, the non-display area includes a first sub-non-display area and a second sub-non-display area. Along the second direction, the display area is located between the first sub-non-display area and the second sub-non-display area. The first extension and the second extension are disposed in the first sub-non-display area. The power chip, the first connection portion, and the second connection portion are disposed in the second sub-non-display area. At least a portion of the second sub-power line extends from the display area to the first sub-non-display area and is connected to the first extension portion. At least a portion of the fourth sub-power line extends from the display area to the second sub-non-display area and is connected to the second extension portion.

3. The display panel according to claim 1, characterized in that, The driving module includes a first transistor, the gate of the first transistor is connected to the second node as the control terminal of the driving module, the first electrode of the first transistor is the first terminal of the driving module, and the second electrode of the first transistor is the second terminal of the driving module. Preferably, the data writing module includes a second transistor, the gate of the second transistor is connected to the third scan signal as the control terminal of the data writing module, the first terminal of the second transistor is connected to the data signal as the first terminal of the data writing module, and the second terminal of the second transistor is connected to the first node as the second terminal of the data writing module. Preferably, the threshold compensation module includes a third transistor, the gate of the third transistor is connected to the second scan signal as the control terminal of the threshold compensation module, the first electrode of the third transistor is connected to the second node as the first terminal of the threshold compensation module, and the second electrode of the third transistor is connected to the second terminal of the driving module as the second terminal of the threshold compensation module. Preferably, the first initialization module includes a fourth transistor, the gate of the fourth transistor is connected to the first scan signal as the control terminal of the first initialization module, the first electrode of the fourth transistor is connected to the second power line as the first terminal of the first initialization module, and the second electrode of the fourth transistor is connected to the first node as the second terminal of the first initialization module. Preferably, the fourth transistor is a dual-gate transistor, and both the first gate and the second gate of the fourth transistor are connected to the first scan signal; Preferably, the first storage module includes a first capacitor, the first terminal of the first capacitor is connected to the first node as the first end of the first storage module, and the second terminal of the first capacitor is connected to the second node as the second end of the first storage module. Preferably, the second storage module includes a second capacitor, the first terminal of the second capacitor is connected to the first node as the first end of the second storage module, and the second terminal of the second capacitor is connected to the first power line as the second end of the second storage module.

4. The display panel according to claim 1, characterized in that, The pixel circuit also includes: A light-emitting module, connected between the third node and the third power line, is used to emit light according to the driving signal; the third power line is used to transmit a second power signal. The pixel circuit includes a non-light-emitting stage and a light-emitting stage. The level of the second power signal in the non-light-emitting stage is a first level, and the level of the second power signal in the light-emitting stage is a second level. The first level is greater than the second level. Preferably, the first level is greater than a first preset value, which is determined based on the potential at the third node when the driving module is turned on.

5. The display panel according to claim 1, characterized in that, The pixel circuit also includes: The second initialization module is connected to the third node and is used to transmit the first initialization signal to the third node according to the fourth scan signal; Preferably, the second initialization module includes a fifth transistor, the gate of the fifth transistor is connected to the fourth scan signal as the control terminal of the second initialization module, the first terminal of the fifth transistor is connected to the first initialization signal as the first terminal of the second initialization module, and the second terminal of the fifth transistor is connected to the third node as the second terminal of the second initialization module. Preferably, the first initialization signal is less than zero.

6. The display panel according to claim 5, characterized in that, The pixel circuit also includes: A light-emitting control module is connected between the first end of the driving module and the first power line, and is used to turn on or off the connection between the first end of the driving module and the first power line according to the light-emitting control signal. Preferably, the light-emitting control module includes a sixth transistor, the gate of the sixth transistor serves as the control terminal of the light-emitting control module and is connected to the light-emitting control signal, the first electrode of the sixth transistor serves as the first terminal of the light-emitting control module and is connected to the first power line, and the second electrode of the sixth transistor serves as the second terminal of the light-emitting control module and is connected to the first terminal of the driving module.

7. The pixel circuit according to claim 5, characterized in that, The pixel circuit also includes: The third initialization module is connected to the first end of the driving module and is used to transmit the second initialization signal to the first end of the driving module according to the fourth scan signal; Preferably, the third initialization module includes a seventh transistor, the gate of the seventh transistor is connected to the fourth scan signal as the control terminal of the third initialization module, the first terminal of the seventh transistor is connected to the second initialization signal as the first terminal of the third initialization module, and the second terminal of the seventh transistor is connected to the first terminal of the driving module as the second terminal of the third initialization module. Preferably, the second initialization signal is less than a second preset value, which is determined based on the first initialization signal and the threshold information of the driving module.

8. The display panel according to claim 1, characterized in that, The pixel circuit includes an initialization phase in one working cycle. In the initialization phase, the first initialization module transmits the first power signal to the first node according to the first scan signal, the threshold compensation module conducts the connection between the second node and the third node according to the second scan signal, the second initialization module transmits the first initialization signal to the third node according to the fourth scan signal, and the third initialization module transmits the second initialization signal to the first end of the driving module according to the fourth scan signal. Wherein, the level of the second power supply signal is the first level; Preferably, a threshold compensation stage is included after the initialization stage. In the threshold compensation stage, the first initialization module transmits the first power signal to the first node according to the first scan signal, the threshold compensation module connects the connection between the second node and the third node according to the second scan signal, and the light emission control module connects the connection between the first end of the driving module and the first power line according to the light emission control signal. Wherein, the level of the second power supply signal is the same as the level of the first power supply signal; Preferably, a data writing stage is included after the threshold compensation stage, in which the data writing module transmits the data signal to the first node according to the third scan signal; Wherein, the level of the second power supply signal is the same as the level of the first power supply signal; Preferably, a light-emitting stage is included after the data writing stage, in which the light-emitting control module connects the first terminal of the driving module to the first power line according to the light-emitting control signal; Wherein, the level of the second power supply signal is the second level, and the first level is greater than the second level.

9. A driving method for a pixel circuit, characterized in that, The driving method is used to drive a pixel circuit in a display panel as described in any one of claims 1 to 9, wherein one working cycle of the pixel circuit includes an initialization phase, a threshold compensation phase, a data writing phase, and a light emission phase, and the driving method includes: During the initialization phase, the level of the first scan signal is controlled to be on, the level of the second scan signal is controlled to be on, and the level of the third scan signal is controlled to be off. During the threshold compensation stage, the level of the first scan signal is controlled to be on, the level of the second scan signal is controlled to be on, and the level of the third scan signal is controlled to be off. During the data writing phase, the level of the first scan signal is controlled to be off, the level of the second scan signal is controlled to be off, and the level of the third scan signal is controlled to be on. During the light emission stage, the level of the first scan signal is controlled to be at the cutoff level, the level of the second scan signal is controlled to be at the cutoff level, and the level of the third scan signal is controlled to be at the cutoff level.

10. The driving method for the pixel circuit according to claim 9, characterized in that, The driving method further includes: During the initialization phase, the level of the fourth scanning signal is controlled to be on, the light emission control signal is controlled to be off, and the level of the second power supply signal is controlled to be the first level. During the threshold compensation stage, the level of the fourth scanning signal is controlled to be cut off, the light emission control signal is controlled to be on, and the level of the second power supply signal is controlled to be the first level. During the data writing phase, the level of the fourth scan signal is controlled to be at the cutoff level, the light emission control signal is controlled to be at the cutoff level, and the level of the second power supply signal is controlled to be at the first level. During the light emission stage, the level of the fourth scanning signal is controlled to be at the cutoff level, the level of the second light emission control signal is controlled to be at the on level, and the level of the second power supply signal is controlled to be at the second level.

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