Composite electronic assembly

Abstract

This disclosure provides a composite electronic component. The composite electronic component includes: a capacitor including a body and an external electrode disposed on the body; and a bump disposed on a lower surface side of the body and connected to the external electrode, wherein the external electrode includes: an electrode layer in contact with an inner electrode; a Ni plating layer disposed on the electrode layer; a first compound layer disposed on the Ni plating layer; a first Sn plating layer disposed on the first compound layer; a second compound layer disposed on the first Sn plating layer; and a second Sn plating layer disposed on the second compound layer. The bump includes: a main portion including a conductive metal; a bump Ni plating layer disposed on the main portion; a first bump compound layer disposed on the bump Ni plating layer; a first bump Sn plating layer disposed on the first bump compound layer; a second bump compound layer disposed on the first bump Sn plating layer; and a second bump Sn plating layer disposed on the second bump compound layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0195147, filed on December 24, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a composite electronic component. Background Technology

[0003] Multilayer ceramic capacitors (MLCCs) are chip capacitors mounted on printed circuit boards in various types of electronic products, such as video display devices (e.g., liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones and mobile phones, and on-board chargers (OBCs) and DC-DC converters for electric vehicles, for charging or discharging.

[0004] Because the dielectric layer included in a multilayer ceramic capacitor has piezoelectricity and electrostriction, piezoelectricity may occur between the internal electrodes when a DC or AC voltage is applied to the multilayer ceramic capacitor, thereby causing vibration.

[0005] The vibration is transmitted through the external electrodes of the multilayer ceramic capacitor to the printed circuit board on which the multilayer ceramic capacitor is mounted, thus producing vibrational sound. This vibrational sound can correspond to audible frequencies in the range of 20Hz to 20000Hz, which can be unpleasant, and this unpleasant vibrational sound is referred to as acoustic noise.

[0006] In the prior art, methods for reducing acoustic noise include making the upper and lower covers of the body have different thicknesses, combining an intermediary containing ceramic material with the lower part of the capacitor, or combining a metal bump with the lower part of the capacitor.

[0007] In detail, in structures where metal bumps are attached to the lower part of the capacitor (such as the structure disclosed in Japanese Patent Application Publication No. 2023-170119), Ni plating and Sn plating are repeatedly disposed on the capacitor and the metal bumps, respectively. In such structures of prior art composite electronic components, during automated mounting, where the capacitor is raised onto the metal bumps to join them, mounting errors may occur due to the uneven surface of the metal bumps. Furthermore, during the reflow soldering process for joining the capacitor and the metal bumps, an excessive and uneven intermetallic compound (IMC) layer may form between the Ni plating and the Sn plating, potentially leading to agglomeration of the Sn plating. Additionally, if the Sn plating is re-plated after the reflow soldering process in this state, the thickness of the Sn plating in the composite electronic component increases, which may lead to an increased soldering defect rate or excessive stress on the composite electronic component when it is mounted on a printed circuit board. Summary of the Invention

[0008] One aspect of this disclosure is to alleviate the problem of mounting defects caused by excessive Sn plating during the process of bonding capacitors and bumps.

[0009] According to one aspect of this disclosure, a composite electronic component includes: a capacitor including a body and an external electrode, the body including a dielectric layer and an internal electrode alternately disposed with respect to the dielectric layer, the external electrode being disposed on the body; and a bump disposed on a lower surface side of the body and connected to the external electrode. The external electrode includes: an electrode layer in contact with the internal electrode; a Ni plating layer disposed on the electrode layer; a first compound layer disposed on the Ni plating layer; a first Sn plating layer disposed on the first compound layer; a second compound layer disposed on the first Sn plating layer; and a second Sn plating layer disposed on the second compound layer. The bump includes: a main portion including a conductive metal; a bump Ni plating layer disposed on the main portion; a first bump compound layer disposed on the bump Ni plating layer; a first bump Sn plating layer disposed on the first bump compound layer; a second bump compound layer disposed on the first bump Sn plating layer; and a second bump Sn plating layer disposed on the second bump compound layer. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will be more clearly understood through the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic perspective view of a composite electronic component according to an embodiment; Figure 2 It is along Figure 1 A cross-sectional view taken from line I-I'; Figure 3 It is along Figure 1 A cross-sectional view taken from line II-II'; Figure 4A and Figure 4B This is a schematic diagram illustrating a process for forming an intermetallic compound layer in a prior art composite electronic component; Figure 5A and Figure 5B This is a schematic diagram illustrating the process of forming a first bump compound layer in a bump according to an embodiment; Figure 6A and Figure 6B This is a schematic diagram illustrating the process of forming a second compound layer and a second bump compound layer in a composite electronic component according to an embodiment; Figure 7 It is shown Figure 2 A schematic diagram of an enlarged view of region P; and Figure 8 This is a schematic diagram illustrating a method for measuring the ten-point average roughness (Rz) of a first bump compound layer according to an embodiment. Detailed Implementation

[0011] In the following description, this disclosure will be illustrated with reference to specific embodiments and accompanying drawings. However, embodiments may be modified in various other forms, and the scope of this disclosure is not limited to the embodiments described below. Furthermore, embodiments are provided to illustrate this disclosure more fully to those skilled in the art. Therefore, for clarity, the shapes and dimensions of elements in the drawings may be exaggerated, and elements indicated by the same reference numerals in the drawings are the same elements.

[0012] Furthermore, for the sake of clarity in the accompanying drawings, parts unrelated to the description have been omitted, and for ease of explanation, the dimensions (e.g., thickness) of each component shown in the drawings are arbitrarily illustrated; therefore, the disclosure is not necessarily limited to what is shown. Additionally, components having the same function within the scope of the same concept are described using the same reference numerals. Moreover, throughout the specification, when a part is referred to as "comprising" a component, this does not mean that other components are excluded, but rather that other components are included, unless otherwise specifically stated.

[0013] In the accompanying drawings, the first direction can be defined as the stacking direction or the thickness direction, the second direction can be defined as the length direction, and the third direction can be defined as the width direction.

[0014] Figure 1 This is a schematic perspective view of a composite electronic component according to an embodiment.

[0015] Figure 2 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0016] Figure 3 It is along Figure 1 The cross-sectional view taken from line II-II'.

[0017] Figure 4A and Figure 4B This is a schematic diagram illustrating a process for forming an intermetallic compound layer in a prior art composite electronic component.

[0018] Figure 5A and Figure 5B This is a schematic diagram illustrating the process of forming a first bump compound layer in a bump according to an embodiment.

[0019] Figure 6A and Figure 6B This is a schematic diagram illustrating the process of forming a second compound layer and a second bump compound layer in a composite electronic component according to an embodiment.

[0020] Figure 7 It is shown Figure 2 A schematic diagram of an enlarged view of region P.

[0021] Figure 8 This is a schematic diagram illustrating a method for measuring the ten-point average roughness (Rz) of a first bump compound layer according to an embodiment.

[0022] In the following text, refer to Figures 1 to 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7 and Figure 8 The composite electronic component 1000 according to the embodiments and its various variant embodiments will be described in detail.

[0023] The composite electronic component 1000 according to an embodiment includes: a capacitor 100 including a body 110 and external electrodes 130 and 140 disposed on the body 110, the body 110 including a dielectric layer 111 and internal electrodes 121 and 122 alternately disposed with the dielectric layer 111; and bumps 230 and 240 disposed on the lower surface side of the body 110 and connected to the external electrodes 130 and 140. The outer electrodes 130 and 140 may include: electrode layers 131 and 141 in contact with the inner electrodes 121 and 122; Ni plating layers 132 and 142 disposed on the electrode layers 131 and 141; first compound layers 135 and 145 disposed on the Ni plating layers 132 and 142; first Sn plating layers 133 and 143 disposed on the first compound layers 135 and 145; second compound layers 136 and 146 disposed on the first Sn plating layers 133 and 143; and second Sn plating layers 134 and 144 disposed on the second compound layers 136 and 146. Bumps 230 and 240 may include: main portions 231 and 241, including conductive metal; bump Ni plating layers 232 and 242 disposed on the main portions 231 and 241; first bump compound layers 235 and 245 disposed on the bump Ni plating layers 232 and 242; first bump Sn plating layers 233 and 243 disposed on the first bump compound layers 235 and 245; second bump compound layers 236 and 246 disposed on the first bump Sn plating layers 233 and 243; and second bump Sn plating layers 234 and 244 disposed on the second bump compound layers 236 and 246.

[0024] The capacitor 100 may include a body 110 and external electrodes 130 and 140 disposed on the body 110.

[0025] The main body 110 may include a dielectric layer 111 and inner electrodes 121 and 122, and the dielectric layer 111 and the inner electrodes 121 and 122 may be alternately disposed in a first direction. For example, in this disclosure, the first direction may refer to the stacking direction of the dielectric layer 111 and the inner electrodes 121 and 122.

[0026] There are no particular restrictions on the specific shape of the main body 110, but as Figure 1 As shown, the body 110 can be formed in a hexahedral shape or a shape similar to a hexahedron. Due to the shrinkage of the ceramic powder included in the body 110 during the firing process, the body 110 may not have a hexahedral shape with perfect straight lines, but may have a generally hexahedral shape.

[0027] The main body 110 may have a first surface 1 and a second surface 2 that are opposite to each other in a first direction, a third surface 3 and a fourth surface 4 that are connected to the first surface 1 and the second surface 2 and are opposite to each other in a second direction perpendicular to the first direction, and a fifth surface 5 and a sixth surface 6 that are connected to the first surface 1 and the second surface 2, connected to the third surface 3 and the fourth surface 4 and are opposite to each other in a third direction perpendicular to the first direction and the second direction.

[0028] Furthermore, since the edge regions of the inner electrodes 121 and 122 on the dielectric layer 111 are not stacked on each other, a step difference is generated due to the thickness of the inner electrodes 121 and 122. When viewed from the first surface 1 or the second surface 2, the edges connecting the first surface 1 with the third surface 3 to the sixth surface 6 and / or the edges connecting the second surface 2 with the third surface 3 to the sixth surface 6 may have a shape that tapers towards the center of the body 110 in the first direction. Optionally, due to the shrinkage behavior of the body 110 during the sintering process, when viewed from the first surface 1 or the second surface 2, the edges connecting the first surface 1 with the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6 and / or the edges connecting the second surface 2 with the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6 may have a shape that tapers towards the center of the body 110 in the first direction. Optionally, in order to prevent defects such as breakage, the edges of each surface of the connecting body 110 can be rounded by performing a separate process, so that the edges connecting the first surface 1 with the third surface 3 to the sixth surface 6 and / or the edges connecting the second surface 2 with the third surface 3 to the sixth surface 6 can have a rounded shape.

[0029] The multiple dielectric layers 111 forming the body 110 are in a sintered state, and adjacent dielectric layers 111 can be integrated to the point that their boundaries are difficult to distinguish without the use of a scanning electron microscope (SEM). The number of dielectric layers stacked is not particularly limited and can be determined by considering the size of the composite electronic components. For example, the body can be formed by stacking 400 or more dielectric layers.

[0030] The dielectric layer 111 can be formed by: manufacturing a ceramic slurry comprising ceramic powder, an organic solvent, and a binder; coating the ceramic slurry onto a carrier film and drying it to prepare a ceramic green sheet; and then firing the ceramic green sheet. There are no particular limitations on the ceramic powder, as long as it can achieve sufficient electrostatic capacitance; however, for example, barium titanate (BaTiO3)-based powder can be used as the ceramic powder. For a more detailed example, the barium titanate (BaTiO3)-based powder can be derived from BaTiO3, (Ba... 1-x Ca x TiO3 (0) <x<1)、Ba(Ti 1-y Ca y )O3(0 <y<1)、(Ba1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) and at least one selected from the group consisting of Ba(Ti 1-y Zr y )O3 (0 < y < 1). Additionally, the CaZrO3-based paraelectric powder can be used as a ceramic powder, and the CaZrO3-based paraelectric powder can be (Ca 1-x Sr x )(Zr 1-y Ti y )O3 (0 < x < 1, 0 < y < 1).

[0031] The average thickness td of the dielectric layer 111 is not particularly limited.

[0032] In order to miniaturize the composite electronic component 1000 and increase the capacitance of the composite electronic component 1000, the average thickness td of the dielectric layer 111 can be 0.35 μm or less, and in order to improve the reliability of the composite electronic component 1000 at high temperatures and high voltages, the average thickness td of the dielectric layer 111 can be 3 μm or more.

[0033] The average thickness td of the dielectric layer 111 can refer to the average thickness of at least one dielectric layer among multiple dielectric layers.

[0034] The average thickness td of the dielectric layer 111 can be measured by using an image obtained by scanning the cross-sections (L-T cross-sections) of the main body 110 in the first direction and the second direction using a scanning electron microscope (SEM). For example, the average thickness td of the dielectric layer 111 can be a value obtained by the following method: using a scanning electron microscope (SEM) to scan the cross-sections (L-T cross-sections) cut from the center in the width direction of the main body 110 to obtain an image, and based on one dielectric layer adjacent to the point where the center line in the length direction and the center line in the thickness direction of the capacitance forming portion intersect, averaging the thicknesses measured at the 1 / 4 point, 2 / 4 point, and 3 / 4 points set by dividing this dielectric layer into four parts in the length direction. If this measurement is extended to the two dielectric layers above and the two dielectric layers below that have equal intervals based on one dielectric layer adjacent to the point where the center line in the length direction and the center line in the thickness direction of the capacitance forming portion intersect, the average thickness of the dielectric layer can be further generalized.

[0035] The main body 110 may include: a capacitance forming portion Ac provided inside the main body 110, and in the capacitance forming portion Ac, a capacitance is formed by including a first internal electrode 121 and a second internal electrode 122 alternately arranged with the dielectric layer 111; and covering portions 112 and 113 formed above and below the capacitance forming portion Ac in the first direction.

[0036] The capacitor forming portion Ac is the part that contributes to the capacitance of the capacitor, and it can be formed by repeatedly stacking a plurality of first internal electrodes 121 and a plurality of second internal electrodes 122 with a dielectric layer 111 located between the first internal electrodes 121 and the second internal electrodes 122, and can refer to the region where the first internal electrodes 121 and the second internal electrodes 122 are stacked in the first direction. Furthermore, the first internal electrode 121 can be disposed at the top end of the capacitor forming portion Ac in the first direction, and the second internal electrode 122 can be disposed at the bottom end of the capacitor forming portion Ac in the first direction.

[0037] The inner electrodes 121 and 122 may include a first inner electrode 121 and a second inner electrode 122. The first inner electrode 121 and the second inner electrode 122 may be alternately disposed with the dielectric layer 111, and the dielectric layer 111 may be interposed between the first inner electrode 121 and the second inner electrode 122. The first inner electrode 121 and the second inner electrode 122 may face each other and may be exposed to the third surface 3 and the fourth surface 4 of the body 110, respectively. For example, in an embodiment, the first inner electrode 121 may have an end that contacts the third surface 3 in a second direction, and the second inner electrode 122 may have an end that contacts the fourth surface 4 in a second direction.

[0038] Reference Figure 2 The first inner electrode 121 can be connected to the first outer electrode 130, and the second inner electrode 122 can be connected to the second outer electrode 140.

[0039] The first inner electrode 121 can be connected to the first outer electrode 130 but not to the second outer electrode 140, and the second inner electrode 122 can be connected to the second outer electrode 140 but not to the first outer electrode 130. For example, the first inner electrode 121 can be formed at a certain distance from the fourth surface 4, and the second inner electrode 122 can be formed at a certain distance from the third surface 3. In addition, the first inner electrode 121 and the second inner electrode 122 can be disposed at a certain distance from the fifth surface 5 and the sixth surface 6 of the body 110.

[0040] The conductive metal included in the inner electrodes 121 and 122 may be at least one selected from the group consisting of Ni, Cu, Pd, Ag, Au, Pt, In, Sn, Al, Ti and alloys thereof, and this disclosure is not limited thereto.

[0041] The average thickness te of the inner electrodes 121 and 122 is not particularly limited and can be varied depending on the purpose. In order to miniaturize the composite electronic component 1000, the average thickness te of the inner electrodes 121 and 122 can be 0.35µm or less, and in order to improve the reliability of the composite electronic component 1000 under high temperature and high voltage, the average thickness te of the inner electrodes 121 and 122 can be 3µm or greater.

[0042] The average thickness te of inner electrodes 121 and 122 may refer to the average thickness of at least one of the multiple inner electrodes.

[0043] The average thickness te of the inner electrodes 121 and 122 can be measured by scanning images of the first and second direction cross sections (LT sections) of the body 110 using a scanning electron microscope (SEM). For example, the average thickness te of the inner electrodes 121 and 122 can be obtained by averaging the thickness measured at the 1 / 4, 2 / 4, and 3 / 4 points, based on a layer of inner electrodes adjacent to the point where the center lines of the length and thickness directions of the capacitor forming portion intersect. If this measurement is extended to two upper and two lower inner electrodes with equal spacing between the points of intersection of the center lines of the length and thickness directions of the capacitor forming portion, the average thickness of the inner electrodes can be further generalized.

[0044] Reference Figure 2 Cover portions 112 and 113 may be disposed on the upper and lower surfaces of the capacitor forming portion Ac in the first direction.

[0045] The covers 112 and 113 can essentially prevent damage to the internal electrodes due to physical stress and / or chemical stress.

[0046] Cover portions 112 and 113 may include the same material as the dielectric layer 111. For example, cover portions 112 and 113 may include a ceramic material, such as a barium titanate (BaTiO3) based ceramic material.

[0047] Furthermore, the thickness of the covers 112 and 113 does not need to be particularly limited. For example, the thickness of the covers 112 and 113 can be 20 μm or less, respectively.

[0048] The average thickness of the covers 112 and 113 may refer to the dimension in the first direction, and may be the average of the dimensions of the covers 112 and 113 in the first direction measured at five equally spaced points above or below the capacitor forming portion Ac.

[0049] Reference Figure 3 Edge portions 114 and 115 may be provided on the side surface of capacitor forming portion Ac.

[0050] Edge portions 114 and 115 may include a first edge portion 114 disposed on one side surface of the capacitor forming portion Ac in the third direction and a second edge portion 115 disposed on the other side surface of the capacitor forming portion Ac in the third direction. For example, edge portions 114 and 115 may be disposed on both side surfaces of the capacitor forming portion Ac in the third direction.

[0051] like Figure 3 As shown, the edges 114 and 115 may refer to the region between the two ends of the first inner electrode 121 and the second inner electrode 122 and the outer surface of the body 110 in a cross section (WT section) cut along the width-thickness direction of the body 110.

[0052] The edges 114 and 115 can essentially prevent damage to the internal electrode due to physical stress and / or chemical stress.

[0053] Edges 114 and 115 can be formed by applying conductive paste to the area of ​​the ceramic green sheet other than the area where the edge is to be formed, to form an internal electrode.

[0054] Furthermore, the widths of the edges 114 and 115 do not need to be particularly limited. For example, the average widths of the edges 114 and 115 can be 20 μm or less, respectively.

[0055] The average width of the edges 114 and 115 can refer to the average size of the regions of the inner electrodes 121 and 122 spaced apart from the fifth surface 5 in the third direction and the average size of the regions of the inner electrodes 121 and 122 spaced apart from the sixth surface 6 in the third direction, and can be the average value of the third-direction dimensions of the edges 114 and 115 measured at five equally spaced points on the side surface of the capacitor forming part Ac.

[0056] External electrodes 130 and 140 may be disposed on the main body 110, and more specifically, may be disposed on the third surface 3 and the fourth surface 4 of the main body 110.

[0057] The external electrodes 130 and 140 may include a first external electrode 130 disposed on the third surface 3 of the body 110 and a second external electrode 140 disposed on the fourth surface 4 of the body 110.

[0058] Furthermore, the external electrodes 130 and 140 are not limited to being disposed only on the third surface 3 and the fourth surface 4 of the main body 110. (See reference...) Figure 1 and Figure 2The first external electrode 130 can be provided by extending from the third surface 3 of the body 110 to a portion of the first surface 1, a portion of the second surface 2, a portion of the fifth surface 5 and a portion of the sixth surface 6, and the second external electrode 140 can be provided by extending from the fourth surface 4 to a portion of the first surface 1, a portion of the second surface 2, a portion of the fifth surface 5 and a portion of the sixth surface 6.

[0059] The outer electrodes 130 and 140 may include electrode layers 131 and 141 disposed on the body 110 and connected to the inner electrodes 121 and 122.

[0060] In detail, the first external electrode 130 may include a first electrode layer 131 disposed on the body 110 and connected to the first internal electrode 121, and the second external electrode 140 may include a second electrode layer 141 disposed on the body 110 and connected to the second internal electrode 122.

[0061] The first electrode layer 131 and the second electrode layer 141 can be connected to the inner electrodes 121 and 122 respectively, and can serve to ensure the electrical connection between the outer electrodes 130 and 140 and the inner electrodes 121 and 122.

[0062] The first electrode layer 131 and the second electrode layer 141 may comprise a conductive metal. Materials with excellent conductivity may be used as the conductive metal, and there are no particular limitations. For example, the conductive metal may be at least one selected from the group consisting of nickel (Ni), copper (Cu), and alloys thereof, and electrode layers 131 and 141 may comprise Cu to ensure conductivity and bonding strength by forming an alloy with the inner electrodes 121 and 122 comprising Ni.

[0063] For a more specific example of the first electrode layer 131 and the second electrode layer 141, the electrode layers 131 and 141 may be sintered electrodes comprising conductive metal and glass, or resin-based electrodes comprising conductive metal and resin.

[0064] The first electrode layer 131 and the second electrode layer 141 may be in the form of a sintered electrode and a resin-based electrode sequentially formed on the body 110. Furthermore, electrode layers 131 and 141 may be formed by transferring a sheet including a conductive metal onto the body 110, or by transferring a sheet including a conductive metal onto a sintered electrode.

[0065] The plating can be applied to electrode layers 131 and 141. The plating improves the sealing and mounting properties of the composite electronic assembly 1000, and also enhances the bonding strength with the bumps 230 and 240, which will be described later. The specific structure of the plating will be described later.

[0066] In addition, there are no particular restrictions on the method of forming the coating, and various methods such as electroless plating and electrolytic plating can be used.

[0067] Bumps 230 and 240 are disposed on the lower surface side of capacitor 100 and can be connected to external electrodes 130 and 140. Bumps 230 and 240 are disposed on the lower surface side of capacitor 100 and can reduce or absorb vibrations transmitted from the substrate to capacitor 100.

[0068] Bumps 230 and 240 may include components that do not melt even during the reflow soldering process, and may have multiple layers to facilitate attachment to capacitor 100.

[0069] According to the embodiment, bumps 230 and 240 may include main portions 231 and 241 containing conductive metal, and the type of conductive metal included in the main portions 231 and 241 is not particularly limited, but when the main portions 231 and 241 include Cu as conductive metal, the effect of suppressing or absorbing vibration can be better.

[0070] Furthermore, since the bumps 230 and 240 according to the embodiment themselves function as electrodes, their conductivity can be excellent. Specifically, the main portions 231 and 241 can be made essentially of only conductive metal. For example, the main portions 231 and 241 may include Cu and O, but the content of O in the main portions 231 and 241 relative to Cu may be at a level of 0.5 at% or less. In this case, the content of O relative to Cu may be greater than 0.01 at%.

[0071] Reference Figure 4A In existing composite electronic components, the capacitor may have the following structure: Ni plating layer 12, Sn plating layer 13, Ni plating layer 14, and Sn plating layer 15 are sequentially disposed on the electrode layer 11, and bonded to bumps in which Ni plating layer 22, Sn plating layer 23, Ni plating layer 24, and Sn plating layer 25 are sequentially disposed on the main portion 21. When a reflow soldering process is performed at a temperature of approximately 270°C to mount such a prior art composite electronic component onto a substrate, as... Figure 4B As shown, a thick and non-uniform intermetallic compound layer 26 can be formed between the Ni plating layer 22 and the Sn plating layer 23 disposed on the main portion 21. Therefore, other plating layers 23, 24, and 25 disposed on the intermetallic compound layer 26 are also prone to form non-uniformly along the surface shape of the intermetallic compound layer 26. This increases the likelihood of agglomeration of the outermost Sn plating layer 25, which directly participates in the mounting process, leading to problems such as reduced mountability of the composite electronic components and increased stress applied to the composite electronic components.

[0072] Reference Figure 2In embodiments of this disclosure, the external electrodes 130 and 140 include: electrode layers 131 and 141 in contact with internal electrodes 121 and 122; Ni plating layers 132 and 142 disposed on electrode layers 131 and 141; first compound layers 135 and 145 disposed on Ni plating layers 132 and 142; first Sn plating layers 133 and 143 disposed on first compound layers 135 and 145; second compound layers 136 and 146 disposed on first Sn plating layers 133 and 143; and second Sn plating layers 134 and 144 disposed on second compound layers 136 and 146. Bumps 230 and 240 may include: main portions 231 and 241, including conductive metal; bump Ni plating layers 232 and 242 disposed on the main portions 231 and 241; first bump compound layers 235 and 245 disposed on the bump Ni plating layers 232 and 242; first bump Sn plating layers 233 and 243 disposed on the first bump compound layers 235 and 245; second bump compound layers 236 and 246 disposed on the first bump Sn plating layers 233 and 243; and second bump Sn plating layers 234 and 244 disposed on the second bump compound layers 236 and 246.

[0073] This structure allows for the uniform formation of the first compound layers 135 and 145 and the first bump compound layers 235 and 245, prevents the agglomeration of the Sn plating layer disposed on the first compound layers 135 and 145 and the first bump compound layers 235 and 245, and prevents identification errors of surface mount technology (SMT) equipment that may occur when mounting the composite electronic component 1000 on the substrate.

[0074] Furthermore, by forming second compound layers 136 and 146 between the first Sn plating layers 133 and 143 and the second Sn plating layers 134 and 144, and by forming second bump compound layers 236 and 246 between the first bump Sn plating layers 233 and 243 and the second bump Sn plating layers 234 and 244, the volume increase of the outermost Sn plating layer due to replating of the Sn plating layers can be suppressed. Therefore, soldering failures or excessive stress on the composite electronic component 1000 that may occur during the process of mounting the composite electronic component 1000 onto the substrate can be effectively mitigated.

[0075] The second compound layers 136 and 146 may be disposed between the first Sn plating layers 133 and 143 and the second Sn plating layers 134 and 144. For example, the first Sn plating layers 133 and 143 and the second Sn plating layers 134 and 144 may be in contact with the second compound layers 136 and 146.

[0076] Similarly, second bump compound layers 236 and 246 may be disposed between the first bump Sn plating layers 233 and 243 and the second bump Sn plating layers 234 and 244. For example, the first bump Sn plating layers 233 and 243 and the second bump Sn plating layers 234 and 244 may be in contact with the second bump compound layers 236 and 246.

[0077] The first compound layers 135 and 145, the second compound layers 136 and 146, the first bump compound layers 235 and 245, and the second bump compound layers 236 and 246 may include intermetallic compounds comprising Ni and Sn.

[0078] The first compound layers 135 and 145, the second compound layers 136 and 146, the first bump compound layers 235 and 245, and the second bump compound layers 236 and 246 may comprise Ni-Sn intermetallic compounds, and examples of Ni-Sn intermetallic compounds include Ni3Sn, Ni3Sn2, and Ni3Sn4. For example, each of the first compound layers 135 and 145, the second compound layers 136 and 146, the first bump compound layers 235 and 245, and the second bump compound layers 236 and 246 may comprise at least one selected from the group consisting of Ni3Sn, Ni3Sn2, and Ni3Sn4.

[0079] Furthermore, in the first compound layers 135 and 145, the second compound layers 136 and 146, the first bump compound layers 235 and 245, and the second bump compound layers 236 and 246, Ni may exist essentially only in the form of Ni-Sn intermetallic compounds. For example, the ratio (e.g., molar ratio or atomic ratio) of Sn to Ni in each of the first compound layers 135 and 145, the second compound layers 136 and 146, the first bump compound layers 235 and 245, and the second bump compound layers 236 and 246 may be 1 / 3 or greater. Additionally, the upper limit of the Sn to Ni ratio in each of the first compound layers 135 and 145, the second compound layers 136 and 146, the first bump compound layers 235 and 245, and the second bump compound layers 236 and 246 is not particularly limited and may vary depending on the type and proportion of the Ni-Sn intermetallic compound. Specifically, when each of the first compound layers 135 and 145, the second compound layers 136 and 146, the first bump compound layers 235 and 245, and the second bump compound layers 236 and 246 is made of Ni3Sn4, the ratio of Sn to Ni (e.g., molar ratio or atomic ratio) can correspond to 4 / 3. Therefore, when each of the first compound layers 135 and 145, the second compound layers 136 and 146, the first bump compound layers 235 and 245, and the second bump compound layers 236 and 246 includes at least one selected from the group consisting of Ni3Sn, Ni3Sn2, and Ni3Sn4, the ratio of Sn to Ni in each of the first compound layers 135 and 145, the second compound layers 136 and 146, the first bump compound layers 235 and 245, and the second bump compound layers 236 and 246 can be greater than or equal to 1 / 3 and less than or equal to 4 / 3.

[0080] In composite electronic components according to embodiments and various variations, compound layers and plating layers can be distinguished by measuring the range of the presence ratios of other elements to a particular element.

[0081] In detail, in the first and second directional cross-sections of the polished composite electronic component towards the third-direction center, specific regions of the external electrodes 130 and 140 or the bumps 230 and 240 can be analyzed by scanning electron microscopy-energy dispersive spectroscopy (SEM-EDS) to obtain the elemental ratios of the corresponding regions. For example, Ni plating layers 132 and 142 in this disclosure may represent regions where Ni element is present at 80 at% or more relative to all elements except oxygen, and the first compound layers 135 and 145 may represent regions where the ratio of Sn element to Ni element is 1 / 3 or greater.

[0082] In this embodiment, the first Sn plating layers 133 and 143 may contact the first bump Sn plating layers 233 and 243, the second compound layers 136 and 146 may contact the second bump compound layers 236 and 246, and the second Sn plating layers 134 and 144 may contact the second bump Sn plating layers 234 and 244. Therefore, the capacitor 100 can be securely bonded to the bumps 230 and 240.

[0083] Reference Figure 2 and Figure 7 In this embodiment, the first bump compound layers 235 and 245 may have surface roughness. Additionally, the first bump compound layers 235 and 245 may be configured to surround the main portions 231 and 241, and in this case, the first bump compound layers 235 and 245 may have surface roughness on the capacitor-side surfaces (e.g., the surfaces of the first bump compound layers 235 and 245 near the capacitor 100). Furthermore, the first bump compound layers 235 and 245 may have surface roughness on all surfaces including the capacitor-side surfaces.

[0084] The surface roughness of the first bump compound layers 235 and 245 can be achieved due to the high heat applied during their formation. However, if the surface roughness of the first bump compound layers 235 and 245 is too high, they will be unevenly formed, and the Sn plating layer on them will be too thick. This may hinder the mitigation of soldering failures or excessive stress on the composite electronic components during the mounting process onto the substrate. Therefore, it is preferable that the surface roughness of the first bump compound layers 235 and 245 does not exceed a specific value.

[0085] Specifically, the ten-point average roughness (Rz) of the first bump compound layers 235 and 245 according to the embodiment can be 1.3 μm or less. For example... Figure 8 As shown, the ten-point average roughness (Rz) can be obtained by using the reference length... The absolute value of the sum of the distances (Yp1+Yp2+Yp3+Yp4+Yp5) between the first, second, third, fourth, and fifth highest peaks and the average line m in the extracted portion, and the reference length. The absolute values ​​of the sum of the distances (Yv1+Yv2+Yv3+Yv4+Yv5) between the first, second, third, fourth, and fifth lowest valleys and the average line m in the extracted portion are added together, and the sum is divided by 5.

[0086] Furthermore, there are no particular limitations on the method for measuring the ten-point average roughness (Rz) of the first bump compound layers 235 and 245. For example, in the first and second direction sections polished to the center of the third direction of the composite electronic assembly 1000, the average roughness (Rz) can be measured by taking the average of the ten-point average roughness (Rz) measured in portions 30 μm from both ends of the second direction on the capacitor (100) side surface (e.g., the surface of the first bump compound layers 235 and 245 near the capacitor 100) or the mounting surface side surface (e.g., the surface of the first bump compound layers 235 and 245 near the mounting surface of the composite electronic assembly 1000) of the first bump compound layers 235 and 245, and in portions 30 μm from the center of the capacitor (100) side surface or the mounting surface side surface of the first bump compound layers 235 and 245.

[0087] In the following, examples of methods for forming the above-described structure according to the embodiments will be described.

[0088] Reference Figure 5A A Ni-plated bump layer 232 and a Sn-plated bump layer 233 can be provided on the main portion 231. Subsequently, a separate preheating treatment can be performed at a temperature of approximately 160°C or lower, which is lower than the temperature in the reflow soldering process. Therefore, as... Figure 5B As shown, a first bump compound layer 235 can be formed between the bump Ni plating layer 232 and the first bump Sn plating layer 233. This preheating treatment can be applied not only to the bumps but also to the capacitor 100. For example, before attaching the bumps 230 and 240 to the capacitor 100, the first compound layers 135 and 145 and the first bump compound layers 235 and 245 may have been formed on the capacitor 100 and the bumps 230 and 240, respectively.

[0089] Since the preheating process corresponds to a temperature below approximately 270°C (approximately 270°C is the temperature of the reflow soldering process), the first compound layers 135 and 145 and the first bump compound layers 235 and 245 can be formed to be thinner and more uniform than in the prior art.

[0090] Next, as Figure 6A As shown, Ni plating layers 137 and 237 and Sn plating layers 134 and 234 can be formed on the capacitor and bumps, respectively, after preheating treatment, for bonding between the capacitor and bumps. Alternatively, for bonding between the capacitor and bumps, a separate preheating process can preferably be performed again, rather than directly mounting on the substrate and as shown in the diagram. Figure 6AThe reflow soldering process is performed while the Ni plating layers 137 and 237 and the Sn plating layers 134 and 234 are formed. The subsequent preheating process can be performed at approximately 160°C or lower, so that the re-plated Ni plating layers 137 and 237 and the Sn plating layers 134 and 234 can react with each other to form a second compound layer 136 and a second bump compound layer 236, as shown below. Figure 6B As shown in the diagram. At this time, when the Ni plating layers 137 and 237 are formed thin enough, the Ni plating layers 137 and 237 in the preheating process can be completely reacted to form the second compound layer 136 and the second bump compound layer 236.

[0091] As described above, according to the embodiments, by suppressing the excessive formation of the outermost Sn plating layer during the process of bonding the capacitor to the bump, the problem of mounting defects in composite electronic components can be mitigated.

[0092] Although embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above embodiments and drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications and alterations can be made by those skilled in the art without departing from the technical spirit of the present disclosure described in the claims, and these also fall within the scope of the present disclosure.

[0093] Furthermore, the expression "(one) embodiment" as used in this disclosure does not imply the same embodiment, but is provided to emphasize and illustrate each unique feature that differs from one another. However, the embodiments presented above do not preclude implementation in combination with features of another embodiment. For example, even if a matter described in a particular embodiment is not described in another embodiment, it may be understood as a description relating to another embodiment, unless a description to the contrary or contradictory of that matter exists in another embodiment.

[0094] The terminology used in this disclosure is for describing one embodiment only and is not intended to limit the disclosure. In this context, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0095] While exemplary embodiments have been described and illustrated above, it will be readily understood by those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A composite electronic component, comprising: A capacitor includes a body and an outer electrode. The body includes a dielectric layer and inner electrodes alternately disposed with the dielectric layer. The outer electrode is disposed on the body. as well as A protrusion is provided on the lower surface side of the body and connected to the external electrode. The external electrode comprises: an electrode layer in contact with the internal electrode; a Ni plating layer disposed on the electrode layer; a first compound layer disposed on the Ni plating layer; a first Sn plating layer disposed on the first compound layer; a second compound layer disposed on the first Sn plating layer; and a second Sn plating layer disposed on the second compound layer. The bump includes: a main portion comprising conductive metal; a bump Ni plating layer disposed on the main portion; a first bump compound layer disposed on the bump Ni plating layer; a first bump Sn plating layer disposed on the first bump compound layer; a second bump compound layer disposed on the first bump Sn plating layer; and a second bump Sn plating layer disposed on the second bump compound layer.

2. The composite electronic assembly of claim 1, wherein, The first bump compound layer has a surface roughness.

3. The composite electronic assembly of claim 1, wherein, The first bump compound layer has a surface roughness on the capacitor-side surface, which is the surface of the first bump compound layer near the capacitor.

4. The composite electronic assembly of claim 3, wherein, The surface roughness is a ten-point average roughness, and The ten-point average roughness of the first bump compound layer is 1.3 μm or less.

5. The composite electronic assembly of claim 1, wherein, The first Sn coating and the second Sn coating are in contact with the second compound layer.

6. The composite electronic assembly of claim 1, wherein, The first bump Sn coating and the second bump Sn coating are in contact with the second bump compound layer.

7. The composite electronic assembly of claim 1, wherein, The first compound layer, the second compound layer, the first bump compound layer, and the second bump compound layer each comprise an intermetallic compound containing Ni and Sn.

8. The composite electronic assembly of claim 7, wherein, The molar ratio of Sn to Ni in each of the first compound layer, the second compound layer, the first bump compound layer, and the second bump compound layer is greater than or equal to 1 / 3 and less than or equal to 4 / 3.

9. The composite electronic assembly of claim 1, wherein, The first Sn coating is in contact with the first bump Sn coating, the second compound layer is in contact with the second bump compound layer, and the second Sn coating is in contact with the second bump Sn coating.

10. The composite electronic assembly of claim 1, wherein, The main part includes Cu.

11. The composite electronic component according to claim 1, wherein, The electrode layer comprises Cu.

12. The composite electronic component according to claim 1, wherein, The main component comprises Cu and O. The content of O relative to Cu is 0.5 at% or less.

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