A 100g coherent acquisition closed-loop demodulation method and system integrating tiadc and demodulation

Abstract

This invention provides a 100G coherent acquisition closed-loop demodulation method and system integrating TIADC and demodulation, belonging to the field of digital signal processing. The method includes: TIADC mismatch correction, frame synchronization and symbol synchronization, resampling clock recovery, frequency domain full dispersion compensation, three-level polarization demultiplexing (CMA+LMS+DDLMS), joint carrier frequency offset estimation and compensation, Viterbi-Viterbi carrier phase recovery, soft decision and full performance monitoring. This invention is the first to use TIADC front-end correction as the first stage of demodulation, achieving deep integration of acquisition and demodulation. The three-level cascaded equalization architecture balances convergence speed and compensation accuracy. A joint carrier recovery closed loop is established through phase residual feedback, significantly improving demodulation robustness and accuracy. This method can output full test indicators in real time, uses FPGA parallel pipelines to reduce processing latency, and is suitable for engineering applications such as 100G coherent acquisition cards and optical communication test instruments.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing, and in particular to a 100G coherent acquisition closed-loop demodulation method and system that integrates TIADC and demodulation. Background Technology

[0002] With the explosive growth of global data traffic, 100G and higher speed coherent optical communication technologies have become the core transmission technologies for backbone networks and metropolitan area networks. Among them, 100G coherent systems using polarization multiplexing-quadrature phase shift keying (PM-QPSK) modulation format have been widely deployed commercially due to their high spectral efficiency and good tolerance to transmission impairments.

[0003] Against this backdrop, coherent acquisition and analysis platforms, used for optical transmission link performance testing, fault location, and system verification, play a crucial role. These platforms need to accurately capture and analyze high-speed optical signals, placing far more stringent demands on the robustness, real-time performance, and observability of their internal digital signal processing (DSP) demodulation algorithms than conventional communication receivers.

[0004] Currently, digital coherent demodulation schemes for 100G PM-QPSK signals typically follow a relatively fixed and sequential processing flow. This flow generally consists of multiple independent functional modules cascaded together, and the main steps include: (1) Dispersion compensation (CD): A static frequency domain equalization filter is usually used in the frequency domain to perform a one-time fixed compensation for the chromatic dispersion accumulated in the fiber optic link. This module usually works independently, and its parameters are based on the link preset and do not participate in the joint optimization of subsequent modules.

[0005] (2) Clock synchronization: An independent clock recovery algorithm, such as the Gardner algorithm, is used to extract the clock error from the received oversampled signal and adjust the sampling phase through an interpolation filter to eliminate the clock frequency and phase deviation between the transmitting and receiving ends.

[0006] (3) Polarization demultiplexing and equalization: The constant modulus algorithm (CMA) is commonly used to perform blind demultiplexing and channel dynamic impairment compensation for polarization multiplexed signals. The CMA algorithm utilizes the constant envelope characteristic of QPSK signals and iteratively updates the adaptive filter coefficients by minimizing the error between the output signal modulus and the desired radius, thereby separating the two polarization signals and compensating for channel impairments such as polarization mode dispersion (PMD).

[0007] (4) Carrier recovery: used to correct the frequency offset and phase noise between the transmitting laser and the local oscillator laser. This process is usually divided into two independent steps: first, the frequency offset is estimated and compensated for over a wide range using a frequency offset estimation algorithm (such as the fourth power spectrum estimation method), and then the residual phase noise is tracked and compensated using a phase estimation algorithm (such as the Viterbi-Viterbi algorithm).

[0008] (5) Decision and output: Perform hard decision on the recovered signal and output the demodulated bit stream.

[0009] In the traditional architecture described above, mismatch correction in a time-interleaved analog-to-digital converter (TIADC) is typically treated as a purely front-end hardware preprocessing step, isolated from the subsequent digital demodulation chain. Any residual errors in the front-end correction stage (such as gain or delay mismatch between channels) will directly and irreversibly enter the demodulation chain, degrading the performance of all subsequent modules as inherent noise.

[0010] However, the above-mentioned solutions in the prior art have the following main drawbacks: (1) Rigid algorithm cascade structure: There is a lack of effective coordination and feedback mechanisms between processing modules, and the structure is completely unidirectional and serial "pipeline". Errors and residual damage generated by the previous module will be passed on and accumulated step by step, which will eventually seriously affect the final signal demodulation quality. Especially under harsh link conditions such as large dispersion, large frequency offset and low signal-to-noise ratio (SNR), it is very easy to cause demodulation failure, constellation diagram divergence and sharp deterioration of bit error rate.

[0011] (2) Slow convergence and poor robustness of polarization equalization: It relies solely on the CMA algorithm for polarization demultiplexing. Although the CMA algorithm can be started blindly, its convergence speed is slow, especially in high dynamic PMD scenarios, requiring tens of thousands or even more symbols to complete convergence. At the same time, the CMA algorithm has a large steady-state error under low signal-to-noise ratio conditions and has limited ability to resist noise and residual interference, making it difficult to meet the dual requirements of coherent acquisition platforms for fast locking and high-precision measurement.

[0012] (3) The carrier recovery module is separate, resulting in weak resistance to large frequency offsets: Since frequency offset estimation and phase recovery are two independent and serial modules, the residual error of the previous frequency offset estimation will be completely transferred to the subsequent phase recovery module. In scenarios with large frequency offsets or wide laser linewidths, even a small residual frequency offset may cause the performance of the subsequent Viterbi-Viterbi phase estimation algorithm to degrade significantly or even fail, limiting the correctable frequency offset range and phase noise tolerance of the system.

[0013] (4) The acquisition front end and demodulation back end are separated: the mismatch correction of TIADC is separated from the demodulation algorithm of the back end, which means that the undesirable characteristics of the acquisition hardware cannot be intelligently perceived and compensated in the back end algorithm. The residual channel mismatch error becomes the "weakest link" that limits the dynamic performance of the entire system.

[0014] (5) Insufficient observability: The design goal of the traditional demodulation process is to provide a reliable bit stream for the communication receiver, and its architecture itself does not take into account the specific needs of the test and measurement field. It cannot provide full performance monitoring indicators required for link analysis and fault diagnosis, such as error vector magnitude (EVM), modulation error ratio (MER), real-time constellation diagram, and eye diagram, and it is difficult to directly adapt to the engineering requirements of high observability of coherent acquisition platforms.

[0015] Therefore, how to provide a 100G coherent demodulation method that can deeply integrate acquisition front-end correction, has cross-module joint optimization capabilities, fast convergence speed, strong robustness, and can meet the requirements of high observability testing is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0016] The purpose of this invention is to overcome the shortcomings of the prior art and provide a complete, robust, and FPGA-based PM-QPSK digital demodulation process in real time, so as to solve the technical problems of rigid algorithm cascade structure, fragmented front-end acquisition and demodulation, slow polarization equalization convergence, poor carrier recovery robustness, and lack of closed-loop feedback in the prior art.

[0017] To achieve the above objectives, this application proposes a 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation, applied to a PM-QPSK coherent optical communication system, comprising the following steps: Step S1: Receive multi-channel sampling signals from a time-interleaved analog-to-digital converter (TIADC), and perform TIADC mismatch correction on the multi-channel sampling signals. The TIADC mismatch correction includes at least channel gain mismatch correction and channel delay mismatch correction to generate a corrected baseband signal. Step S2: Perform frame synchronization and coarse symbol synchronization on the corrected baseband signal to determine the start position of the data frame and the coarse estimate of the symbol boundary, and output the data symbol stream after removing the frame header; Step S3: Based on the coarse estimate of the symbol boundary, perform clock recovery and resampling on the data symbol stream to eliminate clock deviation at the transmitting and receiving ends, and output the synchronized symbol sequence; Step S4: Perform frequency domain dispersion compensation on the synchronized symbol sequence to compensate for chromatic dispersion in the optical fiber link and output the dispersion-compensated signal; Step S5: Perform three-stage cascaded adaptive polarization demultiplexing on the dispersion-compensated signal to separate and compensate for polarization mode dispersion (PMD) and polarization correlation loss (PDL), and output X and Y polarization demultiplexed signals; wherein, the three-stage cascaded process includes sequential execution of constant mode algorithm (CMA) equalization, least mean square algorithm (LMS) equalization, and decision-guided least mean square algorithm (DDLMS) equalization. Step S6: Perform joint carrier recovery on the X and Y polarization demultiplexed signals. The joint carrier recovery includes a frequency offset estimation and compensation step and a carrier phase recovery step. The phase residual information generated by the carrier phase recovery step is fed back to the frequency offset estimation and compensation step to iteratively optimize the frequency offset estimation accuracy and output the carrier-recovered signal. Step S7: Perform decision processing on the signal after carrier recovery, and generate and output demodulated bit stream and full performance monitoring indicators based on the decision result.

[0018] As a further solution, the TIADC mismatch correction in step S1 specifically includes: Step S101: Perform DC bias correction on the output data of each sub-ADC channel by statistically calculating the long-term average of each sub-ADC channel and subtracting the long-term average from the data of each channel. Step S102: Based on the Least Mean Square (LMS) algorithm, with the goal of minimizing the statistical variance of the output signal of each channel, iteratively estimate and compensate for the gain mismatch between each sub-ADC channel; Step S103: Construct a fractional delay filter based on the CORDIC coordinate rotation digital computer algorithm, and dynamically adjust the filter coefficients to compensate for the sampling time deviation according to the estimated time delay error between each sub-ADC channel; Step S104: Use a frequency domain equalization filter to compensate for the frequency response differences between each sub-ADC channel in order to correct the bandwidth mismatch.

[0019] As a further solution, step S2 specifically includes: Barker code with sharp autocorrelation characteristics is used as the frame header synchronization word. The correlation peak is detected by performing sliding correlation operation between the received baseband signal and the local synchronization word sequence. When the correlation peak exceeds the preset adaptive threshold, it is determined to be the frame header position, thereby completing the frame synchronization lock. Autocorrelation is performed on the preamble sequence based on the frame header position, and a coarse estimate of the symbol boundary is obtained by searching for the correlation peak position, thereby completing coarse symbol synchronization.

[0020] As a further solution, step S3 specifically includes: The Gardner clock synchronization algorithm is used to extract the clock error signal from the data symbol stream; The coarse estimate of the symbol boundary obtained in step S2 is used as the initial phase value of the numerically controlled oscillator (NCO) in the clock recovery loop to shorten the lock-in time of clock recovery. After clock recovery is complete and steady-state tracking is entered, stable symbol sampling time information is fed back to the frame synchronization step to help maintain the frame synchronization state.

[0021] As a further solution, the workflow of the three-stage cascaded adaptive polarization demultiplexing in step S5 specifically includes: In the first stage, blind equalization is performed using the constant modulus algorithm (CMA). The equalizer coefficients are iteratively updated using the constant modulus cost function until a first preset condition is met, at which point the process switches to the second stage. The first preset condition is that the CMA convergence residual is lower than a first threshold and the error vector magnitude (EVM) of the equalized signal is lower than a second threshold, or the number of iterations reaches a preset upper limit. The second stage uses the Least Mean Square (LMS) algorithm for fine equalization, updating the equalizer coefficients with the goal of minimizing the equalization error, until the second preset condition is met, then switches to the third stage; the second preset condition is that the mean square value of the equalization error of LMS is lower than the third threshold, and the EVM of the equalized signal is lower than the fourth threshold. The third stage employs the Decision-Guided Least Mean Square (DDLMS) algorithm for high-precision equalization. The equalizer coefficients are updated using the decision error between the sign after the decision and the equalizer output signal to eliminate residual polarization crosstalk.

[0022] As a further solution, step S5 also includes a cross-module error feedback mechanism, specifically: The decision error calculated in the third-level DDLMS equalization step is fed back in real time to the first-level CMA equalization step and / or the second-level LMS equalization step to assist in updating the equalizer tap coefficients of the corresponding level, so as to achieve dynamic joint optimization of the end-link equalization performance.

[0023] As a further solution, the joint carrier recovery in step S6 specifically includes: Step S601: Coarse frequency offset estimation step, performing a fourth power operation on the input signal to eliminate modulation phase information, then performing a Fast Fourier Transform (FFT) and searching for spectral peaks to calculate a coarse frequency offset estimate, and performing initial frequency offset compensation based on the coarse frequency offset estimate. Step S602: Carrier phase recovery step, performing phase estimation based on the Viterbi-Viterbi algorithm on the signal after initial frequency offset compensation to compensate for phase noise, and outputting the phase-recovered signal and the corresponding phase residual value; Step S603: Joint closed-loop iteration step, using a preset symbol period as the unit, calculate the average value of the phase residual value, and feed it back to the frequency offset estimation and compensation step to adjust the frequency offset estimate value to correct the residual error of the frequency offset estimation.

[0024] As a further solution, the full-scale performance monitoring indicators in step S7 include at least one of the following or any combination thereof: Error vector amplitude (EVM), modulation error ratio (MER), signal-to-noise ratio (SNR), bit error rate (BER), constellation diagram data, and eye diagram data.

[0025] As a further solution, all steps of the method are implemented using a parallel pipelined architecture of a field-programmable gate array (FPGA) to achieve a processing latency of less than 200 nanoseconds.

[0026] On the other hand, the present invention also provides a 100G coherent acquisition closed-loop demodulation system integrating TIADC and demodulation, including a TIADC acquisition unit and a digital signal processing unit, wherein the digital signal processing unit is configured to perform a 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation as described in any of the preceding claims.

[0027] Compared with related technologies, the 100G coherent acquisition closed-loop demodulation method and system that integrates TIADC and demodulation provided by this invention has the following advantages: 1. This invention achieves end-to-end joint optimization from acquisition to decision by constructing an eight-level full-link closed-loop architecture and introducing a cross-module error feedback mechanism, effectively suppressing the chain propagation of errors. This invention supports a dispersion compensation range of up to 8000 ps / nm and a frequency offset correction range of ±200 MHz, while maintaining stable demodulation under signal-to-noise ratio conditions as low as 10 dB, and improving OSNR sensitivity by approximately 2 dB compared to traditional solutions.

[0028] 2. This invention features a pioneering three-stage cascaded polarization demultiplexing architecture (CMA+LMS+DDLMS), which combines the rapid locking capability of blind equalization with the high-precision compensation capability of decision-guided equalization. Under the same conditions, the convergence time is reduced from approximately 10,000 symbols to less than 3,000 symbols, improving the convergence speed by more than three times; the demodulated error vector amplitude (EVM) can be stably kept below 9%.

[0029] 3. This invention establishes a joint closed-loop iterative mechanism between frequency offset estimation and phase recovery, and uses phase residual feedback to dynamically correct the frequency offset estimate, which greatly improves the tolerance to large residual frequency offset and high phase noise, and effectively solves the failure problem of traditional discrete processing in high linewidth laser scenarios.

[0030] 4. This invention uses TIADC channel mismatch correction as the first stage of the demodulation process, and performs end-point compensation for the non-ideal nature of the front-end hardware in the digital domain, avoiding the residual propagation problem caused by independent front-end correction, and ensuring the high fidelity of the input back-end link signal.

[0031] 5. This invention integrates a full performance monitoring module at the end of the demodulation link, which can output hard decision bit stream, soft decision log-likelihood ratio information (for FEC), constellation diagram data, eye diagram data, EVM, MER, SNR and BER and other full-dimensional test indicators in real time and in parallel, perfectly adapting to the engineering requirements of 100G coherent acquisition cards and optical communication testers for real-time analysis, debugging and fault diagnosis.

[0032] 6. The entire demodulation process of this invention adopts a parallel pipeline architecture design for field-programmable gate arrays (FPGAs), with a processing latency of less than 200 nanoseconds, which fully meets the real-time and online processing requirements of 100G rate signals and has extremely high engineering practical value. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0035] Figure 1 A flowchart illustrating the steps of the end-to-end processing workflow provided in this embodiment of the invention; Figure 2 This is a schematic diagram of the overall architecture of the demodulation system provided in an embodiment of the present invention; Figure 3 The flowchart of the three-level cascaded adaptive balancing architecture provided by this invention; The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0037] Please see Figure 1 This embodiment provides a 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation, applied to a PM-QPSK coherent optical communication system, including the following steps: Step S1: Receive multi-channel sampling signals from a time-interleaved analog-to-digital converter (TIADC), and perform TIADC mismatch correction on the multi-channel sampling signals. The TIADC mismatch correction includes at least channel gain mismatch correction and channel delay mismatch correction to generate a corrected baseband signal. Step S2: Perform frame synchronization and coarse symbol synchronization on the corrected baseband signal to determine the start position of the data frame and the coarse estimate of the symbol boundary, and output the data symbol stream after removing the frame header; Step S3: Based on the coarse estimate of the symbol boundary, perform clock recovery and resampling on the data symbol stream to eliminate clock deviation at the transmitting and receiving ends, and output the synchronized symbol sequence; Step S4: Perform frequency domain dispersion compensation on the synchronized symbol sequence to compensate for chromatic dispersion in the optical fiber link and output the dispersion-compensated signal; Step S5: Perform three-stage cascaded adaptive polarization demultiplexing on the dispersion-compensated signal to separate and compensate for polarization mode dispersion (PMD) and polarization correlation loss (PDL), and output X and Y polarization demultiplexed signals; wherein, the three-stage cascaded process includes sequential execution of constant mode algorithm (CMA) equalization, least mean square algorithm (LMS) equalization, and decision-guided least mean square algorithm (DDLMS) equalization. Step S6: Perform joint carrier recovery on the X and Y polarization demultiplexed signals. The joint carrier recovery includes a frequency offset estimation and compensation step and a carrier phase recovery step. The phase residual information generated by the carrier phase recovery step is fed back to the frequency offset estimation and compensation step to iteratively optimize the frequency offset estimation accuracy and output the carrier-recovered signal. Step S7: Perform decision processing on the signal after carrier recovery, and generate and output demodulated bit stream and full performance monitoring indicators based on the decision result.

[0038] It should be noted that this embodiment provides a 100G coherent acquisition closed-loop demodulation method that integrates TIADC and demodulation. This method is applicable to coherent optical communication receiving systems with PM-QPSK modulation format, especially for test platforms that require high real-time performance and high observability, such as 100G coherent acquisition cards and optical communication testers.

[0039] Figure 1 A flowchart illustrating the end-to-end processing workflow in one embodiment of the present invention is shown. The following is in conjunction with... Figure 1 The eight-level full-link closed-loop demodulation process of this embodiment is described in detail.

[0040] Level 1: TIADC mismatch correction This step, serving as the entry point for the demodulation process, receives the multi-channel sampled signal from the Time-Interleaved Analog-to-Digital Converter (TIADC) and performs channel mismatch correction on this signal. This embodiment employs a hybrid-domain blind correction algorithm based on statistical characteristics, specifically including the following sub-steps: S101, DC bias correction: Calculate the long-term average value of the output data of each sub-ADC channel, and subtract the statistical average value of the corresponding channel from the original sampled data of each channel to eliminate the DC offset error between each sub-ADC channel.

[0041] S102, Channel Gain Mismatch Correction: An adaptive correction method based on the Least Mean Square (LMS) algorithm is adopted. With minimizing the statistical variance of the output signal of each channel as the optimization objective, the gain correction coefficient of each sub-ADC channel is estimated iteratively, and the data of each channel is multiplied by the corresponding gain correction coefficient, thereby normalizing the signal amplitude between each sub-ADC channel and eliminating gain mismatch.

[0042] S103. Sub-ADC Delay Mismatch (SKEW) Correction: An adjustable fractional delay filter is constructed based on the Coordinate Rotation Digital Computer (CORDIC) algorithm. The tap coefficients of the fractional delay filter are dynamically adjusted according to the pre-estimated or adaptively estimated sampling delay error between each sub-ADC channel to precisely align the delay of each channel's data, thereby compensating for the sampling time deviation caused by the inconsistency of the factor ADC sampling clock phase.

[0043] S104, Frequency Domain Bandwidth Mismatch Equalization: By constructing a frequency domain equalization filter, the frequency response differences of each sub-ADC channel are compensated. This step filters the signals of each channel in the frequency domain to correct the high-frequency channel mismatch caused by the inconsistency of analog bandwidth, and finally outputs a high-fidelity, mismatch-free digital baseband signal.

[0044] This invention uses the aforementioned TIADC mismatch correction stage as the first processing stage of the entire digital demodulation link, realizing the deep integration of front-end acquisition correction and back-end demodulation algorithm, fundamentally avoiding the problem of residual error caused by independent front-end correction in traditional solutions being transmitted to subsequent links.

[0045] Level 2: Frame synchronization and coarse symbol synchronization This step receives the corrected baseband signal from the first stage output and determines the start position of the data frame and a coarse estimate of the symbol boundaries, establishing a unified timing reference for subsequent processing. Specifically, it includes: S201, Frame Synchronization: A 13-bit Barker code with sharp autocorrelation characteristics is designed and adopted as the frame header synchronization word. At the receiving end, the received baseband data stream is subjected to symbol-by-symbol sliding cross-correlation with the locally stored synchronization word sequence. The calculation formula is as follows: in, The moving cross-correlation value, In order to receive signals, For local synchronization of characters, Synchronization word length, These are the iteration parameters. When the detected correlation peak exceeds the preset adaptive threshold (e.g., set to 85% of the theoretical maximum correlation value of the synchronization word), and the confirmation condition of detecting the correlation peak multiple times consecutively (e.g., twice) is met, the current time is determined to be the frame header position, and frame synchronization locking is completed.

[0046] S202, Coarse Symbol Synchronization: Based on the preamble sequence near the frame header determined by frame synchronization, its autocorrelation characteristics are utilized, and a sliding window is used to calculate the correlation metric function between adjacent sampling points. By searching for the peak position of this correlation metric function, a coarse estimate of the symbol start boundary is obtained, thus completing coarse symbol synchronization.

[0047] After completing frame synchronization and coarse symbol synchronization, the frame header overhead field in the received signal is removed, and a clean data symbol stream is output to ensure that the subsequent equalization and demodulation modules start processing from a correct symbol start position.

[0048] Level 3: Resampling and Clock Recovery This step eliminates sampling timing errors introduced by clock source frequency deviations and phase jitter at both the transmitting and receiving ends, achieving precise symbol rate alignment. Simultaneously, this step establishes a linkage mechanism with the second-level frame synchronization module to optimize overall synchronization performance. Specifically, it includes: S301, Clock Recovery: The Gardner clock synchronization algorithm is adopted. This algorithm uses the amplitude and symbol characteristics of adjacent symbol sampling points and their intermediate sampling points to extract the clock timing error signal. The extracted timing error signal is smoothed by a second-order loop filter and then drives a numerically controlled oscillator (NCO) to adjust the interpolation phase of the interpolation resampling filter, thereby outputting a data stream at 1 symbol rate that is precisely aligned with the optimal sampling time of the symbol.

[0049] S302. Linkage Mechanism with Frame Synchronization: Initial Locking Phase: The coarse estimate of the symbol boundary obtained from the second-level coarse symbol synchronization is used as the initial phase control word of the numerically controlled oscillator (NCO) in the clock recovery loop of this step. This significantly reduces the initial acquisition range of the clock recovery loop, shortening the locking time from tens of thousands of symbols required by the traditional independent processing method to less than 2,000 symbols. Steady-State Tracking Phase: After the clock recovery loop enters the locked state, the obtained precise symbol sampling time information is fed back to the second-level frame synchronization module to assist in the tracking and maintenance of the frame synchronization state, thereby avoiding frame synchronization loss due to slow clock drift and improving the stability of the system during long-term operation.

[0050] This step ultimately outputs a strictly aligned symbol rate sequence with no clock frequency or phase offset.

[0051] Level 4: Frequency Domain Total Dispersion Compensation This step is used to compensate for all chromatic dispersion (CD) accumulated in the optical signal in the fiber optic link in a single step. This embodiment employs a frequency-domain fast convolutional equalization technique based on overlap preservation. The received signal is divided into blocks and transformed to the frequency domain using a Fast Fourier Transform (FFT). This is then multiplied in the frequency domain by the inverse function of the pre-stored dispersion transfer function, and finally transformed back to the time domain using an Inverse Fast Fourier Transform (IFFT). This method can support a dispersion compensation range of up to 8000 ps / nm in a parallel and highly efficient manner, effectively eliminating severe inter-symbol interference caused by dispersion and providing a relatively clean input signal for the subsequent polarization demultiplexing module.

[0052] Fifth stage: CMA+LMS+DDLMS three-stage cascaded polarization demultiplexing This step is a core innovation of this invention, used for fine compensation of polarization demultiplexing and residual channel impairments in the dispersion-compensated signal. For example... Figure 3 As shown, this step employs a three-stage adaptive equalizer architecture consisting of Constant Modulus Algorithm (CMA), Least Mean Square Algorithm (LMS), and Decision-Guided Least Mean Square Algorithm (DDLMS), cascaded sequentially to achieve the optimal balance between convergence speed and compensation accuracy.

[0053] S501, Level 1: CMA Constant Modulus Algorithm for Fast Blind Convergence. The CMA equalizer requires no training sequence and iteratively updates the equalizer coefficients by minimizing the Godard cost function Jcma=E[(|yk|²-R²)²] (where R is the ideal constant modulus value of the QPSK signal). CMA is responsible for quickly locking the dominant state of the two polarization states under blind conditions, completing the initial polarization demultiplexing. The equalizer switches from CMA to LMS mode when any of the following preset switching criteria are met: Criterion 1: The convergence residual value of the CMA cost function is lower than the first preset threshold (e.g., 0.01), and the error vector magnitude (EVM) of the current equalized signal is lower than the second preset threshold (e.g., 15%); Criterion 2: The number of iterations of the CMA algorithm reaches the preset upper limit (e.g., 3000 times).

[0054] S502, Level 2: LMS Algorithm Fine Equalization. After switching to LMS mode, the equalizer continues to iteratively update the tap coefficients with the goal of minimizing the mean square error between the equalizer output signal and the desired signal. The LMS algorithm, based on the initial convergence of CMA, can provide more refined compensation for residual polarization mode dispersion (PMD) and inter-symbol interference, further improving signal quality. When the mean square error (MSE) of the LMS algorithm is lower than the third preset threshold (e.g., 0.005), and the EVM of the current equalized signal is lower than the fourth preset threshold (e.g., 12%), the equalizer switches from LMS to DDLMS mode.

[0055] S503, Level 3: DDLMS Decision-Guided High-Precision Equalization. The DDLMS equalizer uses an ideal reference symbol obtained after hard-decision analysis of the current output symbol to calculate the decision error and drives the update of the equalizer coefficients based on this error. This mode can eliminate polarization crosstalk remaining after polarization demultiplexing to the greatest extent, so that the output constellation height converges to the ideal position.

[0056] S504, Cross-Level Error Feedback Mechanism. In this embodiment, the decision error e(n) = d(n) - y(n) (where d(n) is the decision reference symbol and y(n) is the equalizer output) generated by the third-level DDLMS equalizer is not only used for coefficient updates at this level, but is also fed back in real time to the preceding CMA equalizer and / or LMS equalizer modules. The preceding equalizer can use this global error information to assist in updating its own tap coefficients. The coefficient update formula is w(n+1) = w(n) + μ·e(n)·x*(n), where μ is the iteration step size and x(n) is the equalizer input. This closed-loop feedback mechanism realizes dynamic joint optimization of the end-to-end equalization performance.

[0057] After this step, the final output consists of completely separated X-path and Y-path polarization signals with highly suppressed polarization crosstalk.

[0058] Level 6: Joint Carrier Frequency Offset Estimation and Compensation This step is used to estimate and correct the frequency offset between the emitted laser and the local oscillator laser. In this embodiment, it is jointly designed with the subsequent phase retrieval step to form a closed-loop iterative optimization mechanism.

[0059] S601, Fourth-Power Coarse Frequency Offset Estimation. The input signal is subjected to a fourth-power operation to remove QPSK modulation phase information. An estimation window of 1024 consecutive symbols is selected, and a Fast Fourier Transform (FFT) is performed on the data after the fourth-power operation. Zero-padding is used to expand the FFT points to 2048 points to improve frequency resolution. A coarse estimate of the frequency offset is calculated by searching for peak positions in the FFT spectrum. This algorithm supports a wide frequency offset estimation range of ±200MHz, with an estimation accuracy better than 1kHz.

[0060] S602, Joint Closed-Loop Iterative Mechanism. After completing phase estimation, the subsequent seventh-stage carrier phase recovery module (Viterbi-Viterbi algorithm) generates a set of phase residual values ​​Δφ. This step calculates the average value of the phase residual within a preset period (e.g., every 1024 symbols) and feeds this average phase residual back to the frequency offset estimation module in this step. The frequency offset estimation module dynamically adjusts its estimated frequency offset value Δf based on the feedback residual information, thereby updating the frequency control word of the numerically controlled oscillator (NCO) used to compensate for the frequency offset, achieving fine-grained iterative correction of the residual frequency offset.

[0061] Through the above-mentioned joint mechanism, the present invention effectively eliminates the direct impact of frequency offset estimation residuals on subsequent phase recovery performance in traditional serial processing, and greatly improves the carrier recovery robustness in scenarios with large dynamic frequency offsets and high laser linewidths.

[0062] Level 7: Carrier Phase Recovery This step is used to compensate for the phase noise of the laser. This embodiment employs the classic Viterbi-Viterbi algorithm. The signal after joint carrier frequency offset compensation is subjected to a fourth power operation to remove the data modulation phase. Then, multiple consecutive symbols are averaged using a sliding window to smooth out the noise effect. Finally, the estimated value of the phase noise is extracted and inverse compensation is performed. Simultaneously with compensating for phase noise, this step outputs the calculated phase residual Δφ for use by the sixth-stage joint closed-loop iterative mechanism.

[0063] Level 8: Soft Decision and Performance Monitoring This step, as the final stage of the demodulation process, performs the final decision processing on the recovered high-quality signal and generates the full observability test metrics required by the coherent acquisition platform. Specific outputs include: hard-decision bitstream, log-likelihood ratio (LLR) soft information for soft-decision forward error correction (FEC) decoding, original constellation diagram data points, original eye diagram data points, and error vector magnitude (EVM), modulation error ratio (MER), signal-to-noise ratio (SNR), and bit error rate (BER) calculated in real-time based on received signal statistics and decision errors.

[0064] All eight processing steps described in this embodiment can be implemented in hardware using a parallel pipeline architecture based on a Field Programmable Gate Array (FPGA) platform. Thanks to this architecture design, the entire processing latency from ADC sampling signal input to final test result output is controlled within 200 nanoseconds, fully meeting the real-time, online demodulation processing requirements of 100G rate PM-QPSK signals.

[0065] Example 2 Please see Figure 2 This embodiment also provides a 100G coherent acquisition closed-loop demodulation system that integrates TIADC and demodulation, including a TIADC acquisition unit and a digital signal processing unit. The digital signal processing unit is configured to execute a 100G coherent acquisition closed-loop demodulation method that integrates TIADC and demodulation as described in any of the preceding embodiments.

[0066] It should be noted that the 100G coherent acquisition closed-loop demodulation system with TIADC and demodulation fusion provided in this embodiment is an end-to-end closed-loop digital demodulation link with a total of 8 modules, which are cascaded sequentially and support cross-module error feedback. The demodulation error of the later module can be fed back to the previous equalization module to dynamically adjust the equalization coefficient and achieve performance optimization of the entire link. The specific architecture is shown in Figure 2. Module 1: TIADC Mismatch Correction Module. This module is located at the very front end of the system and directly receives the multi-channel sampling signals output by the TIADC acquisition unit. Internally, this module integrates a DC bias correction unit, a channel gain mismatch correction unit, a sub-ADC time delay mismatch (SKEW) correction unit, and a frequency domain bandwidth mismatch equalization unit. This module is used for blind estimation and real-time compensation of time interleaving sampling errors at the acquisition front end, outputting a high-fidelity digital baseband signal. By using TIADC correction as the first-level module of the demodulation system, deep hardware-level integration of the acquisition front end and digital demodulation is achieved.

[0067] Module 2: Frame Synchronization and Symbol Synchronization Module. This module receives the baseband signal output from the TIADC mismatch correction module. Internally, it includes a Barker code-based sliding correlator for detecting the frame header position and locking the frame synchronization; and a symbol boundary estimation unit for extracting a coarse estimate of the symbol start position to achieve coarse symbol synchronization.

[0068] Module 3: Resampling and Clock Recovery Module. This module receives the data symbol stream and coarse synchronization information output from the frame synchronization and symbol synchronization modules. Internally, it includes a Gardner timing error detector, a loop filter, a numerically controlled oscillator (NCO), and an interpolation filter. A significant feature of this module is that its NCO's initial phase input is connected to the output of the symbol boundary estimation unit in Module 2, forming a forward initialization path. Simultaneously, the stable sampling timing information locked by this module is transmitted back to Module 2 via a feedback bus, forming a backward auxiliary tracking path, thus creating a linked optimization mechanism for frame synchronization and clock recovery.

[0069] Module 4: Frequency Domain Full Dispersion Compensation Module. This module receives the synchronization symbol sequence output by the resampling and clock recovery module. Internally, it adopts a parallel FFT / IFFT processing architecture based on the overlap-preservation method, including an overlap-preservation buffer unit, an FFT transform unit, a frequency domain dispersion transfer function multiplier array, and an inverse IFFT transform unit, used to compensate for full chromatic dispersion in the fiber optic link in a single step.

[0070] Module 5: CMA+LMS+DDLMS Three-Level Cascaded Polarization Demultiplexing Module. This module is one of the core innovative modules of the system. Internally, it consists of three sub-equalizer hardware cores cascaded in sequence: the first-level CMA constant mode blind equalizer core, used for fast locking of the dominant polarization state; the second-level LMS fine equalizer core, used for compensating for residual PMD and inter-symbol interference; and the third-level DDLMS decision-guided equalizer core, used for high-precision elimination of polarization crosstalk.

[0071] Each sub-equalizer core is connected by a switching control logic unit, which automatically switches algorithms based on preset convergence residuals, EVM, or iteration count criteria. Furthermore, this module has a global error feedback bus, through which the decision error generated by the third-level DDLMS core is fed back to the preceding equalizer core in real time, assisting in coefficient updates and enabling cross-level joint optimization.

[0072] Module Six: Joint Carrier Frequency Offset Estimation and Compensation Module. This module receives the X and Y polarization demultiplexed signals output from Module Five. Internally, it includes a fourth-power frequency offset estimation unit and a numerically controlled oscillator (NCO) compensation unit. A significant feature of this module is its residual feedback input port, which receives phase residual information from the subsequent module Seven and dynamically adjusts the frequency offset estimate and the NCO frequency control word based on this residual, forming a closed-loop iterative correction circuit.

[0073] Module 7: Carrier Phase Recovery Module. This module receives the frequency offset compensated signal output from Module 6. Internally, it employs a hardware implementation unit of the Viterbi-Viterbi phase estimation algorithm to compensate for laser phase noise. This module has a phase residual output port to feed back the residual value generated during phase estimation to Module 6.

[0074] Module 8: Soft Decision and Performance Monitoring Module. Located at the very end of the system, this module receives the carrier recovery signal output from Module 7. Internally, it includes a hard decision unit, a soft decision log-likelihood ratio (LLR) calculation unit, an EVM real-time statistical calculation unit, a MER / SNR calculation unit, a BER statistical unit, and a constellation diagram / eye diagram data buffer unit. This module connects to the host computer via a standard interface (such as PCIe or Ethernet) and can output the demodulated bitstream and full performance monitoring indicators in real time.

[0075] In a more specific embodiment, the system achieved indicator verification through testing. The main technical indicators achieved by the system in this embodiment are shown in Table 1 below: Table 1 System Indicator Comparison Table In summary, the system described in this embodiment, through the ordered cascading of the above eight modules and the cross-module closed-loop feedback design, possesses the following significant technical advantages compared to traditional discrete demodulation systems: (1) Extremely robust: It can support large dispersion compensation of up to 8000ps / nm and large frequency offset correction of ±200MHz. It can still achieve stable demodulation under signal-to-noise ratio conditions as low as 10dB. The OSNR sensitivity is improved by 2dB compared with the traditional scheme.

[0076] (2) Fast convergence speed: The three-level polarization demultiplexing architecture reduces the convergence time from about 10,000 symbols to less than 3,000 symbols, improving the convergence speed by more than 3 times.

[0077] (3) High demodulation accuracy: The demodulated error vector amplitude (EVM) can be stably below 9%, and the bit error rate (BER) can be as low as 1×10 under typical operating conditions. -12 This reduces costs by three orders of magnitude compared to traditional solutions.

[0078] (4) Full observation capability: It can output constellation diagram, eye diagram, EVM, MER, SNR, BER and other full-dimensional test indicators in real time and in parallel, perfectly adapting to the test requirements of coherent acquisition platform.

[0079] (5) Real-time implementation: The entire system adopts an FPGA parallel pipeline architecture design, and the total processing delay from ADC sampling input to index output is less than 200ns, which meets the real-time online processing requirements of 100G signals.

[0080] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation, applied to a PM-QPSK coherent optical communication system, characterized in that... Includes the following steps: Step S1: Receive multi-channel sampling signals from a time-interleaved analog-to-digital converter (TIADC), and perform TIADC mismatch correction on the multi-channel sampling signals. The TIADC mismatch correction includes at least channel gain mismatch correction and channel delay mismatch correction to generate a corrected baseband signal. Step S2: Perform frame synchronization and coarse symbol synchronization on the corrected baseband signal to determine the start position of the data frame and the coarse estimate of the symbol boundary, and output the data symbol stream after removing the frame header; Step S3: Based on the coarse estimate of the symbol boundary, perform clock recovery and resampling on the data symbol stream to eliminate clock deviation at the transmitting and receiving ends, and output the synchronized symbol sequence; Step S4: Perform frequency domain dispersion compensation on the synchronized symbol sequence to compensate for chromatic dispersion in the optical fiber link and output the dispersion-compensated signal; Step S5: Perform three-stage cascaded adaptive polarization demultiplexing on the dispersion-compensated signal to separate and compensate for polarization mode dispersion (PMD) and polarization correlation loss (PDL), and output X and Y polarization demultiplexed signals; wherein, the three-stage cascaded process includes sequential execution of constant mode algorithm (CMA) equalization, least mean square algorithm (LMS) equalization, and decision-guided least mean square algorithm (DDLMS) equalization. Step S6: Perform joint carrier recovery on the X and Y polarization demultiplexed signals. The joint carrier recovery includes a frequency offset estimation and compensation step and a carrier phase recovery step. The phase residual information generated by the carrier phase recovery step is fed back to the frequency offset estimation and compensation step to iteratively optimize the frequency offset estimation accuracy and output the carrier-recovered signal. Step S7: Perform decision processing on the signal after carrier recovery, and generate and output demodulated bit stream and full performance monitoring indicators based on the decision result.

2. The 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation according to claim 1, characterized in that, The TIADC mismatch correction in step S1 specifically includes: DC bias correction is performed on the output data of each sub-ADC channel by statistically analyzing the long-term average value of each sub-ADC channel and subtracting the long-term average value from the data of each channel. Based on the Least Mean Square (LMS) algorithm, the goal is to minimize the statistical variance of the output signal of each channel, and to iteratively estimate and compensate for the gain mismatch between each sub-ADC channel. A fractional delay filter is constructed based on the CORDIC coordinate rotation digital computer algorithm. The filter coefficients are dynamically adjusted to compensate for the sampling time deviation based on the estimated time delay error between each sub-ADC channel. Frequency domain equalization filters are used to compensate for the frequency response differences between the sub-ADC channels, thereby correcting bandwidth mismatch.

3. The 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation according to claim 1, characterized in that, Step S2 specifically includes: Barker code with sharp autocorrelation characteristics is used as the frame header synchronization word. The correlation peak is detected by performing sliding correlation operation between the received baseband signal and the local synchronization word sequence. When the correlation peak exceeds the preset adaptive threshold, it is determined to be the frame header position, thereby completing the frame synchronization lock. Autocorrelation is performed on the preamble sequence based on the frame header position, and a coarse estimate of the symbol boundary is obtained by searching for the correlation peak position, thereby completing coarse symbol synchronization.

4. The 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation according to claim 1, characterized in that, Step S3 specifically includes: The Gardner clock synchronization algorithm is used to extract the clock error signal from the data symbol stream; The coarse estimate of the symbol boundary obtained in step S2 is used as the initial phase value of the numerically controlled oscillator (NCO) in the clock recovery loop to shorten the lock-in time of clock recovery. After clock recovery is complete and steady-state tracking is entered, stable symbol sampling time information is fed back to the frame synchronization step to help maintain the frame synchronization state.

5. The 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation according to claim 1, characterized in that, The workflow of the three-stage cascaded adaptive polarization demultiplexing in step S5 specifically includes: In the first stage, blind equalization is performed using the constant modulus algorithm (CMA). The equalizer coefficients are iteratively updated using the constant modulus cost function until a first preset condition is met, at which point the process switches to the second stage. The first preset condition is that the CMA convergence residual is lower than a first threshold and the error vector magnitude (EVM) of the equalized signal is lower than a second threshold, or the number of iterations reaches a preset upper limit. The second stage uses the Least Mean Square (LMS) algorithm for fine equalization, updating the equalizer coefficients with the goal of minimizing the equalization error, until the second preset condition is met, then switches to the third stage; the second preset condition is that the mean square value of the equalization error of LMS is lower than the third threshold, and the EVM of the equalized signal is lower than the fourth threshold. The third stage employs the Decision-Guided Least Mean Square (DDLMS) algorithm for high-precision equalization. The equalizer coefficients are updated using the decision error between the sign after the decision and the equalizer output signal to eliminate residual polarization crosstalk.

6. The 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation according to claim 5, characterized in that, Step S5 also includes a cross-module error feedback mechanism, specifically: The decision error calculated in the third-level DDLMS equalization step is fed back in real time to the first-level CMA equalization step and / or the second-level LMS equalization step to assist in updating the equalizer tap coefficients of the corresponding level, so as to achieve dynamic joint optimization of the end-link equalization performance.

7. The 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation according to claim 1, characterized in that, The joint carrier recovery in step S6 specifically includes: The coarse frequency offset estimation step involves performing a fourth power operation on the input signal to eliminate modulation phase information, then performing a Fast Fourier Transform (FFT) and searching for spectral peaks to calculate a coarse frequency offset estimate, and then performing initial frequency offset compensation based on the coarse frequency offset estimate. The carrier phase recovery step performs phase estimation based on the Viterbi-Viterbi algorithm on the signal after initial frequency offset compensation to compensate for phase noise, and outputs the phase-recovered signal and the corresponding phase residual value. The joint closed-loop iterative step calculates the average value of the phase residual value in units of a preset symbol period, and feeds it back to the frequency offset estimation and compensation step to adjust the frequency offset estimate value in order to correct the residual error of the frequency offset estimation.

8. The 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation according to claim 1, characterized in that, The full-scale performance monitoring indicators in step S7 include at least one of the following or any combination thereof: Error vector amplitude (EVM), modulation error ratio (MER), signal-to-noise ratio (SNR), bit error rate (BER), constellation diagram data, and eye diagram data.

9. The 100G coherent acquisition closed-loop demodulation method integrating TIADC and demodulation according to claim 1, characterized in that, All steps of the method are implemented using a parallel pipeline architecture of a field-programmable gate array (FPGA) to achieve a processing latency of less than 200 nanoseconds.

10. A 100G coherent acquisition closed-loop demodulation system integrating TIADC and demodulation, comprising a TIADC acquisition unit and a digital signal processing unit, characterized in that, The digital signal processing unit is configured to perform a 100G coherent acquisition closed-loop demodulation method that integrates TIADC and demodulation as described in any one of claims 1 to 9.

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