A 100g coherent acquisition closed-loop demodulation method and system integrating tiadc and demodulation

By employing a closed-loop demodulation method that integrates TIADC and demodulation, a full-link closed-loop architecture is constructed and cross-module error feedback is introduced. This solves the problems of rigid algorithm cascade structure and insufficient observability in 100G PM-QPSK signal demodulation, achieving high robustness and fast convergence, providing full performance monitoring, and is suitable for 100G coherent acquisition cards and optical communication testers.

CN122293206BActive Publication Date: 2026-08-04THE FIFTH RES INST OF TELECOMM SCI & TECH CO LTD +1
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Patent Information

Application Number
CN202610611845.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-05-07
Publication Date
2026-08-04
Estimated Expiration
2046-05-07

AI Technical Summary

Technical Problem

Existing digital coherent demodulation schemes for 100G PM-QPSK signals suffer from problems such as rigid algorithm cascade structure, disconnect between front-end acquisition and demodulation, slow polarization equalization convergence, poor carrier recovery robustness, and insufficient observability, making it difficult to meet the requirements of high observability testing.

Method used

A closed-loop demodulation method integrating TIADC and demodulation is adopted. By constructing an eight-level full-link closed-loop architecture and introducing a cross-module error feedback mechanism, the joint optimization of the entire process from acquisition to decision is realized. This includes steps such as TIADC mismatch correction, frame synchronization, clock recovery, frequency domain dispersion compensation, adaptive polarization demultiplexing, and joint carrier recovery. Low-latency processing is achieved using an FPGA parallel pipeline architecture.

Benefits of technology

It effectively suppresses error propagation, improves convergence speed and robustness, supports dispersion compensation range of up to 8000ps/nm and frequency offset correction range of ±200MHz, maintains stable demodulation under low signal-to-noise ratio conditions, provides full performance monitoring indicators, and meets the real-time analysis and fault diagnosis needs of 100G coherent acquisition platforms.

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Abstract

This invention provides a 100G coherent acquisition closed-loop demodulation method and system integrating TIADC and demodulation, belonging to the field of digital signal processing. The method includes: TIADC mismatch correction, frame synchronization and symbol synchronization, resampling clock recovery, frequency domain full dispersion compensation, three-level polarization demultiplexing (CMA+LMS+DDLMS), joint carrier frequency offset estimation and compensation, Viterbi-Viterbi carrier phase recovery, soft decision and full performance monitoring. This invention is the first to use TIADC front-end correction as the first stage of demodulation, achieving deep integration of acquisition and demodulation. The three-level cascaded equalization architecture balances convergence speed and compensation accuracy. A joint carrier recovery closed loop is established through phase residual feedback, significantly improving demodulation robustness and accuracy. This method can output full test indicators in real time, uses FPGA parallel pipelines to reduce processing latency, and is suitable for engineering applications such as 100G coherent acquisition cards and optical communication test instruments.
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