A method, system, and medium for crosstalk suppression and timing optimization of a high frequency circuit

Abstract

The application provides a crosstalk suppression and timing optimization method, system and medium for a high-frequency circuit, a sensor array is arranged on a key signal path, high-frequency crosstalk spectrum and timing eye diagram parameters are synchronously collected, a crosstalk intensity matrix (CIM) and a timing margin thermal map (TMM) are generated, and multi-dimensional quantitative characterization of signal integrity is realized; a main interference source is located according to the CIM, a disturbed line terminal impedance is dynamically adjusted, and a reverse compensation current is injected, so that high-frequency crosstalk is cancelled from the source; a pre-training model is used to predict a margin attenuation amount, a disturbed line clock phase is fine-tuned, and timing deviation is compensated; an optimized efficiency index of unit energy consumption after compensation is calculated, and a strategy library is triggered to dynamically update or recompensate a mechanism. The application realizes dynamic cooperation of crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, double-loop compensation, energy efficiency verification and strategy learning.

Description

Technical Field

[0001] This invention relates to the field of high-frequency circuits, and more specifically, to a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. Background Technology

[0002] With the development of technologies such as 5G communication and AI computing, the signal rate of high-speed digital circuits is gradually increasing. However, high-frequency crosstalk and timing jitter have become core bottlenecks restricting system performance. Traditional methods for crosstalk suppression and timing optimization employ a fragmented design approach. Crosstalk suppression relies on static design rules, increasing trace spacing or adding shielding layers, leading to a decrease in wiring density. Timing optimization addresses jitter by fixing clock margins, resulting in wasted bandwidth resources. This fragmented, independent operation creates a trade-off, failing to synergistically address coupling degradation effects in high-speed signal scenarios. Furthermore, excessive crosstalk suppression and timing margin reservations lead to increased power consumption, potentially causing thermal runaway risks in heat-constrained scenarios.

[0003] Therefore, there is an urgent need for adaptive crosstalk suppression and timing optimization techniques for high-frequency circuits based on dual-loop collaborative control and energy efficiency optimization mechanisms. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed in the critical signal path to synchronously collect high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM matrix, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted through a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The unit energy consumption optimization efficiency index after compensation is calculated, triggering a dynamic update of the strategy library or a re-compensation mechanism. This invention, based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning, achieves dynamic synergy between crosstalk suppression and timing optimization, resolving the performance-power consumption contradiction in high-speed circuit design.

[0005] The first aspect of this invention provides a method for crosstalk suppression and timing optimization in high-frequency circuits, the method comprising:

[0006] Based on the sensor array along the key signal path, high-frequency crosstalk information and timing margin information are collected;

[0007] In response to the preset frequency domain analysis and time-series eye diagram feature comparison, a crosstalk intensity matrix and a time-series margin heatmap are generated;

[0008] Based on the crosstalk intensity matrix, the main interference source information is located, and the impedance of the disturbed line and the reverse compensation current are obtained based on the preset dynamic adjustment algorithm.

[0009] Based on the crosstalk intensity matrix and the time margin heatmap, the data is input into the pre-trained margin prediction model to obtain the time margin decay amount.

[0010] The clock phase adjustment of the disturbed line is obtained based on the timing margin attenuation amount.

[0011] Measure the compensated high-frequency crosstalk information and timing margin information, and calculate the optimization index;

[0012] Determine whether the optimization index is higher than a preset index threshold;

[0013] If so, the measurement information and adjustment strategy will be stored in the parameter library of the margin prediction model;

[0014] If not, re-trigger timing compensation.

[0015] In this scheme, the generation of the crosstalk strength matrix specifically involves:

[0016] Based on the preset frequency domain analysis, the high-frequency crosstalk information is parsed, and the spectral amplitude of the preset frequency point is extracted;

[0017] Based on a preset wiring topology database, the trace parallelism, spacing, and dielectric layer parameters of the key signals are matched.

[0018] Based on the spectral amplitude and routing parameters, and using a preset coupling formula, the dynamic weights of the mutual capacitance coupling coefficient and the mutual inductance coupling coefficient are calculated.

[0019] A coupling coefficient matrix with the interference source and the disturbed line as row and column indices is established to obtain the crosstalk intensity matrix.

[0020] In this scheme, the disturbance line impedance and reverse compensation current are obtained based on a preset dynamic adjustment algorithm, specifically as follows:

[0021] The crosstalk strength matrix locates the terminal node of the disturbed line and activates the programmable resistor array of the terminal node.

[0022] If the crosstalk type is capacitive coupling, increase the impedance value of the terminated line of the affected line;

[0023] If the crosstalk type is inductive coupling, then reduce the impedance value of the terminated line of the affected line;

[0024] After adjusting the impedance of the disturbed line, the voltage change waveform of the main interference source is collected;

[0025] Based on the coupling coefficient matrix, determine the phase offset and gain ratio of the injected current;

[0026] Based on the phase offset and the gain ratio, a current mirror circuit is connected to the interference source driving end to generate a canceling current with the opposite polarity to the original crosstalk.

[0027] In this scheme, the step of inputting the crosstalk intensity matrix and the time margin heatmap into a pre-trained margin prediction model to obtain the time margin attenuation specifically includes:

[0028] Input the coupling coefficient of each element in the crosstalk intensity matrix and the margin baseline value of the time margin heatmap;

[0029] Based on the neural network weights of the pre-trained margin prediction model, formant features in the crosstalk spectrum are extracted.

[0030] Based on the characteristics of the resonance peaks, the resonance peak frequency is correlated with the signal edge rate to predict the degradation trend of setup time and hold time.

[0031] Based on the degradation trend, the margin decay amount of the worst path within the future preset clock window is obtained.

[0032] In this scheme, obtaining the clock phase adjustment degree of the disturbed line based on the timing margin attenuation specifically includes:

[0033] Based on the timing margin attenuation, the delay deviation of the critical signal path is analyzed;

[0034] Based on the critical signal path, locate the clock buffer node connected to the disturbed line and enable the digital phase interface of the clock buffer node.

[0035] The timing violation type is determined based on the timing margin decay amount;

[0036] If it is a timing violation, the clock edge arrival time is advanced;

[0037] To prevent timing violations, delay the arrival time of the clock edge;

[0038] The phase alignment signal is output to the digital phase interface based on the delay deviation.

[0039] In this scheme, the calculation of the optimization index based on the measured and compensated high-frequency crosstalk information and timing margin information specifically includes:

[0040] By comparing the eye diagram height and width of the timing margin information before and after measurement, the timing margin recovery ratio is calculated.

[0041] Measure the instantaneous power consumption increment of the impedance regulator and current injection module;

[0042] Based on the preset optimization index relationship, a unit energy consumption optimization efficiency index is generated according to the timing margin recovery ratio and the instantaneous power consumption increment.

[0043] If the unit energy consumption optimization efficiency index continues to be lower than the preset index threshold, a deep optimization instruction from the strategy library will be triggered.

[0044] A second aspect of the present invention provides a crosstalk suppression and timing optimization system for high-frequency circuits, including a crosstalk suppression and timing optimization method program for high-frequency circuits. When the crosstalk suppression and timing optimization method program for high-frequency circuits is executed by the processor, it performs the following steps:

[0045] Based on the sensor array along the key signal path, high-frequency crosstalk information and timing margin information are collected;

[0046] In response to the preset frequency domain analysis and time-series eye diagram feature comparison, a crosstalk intensity matrix and a time-series margin heatmap are generated;

[0047] Based on the crosstalk intensity matrix, the main interference source information is located, and the impedance of the disturbed line and the reverse compensation current are obtained based on the preset dynamic adjustment algorithm.

[0048] Based on the crosstalk intensity matrix and the time margin heatmap, the data is input into the pre-trained margin prediction model to obtain the time margin decay amount.

[0049] The clock phase adjustment of the disturbed line is obtained based on the timing margin attenuation amount.

[0050] Measure the compensated high-frequency crosstalk information and timing margin information, and calculate the optimization index;

[0051] Determine whether the optimization index is higher than a preset index threshold;

[0052] If so, the measurement information and adjustment strategy will be stored in the parameter library of the margin prediction model;

[0053] If not, re-trigger timing compensation.

[0054] In this scheme, the generation of the crosstalk strength matrix specifically involves:

[0055] Based on the preset frequency domain analysis, the high-frequency crosstalk information is parsed, and the spectral amplitude of the preset frequency point is extracted;

[0056] Based on a preset wiring topology database, the trace parallelism, spacing, and dielectric layer parameters of the key signals are matched.

[0057] Based on the spectral amplitude and routing parameters, and using a preset coupling formula, the dynamic weights of the mutual capacitance coupling coefficient and the mutual inductance coupling coefficient are calculated.

[0058] A coupling coefficient matrix with the interference source and the disturbed line as row and column indices is established to obtain the crosstalk intensity matrix.

[0059] In this scheme, the disturbance line impedance and reverse compensation current are obtained based on a preset dynamic adjustment algorithm, specifically as follows:

[0060] The crosstalk strength matrix locates the terminal node of the disturbed line and activates the programmable resistor array of the terminal node.

[0061] If the crosstalk type is capacitive coupling, increase the impedance value of the terminated line of the affected line;

[0062] If the crosstalk type is inductive coupling, then reduce the impedance value of the terminated line of the affected line;

[0063] After adjusting the impedance of the disturbed line, the voltage change waveform of the main interference source is collected;

[0064] Based on the coupling coefficient matrix, determine the phase offset and gain ratio of the injected current;

[0065] Based on the phase offset and the gain ratio, a current mirror circuit is connected to the interference source driving end to generate a canceling current with the opposite polarity to the original crosstalk.

[0066] A third aspect of the present invention provides a computer-readable storage medium comprising a crosstalk suppression and timing optimization method program for a high-frequency circuit, wherein when the crosstalk suppression and timing optimization method program for a high-frequency circuit is executed by a processor, it implements the steps of the crosstalk suppression and timing optimization method for a high-frequency circuit as described in any of the preceding claims.

[0067] This invention provides a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed along the critical signal path to simultaneously acquire high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted using a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The optimized efficiency index per unit energy consumption after compensation is calculated, triggering a dynamic update or re-compensation mechanism for the strategy library. This invention achieves dynamic synergy between crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning. Attached Figure Description

[0068] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope.

[0069] Figure 1 A flowchart of a crosstalk suppression and timing optimization method for a high-frequency circuit according to the present invention is shown;

[0070] Figure 2 A flowchart illustrating the establishment of a crosstalk strength matrix according to an embodiment of the present invention is shown;

[0071] Figure 3 A flowchart illustrating the operation of a crosstalk suppression loop provided in an embodiment of the present invention is shown.

[0072] Figure 4 A block diagram of a crosstalk suppression and timing optimization system for a high-frequency circuit according to the present invention is shown. Detailed Implementation

[0073] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0074] Unless otherwise defined, all terms (including technical and scientific terms) used in embodiments of this invention shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in a common dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as being interpreted in an idealized or highly formalized sense, unless expressly defined in this embodiment of the invention.

[0075] The terms "first," "second," and similar words used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "an," "a," or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Similarly, terms such as "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The steps preceding or following the steps in the method of the embodiments of this invention are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0076] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0077] Figure 1 A flowchart of a crosstalk suppression and timing optimization method for high-frequency circuits according to the present invention is shown.

[0078] like Figure 1 As shown, the first aspect of this invention discloses a method for crosstalk suppression and timing optimization in high-frequency circuits, the method comprising:

[0079] S102, based on the sensor array on the key signal path, collects high-frequency crosstalk information and timing margin information;

[0080] S104, in response to the preset frequency domain analysis and time-series eye diagram feature comparison, generates a crosstalk intensity matrix and a time-series margin heatmap;

[0081] S106. Based on the crosstalk intensity matrix, locate the main interference source information and obtain the interference line impedance and reverse compensation current based on the preset dynamic adjustment algorithm.

[0082] S108, Based on the crosstalk intensity matrix and the time margin heatmap, input them into the pre-trained margin prediction model to obtain the time margin decay amount;

[0083] S110, based on the timing margin attenuation amount, obtain the clock phase adjustment degree of the disturbed line;

[0084] S112, Measure the compensated high-frequency crosstalk information and timing margin information, and calculate the optimization index;

[0085] S114, determine whether the optimization index is higher than a preset index threshold;

[0086] S116, if so, store the measurement information and adjustment strategy in the parameter library of the margin prediction model;

[0087] S118, if not, re-trigger timing compensation.

[0088] It should be noted that in this embodiment, a miniature sensor array deployed on the critical signal path of the circuit board (PCB) continuously collects high-frequency radiated noise waveforms and signal timing jitter data, which are recorded as high-frequency crosstalk information and timing margin information. Commonly used critical signal paths include the end of the clock tree and high-speed data lines. A dedicated signal processing chip compares the noise spectrum with a pre-stored eye diagram template in the frequency domain to identify out-of-range frequencies and generate a matrix of crosstalk intensity to mark the coupling relationship between the interference source and the affected line. Simultaneously, a three-dimensional timing margin heatmap is constructed based on the measurements of timing establishment and timing maintenance. After locating the main interference source based on the high-frequency crosstalk matrix, the processor drives a programmable resistor network to dynamically adjust the impedance value of the affected line's termination, and simultaneously injects a phase-adjustable reverse compensation current at the output of the interference source driver. The crosstalk matrix and the margin heatmap are input into a pre-trained neural network model, which outputs the timing attenuation of the worst path in the future clock cycle. The timing compensation unit calculates the required clock phase offset based on the attenuation and fine-tunes the clock buffer of the affected line through a digital phase-locked loop. Subsequently, the changes in eye diagram height and width and the power consumption increment after compensation are measured, and the unit energy consumption optimization efficiency index is calculated. If the index meets the target, the current temperature and voltage parameters are bound to the compensation strategy and stored in the strategy library; otherwise, the coordinated compensation sequence of impedance, current, and phase is re-triggered until the system stabilizes. This embodiment achieves closed-loop linkage through crosstalk suppression loop and timing compensation loop, avoiding the performance loss caused by traditional step-by-step optimization; in addition, dynamic adjustment replaces fixed design margins, improving the accuracy of compensation.

[0089] In one implementation, if the sensor integrated in the circuit board is an analog sensor, that is, the sensor output signal is an analog signal, the analog signal output by the sensor is converted into a digital signal by an external or processor-integrated analog-to-digital converter (ADC) and then input to the processor for processing.

[0090] Figure 2 A flowchart illustrating the establishment of a crosstalk strength matrix provided by an embodiment of the present invention is shown.

[0091] According to embodiments of the present invention, such as Figure 2 As shown, the generation of the crosstalk strength matrix is ​​specifically as follows:

[0092] S202, Based on the preset frequency domain analysis, the high-frequency crosstalk information is analyzed, and the spectral amplitude of the preset frequency point is extracted;

[0093] S204, based on a preset wiring topology database, match the trace parallelism, spacing, and dielectric layer parameters of the key signals;

[0094] S206, Based on the spectral amplitude and routing parameters, and using a preset coupling formula, calculate the dynamic weights of the mutual capacitance coupling coefficient and the mutual inductance coupling coefficient.

[0095] S208. Establish a coupling coefficient matrix with the interference source and the disturbed line as row and column indices, which is used to obtain the crosstalk intensity matrix.

[0096] It should be noted that this embodiment provides a process for establishing a crosstalk strength matrix. A fast Fourier transform is performed on the raw noise data collected by the sensor using a signal processing unit to extract the amplitude attenuation characteristics of the fundamental and third harmonic frequencies. Then, the trace geometry parameters from the PCB design database are called, including but not limited to parallel length, interlayer spacing, and dielectric constant. Next, the dynamic weights of capacitive and inductive coupling coefficients are calculated using electromagnetic field simulation principles; in the coupling relationship, the capacitive coupling coefficient is inversely proportional to the spacing, and the inductive coupling coefficient is directly proportional to the parallel length. Then, a two-dimensional coupling coefficient matrix is ​​constructed based on the dynamic weight allocation structure; where the matrix row vectors are interference source identifiers, the column vectors are disturbed line identifiers, and the matrix cell values ​​are normalized coupling strength coefficients. When the coefficient of a specific cell exceeds a preset threshold, the interference source is automatically marked as a high-risk target, generating an alarm command containing location coordinates and coupling type. The coupling coefficient matrix serves as the decision basis for subsequent impedance adjustment and current injection, achieving a precise mapping from physical topology to quantized parameters and accurately locating hidden crosstalk sources.

[0097] Figure 3 The diagram shows the operation flowchart of a crosstalk suppression loop provided by an embodiment of the present invention.

[0098] According to embodiments of the present invention, such as Figure 3 As shown, the disturbance line impedance and reverse compensation current are obtained based on a preset dynamic adjustment algorithm, specifically as follows:

[0099] S302, the crosstalk strength matrix locates the terminal node of the disturbed line and activates the programmable resistor array of the terminal node;

[0100] S304. If the crosstalk type is capacitive coupling, increase the impedance value of the terminated line of the affected line.

[0101] S306. If the crosstalk type is inductive coupling, reduce the impedance value of the terminated line of the affected line.

[0102] S308, After adjusting the impedance of the disturbed line, acquire the voltage change waveform of the main interference source;

[0103] S310, Based on the coupling coefficient matrix, determine the phase offset and gain ratio of the injected current;

[0104] S312, based on the phase offset and the gain ratio, a current mirror circuit is connected to the interference source driving end to generate a canceling current with the opposite polarity to the original crosstalk.

[0105] It should be noted that this application provides a compensation parameter configuration strategy for a crosstalk suppression loop. First, high-risk cells in the crosstalk intensity matrix are analyzed to locate the terminal position of the affected line and activate the numerically controlled resistor array of that node. If the spectrum analysis shows that high-frequency attenuation dominates, it indicates that the crosstalk type is determined to be capacitive coupling, and the terminal impedance value is increased to reduce voltage noise sensitivity; if low-frequency diffusion is significant, it indicates that the crosstalk type is determined to be inductive coupling, and the terminal impedance is decreased to suppress current loop interference. Then, after adjusting the impedance of the affected line, a high-speed ADC is used to simultaneously acquire the real-time voltage change rate waveform of the main interference source, based on the phase offset angle determined by the coupling matrix and the gain ratio parameter of the reverse current. A current mirror circuit is connected to the interference source driving end. This circuit generates a canceling current with opposite polarity and matching amplitude to the original crosstalk waveform, and the injection timing is dynamically calibrated through closed-loop negative feedback. Finally, after the reverse current injection is completed, it is verified whether the noise energy of the affected line has attenuated below the background noise level to ensure the effectiveness of the compensation action. This embodiment reduces noise sensitivity through classified dynamic impedance matching and achieves crosstalk cancellation by injecting reverse current from the source, avoiding secondary signal distortion of the affected line.

[0106] According to an embodiment of the present invention, the step of inputting the crosstalk intensity matrix and the time margin heatmap into a pre-trained margin prediction model to obtain the time margin attenuation specifically includes:

[0107] Input the coupling coefficient of each element in the crosstalk intensity matrix and the margin baseline value of the time margin heatmap;

[0108] Based on the neural network weights of the pre-trained margin prediction model, formant features in the crosstalk spectrum are extracted.

[0109] Based on the characteristics of the resonance peaks, the resonance peak frequency is correlated with the signal edge rate to predict the degradation trend of setup time and hold time.

[0110] Based on the degradation trend, the margin decay amount of the worst path within the future preset clock window is obtained.

[0111] It should be noted that this embodiment provides the operational logic of a margin prediction model. The prediction module extracts the coupling coefficients of each unit from the crosstalk intensity matrix and reads the baseline values ​​of the current setup and hold times from the timing margin heatmap. A neural network model trained on a large amount of simulation data is loaded, wherein the input layer of the neural network contains the coupling coefficients and the timing baseline, and the hidden layer contains convolutional modules to extract the formant features in the crosstalk spectrum. Then, the formant frequency is correlated with the actual rise or fall rate of the signal in the time domain to establish a formant-edge degradation mapping relationship, denoted as the formant feature. Based on the formant feature, the possible increase in setup time or the possible decrease in hold time within the next N clock cycles is predicted; wherein, the increase in setup time is used to represent the signal delay risk, and the possible decrease in hold time is used to represent the signal advance risk. Finally, the margin attenuation amount and time window position coordinates of the worst path are output, providing predictive input for timing compensation, improving response speed, and avoiding compensation lag problems caused by passive response. This embodiment uses a resonance peak-edge rate correlation model to predict timing degradation in advance and prevent sudden timing violations.

[0112] According to an embodiment of the present invention, obtaining the clock phase adjustment degree of the disturbed line based on the timing margin attenuation specifically includes:

[0113] Based on the timing margin attenuation, the delay deviation of the critical signal path is analyzed;

[0114] Based on the critical signal path, locate the clock buffer node connected to the disturbed line and enable the digital phase interface of the clock buffer node.

[0115] The timing violation type is determined based on the timing margin decay amount;

[0116] If it is a timing violation, the clock edge arrival time is advanced;

[0117] To prevent timing violations, delay the arrival time of the clock edge;

[0118] The phase alignment signal is output to the digital phase interface based on the delay deviation.

[0119] It should be noted that this embodiment provides a compensation parameter configuration strategy for the timing optimization loop. First, the timing compensation engine receives the margin attenuation output from the prediction module and converts it into a signal path delay deviation value. Then, it locates the clock buffer node connected to the disturbed line and enables the digital phase interpolator control interface integrated into the clock buffer node. Second, it determines the violation type based on the nature of the attenuation. If the data arrives later than the clock, it is determined to be a setup timing violation, and the clock edge position is shifted forward; if the data change is earlier than the clock, it is determined to be a hold timing violation, and the clock edge is delayed backward. Then, the phase offset is calibrated in real time through an on-chip delay-locked loop, dynamically adjusting the interpolator code value until the eye diagram center is re-aligned. Finally, a phase-locked completion signal is output to the global status register to ensure strict synchronization between the clock domain and the data domain. This embodiment, based on a differentiated compensation strategy for setup timing violations and hold timing violations, avoids secondary violations caused by a single phase adjustment.

[0120] According to an embodiment of the present invention, the calculation of the optimization index based on the measured compensated high-frequency crosstalk information and timing margin information specifically includes:

[0121] By comparing the eye diagram height and width of the timing margin information before and after measurement, the timing margin recovery ratio is calculated.

[0122] Measure the instantaneous power consumption increment of the impedance regulator and current injection module;

[0123] Based on the preset optimization index relationship, a unit energy consumption optimization efficiency index is generated according to the timing margin recovery ratio and the instantaneous power consumption increment.

[0124] If the unit energy consumption optimization efficiency index continues to be lower than the preset index threshold, a deep optimization instruction from the strategy library will be triggered.

[0125] It should be noted that this embodiment provides a mechanism for determining the compensation result. High-frequency crosstalk information and timing margin information after compensation are collected, and parameters such as the eye diagram height and width after compensation are analyzed. The timing margin recovery ratio is calculated by comparing it with the original loss value. The instantaneous power consumption increment of the impedance regulator and current injection module is monitored synchronously, and the margin recovery ratio is divided by the power consumption increment to generate a unit energy consumption optimization efficiency index. Then, the efficiency baseline determined to be successfully compensated in the historical operating database is retrieved and recorded as the index threshold. If the current index is continuously lower than this threshold, it is determined to be an inefficient compensation strategy. A deep optimization instruction is triggered in the strategy library, and the reinforcement learning engine is started to regenerate the combination of impedance, current, and phase parameters. This embodiment prevents over-compensation or under-compensation by introducing an energy efficiency ratio evaluation mechanism, and achieves adaptive threshold calibration through historical data comparison to adapt to different operating conditions.

[0126] It is worth mentioning that it also includes:

[0127] Record the current ambient temperature, power supply voltage fluctuations, measurement information, and adjustment strategies to obtain the strategy group data structure;

[0128] The strategy group weights are determined based on the optimization index.

[0129] Based on a preset training period, the margin prediction model is trained according to the policy group data structure and the policy group weights.

[0130] It should be noted that this embodiment provides a self-learning mechanism for the prediction model. First, the current ambient temperature, power supply voltage fluctuation range, sensor dataset, and effective compensation parameters are recorded and encapsulated into a strategy group data structure. Then, dynamic weight values ​​are assigned to the strategy groups based on an optimization index, where a higher index results in a greater weight. Next, at the end of a preset training period, high-weight strategy groups are selected and input into the prediction model for incremental training. Simultaneously, adversarial example augmentation techniques are used to expand the dataset, and an overfitting prevention mechanism is introduced to obtain an updated model. Finally, the updated model prioritizes high-weight strategy parameters under similar environmental conditions and automatically eliminates continuously failing low-weight strategies, achieving continuous adaptation of model parameters to changes in the physical environment. This embodiment improves the system's adaptability by binding environmental parameters to compensation strategies for learning, and automatically filters out failed schemes through a weight elimination mechanism, ensuring the model continuously closely reflects actual physical characteristics.

[0131] It is worth mentioning that the re-triggering timing compensation specifically includes:

[0132] When the impedance adjustment or phase adjustment exceeds the preset safety threshold, all compensation loop outputs are frozen.

[0133] Revert to the previous output configuration file and update the impedance adjustment and phase adjustment.

[0134] It should be noted that this embodiment provides an overload protection mechanism. When the impedance adjustment or phase offset reaches a safety threshold, the protection module immediately freezes all compensation loop output signals and rolls back to the most recently verified configuration file; the configuration file includes snapshot parameters such as impedance settings, current gain coefficient, and phase offset. The same type of compensation operation is prohibited within a preset time window to prevent oscillating overcompensation. A protection mode activation status code and fault location information are sent to the system monitoring terminal to accelerate root cause analysis by engineers. This embodiment achieves second-level fault recovery through an overload protection mechanism using configuration file snapshots, improving reliability.

[0135] Figure 4 A block diagram of a crosstalk suppression and timing optimization system for a high-frequency circuit according to the present invention is shown.

[0136] like Figure 4As shown, the second aspect of the present invention discloses a crosstalk suppression and timing optimization system 4 for high-frequency circuits, including a memory 41 and a processor 42. The memory includes a crosstalk suppression and timing optimization method program for high-frequency circuits. When the crosstalk suppression and timing optimization method program for high-frequency circuits is executed by the processor, it performs the following steps:

[0137] Based on the sensor array along the key signal path, high-frequency crosstalk information and timing margin information are collected;

[0138] In response to the preset frequency domain analysis and time-series eye diagram feature comparison, a crosstalk intensity matrix and a time-series margin heatmap are generated;

[0139] Based on the crosstalk intensity matrix, the main interference source information is located, and the impedance of the disturbed line and the reverse compensation current are obtained based on the preset dynamic adjustment algorithm.

[0140] Based on the crosstalk intensity matrix and the time margin heatmap, the data is input into the pre-trained margin prediction model to obtain the time margin decay amount.

[0141] The clock phase adjustment of the disturbed line is obtained based on the timing margin attenuation amount.

[0142] Measure the compensated high-frequency crosstalk information and timing margin information, and calculate the optimization index;

[0143] Determine whether the optimization index is higher than a preset index threshold;

[0144] If so, the measurement information and adjustment strategy will be stored in the parameter library of the margin prediction model;

[0145] If not, re-trigger timing compensation.

[0146] It should be noted that in this embodiment, a miniature sensor array deployed on the critical signal path of the circuit board (PCB) continuously collects high-frequency radiated noise waveforms and signal timing jitter data, which are recorded as high-frequency crosstalk information and timing margin information. Commonly used critical signal paths include the end of the clock tree and high-speed data lines. A dedicated signal processing chip compares the noise spectrum with a pre-stored eye diagram template in the frequency domain to identify out-of-range frequencies and generate a matrix of crosstalk intensity to mark the coupling relationship between the interference source and the affected line. Simultaneously, a three-dimensional timing margin heatmap is constructed based on the measurements of timing establishment and timing maintenance. After locating the main interference source based on the high-frequency crosstalk matrix, the processor drives a programmable resistor network to dynamically adjust the impedance value of the affected line's termination, and simultaneously injects a phase-adjustable reverse compensation current at the output of the interference source driver. The crosstalk matrix and the margin heatmap are input into a pre-trained neural network model, which outputs the timing attenuation of the worst path in the future clock cycle. The timing compensation unit calculates the required clock phase offset based on the attenuation and fine-tunes the clock buffer of the affected line through a digital phase-locked loop. Subsequently, the changes in eye diagram height and width and the power consumption increment after compensation are measured, and the unit energy consumption optimization efficiency index is calculated. If the index meets the target, the current temperature and voltage parameters are bound to the compensation strategy and stored in the strategy library; otherwise, the coordinated compensation sequence of impedance, current, and phase is re-triggered until the system stabilizes. This embodiment achieves closed-loop linkage through crosstalk suppression loop and timing compensation loop, avoiding the performance loss caused by traditional step-by-step optimization; in addition, dynamic adjustment replaces fixed design margins, improving the accuracy of compensation.

[0147] In one implementation, if the sensor integrated in the circuit board is an analog sensor, that is, the sensor output signal is an analog signal, the analog signal output by the sensor is converted into a digital signal by an external or processor-integrated analog-to-digital converter (ADC) and then input to the processor for processing.

[0148] According to an embodiment of the present invention, the generation of the crosstalk strength matrix specifically involves:

[0149] Based on the preset frequency domain analysis, the high-frequency crosstalk information is parsed, and the spectral amplitude of the preset frequency point is extracted;

[0150] Based on a preset wiring topology database, the trace parallelism, spacing, and dielectric layer parameters of the key signals are matched.

[0151] Based on the spectral amplitude and routing parameters, and using a preset coupling formula, the dynamic weights of the mutual capacitance coupling coefficient and the mutual inductance coupling coefficient are calculated.

[0152] A coupling coefficient matrix with the interference source and the disturbed line as row and column indices is established to obtain the crosstalk intensity matrix.

[0153] It should be noted that this embodiment provides a process for establishing a crosstalk strength matrix. A fast Fourier transform is performed on the raw noise data collected by the sensor using a signal processing unit to extract the amplitude attenuation characteristics of the fundamental and third harmonic frequencies. Then, the trace geometry parameters from the PCB design database are called, including but not limited to parallel length, interlayer spacing, and dielectric constant. Next, the dynamic weights of capacitive and inductive coupling coefficients are calculated using electromagnetic field simulation principles; in the coupling relationship, the capacitive coupling coefficient is inversely proportional to the spacing, and the inductive coupling coefficient is directly proportional to the parallel length. Then, a two-dimensional coupling coefficient matrix is ​​constructed based on the dynamic weight allocation structure; where the matrix row vectors are interference source identifiers, the column vectors are disturbed line identifiers, and the matrix cell values ​​are normalized coupling strength coefficients. When the coefficient of a specific cell exceeds a preset threshold, the interference source is automatically marked as a high-risk target, generating an alarm command containing location coordinates and coupling type. The coupling coefficient matrix serves as the decision basis for subsequent impedance adjustment and current injection, achieving a precise mapping from physical topology to quantized parameters and accurately locating hidden crosstalk sources.

[0154] According to an embodiment of the present invention, the method for obtaining the disturbed line impedance and reverse compensation current based on a preset dynamic adjustment algorithm specifically includes:

[0155] The crosstalk strength matrix locates the terminal node of the disturbed line and activates the programmable resistor array of the terminal node.

[0156] If the crosstalk type is capacitive coupling, increase the impedance value of the terminated line of the affected line;

[0157] If the crosstalk type is inductive coupling, then reduce the impedance value of the terminated line of the affected line;

[0158] After adjusting the impedance of the disturbed line, the voltage change waveform of the main interference source is collected;

[0159] Based on the coupling coefficient matrix, determine the phase offset and gain ratio of the injected current;

[0160] Based on the phase offset and the gain ratio, a current mirror circuit is connected to the interference source driving end to generate a canceling current with the opposite polarity to the original crosstalk.

[0161] It should be noted that this application provides a compensation parameter configuration strategy for a crosstalk suppression loop. First, high-risk cells in the crosstalk intensity matrix are analyzed to locate the terminal position of the affected line and activate the numerically controlled resistor array of that node. If the spectrum analysis shows that high-frequency attenuation dominates, it indicates that the crosstalk type is determined to be capacitive coupling, and the terminal impedance value is increased to reduce voltage noise sensitivity; if low-frequency diffusion is significant, it indicates that the crosstalk type is determined to be inductive coupling, and the terminal impedance is decreased to suppress current loop interference. Then, after adjusting the impedance of the affected line, a high-speed ADC is used to simultaneously acquire the real-time voltage change rate waveform of the main interference source, based on the phase offset angle determined by the coupling matrix and the gain ratio parameter of the reverse current. A current mirror circuit is connected to the interference source driving end. This circuit generates a canceling current with opposite polarity and matching amplitude to the original crosstalk waveform, and the injection timing is dynamically calibrated through closed-loop negative feedback. Finally, after the reverse current injection is completed, it is verified whether the noise energy of the affected line has attenuated below the background noise level to ensure the effectiveness of the compensation action. This embodiment reduces noise sensitivity through classified dynamic impedance matching and achieves crosstalk cancellation by injecting reverse current from the source, avoiding secondary signal distortion of the affected line.

[0162] According to an embodiment of the present invention, the step of inputting the crosstalk intensity matrix and the time margin heatmap into a pre-trained margin prediction model to obtain the time margin attenuation specifically includes:

[0163] Input the coupling coefficient of each element in the crosstalk intensity matrix and the margin baseline value of the time margin heatmap;

[0164] Based on the neural network weights of the pre-trained margin prediction model, formant features in the crosstalk spectrum are extracted.

[0165] Based on the characteristics of the resonance peaks, the resonance peak frequency is correlated with the signal edge rate to predict the degradation trend of setup time and hold time.

[0166] Based on the degradation trend, the margin decay amount of the worst path within the future preset clock window is obtained.

[0167] It should be noted that this embodiment provides the operational logic of a margin prediction model. The prediction module extracts the coupling coefficients of each unit from the crosstalk intensity matrix and reads the baseline values ​​of the current setup and hold times from the timing margin heatmap. A neural network model trained on a large amount of simulation data is loaded, wherein the input layer of the neural network contains the coupling coefficients and the timing baseline, and the hidden layer contains convolutional modules to extract the formant features in the crosstalk spectrum. Then, the formant frequency is correlated with the actual rise or fall rate of the signal in the time domain to establish a formant-edge degradation mapping relationship, denoted as the formant feature. Based on the formant feature, the possible increase in setup time or the possible decrease in hold time within the next N clock cycles is predicted; wherein, the increase in setup time is used to represent the signal delay risk, and the possible decrease in hold time is used to represent the signal advance risk. Finally, the margin attenuation amount and time window position coordinates of the worst path are output, providing predictive input for timing compensation, improving response speed, and avoiding compensation lag problems caused by passive response. This embodiment uses a resonance peak-edge rate correlation model to predict timing degradation in advance and prevent sudden timing violations.

[0168] According to an embodiment of the present invention, obtaining the clock phase adjustment degree of the disturbed line based on the timing margin attenuation specifically includes:

[0169] Based on the timing margin attenuation, the delay deviation of the critical signal path is analyzed;

[0170] Based on the critical signal path, locate the clock buffer node connected to the disturbed line and enable the digital phase interface of the clock buffer node.

[0171] The timing violation type is determined based on the timing margin decay amount;

[0172] If it is a timing violation, the clock edge arrival time is advanced;

[0173] To prevent timing violations, delay the arrival time of the clock edge;

[0174] The phase alignment signal is output to the digital phase interface based on the delay deviation.

[0175] It should be noted that this embodiment provides a compensation parameter configuration strategy for the timing optimization loop. First, the timing compensation engine receives the margin attenuation output from the prediction module and converts it into a signal path delay deviation value. Then, it locates the clock buffer node connected to the disturbed line and enables the digital phase interpolator control interface integrated into the clock buffer node. Second, it determines the violation type based on the nature of the attenuation. If the data arrives later than the clock, it is determined to be a setup timing violation, and the clock edge position is shifted forward; if the data change is earlier than the clock, it is determined to be a hold timing violation, and the clock edge is delayed backward. Then, the phase offset is calibrated in real time through an on-chip delay-locked loop, dynamically adjusting the interpolator code value until the eye diagram center is re-aligned. Finally, a phase-locked completion signal is output to the global status register to ensure strict synchronization between the clock domain and the data domain. This embodiment, based on a differentiated compensation strategy for setup timing violations and hold timing violations, avoids secondary violations caused by a single phase adjustment.

[0176] According to an embodiment of the present invention, the calculation of the optimization index based on the measured compensated high-frequency crosstalk information and timing margin information specifically includes:

[0177] By comparing the eye diagram height and width of the timing margin information before and after measurement, the timing margin recovery ratio is calculated.

[0178] Measure the instantaneous power consumption increment of the impedance regulator and current injection module;

[0179] Based on the preset optimization index relationship, a unit energy consumption optimization efficiency index is generated according to the timing margin recovery ratio and the instantaneous power consumption increment.

[0180] If the unit energy consumption optimization efficiency index continues to be lower than the preset index threshold, a deep optimization instruction from the strategy library will be triggered.

[0181] It should be noted that this embodiment provides a mechanism for determining the compensation result. High-frequency crosstalk information and timing margin information after compensation are collected, and parameters such as the eye diagram height and width after compensation are analyzed. The timing margin recovery ratio is calculated by comparing it with the original loss value. The instantaneous power consumption increment of the impedance regulator and current injection module is monitored synchronously, and the margin recovery ratio is divided by the power consumption increment to generate a unit energy consumption optimization efficiency index. Then, the efficiency baseline determined to be successfully compensated in the historical operating database is retrieved and recorded as the index threshold. If the current index is continuously lower than this threshold, it is determined to be an inefficient compensation strategy. A deep optimization instruction is triggered in the strategy library, and the reinforcement learning engine is started to regenerate the combination of impedance, current, and phase parameters. This embodiment prevents over-compensation or under-compensation by introducing an energy efficiency ratio evaluation mechanism, and achieves adaptive threshold calibration through historical data comparison to adapt to different operating conditions.

[0182] It is worth mentioning that it also includes:

[0183] Record the current ambient temperature, power supply voltage fluctuations, measurement information, and adjustment strategies to obtain the strategy group data structure;

[0184] The strategy group weights are determined based on the optimization index.

[0185] Based on a preset training period, the margin prediction model is trained according to the policy group data structure and the policy group weights.

[0186] It should be noted that this embodiment provides a self-learning mechanism for the prediction model. First, the current ambient temperature, power supply voltage fluctuation range, sensor dataset, and effective compensation parameters are recorded and encapsulated into a strategy group data structure. Then, dynamic weight values ​​are assigned to the strategy groups based on an optimization index, where a higher index results in a greater weight. Next, at the end of a preset training period, high-weight strategy groups are selected and input into the prediction model for incremental training. Simultaneously, adversarial example augmentation techniques are used to expand the dataset, and an overfitting prevention mechanism is introduced to obtain an updated model. Finally, the updated model prioritizes high-weight strategy parameters under similar environmental conditions and automatically eliminates continuously failing low-weight strategies, achieving continuous adaptation of model parameters to changes in the physical environment. This embodiment improves the system's adaptability by binding environmental parameters to compensation strategies for learning, and automatically filters out failed schemes through a weight elimination mechanism, ensuring the model continuously closely reflects actual physical characteristics.

[0187] It is worth mentioning that the re-triggering timing compensation specifically includes:

[0188] When the impedance adjustment or phase adjustment exceeds the preset safety threshold, all compensation loop outputs are frozen.

[0189] Revert to the previous output configuration file and update the impedance adjustment and phase adjustment.

[0190] It should be noted that this embodiment provides an overload protection mechanism. When the impedance adjustment or phase offset reaches a safety threshold, the protection module immediately freezes all compensation loop output signals and rolls back to the most recently verified configuration file; the configuration file includes snapshot parameters such as impedance settings, current gain coefficient, and phase offset. The same type of compensation operation is prohibited within a preset time window to prevent oscillating overcompensation. A protection mode activation status code and fault location information are sent to the system monitoring terminal to accelerate root cause analysis by engineers. This embodiment achieves second-level fault recovery through an overload protection mechanism using configuration file snapshots, improving reliability.

[0191] A third aspect of the present invention provides a computer-readable storage medium comprising a crosstalk suppression and timing optimization method program for a high-frequency circuit, wherein when the crosstalk suppression and timing optimization method program for a high-frequency circuit is executed by a processor, it implements the steps of the crosstalk suppression and timing optimization method for a high-frequency circuit as described in any of the preceding claims.

[0192] In summary, this invention provides a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed along the critical signal path to simultaneously acquire high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted using a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The optimized efficiency index per unit energy consumption after compensation is calculated, triggering a dynamic update or re-compensation mechanism for the strategy library. This invention achieves dynamic synergy between crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning.

[0193] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0194] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for crosstalk suppression and timing optimization in high-frequency circuits, characterized in that, The method includes: Based on the sensor array along the key signal path, high-frequency crosstalk information and timing margin information are collected; In response to the preset frequency domain analysis and time-series eye diagram feature comparison, a crosstalk intensity matrix and a time-series margin heatmap are generated; Based on the crosstalk intensity matrix, the main interference source information is located, and the impedance of the disturbed line and the reverse compensation current are obtained based on the preset dynamic adjustment algorithm. Based on the crosstalk intensity matrix and the time margin heatmap, the data is input into the pre-trained margin prediction model to obtain the time margin decay amount. The clock phase adjustment of the disturbed line is obtained based on the timing margin attenuation amount. Measure the compensated high-frequency crosstalk information and timing margin information, and calculate the optimization index; Determine whether the optimization index is higher than a preset index threshold; If so, the high-frequency crosstalk information and timing margin information measured after compensation, as well as the impedance of the disturbed line, the reverse compensation current and the clock phase adjustment degree of the disturbed line, are stored in the parameter library of the margin prediction model. If not, re-trigger timing compensation; The generation of the crosstalk strength matrix is ​​specifically as follows: Based on the preset frequency domain analysis, the high-frequency crosstalk information is parsed, and the spectral amplitude of the preset frequency point is extracted; Based on a preset wiring topology database, the routing parallelism, spacing, and dielectric layer parameters of the key signal paths are matched. Based on the spectral amplitude, the trace parallelism, spacing, and dielectric layer parameters, and based on a preset coupling formula, the dynamic weights of the mutual capacitance coupling coefficient and the mutual inductance coupling coefficient are calculated. A coupling coefficient matrix with the interference source and the disturbed line as row and column indices is established to obtain the crosstalk strength matrix; The step of inputting the crosstalk intensity matrix and the time margin heatmap into a pre-trained margin prediction model to obtain the time margin attenuation specifically includes: Input the coupling coefficient of each element in the crosstalk intensity matrix and the margin baseline value of the time-series margin heatmap; Based on the neural network weights of the pre-trained margin prediction model, formant features in the crosstalk spectrum are extracted. Based on the characteristics of the resonance peaks, the resonance peak frequency is correlated with the signal edge rate to predict the degradation trend of setup time and hold time. Based on the aforementioned degradation trend, the margin decay amount of the worst path within the future preset clock window is obtained. The re-triggering timing compensation specifically includes: freezing all compensation loop outputs when the impedance adjustment or phase adjustment exceeds a preset safety threshold; reverting to the previous output configuration file and updating the impedance adjustment and phase adjustment.

2. The method for crosstalk suppression and timing optimization of high-frequency circuits according to claim 1, characterized in that, The disturbance line impedance and reverse compensation current are obtained based on a preset dynamic adjustment algorithm, specifically as follows: The crosstalk strength matrix locates the terminal node of the disturbed line and activates the programmable resistor array of the terminal node. If the crosstalk type is capacitive coupling, increase the impedance value of the terminated line of the affected line; If the crosstalk type is inductive coupling, then reduce the impedance value of the terminated line of the affected line; After adjusting the impedance of the disturbed line, the voltage change waveform of the main interference source is collected; Based on the coupling coefficient matrix, determine the phase offset and gain ratio of the injected current; Based on the phase offset and the gain ratio, a current mirror circuit is connected to the interference source driving end to generate a canceling current with the opposite polarity to the original crosstalk.

3. The method for crosstalk suppression and timing optimization of a high-frequency circuit according to claim 2, characterized in that, The step of obtaining the clock phase adjustment degree of the disturbed line based on the timing margin attenuation amount specifically includes: Based on the timing margin attenuation, the delay deviation of the critical signal path is analyzed; Based on the critical signal path, locate the clock buffer node connected to the disturbed line and enable the digital phase interface of the clock buffer node. The timing violation type is determined based on the timing margin decay amount; If it is a timing violation, the clock edge arrival time is advanced; To prevent timing violations, delay the arrival time of the clock edge; The phase alignment signal is output to the digital phase interface based on the delay deviation.

4. The method for crosstalk suppression and timing optimization of a high-frequency circuit according to claim 1, characterized in that, The calculation of the optimization index based on the measured and compensated high-frequency crosstalk information and timing margin information specifically includes: By comparing the eye diagram height and width of the timing margin information before and after measurement, the timing margin recovery ratio is calculated. Measure the instantaneous power consumption increment of the impedance regulator and current injection module; Based on the preset optimization index relationship, a unit energy consumption optimization efficiency index is generated according to the timing margin recovery ratio and the instantaneous power consumption increment. If the unit energy consumption optimization efficiency index continues to be lower than the preset index threshold, a deep optimization instruction from the strategy library will be triggered.

5. A crosstalk suppression and timing optimization system for high-frequency circuits, characterized in that, The system includes a memory and a processor. The memory includes a program for a crosstalk suppression and timing optimization method for high-frequency circuits. When the processor executes the program for the crosstalk suppression and timing optimization method for high-frequency circuits, it performs the following steps: Based on the sensor array along the key signal path, high-frequency crosstalk information and timing margin information are collected; In response to the preset frequency domain analysis and time-series eye diagram feature comparison, a crosstalk intensity matrix and a time-series margin heatmap are generated; Based on the crosstalk intensity matrix, the main interference source information is located, and the impedance of the disturbed line and the reverse compensation current are obtained based on the preset dynamic adjustment algorithm. Based on the crosstalk intensity matrix and the time margin heatmap, the data is input into the pre-trained margin prediction model to obtain the time margin decay amount. The clock phase adjustment of the disturbed line is obtained based on the timing margin attenuation amount. Measure the compensated high-frequency crosstalk information and timing margin information, and calculate the optimization index; Determine whether the optimization index is higher than a preset index threshold; If so, the high-frequency crosstalk information and timing margin information measured after compensation, as well as the impedance of the disturbed line, the reverse compensation current and the clock phase adjustment degree of the disturbed line, are stored in the parameter library of the margin prediction model. If not, re-trigger timing compensation; The generation of the crosstalk strength matrix is ​​specifically as follows: Based on the preset frequency domain analysis, the high-frequency crosstalk information is parsed, and the spectral amplitude of the preset frequency point is extracted; Based on a preset wiring topology database, the routing parallelism, spacing, and dielectric layer parameters of the key signal paths are matched. Based on the spectral amplitude, the trace parallelism, spacing, and dielectric layer parameters, and based on a preset coupling formula, the dynamic weights of the mutual capacitance coupling coefficient and the mutual inductance coupling coefficient are calculated. A coupling coefficient matrix with the interference source and the disturbed line as row and column indices is established to obtain the crosstalk strength matrix; The step of inputting the crosstalk intensity matrix and the time margin heatmap into a pre-trained margin prediction model to obtain the time margin attenuation specifically includes: Input the coupling coefficient of each element in the crosstalk intensity matrix and the margin baseline value of the time-series margin heatmap; Based on the neural network weights of the pre-trained margin prediction model, formant features in the crosstalk spectrum are extracted. Based on the characteristics of the resonance peaks, the resonance peak frequency is correlated with the signal edge rate to predict the degradation trend of setup time and hold time. Based on the aforementioned degradation trend, the margin decay amount of the worst path within the future preset clock window is obtained. The re-triggering timing compensation specifically includes: freezing all compensation loop outputs when the impedance adjustment or phase adjustment exceeds a preset safety threshold; reverting to the previous output configuration file and updating the impedance adjustment and phase adjustment.

6. The crosstalk suppression and timing optimization system for high-frequency circuits according to claim 5, characterized in that, The disturbance line impedance and reverse compensation current are obtained based on a preset dynamic adjustment algorithm, specifically as follows: The crosstalk strength matrix locates the terminal node of the disturbed line and activates the programmable resistor array of the terminal node. If the crosstalk type is capacitive coupling, increase the impedance value of the terminated line of the affected line; If the crosstalk type is inductive coupling, then reduce the impedance value of the terminated line of the affected line; After adjusting the impedance of the disturbed line, the voltage change waveform of the main interference source is collected; Based on the coupling coefficient matrix, determine the phase offset and gain ratio of the injected current; Based on the phase offset and the gain ratio, a current mirror circuit is connected to the interference source driving end to generate a canceling current with the opposite polarity to the original crosstalk.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer-readable storage medium includes a crosstalk suppression and timing optimization method program for a high-frequency circuit. When the crosstalk suppression and timing optimization method program for a high-frequency circuit is executed by a processor, it implements the steps of the crosstalk suppression and timing optimization method for a high-frequency circuit as described in any one of claims 1 to 4.

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