Semiconductor structure and method of manufacturing the same, storage system

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a memory system, relating to the field of semiconductor chip technology, and aims to improve the problem of semiconductor layers being easily damaged during fabrication. The semiconductor structure includes a semiconductor layer, a stacked structure, and a gate isolation structure. The stacked structure is disposed on the semiconductor layer and includes multiple dielectric layers and multiple gate layers alternately stacked along a first direction. The gate isolation structure penetrates the stacked structure and the semiconductor layer along the first direction and extends along a second direction. In a third direction, the semiconductor layer near the gate isolation structure does not exceed the gate layer. In this semiconductor structure, on one side of the semiconductor layer along the third direction, below the stacked structure, there is sufficient space for forming a partial gate isolation structure before the step of removing the semiconductor material using a wet etching process, to protect the morphology of the semiconductor layer and prevent the semiconductor layer from being damaged by subsequent wet etching steps.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0005] The embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, some embodiments of this disclosure provide a semiconductor structure, including: a semiconductor layer, a stacked structure, and a gate isolation structure. The stacked structure is disposed on the semiconductor layer, and the stacked structure includes a plurality of dielectric layers and a plurality of gate layers alternately stacked along a first direction; the gate isolation structure extends through the stacked structure and the semiconductor layer along the first direction, and extends along a second direction; in a third direction, the semiconductor layer adjacent to the gate isolation structure does not exceed the gate layer; the second direction intersects the first direction, and the third direction intersects the plane containing the first direction and the second direction.

[0007] In some embodiments, the distance between the semiconductor layer and the gate isolation structure is greater than or equal to the distance between the gate layer and the gate isolation structure.

[0008] In some embodiments, the gate isolation structure includes a body and an insulating layer, the insulating layer being disposed around the body and located between the body and the stacked structure;

[0009] The distance between the semiconductor layer and the body is greater than the distance between the gate layer and the body.

[0010] In some embodiments, in the third-party direction, the semiconductor layer has a first surface adjacent to the gate isolation structure, and the gate layer has a second surface adjacent to the gate isolation structure;

[0011] The first surface is further away from the gate isolation structure than the second surface.

[0012] In some embodiments, the semiconductor structure includes a first isolation layer located between the semiconductor layer and the gate isolation structure.

[0013] In some embodiments, the first isolation layer is also located between the stacked structure and the gate isolation structure.

[0014] In some embodiments, the semiconductor layer and the gate isolation structure do not overlap in the first direction.

[0015] In some embodiments, on the plane where the semiconductor layer is located, the sidewall of the gate isolation structure extends along the second direction, and the sidewall has a recess in the third direction.

[0016] In some embodiments, on the plane where the semiconductor layer is located, the sidewall of the gate isolation structure has a protrusion, the protrusion and the recess are alternately arranged along the second direction, and the outline of the protrusion includes an arc-shaped edge.

[0017] In some embodiments, the semiconductor layer includes a first portion and a second portion, the first portion and the second portion being located on opposite sides of the gate isolation structure along the third direction.

[0018] In some embodiments, the dimension of the first isolation layer located between the first portion and the gate isolation structure in the third direction is different from the dimension of the first isolation layer located between the second portion and the gate isolation structure in the third direction.

[0019] In some embodiments, the first portion extends along the second direction on the side adjacent to the second portion; and / or, the second portion extends along the second direction on the side adjacent to the first portion.

[0020] In some embodiments, the semiconductor structure further includes a second isolation layer located on the side of the semiconductor layer close to the stacked structure along the first direction.

[0021] In some embodiments, the semiconductor structure further includes: a plurality of channel structures that penetrate the stacked structure and the semiconductor layer along the first direction, at least one of the channel structures being located on one side of the gate isolation structure along the third direction, and at least one of the channel structures being located on the other side of the gate isolation structure along the third direction.

[0022] On the other hand, a method for fabricating a semiconductor structure is also provided, comprising: forming a semiconductor layer; forming a stacked structure, the stacked structure comprising a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked along a first direction, the stacked structure being disposed on the semiconductor layer; replacing the sacrificial layers with gate layers; forming a gate isolation structure, the gate isolation structure penetrating the stacked structure and the semiconductor layer along the first direction, the gate isolation structure extending along a second direction; in a third direction, the semiconductor layer adjacent to the gate isolation structure does not exceed the gate layer; the second direction intersects the first direction, and the third direction intersects the plane containing the first direction and the second direction.

[0023] In some embodiments, forming a semiconductor layer includes: forming an initial semiconductor layer; forming a dielectric layer, wherein the dielectric layer and the initial semiconductor layer are stacked along a first direction; removing a portion of the dielectric layer and a portion of the initial semiconductor layer to form a groove and a semiconductor layer, wherein the groove penetrates the dielectric layer and the semiconductor layer along the first direction; and filling the groove with an insulating material to form a first insulating layer.

[0024] In some embodiments, forming the initial semiconductor layer includes: forming an initial semiconductor layer and a second isolation layer on a substrate, the second isolation layer being located on both sides of the initial semiconductor layer along the first direction.

[0025] In some embodiments, after forming the stacked structure and before replacing the sacrificial layer with the gate layer, the method includes: forming a plurality of first structural holes, the plurality of first structural holes being spaced apart along the second direction, and the first structural holes penetrating the stacked structure, the first isolation layer, the semiconductor layer and a portion of the substrate; removing a portion of the stacked structure and a portion of the first isolation layer through the first structural holes, thereby connecting the plurality of first structural holes to form a gate trench.

[0026] In some embodiments, forming the gate isolation structure includes filling the gate trench with an isolation material.

[0027] In some embodiments, after forming the gate spacer, the method further includes forming a third isolation layer on the surface of a portion of the substrate through the gate spacer.

[0028] In some embodiments, forming a plurality of first structural holes includes: forming a plurality of second structural holes, wherein at least one second structural hole is located on one side of the plurality of first structural holes along the second direction, and at least one second structural hole is located on the other side of the plurality of first structural holes along the second direction; after forming the plurality of second structural holes and before forming the gate spacer, the method further includes: forming a channel structure in the plurality of second structural holes.

[0029] In another aspect, some embodiments of this disclosure also provide a storage system, including: a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor structure to control the semiconductor structure to store data. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 This is a schematic diagram of the three-dimensional structure of a three-dimensional memory according to some embodiments;

[0032] Figure 2 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0033] Figure 3 for Figure 1 A cross-sectional view of a string of storage cells in a three-dimensional memory along section line AA;

[0034] Figure 4 for Figure 3 Equivalent circuit diagram of the memory cell string;

[0035] Figure 5 A schematic diagram of a semiconductor structure according to some embodiments Figure 1 ;

[0036] Figure 6 A schematic diagram of a semiconductor structure according to some embodiments Figure 2 ;

[0037] Figure 7 for Figure 6 Enlarged view of point B in the image;

[0038] Figure 8 A schematic diagram of a semiconductor structure according to some embodiments Figure 3 ;

[0039] Figure 9 A schematic diagram of a semiconductor structure according to some embodiments Figure 4 ;

[0040] Figure 10 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0041] Figure 11 This is a schematic diagram of the structure after forming a semiconductor layer according to some embodiments;

[0042] Figure 12 This is a schematic diagram of the structure after the first isolation layer is formed according to some embodiments;

[0043] Figure 13 This is a schematic diagram of the structure after forming the first structural hole and the second structural hole according to some embodiments;

[0044] Figure 14 This is a schematic diagram of the structure after the channel structure has been formed according to some embodiments;

[0045] Figure 15 This is a schematic diagram of the structure after forming a gate spacer according to some embodiments;

[0046] Figure 16 This is a schematic diagram of the structure after forming the third isolation layer according to some embodiments;

[0047] Figure 17 This is a schematic diagram of the structure after the filling space is formed according to some embodiments;

[0048] Figure 18 This is a block diagram of a storage system according to some embodiments;

[0049] Figure 19 A block diagram of a storage system according to some other embodiments;

[0050] Figure 20 This is a block diagram of an electronic device according to some embodiments.

[0051] Reference numerals: X, first direction; Y, second direction; Z, third direction; 600, semiconductor structure; 610, semiconductor layer; 6101, first surface; 611, first portion; 612, second portion; 620, stacked structure; 621, dielectric layer; 622, gate layer; 6221, second surface; 630, gate isolation structure; 631, insulating layer; 632, body; 633, recess; 634, protrusion; 635, pillar; 640 650. First isolation layer; 410. Second isolation layer; 411. Channel structure; 412. Channel layer; 4123. Functional layer; 4124. Tunneling layer; 4125. Storage layer; 4126. Barrier layer; 700. Stacked structure; 710. Sacrificial layer; 711. Fill space; 720. Initial semiconductor layer; 730. Trench; 740. First structural hole; 750. Second structural hole; 760. Gate trench; 770. Third isolation layer; 780. Substrate. Detailed Implementation

[0052] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0053] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0054] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0055] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0056] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0057] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0058] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0059] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0060] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0061] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0062] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0063] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0064] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0065] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, the difference between the two equalities being less than or equal to 5% of either one.

[0066] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0067] Figure 1 This is a schematic diagram of the three-dimensional structure of a three-dimensional memory according to some embodiments. Figure 2 This is a cross-sectional view of a three-dimensional memory according to some embodiments. Figure 3 for Figure 1 The image shows a cross-sectional view of a string of memory cells along section line AA in a three-dimensional memory. Figure 4 for Figure 3 Equivalent circuit diagram of the storage cell string.

[0068] Please refer to Figure 1 and Figure 2 This disclosure provides a three-dimensional memory 10 located in a three-dimensional coordinate system XYZ. The three-dimensional memory 10 extends in the YZ plane, with the second direction Y being, for example, the extension direction of the word line WL, and the third direction Z being, for example, the extension direction of the bit line BL. The first direction X is perpendicular to the YZ plane.

[0069] It should be noted that the first direction X intersects with the second direction Y, and the third direction Z intersects with the XY plane. This disclosure only uses the example of the first direction X, the second direction Y, and the third direction Z being mutually perpendicular to each other to explain the structure provided in some embodiments of this disclosure.

[0070] See Figure 1 and Figure 2Some embodiments of this disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor device 200. The three-dimensional memory 10 may also include a source layer SL coupled to the semiconductor device 200, and a peripheral device 100 coupled to the semiconductor device 200. The peripheral device 100 may be disposed on the side of the semiconductor device 200 away from the source layer SL.

[0071] The source layer SL may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer SL may also include undoped regions.

[0072] Semiconductor device 200 may include arrays of memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings). Source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0073] Specifically, see Figure 3 and Figure 4 The storage cell string 400 may include multiple transistors T, one transistor T (e.g. Figure 4 Transistors T2 to T5 can be configured as a memory cell, and these transistors T are connected together to form a memory cell string 400. A transistor T (e.g., each transistor T) can be formed by a channel structure 410 and a gate line G surrounding the channel structure 410. The gate line G is configured to control the conduction state of the transistor.

[0074] It should be noted that, Figures 1-4 The number of transistors T is merely illustrative. The storage cell string 400 of the three-dimensional memory 10 provided in this embodiment may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0075] Further, along the first direction X, the lowermost gate line among the multiple gate lines G (e.g., the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source select gate SGS. The source select gate SGS is configured to control the conduction state of transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 400. Along the first direction X, the uppermost gate line among the multiple gate lines G (e.g., the gate line furthest from the source layer SL among the multiple gate lines G) is constructed as a drain select gate SGD. The drain select gate SGD is configured to control the conduction state of transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 400. The middle gate line among the multiple gate lines G can be constructed as multiple word lines WL, such as word lines WL0, WL1, WL2, and WL3. By writing different voltages onto the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be completed.

[0076] See also Figure 1 and Figure 2 In some embodiments, the semiconductor device 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line BL) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor T in the memory cell string 400.

[0077] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, bit line contacts BL-CNT, drain select gate contacts SGD-CNT, and gate line contacts G-CNT. Specifically, the bit line contact BL-CNT is coupled to the bit line BL; the drain select gate contact SGD-CNT is coupled to the drain select gate SGD; and the gate line contact G-CNT is coupled to the gate line G.

[0078] The array interconnect layer 290 may further include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include multiple interconnect lines, such as bit lines BL, and word line interconnect lines WL-CL coupled to word lines WL. The materials of the first interconnect conductor layers 291 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other conductive materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high-dielectric-constant insulating materials, or other insulating materials.

[0079] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0080] Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include the transistor 120.

[0081] The substrate 110 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0082] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0083] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor device 200 and the peripheral device 100. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuitry in the peripheral device 100 can be coupled to the memory cell string in the semiconductor device 200 to achieve the transmission of electrical signals between the peripheral circuitry and the memory cell string. In some possible implementations, an bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, allowing the peripheral interconnect layer 130 and the array interconnect layer 290 to be bonded and coupled to each other through the bonding interface 500.

[0084] This disclosure provides a semiconductor structure in some embodiments, which may be the three-dimensional memory 10 in some of the above embodiments. For example, the semiconductor structure may include peripheral devices 100. Alternatively, the semiconductor structure may be a part of the three-dimensional memory 10, for example, the semiconductor structure may be the semiconductor device 200 in some of the above embodiments.

[0085] In some embodiments, please refer to Figure 5 The semiconductor structure 600 includes: a semiconductor layer 610, a stacked structure 620, and a gate isolation structure 630.

[0086] The constituent materials of the semiconductor layer 610 may include semiconductor materials. Semiconductor materials may include, for example, monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0087] A stacked structure 620 is disposed on the semiconductor layer 610. Exemplarily, the stacked structure 620 may be in direct contact with the semiconductor layer 610. The stacked structure 620 may include a plurality of dielectric layers 621 and a plurality of gate layers 622 alternately stacked along a first direction X. For example, dielectric layers 621 and gate layers 622 may be alternately stacked along the first direction X to form a plurality of spaced-apart dielectric layers 621 and a plurality of spaced-apart gate layers 622. Alternatively, it can be understood that a gate layer 622 and a dielectric layer 621 together form a gate structure pair, and the stacked structure 620 includes a plurality of repeatedly stacked gate structure pairs.

[0088] The gate layer 622 can have 4, 16, 32, 64, 128, 256 layers, etc. Correspondingly, the dielectric layer 621 can also have 4, 16, 32, 64, 128, 256 layers, etc. The thickness of the gate layer 622 (i.e., the dimension of the gate layer 622 along the first direction X) and the thickness of the dielectric layer 621 (i.e., the dimension of the dielectric layer 621 along the first direction X) can be approximately equal or different. For example, the thickness of the dielectric layer 621 can be greater than the thickness of the gate layer 622.

[0089] The constituent materials of the gate layer 622 may include conductive materials. Conductive materials include, but are not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicides, or other suitable conductive materials. In some examples, the gate layer 622 includes a metal layer, such as a tungsten layer. In some examples, the gate layer 622 includes a doped polysilicon layer. Polysilicon can be doped to a desired doping concentration using suitable dopant to make it a conductive material that can be used as the gate layer 622.

[0090] The dielectric layer 621 may comprise an insulating material. The insulating material may include, but is not limited to, one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high-dielectric-constant insulating materials, or other suitable insulating materials. Silicon oxynitride has a higher dielectric constant than silicon oxide; for example, at approximately 20°C, the dielectric constant of silicon oxynitride is between 4 and 7, such as 3.8, 4, 4.8, 5.3, 5.9, 6, 6.36, 6.88, 7, 7.2, etc. In some examples, the dielectric layer 621 comprises a silicon oxide layer. In some examples, the dielectric layer 621 comprises a silicon oxynitride layer.

[0091] The thickness of the gate layer 622 can be between 10nm and 50nm. For example, the thickness of the gate layer 622 can be: 10nm, 15nm, 18.3nm, 20nm, 25nm, 27.7nm, 30nm, 35nm, 40nm, 45nm, 50nm, etc. Similarly, the thickness of the dielectric layer 621 can be between 10nm and 50nm. For example, the thickness of the dielectric layer 621 can be: 10nm, 15nm, 18.3nm, 20nm, 25nm, 27.7nm, 30nm, 35nm, 40nm, 45nm, 50nm, etc. The gate layer 622 can be a gate line G surrounding the memory cell string (see...). Figure 3 ), and can be used as a word line WL (see Figure 1 It extends laterally (i.e., along the second direction Y).

[0092] The gate isolation structure 630 extends through the stacked structure 620 and the semiconductor layer 610 along a first direction X. The gate isolation structure 630 extends along a second direction Y. The gate isolation structure 630 extends in the same direction as the gate layer 622. The gate isolation structure 630 can isolate the gate layer 622 adjacent along a third direction Z, so that the semiconductor structure 600 can perform read and write operations in different regions.

[0093] In some examples, reference Figure 6The gate isolation structure 630 may include an insulating material. The insulating material may be one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or may be other suitable insulating materials.

[0094] In some examples, reference Figure 5 The gate isolation structure 630 may include a semiconductor material, such as polycrystalline silicon or monocrystalline silicon. Compared to insulating materials, semiconductor materials can have greater strength, which is beneficial for providing support for the stacked structure 620.

[0095] In other examples, refer to Figure 5 The gate isolation structure 630 may include insulating and semiconductor materials. For example, the gate isolation structure 630 may include an insulating layer 631 and a body 632, with the insulating layer 631 surrounding the body 632 and located between the body 632 and the stacked structure 620. The insulating layer 631 may be a silicon oxide layer, and the body 632 may be a polysilicon partition. This configuration helps to improve the structural strength and bending resistance of the gate isolation structure 630.

[0096] In this embodiment, reference Figure 5 and Figure 6 The stacked structure 620 includes a plurality of dielectric layers 621 and a plurality of gate layers 622 alternately stacked along the first direction X, and the stacked structure 620 is disposed on the semiconductor layer 610. Thus, when the semiconductor structure 600 is processed on the back side (the side of the semiconductor layer 610 away from the stacked structure 620), the semiconductor layer 610 can protect the stacked structure 620 from damage and protect the structural integrity of the stacked structure 620.

[0097] In this embodiment, in the third direction Z, the semiconductor layer 610 near the gate isolation structure 630 does not exceed the gate layer 622. This can be understood as the semiconductor layer 610 being recessed within the gate layer 622 in the XZ plane. It can also be understood that when the gate isolation structure 630 includes an insulating layer 631 and a body 632, in the third direction Z, the gate layer 622 is closer to the body 632 than the semiconductor layer 610. Furthermore, in the third direction Z, the edge of the orthographic projection of the semiconductor layer 610 in the first direction X is located within the edge of the orthographic projection of the gate layer 622 in the first direction X.

[0098] In the fabrication process of the semiconductor structure 600 in this embodiment, after the semiconductor layer 610 and the stacked structure 620 are formed, and before the gate isolation structure 630 is formed, a step is included in which the semiconductor material is removed by wet etching through the gate slit (the space for forming the gate isolation structure 630). Since the constituent material of the semiconductor layer 610 includes semiconductor material, before the step of removing the semiconductor material by wet etching, a portion of the gate isolation structure 630 can be formed on the sidewall of the semiconductor layer 610 to protect the morphology of the semiconductor layer 610 and prevent the semiconductor layer 610 from being damaged by the subsequent wet etching step.

[0099] In this embodiment, the stacked structure 620 is disposed on the semiconductor layer 610, and the structural layer in contact with the semiconductor layer 610 can be the dielectric layer 621. Furthermore, in the third direction Z, the semiconductor layer 610 near the gate isolation structure 630 does not exceed the gate layer 622; therefore, in the third direction Z, the gate layer 622 protrudes from the semiconductor layer 610 on the side near the gate isolation structure 630. Through the above arrangement, the dielectric layer 621, which is stacked with the gate layer 622, also protrudes from the semiconductor layer 610 in the third direction Z, on the side near the gate isolation structure 630. Therefore, in the third direction Z, the semiconductor layer 610 near the gate isolation structure 630 also does not exceed the dielectric layer 621.

[0100] With the above configuration, the dielectric layer 621 covers the upper surface of the semiconductor layer 610 (one side surface along the first direction X) to protect the morphology of the semiconductor layer 610 and prevent the semiconductor layer 610 from being damaged by subsequent wet etching steps. Furthermore, in the third direction Z, since the stacked structure 620 protrudes from the semiconductor layer 610, there is sufficient space on the side of the semiconductor layer 610 along the third direction Z, and below the stacked structure 620, for forming a partial gate isolation structure 630 before the step of removing the semiconductor material using a wet etching process, to protect the morphology of the semiconductor layer 610 and prevent the semiconductor layer 610 from being damaged by subsequent wet etching steps.

[0101] It should be noted that the material of the gate isolation structure 630 located on the X-side of the stacked structure 620 and on the Z-side of the semiconductor layer 610 may include an insulating material, such as silicon oxide. When the material of the dielectric layer 621 includes silicon oxide, there may be no clear boundary between the gate isolation structure 630 and the end of the dielectric layer 621 that protrudes from the semiconductor layer 610.

[0102] In some embodiments, reference Figure 5 and Figure 6Since, in the third direction Z, the semiconductor layer 610 closest to the gate isolation structure 630 does not exceed the gate layer 622, the gate layer 622 is closer to the gate isolation structure 630 than the semiconductor layer 610. Therefore, the distance between the semiconductor layer 610 and the gate isolation structure 630 is greater than the distance between the gate layer 622 and the gate isolation structure 630.

[0103] For example, the gate layer 622 may be in contact with the gate isolation structure 630. In this case, the distance between the gate layer 622 and the gate isolation structure 630 is 0. However, in the direction from the gate isolation structure 630 to the gate layer 622, the semiconductor layer 610 is recessed within the gate layer 622, and the distance between the semiconductor layer 610 and the gate isolation structure 630 is greater than 0. Therefore, the distance between the semiconductor layer 610 and the gate isolation structure 630 is greater than the distance between the gate layer 622 and the gate isolation structure 630.

[0104] With the above configuration, a gap is formed on the side of the semiconductor layer 610 along the third direction Z close to the gate isolation structure 630 and on the side of the stacked structure 620 along the first direction X. A dielectric material layer can be formed in the gap to protect the semiconductor layer 610 from being damaged in the subsequent wet etching step, which is beneficial to maintaining the structural integrity of the semiconductor layer 610.

[0105] In some embodiments, reference Figure 5 and Figure 6 The dielectric material layer formed within the aforementioned gap can constitute part of the gate isolation structure 630. In this case, the distance between the semiconductor layer 610 and the gate isolation structure 630 is also 0. At this time, the interval between the semiconductor layer 610 and the gate isolation structure 630 is equal to the interval between the gate layer 622 and the gate isolation structure 630.

[0106] With the above configuration, a partial gate isolation structure 630 can be formed first on the side of the semiconductor layer 610 along the third direction Z close to the gate isolation structure 630 and on the side of the stacked structure 620 along the first direction X, so as to protect the semiconductor layer 610 from being damaged in the subsequent wet etching steps, which is beneficial to maintaining the structural integrity of the semiconductor layer 610.

[0107] In some embodiments, reference Figure 5 The gate isolation structure 630 includes a body 632 and an insulating layer 631. The insulating layer 631 is disposed around the body 632 and is located between the body 632 and the stacked structure 620.

[0108] For example, the material of insulating layer 631 may include an insulating material. The insulating material may be one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other insulating materials.

[0109] For example, the material of body 632 may include a semiconductor material. The semiconductor material is, for example, monocrystalline silicon or polycrystalline silicon.

[0110] Compared to insulating materials, semiconductor materials can have greater strength, which is beneficial for providing support for the stacked structure 620, thereby improving the structural strength of the gate isolation structure 630 and its bending resistance.

[0111] In this embodiment, since the semiconductor layer 610 closest to the gate isolation structure 630 does not exceed the gate layer 622 in the third direction Z, the gate layer 622 is closer to the gate isolation structure 630 than the semiconductor layer 610. Therefore, the spacing between the semiconductor layer 610 and the body is greater than the spacing between the gate layer 622 and the body.

[0112] With the above configuration, a partial gate isolation structure 630 can be formed first on the side of the semiconductor layer 610 along the third direction Z close to the gate isolation structure 630 and on the side of the stacked structure 620 along the first direction X, so as to protect the semiconductor layer 610 from being damaged in the subsequent wet etching steps, which is beneficial to maintaining the structural integrity of the semiconductor layer 610.

[0113] In some embodiments, reference Figure 6 and Figure 7 The semiconductor layer 610 has two surfaces arranged in the third direction Z, wherein the surface closer to the gate isolation structure 630 is the first surface 6101. The gate layer 622 also has two surfaces arranged in the third direction Z, wherein the surface closer to the gate isolation structure 630 is the second surface 6221. The first surface 6101 is further away from the gate isolation structure 630 than the second surface 6221.

[0114] With the above configuration, a dielectric material can be formed between the first surface 6101 and the gate isolation structure 630 to protect the semiconductor layer 610 from being damaged in the subsequent wet etching step, which is beneficial to maintaining the structural integrity of the semiconductor layer 610.

[0115] In some embodiments, reference Figure 6 and Figure 7The semiconductor structure 600 includes a first isolation layer 640 located between the semiconductor layer 610 and the gate isolation structure 630. In some examples, the first isolation layer 640 is made of silicon oxide, in which case, when the gate isolation structure 630 is also made of silicon oxide, the first isolation layer 640 can be part of the gate isolation structure 630. In other examples, the material of the first isolation layer 640 may include one or more of silicon oxynitride and a high-dielectric-constant insulating material, or other suitable insulating materials.

[0116] This disclosure does not limit the size of the first isolation layer 640 in the third direction Z.

[0117] For example, the thickness of the first isolation layer 640 in the first direction X may be greater than the thickness of the semiconductor layer 610 in the first direction X. Alternatively, the thickness of the first isolation layer 640 in the first direction X may be the same as the thickness of the semiconductor layer 610 in the first direction X.

[0118] With the above configuration, the first isolation layer 640 can protect the structural integrity of the semiconductor layer 610 and prevent the semiconductor layer 610 from being damaged by the wet etching step in the preparation process.

[0119] In some embodiments, reference Figure 6 and Figure 8 The first isolation layer 640 is also located between the stacked structure 620 and the gate isolation structure 630. In this embodiment, the thickness of the first isolation layer 640 in the first direction X is greater than the thickness of the semiconductor layer 610 in the first direction X. For example, the first isolation layer 640 may be located between the dielectric layer 621 and the gate isolation structure 630.

[0120] With the above configuration, the first isolation layer 640 is located not only between the semiconductor layer 610 and the gate isolation structure 630, but also between the stacked structure 620 and the gate isolation structure 630. This improves the problem that gaps easily exist at the junction of the stacked structure 620 and the first isolation layer 640, which could lead to the semiconductor layer 610 being damaged by the wet etching step in the fabrication process. The dielectric layer 621, which is closest to the semiconductor layer 610 in the stacked structure 620, and the first isolation layer 640 jointly isolate the semiconductor layer 610, which helps protect the structural integrity of the semiconductor layer 610 and prevents it from being damaged by the wet etching step in the fabrication process.

[0121] In some embodiments, reference Figure 6A semiconductor layer 610 is disposed on a substrate 780, and a stacked structure 620 is disposed on the semiconductor layer 610. In the third direction Z, the semiconductor layer 610 near the gate isolation structure 630 does not exceed the gate layer 622. The substrate 780, the semiconductor layer 610, and the stacked structure 620 can enclose a space, and a portion of the gate isolation structure 630 can extend into this space.

[0122] For example, substrate 780 may include silicon oxide material.

[0123] In this embodiment, the semiconductor layer 610 and the gate isolation structure 630 do not overlap in the first direction X. This can be understood as the projection of the semiconductor layer 610 in the first direction X not overlapping with the projection of the gate isolation structure 630 in the first direction X. The semiconductor layer 610 may be located on both sides of the gate isolation structure 630 along the third direction Z, and the semiconductor layer 610 may contact the sidewall of the gate isolation structure 630, but the semiconductor layer 610 does not penetrate the gate isolation structure 630, so that the semiconductor layer 610 and the gate isolation structure 630 do not overlap in the first direction X.

[0124] With the above configuration, the semiconductor layer 610 can be recessed within the stacked structure 620 and the substrate 780. A portion of the gate isolation structure 630 can be formed on the side of the semiconductor layer 610 along the third direction Z close to the gate isolation structure 630, and on the side of the stacked structure 620 along the first direction X. This protects the semiconductor layer 610 from damage during subsequent wet etching steps and helps maintain the structural integrity of the semiconductor layer 610.

[0125] In addition, from the third-party perspective, the fact that the semiconductor layer 610 does not penetrate the gate isolation structure 630 also helps to improve the structural regularity of the gate isolation structure 630 itself.

[0126] In some embodiments, reference Figure 6 and Figure 8 On the plane where the semiconductor layer 610 is located, the sidewall of the gate isolation structure 630 extends along the second direction Y, and the sidewall has a recess 633 in the third direction Z.

[0127] In this embodiment, the sidewalls of the gate isolation structure 630 extend along the second direction Y, and the gate isolation structure 630 is an integral structure extending along the second direction Y. On the plane where the semiconductor layer 610 is located, the outline of the gate isolation structure 630 is a closed pattern.

[0128] Exemplarily, on the plane where the semiconductor layer 610 is located, the gate isolation structure 630 may include a plurality of pillars 635, which may be arranged sequentially and connected along the second direction Y. Exemplarily, the pillars 635 may include cylinders 635. Exemplarily, the number of connected pillars 635 included in the gate isolation structure 630 can be determined based on the number of arc-shaped edges. A recess 633 may be formed on the sidewall at the connection between two adjacent pillars 635.

[0129] Furthermore, on the plane where the semiconductor layer 610 is located, the first isolation layer 640 can be disposed around the gate isolation structure 630, and the first isolation layer 640 can contact the recess 633 on the sidewall of the gate isolation structure 630.

[0130] In some examples, reference Figure 6 and Figure 8 The material of the first isolation layer 640 is silicon oxide, and the material of the gate isolation structure 630 is also silicon oxide. Therefore, there is no obvious boundary between the first isolation layer 640 and the gate isolation structure 630, and the first isolation layer 640 can contact the recess 633 on the sidewall of the gate isolation structure 630. Thus, the recess 633 on the sidewall of the gate isolation structure 630 cannot be observed.

[0131] In other examples, the first isolation layer 640 is made of silicon oxide, and the gate isolation structure 630 includes an insulating layer 631 and a body 632, with the insulating layer 631 surrounding the body 632. The insulating layer 631 can be a silicon oxide layer, and the body 632 can be a polysilicon partition. The presence of a recess 633 on the sidewall of the gate isolation structure 630 can be determined by the presence of a recess 633 on the sidewall of the body 632.

[0132] With the above configuration, compared to the gate isolation structure 630 in some embodiments which consists of multiple spaced pillars 635, the gate isolation structure 630 in this embodiment is a single integrated structure with recesses 633 on its sidewalls, which is beneficial for improving the stress strength of the gate isolation structure 630. Furthermore, in some examples, the dimensions of the gate isolation structure 630 in the second direction Y and the third direction Z can be designed by changing the diameter and number of pillars 635, so as to form gate isolation structures 630 of various sizes according to different needs, without requiring additional process steps, thus simplifying the fabrication of the semiconductor structure 600.

[0133] In some embodiments, reference Figure 6 and Figure 8On the plane containing the semiconductor layer 610, the sidewalls of the gate isolation structure 630 extend along the second direction Y, and the sidewalls have recesses 633 and protrusions 634 in the third direction Z. The protrusions 634 and recesses 633 are alternately arranged along the second direction Y. The outline of the protrusions 634 includes arcuate edges, and the centers of the plurality of arcuate edges are all located within the gate isolation structure 630.

[0134] In this embodiment, the gate isolation structure 630 may include a plurality of pillar 635 structures arranged and connected sequentially along the second direction Y, such as cylinders. With this configuration, the sidewalls of the cylinder 635 structures have an arc-shaped profile on the plane where the semiconductor layer 610 is located, and the center of this arc is located within the gate isolation structure 630. Furthermore, the connection points of two adjacent arc-shaped sides create recesses 633 on the sidewalls of the gate isolation structure 630, thereby forming sidewalls with alternating protrusions 634 and recesses 633 along the second direction Y. Since the protrusions 634 have an arc-shaped profile on the plane where the semiconductor layer 610 is located, the sidewalls of the gate isolation structure 630 can be a plurality of arc-shaped sides connected sequentially along the second direction Y.

[0135] For example, the radial lengths of the plurality of pillars 635 may be the same to improve the structural regularity of the gate isolation structure 630. The radial lengths of the plurality of pillars 635 may be different, thereby changing the dimensions of the gate isolation structure 630 in the second direction Y and the third direction Z. This allows the dimensions of the gate isolation structure 630 in the second direction Y and the third direction Z to be adjusted according to the arrangement of the channel structures 410 located on both sides of the gate isolation structure 630 along the third direction Z.

[0136] With the above settings, the gate isolation structure 630 can be designed in the second direction Y and the third direction Z by setting the number of arc edges and the curvature of the arc edges, so as to form gate isolation structures 630 of various sizes according to different needs, without adding new process steps, which helps to simplify the fabrication difficulty of semiconductor structure 600.

[0137] Additionally, it should be noted that in some examples, references Figure 8 and Figure 9 The semiconductor structure 600 includes a first isolation layer 640, which is located between the gate isolation structure 630 and the semiconductor layer 610.

[0138] The first isolation layer 640 can contact both the protrusions 634 and the recesses 633 on the sidewall of the gate isolation structure 630.

[0139] In some examples, the gate isolation structure 630 may include an insulating layer 631 and a body 632, with the insulating layer 631 surrounding the body 632. When the material of the first isolation layer 640 is the same as that of the insulating layer 631, for example, when both the first isolation layer 640 and the insulating layer 631 are made of silicon oxide and there is no clear boundary between them, the boundary can be determined based on the contour of the body 632.

[0140] In this embodiment, reference continues to be made to Figure 8 and Figure 9 On the plane where the semiconductor layer 610 is located, the sidewalls of the main body 632 can extend along the second direction Y, and the sidewalls of the main body 632 have protrusions and recesses in the third direction Z, and the protrusions and recesses can be alternately arranged along the second direction Y. Furthermore, the outline of the protrusions can include arc-shaped edges. Therefore, on the plane where the semiconductor layer 610 is located, the outline of the main body 632 can include multiple interconnected arc-shaped edges, the centers of which are all located within the main body 632.

[0141] With the above configuration, on the plane where the semiconductor layer 610 is located, compared to the gate isolation structure 630 in other embodiments which consists of multiple pillars 635 spaced apart, the gate isolation structure 630 in this embodiment is an integral structure with a recess 633 on the sidewall, which is beneficial to improving the stress strength of the gate isolation structure 630.

[0142] In some embodiments, reference Figure 6 , Figure 8 and Figure 9 The semiconductor layer 610 includes a first portion 611 and a second portion 612, which are located on both sides of the gate isolation structure 630 along the third direction Z.

[0143] In this embodiment, the gate isolation structure 630 divides the semiconductor layer 610 into a first portion 611 and a second portion 612 spaced apart along the third direction Z, and the first portion 611 and the second portion 612 do not contact each other.

[0144] Furthermore, the gate isolation structure 630 isolates the gate layer 622 adjacent to it along the third direction Z. With the above arrangement, the first portion 611 near the gate isolation structure 630 does not exceed the gate layer 622, and the second portion 612 near the gate isolation structure 630 also does not exceed the gate layer 622. Therefore, there is space on the side of the first portion 611 near the gate isolation structure 630, and there is also space on the side of the second portion 612 near the gate isolation structure 630. These spaces can be used to form the first isolation layer 640 to protect the morphology of the semiconductor layer 610 and prevent the semiconductor layer 610 from being damaged by the wet etching step during the fabrication process.

[0145] In some embodiments, reference Figure 6 and Figure 8 The dimension of the first isolation layer 640 located between the first portion 611 and the gate isolation structure 630 in the third direction Z is the same as the dimension of the first isolation layer 640 located between the second portion 612 and the gate isolation structure 630 in the third direction Z.

[0146] Here, the dimension of the first isolation layer 640 located between the first portion 611 and the gate isolation structure 630 in the third direction Z can be understood as the width of the first isolation layer 640 located between the first portion 611 and the gate isolation structure 630 in the third direction Z.

[0147] "Same" includes absolute sameness and approximately sameness. For example, the acceptable deviation range for approximately sameness can be that the difference between two equal items is less than or equal to 5% of the size of either one.

[0148] However, the dimensions of the first isolation layer 640 located between the first portion 611 and the gate isolation structure 630 in the third direction Z are the same as those of the first isolation layer 640 located between the second portion 612 and the gate isolation structure 630 in the third direction Z. This places higher demands on the fabrication process of the semiconductor structure 600 and requires a higher process window.

[0149] In other embodiments, reference is made to Figure 6 and Figure 8 The dimension of the first isolation layer 640 located between the first portion 611 and the gate isolation structure 630 in the third direction Z is different from the dimension of the first isolation layer 640 located between the second portion 612 and the gate isolation structure 630 in the third direction Z.

[0150] For example, the dimension of the first isolation layer 640 located between the first portion 611 and the gate isolation structure 630 in the third direction Z is greater than the dimension of the first isolation layer 640 located between the second portion 612 and the gate isolation structure 630 in the third direction Z. Alternatively, the dimension of the first isolation layer 640 located between the first portion 611 and the gate isolation structure 630 in the third direction Z is smaller than the dimension of the first isolation layer 640 located between the second portion 612 and the gate isolation structure 630 in the third direction Z.

[0151] With the above configuration, the first isolation layer 640 can protect the morphology of the semiconductor layer 610 and prevent the semiconductor layer 610 from being damaged by the wet etching step during the fabrication process. In addition, it can reduce the fabrication process requirements and process window of the semiconductor structure 600, thereby reducing the fabrication difficulty of the semiconductor structure 600.

[0152] In some embodiments, reference Figure 6 and Figure 8 The side of the first part 611 closest to the second part 612 extends along the second direction Y. Therefore, the side of the first part 611 closest to the second part 612 can be a plane parallel to the second direction Y, and the side of the first part 611 closest to the second part 612 extends along the second direction Y. (Reference) Figure 8 On the plane where the semiconductor layer 610 is located, the boundary of the first part 611 near the gate isolation structure 630 can be a straight line extending along the second direction Y.

[0153] In this embodiment, similarly, the side of the second portion 612 near the first portion 611 can also extend along the second direction Y. Therefore, the side of the second portion 612 near the first portion 611 can be a plane parallel to the second direction Y, and the side of the second portion 612 near the first portion 611 extends along the second direction Y. Referring to the figure, on the plane where the semiconductor layer 610 is located, the boundary of the second portion 612 near the gate isolation structure 630 can be a straight line extending along the second direction Y.

[0154] In this embodiment, the side of the first portion 611 near the gate isolation structure 630 has a regular pattern (planar shape), and the side of the second portion 612 near the gate isolation structure 630 also has a regular pattern. This arrangement helps to control the side of the first portion 611 near the gate isolation structure 630, ensuring it does not exceed the gate layer 622 in the third direction (Z). Similarly, it helps to control the side of the second portion 612 near the gate isolation structure 630, ensuring it does not exceed the gate layer 622 in the third direction (Z). This facilitates the formation of a first isolation layer 640 on the side of the first portion 611 near the gate isolation structure 630, and on the side of the second portion 612 near the gate isolation structure 630, protecting the morphology of the first portion 611 and the second portion 612 and preventing them from being damaged by subsequent wet etching steps.

[0155] In some embodiments, reference Figure 6 The semiconductor structure 600 further includes a second isolation layer 650, which is located on the side of the semiconductor layer 610 along the first direction X near the stacked structure 620. The second isolation layer 650 may be stacked with the semiconductor layer 610 along the first direction X. For example, the material of the second isolation layer 650 may include silicon nitride.

[0156] By providing a second isolation layer 650 on the surface of the semiconductor structure 600, it is beneficial to prevent the semiconductor layer 610 from being wet-oxidized during the fabrication process, and to prevent the semiconductor layer 610 from being damaged during the fabrication process of the semiconductor structure 600.

[0157] In some embodiments, reference Figure 6The semiconductor structure 600 also includes a plurality of channel structures 410. The channel structures 410 penetrate the stacked structure 620 and the semiconductor layer 610 along a first direction X, at least one channel structure 410 is located on one side of the gate isolation structure 630 along a third direction Z, and at least one channel structure 410 is located on the other side of the gate isolation structure 630 along a third direction Z.

[0158] In this embodiment, the channel structure 410 includes a channel layer 411 and a functional layer 412, with the functional layer 412 surrounding a portion of the channel layer 411. The channel layer 411 can be made of a semiconductor material, including but not limited to amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The voltage provided by the gate layer 622 can control the movement or cessation of charge carriers (electrons or holes) within the channel layer 411.

[0159] Functional layer 412 is disposed around a portion of channel layer 411. Functional layer 412 may include a tunneling layer 4121, a storage layer 4122, and a barrier layer 4123 disposed sequentially in a direction away from channel layer 411. Carriers in channel layer 411 can tunnel through tunneling layer 4121 into storage layer 4122, storage layer 4122 is configured to store carriers, and barrier layer 4123 is configured to prevent carrier overflow.

[0160] The material of the tunneling layer 4121 may include, but is not limited to, one or more combinations of silicon oxide and silicon oxynitride. In some examples, the tunneling layer 4121 may be a single-layer dielectric, such as a silicon oxide layer. In other examples, the tunneling layer 4121 may be a composite dielectric layer 621, such as a stacked structure 700 of a first silicon oxide layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a second silicon oxide layer.

[0161] The material of the barrier layer 4123 may include one or more combinations of silicon oxide, silicon nitride, and high dielectric constant materials. In some examples, the barrier layer 4123 may be a single-layer dielectric, such as a silicon oxide layer. In other examples, the barrier layer 4123 may be a composite dielectric layer 621, such as a stacked structure 700 of silicon nitride and aluminum oxide layers.

[0162] The storage layer 4122 is configured to store charge carriers. The material of the storage layer 4122 may include silicon nitride, or other suitable materials for storing charge carriers, which are not limited here.

[0163] In this embodiment, multiple channel structures 410 can be arranged in multiple rows and columns along the second direction Y and the third direction Z. The multiple channel structures 410 can be symmetrically arranged with the gate isolation structure 630 as the plane of symmetry. Here, "symmetrical arrangement" means that the multiple channel structures 410 can include absolute symmetry and approximate symmetry. Approximate symmetry can be understood as the multiple channel structures 410 on one side of the gate isolation structure 630 along the third direction Z being symmetrical to the multiple channel structures 410 on the other side of the gate isolation structure 630 along the third direction Z, with local variations in one or more of the channel structures 410. For example, the dimensions of one channel structure 410 in the second direction Y and the third direction Z can be relatively larger or relatively smaller compared to the other channel structures 410.

[0164] In this embodiment, the channel structure 410 penetrates the semiconductor layer 610, so that on the side of the semiconductor layer 610 facing away from the stacked structure 620, the channel structure 410 can be opened by a back-side process, thereby bringing out the channel layer 411 in the channel structure 410. Furthermore, through the above arrangement, during the back-side process, the semiconductor layer 610 can protect the structural integrity of the stacked structure 620, which helps prevent damage to the morphology of the stacked structure 620.

[0165] In some embodiments, reference Figure 6 The surface area of ​​the channel structure 410 away from the semiconductor layer 610 along the first direction X is larger than the surface area of ​​the channel structure 410 close to the semiconductor layer 610 along the first direction X. Viewed from the XZ plane, the end of the channel structure 410 away from the semiconductor layer 610 along the first direction X is wider, and the end close to the semiconductor layer 610 is narrower. This arrangement helps to improve the process window for connecting the end of the channel structure 410 away from the semiconductor layer 610 along the first direction X to other conductive structures.

[0166] This disclosure also provides a method for fabricating a semiconductor structure 600 in some embodiments, which will be described below in conjunction with... Figures 10-17 The preparation method of a semiconductor structure 600 is explained.

[0167] Figure 10 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments. Figure 10 As shown, some embodiments of this disclosure provide a method for fabricating a semiconductor structure 600, including: S1 to S4.

[0168] S1, Forming a semiconductor layer.

[0169] refer to Figure 11This step includes forming an initial semiconductor layer 720. Exemplarily, this step may employ a deposition process to form the initial semiconductor layer 720 and a second isolation layer 650 on a substrate 780, the second isolation layer 650 being located on both sides of the initial semiconductor layer 720 along a first direction X.

[0170] The deposition process includes, but is not limited to, one or more thin film deposition processes among Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

[0171] It should be noted that the material of substrate 780 may include semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and other semiconductor materials. Alternatively, the material of substrate 780 may include non-semiconductor materials, such as silicon oxide. Alternatively, substrate 780 may include multiple material layers, and the materials of substrate 780 may include both semiconductor and non-semiconductor materials. For example, in this embodiment, substrate 780 includes a semiconductor material layer 781 and a dielectric material layer 782, wherein the semiconductor material layer 781 is made of monocrystalline silicon or polycrystalline silicon, and the dielectric material layer 782 is made of silicon oxide.

[0172] refer to Figure 11 and Figure 12 After forming the initial semiconductor layer 720, a dielectric material can be deposited on the initial semiconductor layer 720 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a dielectric layer 621. The dielectric layer 621 and the initial semiconductor layer 720 are stacked along a first direction X. For example, the dielectric material may include silicon oxide.

[0173] refer to Figure 11 and Figure 12 After the dielectric layer 621 is formed, a portion of the dielectric layer 621 and a portion of the initial semiconductor layer 720 can be removed to form a groove 730 and a semiconductor layer 610. The groove 730 penetrates the dielectric layer 621 and the semiconductor layer 610 along the first direction X.

[0174] The recess 730 can be formed using any suitable process. For example, a patterned photoresist layer can be formed on the dielectric layer 621. The patterned photoresist layer can expose the portion of the dielectric layer 621 used to form the recess 730. A suitable etching process can be performed to remove the portion of the dielectric layer 621 and the initial semiconductor layer 720 used to form the recess 730. For example, the etching process can include a dry etching process.

[0175] After the groove 730 and the semiconductor layer 610 are formed, the patterned photoresist layer on the dielectric layer 621 can be removed, for example, by planarizing the surface of the dielectric layer 621 by chemical mechanical polishing (CMP) to remove the patterned photoresist layer covering the dielectric layer 621.

[0176] After removing the patterned photoresist layer covering the dielectric layer 621, a deposition process can be used to fill the groove 730 with a dielectric material, such as silicon oxide, to form the first isolation layer 640.

[0177] S2. A stacked structure is formed, the stacked structure including multiple dielectric layers and multiple sacrificial layers alternately stacked along a first direction, the stacked structure being disposed on a semiconductor layer.

[0178] refer to Figure 12 and Figure 13 In this step, a sacrificial layer 710 and a dielectric layer 621 may be alternately formed on the semiconductor layer 610 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a stacked structure 700.

[0179] It should be noted that in the step of forming the groove 730, a dielectric layer 621 is formed on the semiconductor layer 610, and the dielectric layer 621 can be part of the stacked structure 700.

[0180] For example, the material of the dielectric layer 621 may include an insulating material, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride and high dielectric constant insulating materials, or other suitable insulating materials.

[0181] For example, the material of the sacrificial layer 710 may include an insulating material. However, since the sacrificial layer 710 needs to be removed in subsequent fabrication steps, the composition of the sacrificial layer 710 needs to be different from that of the dielectric layer 621 to prevent damage to the dielectric layer 621 during the removal of the sacrificial layer 710. This embodiment uses silicon oxide as the composition of the dielectric layer 621 and silicon nitride as the composition of the sacrificial layer 710 as an example for explanation.

[0182] refer to Figure 13After forming the stacked structure 700, a plurality of first structural holes 740 and a plurality of second structural holes 750 can be formed. The plurality of first structural holes 740 are spaced apart along the second direction Y, and the first structural holes 740 penetrate the stacked structure 700, the first isolation layer 640, the semiconductor layer 610, and a portion of the substrate 780. At least one second structural hole 750 is located on one side of the plurality of first structural holes 740 along the second direction Y, and at least one second structural hole 750 is located on the other side of the plurality of first structural holes 740 along the second direction Y.

[0183] In this embodiment, the first structural hole 740 and the second structural hole 750 can be formed by any suitable process. For example, a patterned photoresist layer can be formed on the stacked structure 700. The patterned photoresist layer can expose the portions of the stacked structure 700 used to form the first structural hole 740 and the second structural hole 750. Suitable etching processes can be performed to remove the portions of the stacked structure 700, the first isolation layer 640, and the substrate 780 used to form the first structural hole 740, and to remove the portions of the stacked structure 700 and the substrate 780 used to form the second structural hole 750. For example, the etching process can include a dry etching process.

[0184] refer to Figure 13 and Figure 14 After forming the first structural hole 740 and the second structural hole 750, a channel structure 410 can be formed in the plurality of second structural holes 750.

[0185] In this step, refer to Figure 14 For example, a functional layer 412 and a channel layer 411 can be sequentially formed within the second structural aperture 750 using one or more thin-film deposition processes, including but not limited to PVD, CVD, and ALD. The functional layer 412 surrounds the channel layer 411, and the functional layer 412 and the channel layer 411 together constitute the channel structure 410. The channel structure 410 penetrates the stacked structure 700, the semiconductor layer 610, and a portion of the substrate 780. The functional layer 412 formed within the second structural aperture 750 includes a barrier layer 4123, a storage layer 4122, and a tunneling layer 4121 sequentially formed within the second structural aperture 750.

[0186] Exemplarily, the material of tunneling layer 4121 may include, but is not limited to, one or more combinations of silicon oxide and silicon oxynitride. The material of barrier layer 4123 may include, but is not limited to, one or more combinations of silicon oxide, silicon nitride, and high dielectric constant materials. The material of storage layer 4122 may include silicon nitride, or other suitable materials for storing charge carriers. The material of channel layer 411 may include, but is not limited to, amorphous silicon, polycrystalline silicon, or monocrystalline silicon.

[0187] refer to Figure 13 and Figure 14After forming the first structural hole 740 and the second structural hole 750, the patterned photoresist layer on the stacked structure 700 can also be removed. For example, the surface of the stacked structure 700 can be planarized by chemical mechanical polishing to remove the patterned photoresist layer covering the stacked structure 700.

[0188] refer to Figure 13 , Figure 14 and Figure 15 After forming the first structural hole 740 and the second structural hole 750, a wet etching process can be used to remove part of the stacked structure 700 and part of the first isolation layer 640 through the first structural hole 740, so that adjacent first structural holes 740 are connected, thereby connecting multiple first structural holes 740 to form a gate spacer 760.

[0189] In this step, since the sacrificial layer 710 and the dielectric layer 621 are made of different materials, multiple wet etching processes can be performed through the first structural hole 740 to remove part of the stacked structure 700 and part of the first isolation layer 640 through the first structural hole 740.

[0190] Furthermore, it should be noted that when removing part of the stacked structure 700 and part of the first isolation layer 640 through multiple wet etching processes, the dimensions of the gate partition 760 in the second direction Y and the third direction Z can be controlled, for example, by controlling the number of etching operations, the etching duration, and the volume of the etching solution. Moreover, the first isolation layer 640 surrounding the gate partition 760 is retained; the first isolation layer 640 is provided on both sides of the gate partition 760 along the second direction Y and on both sides of the gate partition 760 along the third direction Z, to prevent the first isolation layer 640 from being removed.

[0191] refer to Figure 15 , Figure 16 and Figure 17 After forming the gate spacer 760, a portion of the sacrificial layer 710 can be removed using a wet etching process through the gate spacer 760 to expose a portion of the dielectric layer 621. This process is repeated, using wet etching again through the gate spacer 760, to further remove a portion of the dielectric layer 621, thus thinning the thickness of the dielectric layer 621 exposed in the gate spacer 760. Through these steps, the spacing between adjacent dielectric layers 621 exposed in the gate spacer 760 is greater than the thickness of the sacrificial layer 710. This results in a large opening on the side of the adjacent dielectric layer 621 closest to the gate spacer 760, facilitating the filling of material in the subsequent step of replacing the sacrificial layer 710 with the gate layer 622.

[0192] refer to Figure 15 , Figure 16 and Figure 17After forming the gate spacer 760, a third isolation layer 770 can be formed on the surface of a portion of the substrate 780 using a deposition process through the gate spacer 760. For example, one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, can be used to deposit an insulating material on the surface of the substrate 780 exposed in the gate spacer 760 to form the third isolation layer 770, thereby protecting the substrate 780 from damage during subsequent wet etching steps.

[0193] S3. Replace the sacrificial layer with the gate layer.

[0194] refer to Figure 6 , Figure 15 , Figure 16 and Figure 17 In this step, a wet etching process can be used through the gate partition 760, for example, by injecting etching solution into the gate partition 760 to remove the sacrificial layer 710 to form a filling space 711, which is connected to the gate partition 760.

[0195] In other embodiments, when the material of the sacrificial layer 710 includes carbon, the process of removing the sacrificial layer 710 may include ashing to remove all of the sacrificial layer 710 to form the filling space 711.

[0196] After the filling space 711 is formed, one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, can be used to deposit conductive material in the filling space 711 to form the gate layer 622.

[0197] For example, the conductive material includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0198] S4. A gate isolation structure is formed, which penetrates the stacked structure and the semiconductor layer along the first direction and extends along the second direction; in the third direction, the semiconductor layer near the gate isolation structure does not exceed the gate layer; the second direction intersects the first direction, and the third direction intersects the plane containing the first and second directions.

[0199] refer to Figure 6 , Figure 15 , Figure 16 and Figure 17In this step, one or more thin-film deposition processes, including but not limited to PVD, CVD, and ALD, can be used to sequentially deposit an insulating material and a semiconductor material in the gate isolation trench 760, such as silicon oxide and polysilicon, to form an insulating layer 631 and a body 632. The insulating layer 631 covers the sidewalls of the gate isolation trench 760 and surrounds the body 632. The insulating layer 631 and the body 632 together constitute the gate isolation structure 630.

[0200] In some embodiments, the material of the first insulating layer 640 includes silicon oxide, and the material of the insulating layer 631 also includes silicon oxide. In this case, there is no clear boundary between the first insulating layer 640 and the insulating layer 631, therefore, the first insulating layer 640 can also be considered as part of the insulating layer 631.

[0201] In some other embodiments, the material of the first isolation layer 640 is different from that of the insulating layer 631. In this case, the first isolation layer 640 is located between the semiconductor layer 610 and the gate isolation structure 630, and the first isolation layer 640 is also located between the dielectric layer 621 and the gate isolation structure 630.

[0202] Since a first isolation layer 640 is formed after the formation of the groove 730 and the semiconductor layer 610, the first isolation layer 640 remains located on the side of the semiconductor layer 610 along the third direction Z during the subsequent fabrication steps of the semiconductor structure 600. This can also be understood as the first isolation layer 640 remaining between the semiconductor layer 610 and the gate isolation trench 760. Therefore, through this configuration, the first isolation layer 640 can protect the structural integrity of the semiconductor layer 610 and prevent it from being damaged during the subsequent wet etching step. After the gate layer 622 is formed in the filling space 711, the gate layer 622 is also located on the side of the first isolation layer 640 along the first direction X. Therefore, the gate layer 622 protrudes from the semiconductor layer 610 in the third direction Z. This can also be understood as the semiconductor layer 610 near the gate isolation structure 630 not exceeding the gate layer 622 in the third direction Z.

[0203] Figure 18 This is a block diagram of a storage system according to some embodiments. Figure 19 This is a block diagram of a storage system according to some other embodiments. Please refer to... Figure 18 and Figure 19 This disclosure also provides a storage system 1000 in some embodiments, which includes a controller 20 and a semiconductor structure 600 provided in the above embodiments. The controller 20 is coupled to the semiconductor structure 600 to control the semiconductor structure 600 to store data.

[0204] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0205] In some embodiments, see Figure 18 The storage system 1000 includes a controller 20 and a semiconductor structure 600, and the storage system 1000 can be integrated into a memory card. Exemplarily, the semiconductor structure 600 can be a memory with a three-dimensional structure (3D NAND).

[0206] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD device) card, and UFS.

[0207] In other embodiments, see Figure 19 The storage system 1000 includes a controller 20 and multiple semiconductor structures 600, and the storage system 1000 is integrated into a solid state drive (SSD device).

[0208] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD device card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0209] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment in an SSD device or eMMC used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays.

[0210] In some embodiments, controller 20 may be configured to manage data stored in semiconductor structure 600 and to communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of semiconductor structure 600, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in semiconductor structure 600, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to semiconductor structure 600.

[0211] Of course, controller 20 can also perform any other suitable functions, such as formatting semiconductor structure 600; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0212] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESD Device I) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0213] The controller 20 in the above embodiments may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0214] This disclosure also provides an electronic device in some embodiments. Figure 20 This is a block diagram of an electronic device according to some embodiments. For example... Figure 20As shown, the electronic device 3000 includes a motherboard 2000 and a storage system 1000 provided in some of the above embodiments. The motherboard 2000 is electrically connected to the storage system 1000. In addition, the electronic device 3000 may also include at least one of a central processing unit (CPU) and a cache.

[0215] For example, the electronic device 3000 can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0216] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor layer; A stacked structure disposed on the semiconductor layer, the stacked structure comprising a plurality of dielectric layers and a plurality of gate layers alternately stacked along a first direction; A gate isolation structure, wherein the gate isolation structure extends through the stacked structure and the semiconductor layer along a first direction, and the gate isolation structure extends along a second direction; In the third direction, the semiconductor layer adjacent to the gate isolation structure does not exceed the gate layer; The second direction intersects the first direction, and the third direction intersects the plane containing the first direction and the second direction.

2. The semiconductor structure according to claim 1, characterized in that, The distance between the semiconductor layer and the gate isolation structure is greater than or equal to the distance between the gate layer and the gate isolation structure.

3. The semiconductor structure according to claim 2, characterized in that, The gate isolation structure includes a body and an insulating layer, the insulating layer being disposed around the body and located between the body and the stacked structure; The distance between the semiconductor layer and the body is greater than the distance between the gate layer and the body.

4. The semiconductor structure according to claim 1, characterized in that, In the third direction, the semiconductor layer has a first surface adjacent to the gate isolation structure, and the gate layer has a second surface adjacent to the gate isolation structure; The first surface is further away from the gate isolation structure than the second surface.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a first isolation layer located between the semiconductor layer and the gate isolation structure.

6. The semiconductor structure according to claim 5, characterized in that, The first isolation layer is also located between the stacked structure and the gate isolation structure.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor layer and the gate isolation structure do not overlap in the first direction.

8. The semiconductor structure according to claim 1, characterized in that, On the plane where the semiconductor layer is located, the sidewall of the gate isolation structure extends along the second direction, and the sidewall has a recess in the third direction.

9. The semiconductor structure according to claim 8, characterized in that, On the plane where the semiconductor layer is located, the sidewall of the gate isolation structure has a protrusion, and the protrusion and the recess are alternately arranged along the second direction, and the outline of the protrusion includes an arc-shaped edge.

10. The semiconductor structure according to any one of claims 1-9, characterized in that, The semiconductor layer includes a first portion and a second portion, which are located on opposite sides of the gate isolation structure along the third direction.

11. The semiconductor structure according to claim 10, characterized in that, The dimension of the first isolation layer located between the first portion and the gate isolation structure in the third direction is different from the dimension of the first isolation layer located between the second portion and the gate isolation structure in the third direction.

12. The semiconductor structure according to claim 10, characterized in that, The first portion extends along the second direction from the side of the second portion; And / or, the second portion extends along the second direction from the side of the first portion.

13. The semiconductor structure according to any one of claims 1-9, characterized in that, It also includes a second isolation layer, which is located on the side of the semiconductor layer close to the stacked structure along the first direction.

14. The semiconductor structure according to any one of claims 1-9, characterized in that, Also includes: Multiple channel structures are provided, the channel structures extending through the stacked structure and the semiconductor layer along the first direction, at least one of the channel structures being located on one side of the gate isolation structure along the third direction, and at least one of the channel structures being located on the other side of the gate isolation structure along the third direction.

15. A method for fabricating a semiconductor structure, characterized in that, include: Forming a semiconductor layer; A stacked structure is formed, the stacked structure comprising a plurality of dielectric layers and a plurality of sacrificial layers alternately stacked along a first direction, the stacked structure being disposed on the semiconductor layer; Replace the sacrificial layer with a gate layer; A gate isolation structure is formed, wherein the gate isolation structure penetrates the stacked structure and the semiconductor layer along a first direction and extends along a second direction; In the third direction, the semiconductor layer adjacent to the gate isolation structure does not exceed the gate layer; The second direction intersects the first direction, and the third direction intersects the plane containing the first direction and the second direction.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The formation of the semiconductor layer includes: Forming the initial semiconductor layer; A dielectric layer is formed, wherein the dielectric layer and the initial semiconductor layer are stacked along the first direction; A portion of the dielectric layer and a portion of the initial semiconductor layer are removed to form a groove and a semiconductor layer, the groove penetrating the dielectric layer and the semiconductor layer along the first direction; The groove is filled with insulating material to form a first insulating layer.

17. The method for preparing a semiconductor structure according to claim 16, characterized in that, The formation of the initial semiconductor layer includes: An initial semiconductor layer and a second isolation layer are formed on a substrate, the second isolation layer being located on both sides of the initial semiconductor layer along the first direction.

18. The method for preparing a semiconductor structure according to claim 17, characterized in that, After the formation of the stacked structure and before the replacement of the sacrificial layer with the gate layer, the following is included: A plurality of first structural holes are formed, the plurality of first structural holes are spaced apart along the second direction, and the first structural holes penetrate the stacked structure, the first isolation layer, the semiconductor layer and a portion of the substrate; By removing a portion of the stacked structure and a portion of the first isolation layer through the first structural aperture, the plurality of first structural apertures are connected to form a gate spacer.

19. The method for preparing a semiconductor structure according to claim 18, characterized in that, The formation of the gate isolation structure includes: The gate spacer is filled with insulating material.

20. The method for preparing a semiconductor structure according to claim 18, characterized in that, After forming the gate spacer, the method further includes: A third isolation layer is formed on the surface of a portion of the substrate through the gate trench.

21. The method for preparing a semiconductor structure according to claim 18, characterized in that, The formation of multiple first structural holes includes: A plurality of second structural holes are formed, at least one second structural hole is located on one side of the plurality of first structural holes along the second direction, and at least one second structural hole is located on the other side of the plurality of first structural holes along the second direction; After forming the plurality of second structural holes and before forming the gate spacer, the method further includes: A channel structure is formed in the plurality of second structural holes.

22. A storage system, characterized in that, include: The semiconductor structure as described in any one of claims 1-14; A controller, the control being coupled to the semiconductor structure, to control the semiconductor structure to store data.

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