A gallium oxide phase junction power device and a method of manufacturing the same

Abstract

This invention discloses a gallium oxide (GaO) junction device, primarily addressing the limitations of β-Ga2O3-based devices and the lack of substrate-level bulk single crystals in α-Ga2O3-based devices, resulting in poor crystal quality. The device comprises a β-Ga2O3 substrate and an α-Ga2O3 epitaxial structure layer, with an auxiliary transfer layer and a liquid metal-based GaO nucleation layer between them. These layers are used for the transfer and epitaxial growth of α-Ga2O3, respectively, to form an α-Ga2O3-β-Ga2O3 junction structure. GaO diodes and vertical GaO transistors are fabricated on this junction structure according to requirements. This invention combines the ultra-high voltage withstand capability of α-Ga2O3 with the low-cost mass production potential of the β-Ga2O3 substrate, effectively improving the quality of the α-Ga2O3 epitaxial structure layer and providing a new technical path for performance and cost control of GaO-based power devices. It can be used in high-voltage, low-loss power electronic circuits.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a gallium oxide junction power device and its fabrication method, which can be used in high-voltage, low-loss power electronic circuits. Background Technology

[0002] With the rapid development of high-power power electronics technology, Ga2O3, with its ultra-wide bandgap, high breakdown field strength, and excellent Baliga quality factor, has become an ideal candidate material for high-frequency, high-power devices to meet the demands of future energy systems for higher voltage withstand and lower losses. Ga2O3 has five crystal phases: α, β, γ, δ, and ε(k). Among them, β-Ga2O3, which belongs to the monoclinic crystal system, is the most thermodynamically stable of all crystal phases. It can be used to produce high-quality, large-size, low-cost, and controllable-doped single-crystal substrates through a melting method, which lays a key foundation for the large-scale production of its power devices.

[0003] Significant progress has been made in the research of β-Ga2O3-based power devices in recent years. Liu et al. fabricated a vertical β-Ga2O3 SBD device, which significantly reduced the electron concentration in the near-surface region of the β-Ga2O3 substrate through thermal oxidation. The device exhibited a breakdown voltage of 460 V, a specific on-resistance of 10.5 mΩ·cm², and a power factor of quality (PFOM) of 20.2 MW / cm². 2 The high-performance enhancement-mode β-Ga2O3 multi-fin field-effect transistor developed by Guo et al., fabricated using a highly selective etching and two-step photolithography planarization process, achieved a transistor breakdown voltage of 975 V and a specific on-resistance of 4.3 mΩ⋅cm. 2 These two types of β-Ga2O3SBD and MOSFET devices, relying on their electrical characteristics that can be adapted to high-voltage scenarios, have made significant progress in the field of high-voltage, low-loss power devices, providing important support for the application and transformation of gallium oxide-based power devices.

[0004] Compared to β-Ga₂O₃, α-Ga₂O₃ possesses a wider bandgap of ~5.3 eV and a higher breakdown field strength of ~10 MV / cm, giving it a natural competitive advantage in power devices. α-Ga₂O₃ devices fabricated by researchers using heteroepitaxial growth have demonstrated outstanding performance in high-voltage applications. Compared to β-Ga₂O₃ SBDs, the α-Ga₂O₃ SBD device fabricated by Yang et al. using mist chemical vapor deposition (mist-CVD) on a 1.5 μm microcavity embedded sapphire substrate achieved a breakdown voltage of 679 V. Compared to β-Ga₂O₃ MOSFETs, the α-Ga₂O₃ MOSFET device fabricated by Jeong et al. using halide vapor phase epitaxy (HVA) achieved a specific on-resistance of 335 mΩ·cm², a breakdown voltage of 2.3 kV, and a critical electric field of 1 MV / cm, demonstrating its potential for ultra-high voltage applications. However, it should be noted that due to the thermodynamically metastable nature of α-Ga2O3, it is difficult to retain the target α-phase structure. Therefore, it is not yet possible to directly prepare large-size, low-defect-density α-Ga2O3 substrate-level bulk single crystals that meet the requirements of device-level epitaxy using a low-cost, large-scale melt method. Currently, its preparation can only be achieved through heteroepitaxial technology.

[0005] In summary, monoclinic β-Ga₂O₃ exhibits excellent thermodynamic stability, and its use as a substrate can be achieved through low-cost mass production using mature, large-scale fabrication techniques such as melt processing. α-Ga₂O₃, with its wider band gap and higher breakdown field strength, demonstrates greater application potential than β-Ga₂O₃ in high-voltage power devices. However, since α-Ga2O3 lacks substrate-level bulk single crystals, if high-quality α-Ga2O3 films can be constructed on mature and low-cost β-Ga2O3 substrates, it is expected to combine the ultra-high breakdown voltage characteristics of α-Ga2O3 with the advantages of large-scale preparation of β-Ga2O3 substrates. However, this approach faces core scientific and technological challenges: since β-Ga2O3 is a monoclinic crystal system with space group C2 / m, while α-Ga2O3 is a trigonal crystal system with space group R-3c, there are intrinsic differences in their crystal structures. Therefore, during direct heteroepitaxialization, defects such as high-density dislocations, twins, and interface stress cracking will be caused by lattice mismatch, which will seriously damage the crystal integrity of the α-Ga2O3 film, resulting in a significant decrease in device breakdown voltage and making it difficult to fully release its ultra-high breakdown voltage potential. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of the prior art by proposing a gallium oxide-structured power device and its fabrication method. This method avoids the lattice mismatch of direct heteroepitaxial α-Ga2O3, fully integrates the ultra-high voltage withstand characteristics of α-Ga2O3 with the advantages of large-scale fabrication of β-Ga2O3 substrates, and improves the key indicators of power device in terms of voltage withstand performance and cost control.

[0007] The technical approach to achieve the objective of this invention is as follows: using gallium oxide prepared based on liquid metal as the nucleation layer, and employing epitaxial growth techniques such as HVPE, MIST-CVD, and MOCVD, the lattice mismatch of direct heteroepitaxial growth of α-Ga2O3 is avoided, thus achieving the growth of high-quality α-Ga2O3 thin films. Furthermore, the gallium oxide nucleation layer can effectively prevent oxidation damage to the auxiliary transfer layer. Relying on the weak van der Waals forces of the auxiliary transfer layer, the α-Ga2O3 thin film can be transferred to the surface of a β-Ga2O3 substrate through a mechanical lift-off process, constructing an α-Ga2O3 / β-Ga2O3 phase junction structure. This completes the overall construction of Ga2O3-based power devices, fully leveraging the performance advantages of both α-Ga2O3 and β-Ga2O3, improving the breakdown voltage performance of power devices, and reducing device fabrication costs.

[0008] Based on the above ideas, the technical solution of the present invention includes:

[0009] 1. A gallium oxide junction power diode, comprising: a substrate, an epitaxial layer, a cathode located below the substrate, and an anode located above the epitaxial layer, characterized in that the substrate is made of β-Ga2O3 material, the epitaxial layer is made of α-Ga2O3 material, and an auxiliary transfer layer and a gallium oxide nucleation layer are provided between the β-Ga2O3 substrate and the α-Ga2O3 epitaxial layer, respectively used for the transfer and epitaxial growth of α-Ga2O3 to form an α-Ga2O3 and β-Ga2O3 junction structure.

[0010] Furthermore, the β-Ga2O3 substrate has a thickness of 400-700 μm; the α-Ga2O3 epitaxial layer has a thickness of 1-5 μm.

[0011] Furthermore, the auxiliary transfer layer is made of graphene or boron nitride and has a thickness of 1-3 nm; the gallium oxide nucleation layer has a thickness of 4-10 nm.

[0012] 2. A gallium oxide junction vertical power transistor, comprising: a substrate, an epitaxial layer, a drain, a current blocking layer, and an N-type junction. + The source contact region, source electrode, gate dielectric layer, and gate metal are characterized in that the substrate is made of β-Ga2O3 material, the epitaxial layer is made of α-Ga2O3 material, and an auxiliary transfer layer and a gallium oxide nucleation layer are provided between the β-Ga2O3 substrate and the α-Ga2O3 epitaxial layer, which are respectively used for the transfer and epitaxial growth of the α-Ga2O3 epitaxial layer to form an α-Ga2O3 and β-Ga2O3 phase junction structure.

[0013] Furthermore, the β-Ga2O3 substrate has a thickness of 400-700 μm; the α-Ga2O3 epitaxial layer has a thickness of 1-5 μm.

[0014] Furthermore, the drain is located below the substrate, and the current blocking layers are located on both sides of the upper part of the epitaxial layer, N + The source contact region is located above the current blocking layer, and the source electrode is located at N. + Above the source contact region, the gate dielectric layer is located above the epitaxial layer and is situated between two current blocking layers and N. + Between the source contact regions, and covering part of the epitaxial layer and N. + On the surface of the source contact area, the gate metal is located inside the groove formed by the gate dielectric layer.

[0015] 3. A method for fabricating a gallium oxide junction power diode, characterized in that it includes:

[0016] S1) The auxiliary transfer layer is transferred to the surface of a sapphire or silicon carbide substrate using a wet transfer technique and then subjected to low-temperature annealing to remove organic residues;

[0017] S2) Using extrusion, transfer or scraping methods, with liquid gallium metal as a precursor, a gallium oxide nucleation layer is initially formed on the surface of the auxiliary transfer layer, and the residual liquid gallium metal is cleaned up.

[0018] S3) The gallium oxide nucleation layer is first annealed in situ using hydride vapor phase epitaxy (HVPE), mist-CVD, or metal-organic vapor phase deposition (MOCVD) techniques, and then an α-Ga2O3 epitaxial structure layer is epitaxially grown on its surface.

[0019] S4) Utilizing the weak van der Waals forces of the auxiliary transfer layer, the α-Ga2O3 epitaxial layer is transferred to the β-Ga2O3 substrate by mechanical exfoliation. Annealing is then used to enhance the interaction between α-Ga2O3 and β-Ga2O3, forming an α-Ga2O3 / β-Ga2O3 phase junction structure with an auxiliary transfer layer and a gallium oxide nucleation layer between them.

[0020] S5) A cathode electrode was prepared by vapor deposition of titanium and gold multilayer metal on the surface of a β-Ga2O3 substrate and rapid annealing.

[0021] S6) Nickel and gold multilayer metals are deposited on the surface of the α-Ga2O3 epitaxial layer, and the anode electrode is obtained through a patterning process to complete the fabrication of the power diode.

[0022] Furthermore, the mechanical lift-off technique in S4) and the transfer of the α-Ga2O3 epitaxial layer onto the β-Ga2O3 substrate are implemented as follows:

[0023] First, an organic transfer support layer is prepared on the α-Ga2O3 epitaxial layer, and then thermal release tape (TRT) is pasted on top of it as a temporary support.

[0024] The entire sample was immersed in deionized water at room temperature. One edge of the TRT was lifted to facilitate the separation of the auxiliary transfer layer from the sapphire or silicon carbide substrate, and then transferred to the β-Ga2O3 substrate.

[0025] The transferred structure was placed on a hot plate to peel off the TRT, the organic transfer support layer was dissolved, and then the organic residue was cleaned up.

[0026] 4. A method for fabricating a gallium oxide-junction vertical power transistor, characterized in that it includes:

[0027] §1) The auxiliary transfer layer is transferred to the surface of a sapphire or silicon carbide substrate using a wet transfer technique and then subjected to low-temperature annealing to remove organic residues;

[0028] §2) Using extrusion, transfer or blade coating, a uniform and continuous gallium oxide nucleation layer is prepared on the surface of the auxiliary transfer layer with liquid gallium as the precursor, and the residual liquid gallium is cleaned up.

[0029] §3) An α-Ga2O3 epitaxial structure layer is epitaxially grown on the gallium oxide nucleation layer using hydride vapor phase epitaxy (HVPE), mist vapor deposition (mist-CVD), or metal-organic vapor deposition (MOCVD) techniques.

[0030] §4) With the help of the weak van der Waals forces of the auxiliary transfer layer, the α-Ga2O3 epitaxial layer grown on the gallium oxide nucleation layer based on liquid gallium metal is transferred to the β-Ga2O3 substrate by mechanical lift-off technology. The interaction between α-Ga2O3 and β-Ga2O3 is enhanced by annealing to form an α-Ga2O3 / β-Ga2O3 phase junction structure with an auxiliary transfer layer and a gallium oxide nucleation layer between them.

[0031] §5) Deposit titanium / gold multilayer metal as bottom drain electrode by electron beam evaporation, deposit titanium / gold multilayer metal and pattern it by lift-off process as source contact metal, and rapidly anneal in nitrogen atmosphere to form ohmic contact;

[0032] §6) By photolithographic patterning, in N + The location of the gate trench is defined on the surface of the source contact region, and the gate trench is etched in an inductively coupled plasma system. The etching damage is then removed in a piranha solution. The sample is then sent into an atomic layer deposition chamber for gate dielectric deposition. A nickel / gold multilayer metal is deposited by magnetron sputtering and patterned as the gate metal to complete the fabrication of the vertical power transistor.

[0033] Furthermore, the α-Ga2O3 epitaxial structure layer in §3) comprises, from bottom to top: an α-Ga2O3 epitaxial layer, a Mg-doped α-Ga2O3 current blocking layer, and a silicon-doped N2O3 current blocking layer. + Source contact area.

[0034] Compared with the prior art, the present invention has the following advantages:

[0035] Firstly, this invention constructs a high-quality α-Ga2O3 on a β-Ga2O3 substrate to form an α-Ga2O3 and β-Ga2O3 phase junction structure, which can synergize the ultra-high voltage withstand characteristics of α-Ga2O3 with the low-cost mass production potential of the β-Ga2O3 substrate, providing a new technical path for performance and cost control of gallium oxide-based power devices.

[0036] Secondly, this invention introduces gallium oxide prepared based on liquid metal as the nucleation layer for α-Ga2O3 epitaxial growth, which can effectively alleviate lattice mismatch, prevent oxidation damage to the auxiliary transfer layer, promote the stable formation and ordered orientation of α-phase crystals, and improve the quality of α-Ga2O3 epitaxial layer.

[0037] Third, the α-Ga2O3 / β-Ga2O3 phase junction structure described in this invention can be further extended to the ε-Ga2O3 / β-Ga2O3 phase junction structure, expanding the application of gallium oxide materials in electronic and optoelectronic devices, and providing an expandable technical path for upgrading the performance of gallium oxide-based power devices. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of a gallium oxide junction power diode structure provided in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of a gallium oxide junction vertical power transistor structure provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram illustrating the process of fabricating gallium oxide junctions according to the present invention;

[0041] Figure 4 This is a schematic diagram illustrating the process of fabricating a gallium oxide junction power diode according to the present invention;

[0042] Figure 5 This is a schematic diagram illustrating the implementation process of fabricating a gallium oxide junction vertical power transistor according to the present invention. Detailed Implementation

[0043] The technical solution of the present invention will be further described in full and in detail below with reference to the accompanying drawings and embodiments.

[0044] Reference Figure 1 The gallium oxide junction power diode of this example includes: a substrate 11, an auxiliary transfer layer 12, a gallium oxide nucleation layer 13, an epitaxial layer 14, a cathode 15, and an anode 16, wherein:

[0045] The substrate 11 is made of β-Ga2O3 material with a thickness of 400-700μm;

[0046] The auxiliary transfer layer 12 is located on the upper surface of the substrate 11, and it is made of graphene or boron nitride material with a thickness of 1-3 nm.

[0047] The gallium oxide nucleation layer 13 is located on the surface of the auxiliary transfer layer 12 and has a thickness of 4-10 nm.

[0048] The epitaxial layer 14 is located on the surface of the gallium oxide nucleation layer 13. It is made of α-Ga2O3 material and has a thickness of 1-5μm. It and the substrate 11 made of β-Ga2O3 material form a phase junction structure.

[0049] The cathode 15 is located above the lower surface of the substrate 11 and is a stacked metal of titanium with a thickness of 30-50 nm and gold with a thickness of 100-200 nm.

[0050] The anode 16 is located above the upper surface of the epitaxial layer 14 and is a stacked metal of nickel with a thickness of 100-120 nm and gold with a thickness of 100-200 nm.

[0051] The substrate 11 of the β-Ga2O3 material and the epitaxial layer 14 of the α-Ga2O3 material form a phase junction structure, the principle of which is as follows:

[0052] This embodiment takes into account the lack of substrate-level bulk single crystals of α-Ga2O3, whose preparation mainly relies on epitaxial technology. However, β-Ga2O3 belongs to the monoclinic crystal system with space group C2 / m, while α-Ga2O3 belongs to the trigonal crystal system with space group R-3c. The two have intrinsic differences in crystal structure. Directly heteroepitaxially growing α-Ga2O3 material on the substrate surface of β-Ga2O3 material will lead to defects such as high-density dislocations, twins, and interface stress cracking due to lattice mismatch during the epitaxial process, severely damaging the crystal integrity of the α-Ga2O3 material and causing a significant decrease in device breakdown voltage, making it difficult to fully release its ultra-high breakdown voltage potential. Therefore, this invention, on the one hand, addresses the issue of α-Ga2O3 epitaxial growth... In this process, gallium oxide, prepared using liquid metal, is used as the nucleation layer. High-quality α-Ga2O3 epitaxial layers are prepared through epitaxial growth techniques such as HVPE, MIST-CVD, and MOCVD. The introduction of the gallium oxide nucleation layer can effectively alleviate lattice mismatch, promote the stable formation and ordered orientation of the α-phase crystal, improve the epitaxial quality of the α-Ga2O3 material, and fully utilize the ultra-high voltage withstand capability of α-Ga2O3. On the other hand, the introduction of the gallium oxide nucleation layer can avoid oxidation damage to the auxiliary transfer layer. Thus, with the help of the weak van der Waals forces of the auxiliary transfer layer, the α-Ga2O3 epitaxial layer can be transferred to the surface of the β-Ga2O3 substrate through a mechanical lift-off process, forming an α-Ga2O3 / β-Ga2O3 phase junction structure. This phase junction integrates the ultra-high voltage withstand capability of α-Ga2O3 with the advantages of large-scale fabrication of the β-Ga2O3 substrate, achieving synergistic optimization of device voltage withstand performance and process cost, and providing a new structural innovation solution for ultra-high voltage gallium oxide-based power devices.

[0053] Reference Figure 2 The gallium oxide junction vertical power transistor of this example includes: a substrate 21, an auxiliary transfer layer 22, a gallium oxide nucleation layer 23, an epitaxial layer 24, a drain 25, a current blocking layer 26, and an N-type junction. + Source contact region 27, source electrode 28, gate dielectric layer 29, gate metal 210, wherein:

[0054] The substrate 21 is made of β-Ga2O3 material with a thickness of 400-700μm;

[0055] The auxiliary transfer layer 22 is located on the upper surface of the substrate 21 and is made of graphene or boron nitride material with a thickness of 1-3 nm.

[0056] The gallium oxide nucleation layer 23 is located on the surface of the auxiliary transfer layer 22 and has a thickness of 4-10 nm.

[0057] The epitaxial layer 24 is located on the surface of the gallium oxide nucleation layer 23, and is made of α-Ga2O3 material with a thickness of 1-5μm. It forms a phase junction structure with the substrate 21 made of β-Ga2O3 material.

[0058] The drain electrode 25 is located below the substrate 21 and is made of a multilayer metal consisting of titanium with a thickness of 30-50 nm and gold with a thickness of 100-200 nm.

[0059] The current blocking layer 26 is located on both sides of the upper part of the epitaxial layer 24, and it is made of magnesium-doped α-Ga2O3 material with a magnesium doping concentration of 3×10⁻⁶. 18 ~5×10 18 cm -3 The thickness is 0.2-0.5μm;

[0060] The N + The source contact region 27 is located above the current blocking layer 26 and is made of silicon-doped α-Ga2O3 material with a silicon doping concentration of 3 × 10⁻⁶. 19 ~5×10 19 cm -3 The thickness is 0.05-0.15μm;

[0061] The source electrode 28 is located in N + Above the source contact region 27, a multilayer metal of 30-50 nm titanium and 100-200 nm gold is used;

[0062] The gate dielectric layer 29 is located above the epitaxial layer 24 and is situated between the two current blocking layers 26 and N. + Between the source contact region 27, and covering part of the epitaxial layer 24 and N. + The surface of the source contact region 27 is made of alumina material with a thickness of 80-120 nm;

[0063] The gate metal 210 is located inside the groove formed by the gate dielectric layer 29, and it is a multilayer metal with a thickness of 80-120nm nickel and 100-200nm gold.

[0064] Reference Figure 3 This invention provides three embodiments for fabricating power diodes with gallium oxide junctions:

[0065] Example 1: Graphene was used as an auxiliary transfer layer, gallium oxide nucleation layer was formed by extrusion, α-Ga2O3 was epitaxially grown using MIST-CVD technology, and PMMA adhesive was used to transfer α-Ga2O3 to a β-Ga2O3 substrate to prepare a gallium oxide power diode with α-Ga2O3 / β-Ga2O3 junction.

[0066] Reference Figure 3 The process for preparing the α-Ga2O3 / β-Ga2O3 phase junction is as follows:

[0067] Step 1: Transfer graphene onto a sapphire substrate to form an auxiliary transfer layer.

[0068] 1.1) Select sapphire as the substrate, and ultrasonically clean it with acetone and isopropanol for 5 minutes each, then rinse it with running deionized water for 5 minutes, and dry it with a nitrogen gun.

[0069] 1.2) Select commercially available multilayer graphene / copper foil, and ultrasonically clean it with acetone and anhydrous ethanol for 4 min in sequence, and dry it with a nitrogen gun; spin coat PMMA glue onto the graphene using a spin coater, rotate the sample at a speed of 1500 r / min for 10 seconds in sequence, rotate the sample at a speed of 3000 r / min for 40 s in sequence, and then place it on a hot plate at 110℃ to cure for 5 min.

[0070] 1.3) The sample after passing 1.2) above was placed in an etching solution composed of 1M FeCl3 and 5% HCl to etch the copper foil for 40 min, and then rinsed in deionized water. The deionized water was replaced every 3 min and repeated three times. Then the PMMA-supported graphene was transferred to the cleaned sapphire substrate surface and dried on a hot plate at 180°C for 10 min.

[0071] 1.4) After cooling to room temperature, immerse the entire sample in 60℃ acetone for 10 minutes to remove the PMMA adhesive. Then, clean the sample surface with acetone and anhydrous ethanol for 5 minutes in sequence, and dry it with a nitrogen gun to form a graphene auxiliary layer 12 with a thickness of 2nm on the sapphire substrate.

[0072] Step 2: A uniform and continuous gallium oxide nucleation layer based on liquid metal is initially prepared on the graphene surface using an extrusion method.

[0073] 2.1) Place a drop of liquid gallium metal on the surface of the graphene auxiliary layer and place it on a hot plate at 130°C. Then, use a force of 5-10N to press a clean glass slide vertically down onto the droplet to allow the liquid gallium to spread fully. Then, place it in an atmosphere with an oxygen flow rate of 10 L / min for 10-20 minutes to oxidize it.

[0074] 2.2) Use a cotton swab dipped in warm ethanol at 90°C to clean the residual trace amount of liquid gallium metal, and initially obtain a gallium oxide nucleation layer 13 with a thickness of 5nm.

[0075] Step 3: α-Ga2O3 is epitaxially grown on the initially prepared gallium oxide nucleation layer using the mist-CVD technique.

[0076] 3.1) Dissolve gallium acetylacetonate Ga(acac)3 powder in deionized water and add 1-3% hydrochloric acid to prepare a gallium source solution of 0.02-0.05 mol / L, and put it into the atomization chamber for later use;

[0077] 3.2) Place the sample prepared in step 2 into the center of the reaction chamber of the MIST-CVD. Control the temperature of the reaction chamber to rise to 450-500℃ at a rate of 8-10℃ / min. Use nitrogen gas with a flow rate of 600-700 sccm as a carrier gas to carry oxygen gas with a flow rate of 40-50 sccm into the reaction chamber. Anneal the initially prepared gallium oxide nucleation layer for 5 min. Then raise the temperature of the reaction chamber to 550-600℃, turn on the atomization device, set the working frequency of the ultrasonic atomizer to 1-3MHz, atomize the prepared gallium source solution into micron-sized particles and introduce them into the reaction chamber to start the α-Ga2O3 epitaxial growth.

[0078] 3.3) After the α-Ga2O3 film thickness reaches 3μm, the atomization device is turned off, and the temperature of the reaction chamber is controlled to drop to room temperature at a rate of less than 10℃ / min, so that an α-Ga2O3 epitaxial layer 14 is formed on the gallium oxide nucleation layer 13.

[0079] Step 4: Transfer the α-Ga2O3 epitaxial layer onto the β-Ga2O3 substrate to construct an α-Ga2O3 / β-Ga2O3 phase junction structure.

[0080] 4.1) The β-Ga2O3 substrate with a thickness of 550μm was cleaned and prepared for use. Specifically, it was ultrasonically cleaned with acetone and isopropanol for 5 minutes each, then rinsed with deionized water for 5 minutes, and dried with a nitrogen gun.

[0081] 4.2) Spin-coating PMMA adhesive onto the α-Ga2O3 epitaxial layer prepared in step 3 using a spin coater. The sample was rotated at a speed of 1500 r / min for 10 seconds, followed by a speed of 3000 r / min for 40 seconds. The sample was then placed on a hot plate at 110°C for 5 minutes to cure. Then, thermal release adhesive tape (TRT) was attached to the PMMA surface as a temporary support.

[0082] 4.3) Immerse the TRT / PMMA / α-Ga2O3 / gallium oxide nucleation layer / graphene / sapphire substrate sample obtained in step 4.2) into deionized water at room temperature, peel off one edge of TRT to promote rapid separation of graphene and sapphire substrate, and then transfer the sample with TRT support to the surface of β-Ga2O3 substrate.

[0083] 4.4) Place the sample obtained in step 4.3) on a hot plate at 110°C for 10 seconds to peel off the TRT; then immerse it in acetone at 60°C for 10 minutes to dissolve the PMMA support layer; rinse the surface with anhydrous ethanol for 5 minutes to remove residual solvent, and dry it with a nitrogen gun. Place it in a tube furnace and set the vacuum level inside the furnace to 10. -2Torr, annealed at 400-450℃ for 10 min, enhances the bonding force between α-Ga2O3 and β-Ga2O3, resulting in an α-Ga2O3 / β-Ga2O3 phase structure from bottom to top consisting of a β-Ga2O3 substrate, a graphene-assisted transfer layer, a gallium oxide nucleation layer, and an α-Ga2O3 epitaxial layer.

[0084] Step 5: Based on the obtained junction structure, fabricate a power diode with a gallium oxide junction.

[0085] Reference Figure 4 The implementation process for this step is as follows:

[0086] 5.1) Electron beam evaporation was used to deposit 30 nm titanium and 200 nm gold stacked metals on the lower surface of β-Ga2O3; then rapid annealing was carried out at 470-500℃ in N2 atmosphere for 1-3 min to achieve ohmic contact between the titanium / gold stacked metal and β-Ga2O3 to form cathode electrode 15.

[0087] 5.2) Photoresist is coated on the surface of α-Ga2O3. After exposure and development, the area where the anode metal needs to be deposited is exposed. Electron beam evaporation is used to deposit 100nm of nickel and 200nm of gold multilayer metal, respectively. Then, a patterned anode metal array is obtained by lift-off process as the anode electrode 16 to complete the fabrication of the power diode.

[0088] Example 2: Boron nitride was used as an auxiliary transfer layer, gallium oxide nucleation layer was formed by transfer printing, α-Ga2O3 was epitaxially grown using HVPE technology, and PMMA adhesive was used to transfer α-Ga2O3 to β-Ga2O3 substrate to prepare gallium oxide power diode with α-Ga2O3 / β-Ga2O3 junction.

[0089] Reference Figure 3 Preparation of α-Ga2O3 / β-Ga2O3 phase junctions:

[0090] Step 1: Transfer boron nitride onto a sapphire substrate to form an auxiliary transfer layer.

[0091] 1-1) Select sapphire as the substrate, and ultrasonically clean it with acetone and isopropanol for 5 minutes each, then rinse it with running deionized water for 5 minutes, and dry it with a nitrogen gun.

[0092] 1-2) Select a multilayer boron nitride / copper foil, and ultrasonically clean it with acetone and anhydrous ethanol for 5 min in sequence, and then dry it with a nitrogen gun; then spin-coat the boron nitride with PMMA glue using a spin coater, and rotate the sample at a speed of 1500 r / min for 10 seconds and at a speed of 3000 r / min for 40 seconds in sequence; then place it on a hot plate at 110℃ to cure for 5 min.

[0093] 1-3) The sample after step 1-2) is placed in an etching solution composed of 1M FeCl3 and 5% HCl to etch the copper foil for 40 minutes, then rinsed in deionized water, changing the deionized water every 3 minutes, and repeating three times; then the PMMA-supported boron nitride is transferred to the cleaned sapphire substrate surface and dried on a hot plate at 180°C for 10 minutes.

[0094] 1-4) After cooling to room temperature, immerse the entire sample in 60℃ acetone for 10 minutes to remove the PMMA adhesive. Then, clean the sample surface with acetone and anhydrous ethanol for 5 minutes in sequence, and dry it with a nitrogen gun to form a boron nitride auxiliary layer 12 with a thickness of 3nm on the sapphire substrate.

[0095] Step 2: A gallium oxide nucleation layer based on liquid metal is initially prepared on the boron nitride surface using a transfer method.

[0096] 2-1) Drop liquid gallium onto KAPTON tape, then coat it evenly onto PDMS. Quickly attach the PDMS loaded with gallium droplets to the surface of the auxiliary transfer layer. Place the entire sample on a hot plate at 80°C and heat for 20 seconds. Vertically peel off the PDMS and oxidize it in an atmosphere with an oxygen flow rate of 10 L / min for 10-20 minutes.

[0097] 2-2) Use a cotton swab dipped in warm ethanol at 90°C to clean away the residual trace amount of liquid gallium metal, and a gallium oxide nucleation layer 13 with a thickness of 8nm can be initially obtained on the surface of the boron nitride auxiliary layer 12.

[0098] Step 3: α-Ga2O3 is epitaxially grown on the initially prepared gallium oxide nucleation layer using HVPE technology.

[0099] 3-1) Place the sample obtained in step 2 into the quartz tray of the HVPE system, and put the gallium metal into the precursor cavity. Set the temperature of the precursor cavity to 650-750℃ and the pressure of the cavity to 500-550 Torr. Then, use N2 to carry HCl gas with a flow rate of 10-30 sccm into the precursor cavity to form GaCl with the gallium metal.

[0100] 3-2) Then, O2 with a flow rate of 200-300 sccm is introduced into the reaction chamber of the HVPE system, and the chamber temperature is controlled at 450-500℃. The initially prepared gallium oxide nucleation layer is annealed for 5 min. Then, N2 carrying GaCl is introduced into the reaction chamber of the HVPE system, and the chamber temperature is controlled at 550-600℃. After an α-Ga2O3 film with a thickness of 4 μm is epitaxially grown on the surface of the gallium oxide nucleation layer 13, the heating of the precursor chamber and the reaction chamber is stopped, and they are both controlled to cool down to room temperature at a rate of less than 10℃ / min, that is, an α-Ga2O3 epitaxial layer 14 is formed on the gallium oxide nucleation layer 13.

[0101] Step four: Transfer the α-Ga2O3 epitaxial layer onto the β-Ga2O3 substrate to construct an α-Ga2O3 / β-Ga2O3 phase junction structure.

[0102] 4-1) Place the 550μm thick β-Ga2O3 substrate in acetone and isopropanol for ultrasonic cleaning for 5 min each, rinse with deionized water for 5 min, and dry with a nitrogen gun.

[0103] 4-2) Spin-coating PMMA adhesive onto the α-Ga2O3 epitaxial layer prepared in step 3 using a spin coater. First, spin the sample at a speed of 1500 r / min for 10 seconds, then spin the sample at a speed of 3000 r / min for 40 seconds; then place it on a hot plate at 110℃ to cure for 5 minutes; then attach thermal release adhesive tape (TRT) to the PMMA surface as a temporary support.

[0104] 4-3) Immerse the TRT / PMMA / α-Ga2O3 / gallium oxide nucleation layer / boron nitride / sapphire substrate sample obtained in step 4-2) into deionized water at room temperature, peel off one edge of TRT to promote rapid separation of boron nitride from sapphire substrate, and then transfer the sample with TRT support to the surface of β-Ga2O3 substrate.

[0105] 4-4) Place the sample obtained in step 4-3) on a hot plate at 110°C for 10 seconds to peel off the TRT; then immerse the peeled sample in acetone at 60°C for 10 minutes to dissolve the PMMA support layer; rinse the surface with anhydrous ethanol for 5 minutes to remove residual solvent, dry with a nitrogen gun, and then place it in a tube furnace with a vacuum level of 10. -2 Torr, annealed at 400-450℃ for 10 min, to enhance the bonding force between α-Ga2O3 and β-Ga2O3, resulting in an α-Ga2O3 / β-Ga2O3 phase structure from bottom to top consisting of a β-Ga2O3 substrate, a boron nitride-assisted transfer layer, a gallium oxide nucleation layer, and an α-Ga2O3 epitaxial layer.

[0106] Step 5: Based on the obtained junction structure, fabricate a power diode with a gallium oxide junction.

[0107] Reference Figure 4 The specific implementation of this step is the same as step 5 in Example 1.

[0108] Example 3: Graphene was used as an auxiliary transfer layer. The gallium oxide nucleation layer based on liquid metal was grown by a blade coating method and MOCVD technology. PPC adhesive was used to transfer the α-Ga2O3 to the β-Ga2O3 substrate to prepare a gallium oxide power diode with an α-Ga2O3 / β-Ga2O3 junction.

[0109] Reference Figure 3 The process for preparing the α-Ga2O3 / β-Ga2O3 phase junction is as follows:

[0110] Step A: Transfer graphene onto a silicon carbide substrate to form an auxiliary transfer layer.

[0111] A1) Select silicon carbide as the substrate, and clean it with acetone and isopropanol for 5 minutes each, then rinse it with running deionized water for 5 minutes, and dry it with a nitrogen gun.

[0112] A2) Select multilayer graphene / copper foil, and clean it sequentially with acetone and anhydrous ethanol using ultrasonic cleaning for 5 minutes each, and then dry it with a nitrogen gun; then spin-coat PMMA glue onto the graphene using a spin coater, and rotate the sample sequentially at a speed of 1500 r / min for 10 seconds, and at a speed of 3000 r / min for 40 seconds, and then place it on a hot plate at 110℃ to cure for 5 minutes.

[0113] A3) The sample after step A2) is placed in an etching solution composed of 1M FeCl3 and 5% HCl to etch the copper foil for 40 minutes, then rinsed in deionized water, and the deionized water is replaced every 3 minutes, and repeated three times; then the PMMA-supported graphene is transferred to the cleaned silicon carbide substrate surface and dried on a hot plate at 180°C for 10 minutes.

[0114] A4) After cooling to room temperature, immerse the entire sample in 60℃ acetone for 10 minutes to remove the PMMA adhesive. Then, clean the sample surface with acetone and anhydrous ethanol for 5 minutes in sequence, and dry it with a nitrogen gun to form a graphene auxiliary layer 12 with a thickness of 2nm on the silicon carbide substrate.

[0115] Step B involves using a blade coating method to initially prepare a gallium oxide nucleation layer based on liquid metal on the graphene surface.

[0116] B1) Drop liquid gallium metal onto one side of the graphene surface and place it on a heating plate to heat to 150°C. Then oxidize it for 10-20 minutes in an atmosphere with an oxygen flow rate of 10 L / min.

[0117] B2) A two-dimensional gallium oxide film is obtained by scraping gallium droplets over a silicon wafer, and then a trace amount of liquid gallium metal is cleaned with an ethanol solution at 90°C to initially obtain a gallium oxide nucleation layer 13 with a thickness of 10 nm on the surface of the graphene auxiliary layer 12.

[0118] Step C: α-Ga2O3 is epitaxially grown on the gallium oxide nucleation layer using MOCVD technology.

[0119] C1) The sample obtained in step B is placed into the reaction chamber of the MOCVD system, and argon is used as a carrier gas to carry oxygen at a flow rate of 150-170 sccm into the reaction chamber. The chamber temperature is controlled at 450-500℃, and the initially prepared gallium oxide nucleation layer is annealed for 5 min. Then, the pressure of the reaction chamber is set to 10-20 Torr, the chamber temperature is set to 550-600℃, and argon is used as a carrier gas to carry triethylgallium at a flow rate of 2-3 sccm into the reaction chamber to epitaxially grow an α-Ga2O3 thin film on the surface of the gallium oxide nucleation layer.

[0120] C2) After the α-Ga2O3 film grows to a thickness of 5 μm, the heating of the reaction chamber is stopped, and the temperature of the reaction chamber is controlled to drop to room temperature at a rate of less than 10 °C / min, so that an α-Ga2O3 epitaxial layer 14 can be formed on the gallium oxide nucleation layer 13 based on liquid metal.

[0121] Step D: Transfer the α-Ga2O3 epitaxial layer onto the β-Ga2O3 substrate to construct an α-Ga2O3 / β-Ga2O3 phase junction structure.

[0122] D1) Clean the 550μm thick β-Ga2O3 substrate for later use; specifically, use acetone and isopropanol for ultrasonic cleaning for 5 minutes each, then rinse with deionized water for 5 minutes, and dry with a nitrogen gun.

[0123] D2) Spin coat the α-Ga2O3 epitaxial layer prepared in step C with PPC adhesive using a spin coater. First, spin the sample at a speed of 2500 r / min for 10 seconds, and then spin the sample at a speed of 5000 r / min for 60 seconds. Then place it on a hot plate at 90°C for 60 seconds to cure. Then attach thermal release adhesive tape (TRT) to the PPC surface as a temporary support.

[0124] D3) Immerse the TRT / PPC / α-Ga2O3 / gallium oxide nucleation layer / graphene / silicon carbide substrate sample obtained in D2) into deionized water at room temperature, peel off one edge of TRT to promote rapid separation of graphene and silicon carbide substrate, and then transfer the entire sample with TRT support to the surface of β-Ga2O3 substrate.

[0125] D4) After heating the sample obtained in step D3) on a hot plate at 110°C for 10 seconds to peel off the TRT, immerse it in acetone at 60°C for 8 minutes to dissolve the PPC support layer. Then rinse the surface with anhydrous ethanol for 6 minutes to remove residual solvent, dry it with a nitrogen gun, and place it in a tube furnace with a vacuum of 10°C. -2 Torr, annealed at 400-450℃ for 10 min, enhances the bonding force between α-Ga2O3 and β-Ga2O3, resulting in an α-Ga2O3 / β-Ga2O3 phase structure from bottom to top consisting of a β-Ga2O3 substrate, a graphene-assisted transfer layer, a gallium oxide nucleation layer, and an α-Ga2O3 epitaxial layer.

[0126] Step E: Based on the obtained junction structure, fabricate a gallium oxide junction power diode.

[0127] Reference Figure 4 The specific implementation of this step is the same as step 5 in Example 1.

[0128] Reference Figure 3 and Figure 5 This invention provides three embodiments for fabricating vertical power transistors with gallium oxide junctions:

[0129] Each embodiment includes fabricating a junction and a transistor structure fabricated on the junction.

[0130] Example 4: Graphene was used as an auxiliary transfer layer. The gallium oxide nucleation layer based on liquid metal was grown by extrusion. α-Ga2O3 was epitaxially grown using MIST-CVD technology. PMMA adhesive was used to transfer α-Ga2O3 to a β-Ga2O3 substrate to prepare a gallium oxide vertical power transistor with an α-Ga2O3 / β-Ga2O3 junction.

[0131] Reference Figure 3 The process for preparing the α-Ga2O3 / β-Ga2O3 phase junction is as follows:

[0132] The first step is to transfer graphene onto a sapphire substrate to form an auxiliary transfer layer.

[0133] The implementation of this step is the same as step 1 in Example 1.

[0134] The second step involves using an extrusion method to initially prepare a uniform and continuous gallium oxide nucleation layer based on liquid metal on the graphene surface.

[0135] The implementation of this step is the same as step 2 in Example 1.

[0136] The third step involves using the MIST-CVD technique to epitaxially grow an α-Ga2O3 epitaxial structure layer on the gallium oxide nucleation layer.

[0137] (3.1) Dissolve gallium acetylacetonate Ga(acac)3 powder in deionized water and add 1-3% hydrochloric acid to prepare a gallium source solution of 0.02-0.05 mol / L, and put it into the atomization chamber for later use;

[0138] (3.2) Place the sample prepared in step 2 into the center of the reaction chamber of the MIST-CVD. Control the temperature of the reaction chamber to rise to 450-500℃ at a rate of 8-10℃ / min. Use nitrogen gas with a flow rate of 600-700 sccm as a carrier gas to carry oxygen gas with a flow rate of 40-50 sccm to the reaction chamber. Anneal the initially prepared gallium oxide nucleation layer for 5 min. Then raise the temperature of the reaction chamber to 550-600℃, turn on the atomization device, set the working frequency of the ultrasonic atomizer to 1-3MHz, atomize the prepared gallium source solution into micron-sized particles and introduce them into the reaction chamber to start the growth of the α-Ga2O3 epitaxial layer 24.

[0139] (3.3) After the α-Ga2O3 film thickness reaches 4 μm, magnesium sulfate heptahydrate MgSO4・7H2O with a concentration of 0.2 ~ 0.5 mmol / L is introduced into the reaction chamber to form a film with a thickness of 0.2 μm and a magnesium doping concentration of 3 × 10⁻⁶. 18 ~5×10 18 cm -3 α-Ga2O3 current blocking layer 26;

[0140] (3.4) Stop the introduction of magnesium sulfate heptahydrate, and introduce (3-cyanopropyl)dimethylchlorosilane at a concentration of 3-5 mmol / L into the reaction chamber to grow a thickness of 0.08 μm and a silicon doping concentration of 3 × 10⁻⁶. 19 ~5×10 19 cm -3 α-Ga2O3 thin film, as N + Source contact region 27; After growth is complete, stop heating the reaction chamber and control the temperature of the reaction chamber to drop to room temperature at a rate of less than 10℃ / min to complete the preparation of the α-Ga2O3 epitaxial structure layer.

[0141] The fourth step is to transfer the α-Ga2O3 epitaxial structure layer onto the β-Ga2O3 substrate to construct an α-Ga2O3 / β-Ga2O3 phase junction structure.

[0142] The implementation of this step is the same as step 4 in Example 1.

[0143] The fifth step involves fabricating a gallium oxide vertical power transistor based on the prepared α / β-Ga2O3 phase junction structure.

[0144] Reference Figure 5 The implementation of this step includes the following:

[0145] (5.1) A metal stack of 30 nm thick Ti and 200 nm thick Au was deposited on the back side of the sample by electron beam evaporation as the drain metal; then, an N-type metal was deposited on the back side of the sample. + Photoresist was spin-coated onto the surface of the source contact area and patterned by photolithography to define the source region. A metal stack with a thickness of 30nm Ti and 200nm Au was deposited by electron beam evaporation and patterned by a lift-off process to serve as the source contact metal. The sample was annealed for 1-3 minutes in a nitrogen atmosphere at an annealing temperature of 470-500℃ to achieve ohmic contact between the titanium / gold stack metal and gallium oxide, forming the drain 25 and the source 28.

[0146] (5.2) By photolithographic patterning, in N + The gate trench location is defined on the surface of the source contact region 27. The entire sample is then placed in an inductively coupled plasma system, and the gate trench is etched for 20-30 minutes using a BCl3 / Ar mixed etching gas to a depth of 0.3-0.5 μm. The sample is then placed in a piranha solution of H2SO4:H2O2=3:1 for 15 minutes to remove etching damage.

[0147] (5.3) The sample obtained in (5.2) above is placed in an atomic layer deposition chamber and a 100 nm thick Al2O3 layer is deposited at 250-300 °C as a gate dielectric layer; then a 100 nm thick nickel and 200 nm thick gold stacked metal is deposited by magnetron sputtering and patterned as a gate metal to complete the fabrication of the gallium oxide vertical power transistor.

[0148] In Example 5, boron nitride was used as an auxiliary transfer layer, and gallium oxide nucleation layer based on liquid metal was grown by transfer method using HVPE technology. α-Ga2O3 was epitaxially grown using PMMA adhesive, and the α-Ga2O3 was transferred to the β-Ga2O3 substrate to prepare a gallium oxide vertical power transistor with an α-Ga2O3 / βGa2O3 junction.

[0149] Reference Figure 3 Preparation of α-Ga2O3 / β-Ga2O3 phase junctions:

[0150] Step 1: Boron nitride is transferred onto a sapphire substrate to form an auxiliary transfer layer.

[0151] The implementation of this step is the same as step one in Example 2.

[0152] Step 2: A gallium oxide nucleation layer based on liquid metal is initially prepared on the boron nitride surface using a transfer method.

[0153] The implementation of this step is the same as step two in Example 2.

[0154] Step 3: Using HVPE technology, an α-Ga2O3 epitaxial structure layer is epitaxially grown on the initially prepared gallium oxide nucleation layer.

[0155] (3-1) Place the sample obtained in step 2 into the quartz tray of the HVPE system, and put the gallium metal into the precursor cavity. Set the temperature of the precursor cavity to 650-750℃ and the pressure of the cavity to 500-550 Torr. Then, use N2 to carry HCl gas with a flow rate of 10-30 sccm into the precursor cavity to form GaCl with the gallium metal.

[0156] (3-2) Then, O2 with a flow rate of 200-300 sccm is introduced into the reaction chamber of the HVPE system, and the chamber temperature is controlled at 450-500℃. The gallium oxide nucleation layer prepared based on liquid metal is annealed for 5 min. Then, N2 carrying GaCl is introduced into the reaction chamber of the HVPE system, and the chamber temperature is controlled at 550-600℃. An α-Ga2O3 thin film with a thickness of 5 μm is epitaxially grown on the surface of the gallium oxide nucleation layer 23 to form an α-Ga2O3 epitaxial layer 24.

[0157] (3-3) After the epitaxial layer 24 is grown, magnesium oxide is used as the magnesium source and placed in an independent heating source region. The temperature of the MgO source region is controlled at 550-600 ℃. HCl gas with a flow rate of 10 sccm is introduced into the magnesium oxide source region to react and generate MgCl2 doped precursor, which enters the cavity with the main gas path. A thickness of 0.4 μm is epitaxially grown in situ on the surface of epitaxial layer 24, with a magnesium doping concentration of 3×10⁻⁶. 18 ~5×10 18 cm -3 α-Ga2O3, as a current blocking layer 26;

[0158] (3-4) After completing the growth of the current blocking layer 26, stop the HCl gas supply to the magnesium source region and introduce silane SiH4 at a flow rate of 8-12 sccm into the reaction chamber to grow a thickness of 0.12 μm and a silicon doping concentration of 3 × 10⁻⁶. 19 ~5×10 19 cm -3 α-Ga2O3 thin film, as N +Source contact region 27; then stop heating the reaction chamber and control the temperature of the reaction chamber to drop to room temperature at a rate of less than 10℃ / min to complete the preparation of the α-Ga2O3 epitaxial structure layer.

[0159] Step 4: Transfer the α-Ga2O3 epitaxial layer onto the β-Ga2O3 substrate to construct the α-Ga2O3 / β-Ga2O3 phase junction structure.

[0160] The implementation of this step is the same as step four in Example 2.

[0161] Step 5: Based on the prepared α / β-Ga2O3 phase junction structure, a gallium oxide vertical power transistor is fabricated.

[0162] Reference Figure 5 The implementation of this step is the same as the fifth step in Example 4.

[0163] Example 6: Graphene was used as an auxiliary transfer layer. Based on liquid metal gallium oxide, α-Ga2O3 was epitaxially grown using MOCVD technology via a blade coating method. PPC adhesive was used to transfer α-Ga2O3 to a β-Ga2O3 substrate to prepare a gallium oxide vertical power transistor with an α-Ga2O3 / β-Ga2O3 junction.

[0164] Reference Figure 3 Preparation of α-Ga2O3 / β-Ga2O3 phase junctions:

[0165] Step A: Transfer graphene onto a silicon carbide substrate to form an auxiliary transfer layer.

[0166] The implementation of this step is the same as step A in Example 3.

[0167] Step B involves using a blade coating method to initially prepare a gallium oxide nucleation layer based on liquid metal on the graphene surface.

[0168] The implementation of this step is the same as step B in Example 3.

[0169] Step C involves using MOCVD technology to epitaxially grow an α-Ga2O3 epitaxial structure layer on the initially prepared gallium oxide nucleation layer.

[0170] (C.1) The sample obtained in step B is placed into the reaction chamber of the MOCVD system, and argon is used as the carrier gas to carry oxygen at a flow rate of 150-170 sccm into the reaction chamber. The chamber temperature is controlled at 450-500℃, and the gallium oxide nucleation layer prepared based on liquid metal is annealed for 5 min. Then, the pressure of the reaction chamber is set to 10-20 Torr, the chamber temperature is set to 550-600℃, and argon is used as the carrier gas to carry triethylgallium at a flow rate of 2-3 sccm into the reaction chamber. An α-Ga2O3 film with a thickness of 5 μm is epitaxially grown on the surface of the gallium oxide nucleation layer as the α-Ga2O3 epitaxial layer 24.

[0171] (C.2) After the epitaxial layer growth is completed, magnesium dicerocene with a molar flow rate of 100-110 nmol / min is introduced into the reaction chamber to form a 0.4 μm thick magnesium doping concentration of 3 × 10⁻⁶. 18 ~5×10 18 cm -3 α-Ga2O3 current blocking layer 26;

[0172] (C.3) Stop the magnesium pyrocene flow and introduce silane SiH4 at a flow rate of 8-12 sccm into the reaction chamber to grow a thickness of 0.12 μm with a silicon doping concentration of 3 × 10⁻⁶. 19 ~5×10 19 cm -3 α-Ga2O3 thin film, as N + Source contact region 27; then stop heating the reaction chamber and control the temperature of the reaction chamber to drop to room temperature at a rate of less than 10℃ / min to complete the preparation of the α-Ga2O3 epitaxial structure layer.

[0173] Step D: Transfer the α-Ga2O3 epitaxial layer onto the β-Ga2O3 substrate to construct the α-Ga2O3 / β-Ga2O3 phase junction structure.

[0174] The implementation of this step is the same as step D in Example 3.

[0175] Step E: Based on the prepared α / β-Ga2O3 phase junction structure, a gallium oxide vertical power transistor is fabricated.

[0176] The implementation of this step is the same as the fifth step in Example 4.

[0177] The above descriptions are merely six specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. For example, the preparation scheme of gallium oxide nucleation layer based on liquid metal also includes spin coating, gas injection, etc. The materials that can be selected for the organic support layer include rosin, PR adhesive, PI adhesive, etc. It also covers various thin films prepared based on liquid metal gallium oxide, as well as gallium oxide phase junction structures formed by transfer. For α-Ga2O3 growth substrates, it also includes silicon, α-Fe2O3, etc. The anode materials of diodes also include Ni / Pt, W / Au, etc. In vertical transistors, the doping element of the current blocking layer can also be replaced with nitrogen, and the gate metal can also be Ti / Ni, Ti / Pt / Au, etc. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A gallium oxide junction power diode, comprising: The substrate (11), the epitaxial layer (14), the cathode (15) located below the substrate (11) and the anode (16) located above the epitaxial layer (14) are characterized in that the substrate (11) is made of β-Ga2O3 material, the epitaxial layer (14) is made of α-Ga2O3 material, and an auxiliary transfer layer (12) and a gallium oxide nucleation layer (13) are provided between the β-Ga2O3 substrate and the α-Ga2O3 epitaxial layer, respectively used for the transfer and epitaxial growth of α-Ga2O3 to form an α-Ga2O3 and β-Ga2O3 phase junction structure.

2. The diode according to claim 1, characterized in that: The β-Ga2O3 substrate (11) has a thickness of 400-700 μm. The α-Ga2O3 epitaxial layer (14) has a thickness of 1-5 μm.

3. The diode according to claim 1, characterized in that: The auxiliary transfer layer (12) is made of graphene or boron nitride and has a thickness of 1-3 nm. The gallium oxide nucleation layer (13) has a thickness of 4-10 nm.

4. A vertical power transistor with a gallium oxide junction, comprising: Substrate (21), epitaxial layer (24), drain (25), current blocking layer (26), N + The source contact region (27), source electrode (28), gate dielectric layer (29), and gate metal (210) are characterized in that the substrate (21) is made of β-Ga2O3 material, the epitaxial layer (24) is made of α-Ga2O3 material, and an auxiliary transfer layer (22) and a gallium oxide nucleation layer (23) are provided between the β-Ga2O3 substrate and the α-Ga2O3 epitaxial layer, respectively used for the transfer and epitaxial growth of the α-Ga2O3 epitaxial layer to form an α-Ga2O3 and β-Ga2O3 phase junction structure.

5. The vertical power transistor according to claim 4, characterized in that: The β-Ga2O3 substrate (21) has a thickness of 400-700 μm. The α-Ga2O3 epitaxial layer (24) has a thickness of 1-5 μm.

6. The vertical power transistor according to claim 4, characterized in that: The drain (25) is located below the substrate (21); The current blocking layer (26) is located on both sides of the upper part of the epitaxial layer (24); The N + The source contact area (27) is located above the current blocking layer (26); The source (28) is located in N + Above the source contact area (27); The gate dielectric layer (29) is located above the epitaxial layer (24) and is situated between the two current blocking layers (26) and N. + Between the source contact region (27), and partially covered by the α-Ga2O3 epitaxial layer (24) and N + Source contact area (27) surface; The metal (210) is located inside the groove formed by the gate dielectric layer (29).

7. A method for fabricating a power diode with a gallium oxide junction, characterized in that, include: S1) The auxiliary transfer layer is transferred to the surface of a sapphire or silicon carbide substrate using a wet transfer technique and then subjected to low-temperature annealing to remove organic residues; S2) Using extrusion, transfer or scraping methods, with liquid gallium metal as a precursor, a gallium oxide nucleation layer is initially formed on the surface of the auxiliary transfer layer, and the residual liquid gallium metal is cleaned up. S3) The gallium oxide nucleation layer is first annealed in situ using hydride vapor phase epitaxy (HVPE), mist-CVD, or metal-organic vapor phase deposition (MOCVD) techniques, and then an α-Ga2O3 epitaxial structure layer is epitaxially grown on its surface. S4) Using the weak van der Waals forces of graphene or boron nitride, the α-Ga2O3 epitaxial structure layer grown on the gallium oxide nucleation layer is transferred to the β-Ga2O3 substrate by mechanical exfoliation. The interaction between α-Ga2O3 and β-Ga2O3 is enhanced by annealing to form an α-Ga2O3 / β-Ga2O3 phase junction structure with an auxiliary transfer layer and a gallium oxide nucleation layer between them. S5) A cathode electrode was prepared by vapor deposition of titanium and gold multilayer metal on the surface of a β-Ga2O3 substrate and rapid annealing. S6) Nickel and gold multilayer metals are deposited on the surface of the α-Ga2O3 epitaxial layer, and the anode electrode is obtained through a patterning process to complete the fabrication of the power diode.

8. The method according to claim 7, characterized in that: The wet transfer technology in S1) has the following process conditions: an organic transfer support layer is spin-coated onto commercially purchased multilayer graphene or boron nitride, and then placed on a hot plate for curing. The substrate is then removed by placing it in an etching solution, rinsed, transferred to the surface of a sapphire or silicon carbide substrate, and dried. The organic transfer support layer is then removed by an organic solution to complete the transfer of the auxiliary transfer layer. In step S2), the extrusion method, transfer method, or scraping method are used, and the process conditions are as follows: Extrusion method: Liquid gallium metal is dropped onto the surface of the auxiliary transfer layer, and the entire sample is placed on a hot plate at 100-150℃. A clean glass slide is pressed vertically onto the droplet with a force of 5-10N to allow the liquid gallium to spread fully. The sample is then placed in an oxygen environment to oxidize. Finally, trace amounts of liquid gallium metal are removed with ethanol to form a gallium oxide nucleation layer. Transfer method: Liquid gallium metal is dropped onto tape and then evenly coated onto PDMS. The PDMS loaded with gallium droplets is quickly attached to the surface of the auxiliary transfer layer. The entire sample is then placed on a hot plate at 70-90℃ and heated for 20-30 seconds. The PDMS is then vertically peeled off, placed in an oxygen-containing environment for oxidation, and the trace gallium droplets on its surface are removed with warm ethanol to form a gallium oxide nucleation layer. Scraping method: Liquid gallium metal is dropped onto the surface of the auxiliary transfer layer and heated to 130-150°C on a heating plate. The gallium drop is scraped over with a silicon wafer, placed in an oxygen environment for oxidation, and then a trace amount of liquid gallium metal is removed with ethanol to form a gallium oxide nucleation layer. In S3), the α-Ga2O3 epitaxial structure layer is an α-Ga2O3 epitaxial layer with a thickness of 1-5 μm.

9. The method according to claim 7, characterized in that, The mechanical stripping technique described in S4, and the transfer of the α-Ga2O3 epitaxial layer grown on the gallium oxide nucleation layer prepared with liquid gallium metal as a precursor to the β-Ga2O3 substrate, are implemented as follows: First, an organic transfer support layer is spin-coated onto the α-Ga2O3 epitaxial layer, and then a thermal release tape (TRT) is attached to the top of it as a temporary support. The entire sample was immersed in deionized water at room temperature. One edge of the TRT was lifted to facilitate the separation of the auxiliary transfer layer from the sapphire or silicon carbide substrate, and then transferred to the β-Ga2O3 substrate. The entire transferred sample was placed on a hot plate to peel off the TRT, then placed in an organic solution to dissolve the organic transfer support layer, and finally the organic residue was cleaned up.

10. A method for fabricating a gallium oxide-junction vertical power transistor, characterized in that, include: §1) The auxiliary transfer layer is transferred to the surface of a sapphire or silicon carbide substrate using a wet transfer technique and then subjected to low-temperature annealing to remove organic residues; §2) Using liquid gallium metal as a precursor, a preliminary gallium oxide nucleation layer is formed on the surface of the auxiliary transfer layer by extrusion, transfer or scraping methods, and residual liquid gallium metal is cleaned up. §3) The gallium oxide nucleation layer initially formed is subjected to in-situ annealing using hydride vapor phase epitaxy (HVPE), mist-CVD, or metal-organic vapor phase deposition (MOCVD) techniques, and then epitaxially grown to obtain an α-Ga2O3 epitaxial structure layer. §4) With the help of the weak van der Waals forces of the auxiliary transfer layer, the α-Ga2O3 epitaxial structure layer grown on the gallium oxide nucleation layer is transferred to the β-Ga2O3 substrate by mechanical lift-off technology. The interaction between α-Ga2O3 and β-Ga2O3 is enhanced by annealing to form an α-Ga2O3 / β-Ga2O3 phase junction structure with an auxiliary transfer layer and a gallium oxide nucleation layer between them. §5) Deposit titanium / gold multilayer metal as bottom drain electrode by electron beam evaporation, deposit titanium / gold multilayer metal and pattern it by lift-off process as source contact metal, and rapidly anneal in nitrogen atmosphere to form ohmic contact; §6) By photolithographic patterning, in N + The location of the gate trench is defined on the surface of the source contact region, and the gate trench is etched in an inductively coupled plasma system. The etching damage is then removed in a piranha solution. The sample is then sent into an atomic layer deposition chamber for gate dielectric deposition. A nickel / gold multilayer metal is deposited by magnetron sputtering and patterned as the gate metal to complete the fabrication of the vertical power transistor.

11. The method according to claim 10, characterized in that: The α-Ga2O3 epitaxial structure layer in §3) comprises, from bottom to top: an α-Ga2O3 epitaxial layer (24) with a thickness of 1-5 μm, and a magnesium doping concentration of 3 × 10⁻⁶ μm. 18 ~5×10 18 cm -3 The α-Ga₂O₃ current blocking layer (26) has a thickness of 0.05-0.15 μm and a silicon doping concentration of 3 × 10⁻⁶. 19 ~5×10 19 cm -3 N + Source contact area (27).

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