Semiconductor device structure and method of fabricating the same

Abstract

This application relates to a semiconductor device structure and its fabrication method. The semiconductor device structure includes: a substrate of a first conductivity type; a drift region including pillars of a first conductivity type and pillars of a second conductivity type; the pillars of the second conductivity type and the pillars of the first conductivity type are alternately arranged in a direction parallel to the surface of the substrate; a carrier storage layer of the first conductivity type is located on the side of the drift region away from the substrate; a plurality of spaced-apart first gate trench structures penetrate the carrier storage layer along the thickness direction and extend into the pillars of the second conductivity type; and a first injection region of the second conductivity type is located within the carrier storage layer and between adjacent first gate trench structures extending into the same pillar of the second conductivity type. This application can hinder the outflow of holes when the semiconductor device structure is turned on, thereby reducing turn-on losses and turn-off losses; it can also reduce the electric field distortion between the first gate trench structures, thereby reducing EMI oscillations and ensuring the withstand voltage reliability of the semiconductor device structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device structure and its fabrication method. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) are characterized by high input impedance, low on-state voltage drop, fast switching speed, and low losses. They are often used in high-voltage, high-current applications, such as new energy, transportation, power grids, and industry. These applications often require devices with excellent performance, such as high withstand voltage, low switching losses, and fast switching.

[0003] With the advancement of end-application technologies, increasingly stringent requirements are being placed on IGBT devices, which are core components. These requirements include extremely low switching losses, fast switching capabilities combined with extremely low EMI (Electromagnetic Interference) oscillations, and high voltage withstand stability. However, existing IGBTs have a trade-off between turn-on and turn-off losses, making it difficult to reduce them simultaneously and thus failing to meet these increasingly stringent requirements. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device structure and its fabrication method to address the technical problems mentioned above in the background art.

[0005] In a first aspect, this application provides a semiconductor device structure, the semiconductor device structure comprising:

[0006] Substrate of the first conductivity type;

[0007] The drift region, located on one side of the front side of the substrate, includes: a first conductivity type pillar and a second conductivity type pillar; the second conductivity type pillar and the first conductivity type pillar are alternately arranged in a direction parallel to the surface of the substrate;

[0008] A carrier storage layer of the first conductivity type is located on the side of the drift region away from the substrate;

[0009] Multiple spaced-apart first gate trench structures penetrate the carrier storage layer along the thickness direction and extend into the second conductivity type pillar;

[0010] The first injection region of the second conductivity type is located within the carrier storage layer and between adjacent first gate trench structures extending into the same second conductivity type pillar.

[0011] In the aforementioned semiconductor device structure, by forming a carrier storage layer of the first conductivity type on the side of the drift region away from the substrate, the outflow of holes can be hindered when the semiconductor device structure is turned on, reducing turn-on losses. The first gate trench structure extends into the second conductivity type pillar, which can cover the bottom of the first gate trench structure, thus both hindering hole outflow and solving the failure problem caused by electric field concentration in the bottom region of the first gate trench structure. By forming a first injection region of the second conductivity type in the carrier storage layer of the first conductivity type between adjacent first gate trench structures extending into the same second conductivity type pillar, the first injection region... The carrier storage layer can form a first conductivity type-second conductivity type-first conductivity type structure (e.g., NPN structure). When a positive voltage is applied to the first gate trench structure, the second conductivity type can be depleted, preventing carriers from flowing out. When the first gate trench structure is turned off, this effect is not present, and it can act as a carrier extraction mechanism. This reduces both turn-on and turn-off losses. In addition, since there is a first injection region of the second conductivity type between adjacent first gate trench structures extending into the same second conductivity type pillar, the electric field distortion between the first gate trench structures is reduced, EMI oscillation is lowered, and the withstand voltage reliability of the semiconductor device structure can be guaranteed.

[0012] In some embodiments, the first gate trench structure includes:

[0013] The first gate trench penetrates the carrier storage layer along the thickness direction and extends into the second conductivity type pillar;

[0014] A first gate oxide layer covers the sidewalls and bottom of the first gate trench; the thickness of the first gate oxide layer covering the bottom of the first gate trench is greater than the thickness of the first gate oxide layer covering the sidewalls of the first gate trench.

[0015] The first gate is located within the first gate trench.

[0016] In the first gate trench structure, the thickness of the first gate oxide layer covering the bottom of the first gate trench is greater than the thickness of the first gate oxide layer covering the sidewall of the first gate trench, which reduces the Miller capacitance and increases the switching speed.

[0017] In some embodiments, the semiconductor device structure further includes:

[0018] The second gate trench structure includes a second gate trench, a second gate oxide layer, and a second gate; the second gate trench penetrates the carrier storage layer along the thickness direction and extends into the first conductivity type pillar; the second gate oxide layer covers the sidewalls and bottom of the second gate trench, and the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer covering the bottom of the first gate trench; the second gate is located within the second gate trench.

[0019] An emitter trench structure includes: an emitter trench, a third gate oxide layer, and an emitter; the emitter trench penetrates the carrier storage layer along its thickness direction and extends into the first conductivity type pillar; the third gate oxide layer covers the sidewalls and bottom of the emitter trench, and the thickness of the third gate oxide layer is less than the thickness of the first gate oxide layer covering the bottom of the first gate trench; the emitter is located within the emitter trench.

[0020] In some embodiments, the semiconductor device structure further includes:

[0021] The dielectric layer is located on the side of the carrier storage layer away from the drift region;

[0022] The body region of the second conductivity type is located within the carrier storage layer and on opposite sides of the second gate trench structure;

[0023] The active region of the first conductivity type is located within the body region and between the second gate trench structure and the first gate trench structure;

[0024] The first contact hole is located between the second gate trench structure and the first gate trench structure, penetrates the dielectric layer and the active region along the thickness direction, and extends into the body region;

[0025] The second injection region of the second conductivity type is located within the body region and at the bottom of the first contact hole;

[0026] The second contact hole is located between adjacent first gate trench structures extending into the same second conductivity type pillar, penetrates the dielectric layer in the thickness direction, and extends into the carrier storage layer; the first injection region is located at the bottom of the second contact hole;

[0027] The third contact hole penetrates the dielectric layer along the thickness direction, exposing the second gate.

[0028] In some embodiments, the doping dose of the second conductivity type ions in the first implanted region is less than the doping dose of the second conductivity type ions in the second implanted region.

[0029] In some embodiments, the semiconductor device structure further includes:

[0030] Emitter metal extends from the first contact hole and the second contact hole to the side of the dielectric layer away from the carrier storage layer;

[0031] The gate metal extends from the third contact hole to the side of the dielectric layer away from the carrier storage layer and is spaced from the emitter metal.

[0032] The collector is located on the back side of the substrate;

[0033] The collector metal is located on the side of the collector away from the substrate.

[0034] Secondly, this application also provides a method for fabricating a semiconductor device structure, the method comprising:

[0035] Provide a substrate of the first conductivity type;

[0036] A drift region is formed on one side of the front side of the substrate of the first conductivity type. The drift region includes a first conductivity type pillar and a second conductivity type pillar. The second conductivity type pillar and the first conductivity type pillar are arranged alternately in a direction parallel to the surface of the substrate.

[0037] A carrier storage layer of a first conductivity type is formed on the side of the drift region away from the substrate;

[0038] Multiple first gate trench structures are formed at intervals, the first gate trench structures penetrate the carrier storage layer along the thickness direction and extend into the second conductivity type pillar;

[0039] A first injection region of a second conductivity type is formed within the carrier storage layer, the first injection region being located between adjacent first gate trench structures extending into the same second conductivity type pillar.

[0040] In the above-described method for fabricating a semiconductor device structure, by forming a carrier storage layer of a first conductivity type on the side of the drift region away from the substrate, the outflow of holes can be hindered when the semiconductor device structure is turned on, reducing turn-on losses. The multiple spaced-apart first gate trench structures extend into the second conductivity type pillars, which can cover the bottom of the first gate trench structures, thus both hindering hole outflow and solving the failure problem caused by electric field concentration at the bottom of the first gate trench structures. Furthermore, by forming a first conductivity type carrier storage layer of the second conductivity type between adjacent first gate trench structures extending into the same second conductivity type pillar, the first conductivity type of the second conductivity type can be further enhanced. The injection region, the first injection region, and the carrier storage layer can form a first conductivity type-second conductivity type-first conductivity type structure (e.g., an NPN structure). When a positive voltage is applied to the first gate trench structure, the second conductivity type can be depleted, preventing carriers from flowing out. When the first gate trench structure is turned off, this effect is not present, and it can serve to extract carriers. This reduces both turn-on and turn-off losses. In addition, since there is a first injection region of the second conductivity type between adjacent first gate trench structures extending into the same second conductivity type pillar, the electric field distortion between the first gate trench structures is reduced, EMI oscillation is reduced, and the withstand voltage reliability of the semiconductor device structure can be guaranteed.

[0041] In some embodiments, forming a drift region on the front side of the substrate of the first conductivity type includes:

[0042] An initial drift region is formed on one side of the substrate of the first conductivity type;

[0043] A second type of conductive pillar trench is formed in the initial drift region; a first type of conductive pillar is formed in the initial drift region between the second type of conductive pillar trenches; the first type of conductive pillar and the second type of conductive pillar trench are alternately arranged in a direction parallel to the surface of the substrate.

[0044] The second conductivity type pillar is formed by filling the trench of the second conductivity type pillar with a second conductivity type doped material.

[0045] In some embodiments, the formation of a plurality of spaced-apart first gate trench structures includes:

[0046] A first gate trench is formed, which penetrates the carrier storage layer along the thickness direction and extends into the second conductivity type pillar;

[0047] Forming a first gate oxide layer within the first gate trench includes: forming a first sub-gate oxide layer within the first gate trench; depositing a gate oxide material layer within the first gate trench; and etching back to remove a portion of the gate oxide material layer to obtain a second sub-gate oxide layer located at the bottom of the first gate trench, wherein the second sub-gate oxide layer and the first sub-gate oxide layer together constitute the first gate oxide layer; the thickness of the first gate oxide layer covering the bottom of the first gate trench is greater than the thickness of the first gate oxide layer covering the sidewalls of the first gate trench.

[0048] A first gate is formed within the first gate trench.

[0049] In the formed first gate trench structure, the thickness of the first gate oxide layer covering the bottom of the first gate trench is greater than the thickness of the first gate oxide layer covering the sidewall of the first gate trench, which reduces Miller capacitance and increases switching speed.

[0050] In some embodiments, while forming the first gate trench structure, a second gate trench structure and an emitter trench structure are also formed, including:

[0051] While forming the first gate trench, a second gate trench and an emitter trench are also formed; the second gate trench penetrates the carrier storage layer along the thickness direction and extends into the first conductivity type pillar; the emitter trench penetrates the carrier storage layer along the thickness direction and extends into the first conductivity type pillar.

[0052] While forming a first sub-gate oxide layer in the first gate trench, a second gate oxide layer is also formed in the second gate trench, and a third gate oxide layer is formed in the emitter trench; the second gate oxide layer covers the sidewalls and bottom of the second gate trench, and the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer covering the bottom of the first gate trench; the third gate oxide layer covers the sidewalls and bottom of the emitter trench, and the thickness of the third gate oxide layer is less than the thickness of the first gate oxide layer covering the bottom of the first gate trench;

[0053] While forming a first gate in the first gate trench, a second gate is also formed in the second gate trench, and an emitter is formed in the emitter trench.

[0054] In some embodiments, after forming the first gate trench structure, the second gate trench structure, and the emitter trench structure, and before forming the first injection region of the second conductivity type within the carrier storage layer, the method further includes:

[0055] A body region of a second conductivity type is formed within the carrier storage layer, the body region being located on opposite sides of the second gate trench structure;

[0056] An active region of a first conductivity type is formed within the body region, the active region being located between the second gate trench structure and the first gate trench structure;

[0057] A dielectric layer is formed on the side of the carrier storage layer away from the drift region;

[0058] A first contact hole and a third contact hole are formed; the first contact hole is located between the second gate trench structure and the first gate trench structure, penetrates the dielectric layer and the active region along the thickness direction, and extends into the body region; the third contact hole penetrates the dielectric layer along the thickness direction and exposes the second gate.

[0059] Based on the first contact hole, ion implantation of a second conductivity type is performed in the body region to form a second implantation region of the second conductivity type at the bottom of the first contact hole;

[0060] A second contact hole is formed between adjacent first gate trench structures extending into the same second conductivity type pillar, penetrating the dielectric layer in the thickness direction, and extending into the carrier storage layer; the first implantation region is formed by second conductivity type ion implantation in the carrier storage layer via the second contact hole.

[0061] In some embodiments, after forming a first injection region of a second conductivity type within the carrier storage layer, the method further includes:

[0062] An emitter metal and a gate metal are formed; the emitter metal extends from the first contact hole and the second contact hole to the side of the dielectric layer away from the carrier storage layer; the gate metal extends from the third contact hole to the side of the dielectric layer away from the carrier storage layer and has a gap with the emitter metal;

[0063] The back side of the substrate is thinned.

[0064] Ion implantation of a second conductivity type is performed on the back side of the self-thinned substrate to form a collector electrode;

[0065] A collector metal is formed on the side of the collector electrode away from the substrate. Attached Figure Description

[0066] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.

[0067] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device structure provided in one embodiment of this application;

[0068] Figure 2 This is a flowchart of a method for fabricating a semiconductor device structure provided in another embodiment of this application;

[0069] Figure 3 This is a schematic cross-sectional view of a substrate of the first conductivity type provided in the method for fabricating a semiconductor device structure according to another embodiment of this application;

[0070] Figure 4 This is a schematic cross-sectional view of the structure obtained after forming the initial drift region in the fabrication method of the semiconductor device structure provided in another embodiment of this application;

[0071] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming the drift region in the fabrication method of the semiconductor device structure provided in another embodiment of this application.

[0072] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming a carrier storage layer in a method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0073] Figure 7 This is a schematic cross-sectional view of the structure obtained after forming the first gate trench, the second gate trench, and the emitter trench in the method for fabricating the semiconductor device structure provided in another embodiment of this application.

[0074] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming the first gate oxide layer, the second gate oxide layer and the third gate oxide layer in the fabrication method of the semiconductor device structure provided in another embodiment of this application;

[0075] Figure 9 This is a schematic cross-sectional view of the structure obtained after forming the first gate, the second gate, and the emitter in a method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0076] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming the bulk region in the fabrication method of the semiconductor device structure provided in another embodiment of this application.

[0077] Figure 11 This is a schematic cross-sectional view of the structure obtained after forming the active region in the fabrication method of the semiconductor device structure provided in another embodiment of this application.

[0078] Figure 12This is a schematic cross-sectional view of the structure obtained after forming a dielectric layer, a first contact hole, and a second implantation region in a method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0079] Figure 13 This is a schematic cross-sectional view of the structure obtained after forming the second contact hole and the first injection region in a method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0080] Figure 14 This is a schematic cross-sectional view of the structure obtained after forming the emitter metal in the method for fabricating a semiconductor device structure provided in another embodiment of this application.

[0081] Figure 15 This is a schematic cross-sectional view of the structure obtained after forming the collector electrode in the fabrication method of the semiconductor device structure provided in another embodiment of this application.

[0082] Explanation of reference numerals in the attached figures:

[0083] 10. Substrate; 11. Initial drift region; 111. First conductivity type pillar; 112. Second conductivity type pillar; 12. Carrier storage layer; 13. First gate trench structure; 131. First gate trench; 132. First gate oxide layer; 133. First gate; 14. First injection region; 15. Second gate trench structure; 151. Second gate trench; 152. Second gate oxide layer; 153. Second gate; 16. Dielectric layer; 17. Body region; 18. Active region; 19. First contact hole; 20. Second contact hole; 21. Emitter metal; 22. Collector; 23. Collector metal. Detailed Implementation

[0084] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0086] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0087] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0088] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0089] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures). Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of the application.

[0090] In one embodiment, see Figure 1 This application provides a semiconductor device structure, which may include: a substrate 10 of a first conductivity type; a drift region located on the front side of the substrate 10, the drift region may include: a first conductivity type pillar 111 and a second conductivity type pillar 112; the second conductivity type pillar 112 and the first conductivity type pillar 111 may be alternately arranged in a direction parallel to the surface of the substrate 10; a first conductivity type carrier storage layer 12, the carrier storage layer 12 may be located on the side of the drift region away from the substrate 10; a plurality of spaced first gate trench structures 13, the first gate trench structures 13 penetrating the carrier storage layer 12 along the thickness direction and extending into the second conductivity type pillar 112; and a second conductivity type first injection region 14, the first injection region 14 located in the carrier storage layer 12 and between adjacent first gate trench structures 13 extending into the same second conductivity type pillar 112.

[0091] In the aforementioned semiconductor device structure, by forming a carrier stored layer (CS) 12 of a first conductivity type on the side of the drift region away from the substrate 10, the outflow of holes can be hindered when the semiconductor device structure is turned on, reducing turn-on losses. The first gate trench structure 13 extends into the second conductivity type pillar 112, and the second conductivity type pillar 112 can cover the bottom of the first gate trench structure 13, which can both hinder the outflow of holes and solve the failure problem caused by electric field concentration in the bottom region of the first gate trench structure 13. By forming a first injection region 14 of a second conductivity type in the carrier stored layer 12 between adjacent first gate trench structures 13 extending into the same second conductivity type pillar 112, the first injection region 14 and the carrier stored layer 12 can form a... The first conductivity type-second conductivity type-first conductivity type structure (e.g., NPN structure) can deplete the second conductivity type when a positive voltage is applied to the first gate trench structure 13, preventing carrier outflow. This effect is not present when the first gate trench structure 13 is turned off, and it can extract carriers. This reduces both turn-on and turn-off losses. In addition, since there is a first injection region 14 of the second conductivity type between adjacent first gate trench structures 13 extending into the same second conductivity type pillar 112, the electric field distortion between the first gate trench structures 13 is reduced, EMI oscillation is reduced, and the withstand voltage reliability of the semiconductor device structure can be guaranteed.

[0092] As an example, the first conductivity type can be N-type and the second conductivity type can be P-type; alternatively, the first conductivity type can be P-type and the second conductivity type can be N-type. Specifically, P-type ions can include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions. N-type impurity ions can include, but are not limited to, one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0093] In this embodiment, the substrate 10 of the first conductivity type can be an N-type substrate; it can be constructed from semiconductor materials, conductor materials, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Specifically, in this embodiment, the substrate 10 of the first conductivity type can be a single-crystal silicon wafer with a high concentration of N-type ion doping (as a field stop, FS).

[0094] As an example, the first conductivity type pillar 111 in the drift region can be an epitaxial layer retained after the formation of the second conductivity type pillar trench in the epitaxial layer formed by the epitaxial process. The second conductivity type pillar 112 in the drift can be formed by filling the second conductivity type pillar trench with a second conductivity type material after the formation of the second conductivity type pillar trench in the epitaxial layer. Specifically, the epitaxial layer can be an N-type doped silicon layer; the second conductivity type material can be a P-type doped silicon.

[0095] As an example, the doping concentration of the first conductivity type ions in the carrier storage layer 12 is higher than the doping concentration of the first conductivity type ions in the drift region (i.e., the ion doping concentration in the first conductivity type pillar 111). Specifically, the doping concentration of the first conductivity type ions in the carrier storage layer 12 is at least one order of magnitude higher than the doping concentration of the first conductivity type ions in the drift region.

[0096] As an example, please continue reading Figure 1 The first gate trench structure 13 may include: a first gate trench 131, a first gate oxide layer 132, and a first gate 133; wherein, the first gate trench 131 penetrates the carrier storage layer 12 along the thickness direction and extends into the second conductivity type pillar 112; the first gate oxide layer 132 covers the sidewalls and bottom of the first gate trench 131; the thickness of the first gate oxide layer 132 covering the bottom of the first gate trench 131 is greater than the thickness of the first gate oxide layer 132 covering the sidewalls of the first gate trench 131; the first gate 133 is located within the first gate trench 131.

[0097] Specifically, the longitudinal cross-sectional shape of the first gate trench 131 can be set according to actual needs; in this embodiment, the longitudinal cross-sectional shape of the first gate trench 131 can be as follows: Figure 1 The U-shape shown.

[0098] As an example, the orthographic projection of the first gate trench 131 onto the surface of the drift region away from the substrate 10 is located within the second conductivity type pillar 112.

[0099] As an example, the first gate oxide layer 132 may be located between the first gate 133 and the first gate trench 131; the first gate oxide layer 132 may include a silicon oxide layer.

[0100] As an example, the thickness of the first gate oxide layer 132 covering the bottom of the first gate trench 131 can be 5 to 20 times the thickness of the first gate oxide layer 132 covering the sidewalls of the first gate trench 131. For instance, the thickness of the first gate oxide layer 132 covering the bottom of the first gate trench 131 can be 5, 10, 15, or 20 times the thickness of the first gate oxide layer 132 covering the sidewalls of the first gate trench 131, etc. Of course, in other examples, the thickness of the first gate oxide layer 132 covering the bottom of the first gate trench 131 can be 1, 2, 3, or 4 times the thickness of the first gate oxide layer 132 covering the sidewalls of the first gate trench 131, etc.

[0101] In the first gate trench structure 13, by setting the thickness of the first gate oxide layer 132 covering the bottom of the first gate trench 131 to be greater than the thickness of the first gate oxide layer 132 covering the sidewall of the first gate trench 131, the Miller capacitance is reduced and the switching speed is increased.

[0102] As an example, the first gate 133 may include, but is not limited to, doped polysilicon, such as N-type doped polysilicon, etc.

[0103] As an example, there can be multiple first gate trench structures 13, and these multiple first gate trench structures 13 can be arranged at intervals; the specific number of first gate trench structures 13 can be set according to actual needs.

[0104] As an example, adjacent first gate trench structures 13 extending into the same second conductivity type post 112 may have a first spacing, the first spacing being less than the width of the second conductivity type post 112.

[0105] As an example, please continue reading Figure 1The semiconductor device structure may further include: a second gate trench structure 15 and an emitter trench structure (not shown); wherein, the second gate trench structure 15 may include a second gate trench 151, a second gate oxide layer 152 and a second gate 153; the second gate trench 151 penetrates the carrier storage layer 12 along the thickness direction and extends into the first conductivity type pillar 111; the second gate oxide layer 152 covers the sidewalls and bottom of the second gate trench 151, and the thickness of the second gate oxide layer 152 is less than the thickness of the first gate oxide layer 132 covering the bottom of the first gate trench 131; the second gate 153 is located in the second gate trench 151. The emitter trench structure may include: an emitter trench (not shown), a third gate oxide layer (not shown), and an emitter (not shown); the emitter trench penetrates the carrier storage layer 12 along the thickness direction and extends into the first conductivity type pillar 111; the third gate oxide layer covers the sidewalls and bottom of the emitter trench, and the thickness of the third gate oxide layer is less than the thickness of the first gate oxide layer 132 covering the bottom of the first gate trench 131; the emitter is located in the emitter trench.

[0106] As an example, the thickness of the second gate oxide layer 152 and the thickness of the third gate oxide layer can be the same as the thickness of the first gate oxide layer 132 covering the sidewall of the first gate trench 131.

[0107] As an example, the shape of the second gate trench 151 and the shape of the emitter trench can be the same as the shape of the first gate trench 131; the depths of the first gate trench 131, the second gate trench 151, and the emitter trench can be the same or different. The depths of the first gate trench 131, the second gate trench 151, and the emitter trench can be set according to actual needs. In this embodiment, the depths of the first gate trench 131, the second gate trench 151, and the emitter trench can all be 4μm to 6μm, for example, the depths of the first gate trench 131, the second gate trench 151, and the emitter trench can all be 4μm, 5μm, or 6μm, etc.

[0108] As an example, both the second gate oxide layer 152 and the third gate oxide layer can be silicon oxide layers formed by thermal oxidation. The second gate electrode 153 and the emitter can both be doped polysilicon layers, such as N-type doped polysilicon, etc.

[0109] As an example, the second gate trench structure 15 may have a second spacing with the adjacent first gate trench structure 13, the second spacing being greater than the first spacing and less than the width of the first conductivity type pillar 111.

[0110] In the above-described semiconductor device structure, adjacent first gate trench structures 13 extending into the same second conductivity type pillar 112 may have a first spacing, which is smaller than the second spacing between the second gate trench structure 15 and the adjacent first gate trench structure 13. This can further enhance the depletion effect of the first gate trench structure 13 when the device is turned on, and further improve the switching speed.

[0111] As an example, the number of the second gate trench structure 15 and the emitter trench structure can both be multiple.

[0112] As an example, the semiconductor device structure may further include: a dielectric layer 16, a body region 17 of a second conductivity type, an active region 18 of a first conductivity type, a first contact hole 19, a second injection region (not shown) of a second conductivity type, a second contact hole 20, and a third contact hole (not shown). The dielectric layer 16 is located on the side of the carrier storage layer 12 away from the drift region; the dielectric layer 16 may include, but is not limited to, a silicon dioxide layer. The body region 17 is located within the carrier storage layer 12 and on opposite sides of the second gate trench structure 15; the depth of the body region 17 is less than the thickness of the carrier storage layer 12. It should be noted that there is no body region 17 between the first gate trench structures 13. The active region 18 is located within the body region 17 and between the second gate trench structure 15 and the first gate trench structure 13; the depth of the active region 18 is less than the depth of the body region 17. Figure 1 As shown, one end of the active region 18 is adjacent to the second gate trench structure 15, and the other end of the active region 18 is spaced from the first gate trench structure 13. The first contact hole 19 is located between the second gate trench structure 15 and the first gate trench structure 13, penetrates the dielectric layer 16 and the active region 18 along the thickness direction, and extends into the body region 17 (near the silicon surface, at 10...). -7 The depth of the first contact hole 19 is on the order of magnitude, i.e., a few tenths of a micrometer, for example, the depth of the first contact hole 19 can be 0.2μm to 0.6μm; in this example, the depth of the first contact hole 19 can be 0.4μm). The second injection region is located within the body region 17 and at the bottom of the first contact hole 19, i.e., the second injection region is located within the body region 17 below the first contact hole 19; specifically, the second injection region can prevent latch-up during application. The second contact hole 20 is located between adjacent first gate trench structures 13 extending into the same second conductivity type pillar 112, penetrating the dielectric layer 16 along the thickness direction, and extending into the carrier storage layer 12; the first injection region 14 is located at the bottom of the second contact hole 20, i.e., the first injection region 14 is located within the carrier storage layer 12 below the second contact hole 20. The third contact hole penetrates the dielectric layer 16 along the thickness direction, exposing the second gate 153.

[0113] As an example, the doping dose of the second conductivity type ions in the first implantation region 14 is lower than the doping dose of the second conductivity type ions in the second implantation region. Specifically, the doping dose of the second conductivity type ions in the first implantation region 14 is two orders of magnitude lower than the doping dose of the second conductivity type ions in the second implantation region.

[0114] As an example, the semiconductor device structure may further include: an emitter metal 21, a gate metal (not shown), a collector 22, and a collector metal 23. The emitter metal 21 extends from the first contact hole 19 and the second contact hole 20 to the side of the dielectric layer 16 away from the carrier storage layer 12; the gate metal extends from the third contact hole to the side of the dielectric layer 16 away from the carrier storage layer 12, and is spaced from the emitter metal 21; the collector 22 is located on the back side of the substrate 10; and the collector metal 23 is located on the side of the collector 22 away from the substrate 10.

[0115] As an example, the materials of the emitter metal 21 and the gate metal can be the same; the material of the collector metal 23 can be the same as the materials of the emitter metal 21 and the gate metal.

[0116] As an example, the collector 22 can be a doped region of a second conductivity type, specifically formed by implanting ions of a second conductivity type from the back side of the substrate 10. The collector 22 can be a transparent collector region.

[0117] In another embodiment, please refer to Figure 2 This application also provides a method for fabricating a semiconductor device structure, which may include the following steps: S100~S110.

[0118] S100: Provides a substrate of the first conductivity type.

[0119] S101: A drift region is formed on one side of the front side of the substrate of the first conductivity type. The drift region includes first conductivity type pillars and second conductivity type pillars. The second conductivity type pillars and the first conductivity type pillars are arranged alternately in a direction parallel to the surface of the substrate.

[0120] S102: A carrier storage layer of the first conductivity type is formed on the side of the drift region away from the substrate.

[0121] S103: Form a plurality of spaced first gate trench structures, the first gate trench structures penetrate the carrier storage layer along the thickness direction and extend into the second conductivity type pillar.

[0122] S110: A first injection region of a second conductivity type is formed in the carrier storage layer, the first injection region being located between adjacent first gate trench structures extending into the same second conductivity type pillar.

[0123] In the above-described method for fabricating a semiconductor device structure, by forming a carrier storage layer of a first conductivity type on the side of the drift region away from the substrate, the outflow of holes can be hindered when the semiconductor device structure is turned on, reducing turn-on losses. The multiple spaced-apart first gate trench structures extend into the second conductivity type pillars, which can cover the bottom of the first gate trench structures, thus both hindering hole outflow and solving the failure problem caused by electric field concentration at the bottom of the first gate trench structures. Furthermore, by forming a first conductivity type carrier storage layer of the second conductivity type between adjacent first gate trench structures extending into the same second conductivity type pillar, the first conductivity type of the second conductivity type can be further enhanced. The injection region, the first injection region, and the carrier storage layer can form a first conductivity type-second conductivity type-first conductivity type structure (e.g., an NPN structure). When a positive voltage is applied to the first gate trench structure, the second conductivity type can be depleted, preventing carriers from flowing out. When the first gate trench structure is turned off, this effect is not present, and it can serve to extract carriers. This reduces both turn-on and turn-off losses. In addition, since there is a first injection region of the second conductivity type between adjacent first gate trench structures extending into the same second conductivity type pillar, the electric field distortion between the first gate trench structures is reduced, EMI oscillation is reduced, and the withstand voltage reliability of the semiconductor device structure can be guaranteed.

[0124] As an example, the first conductivity type can be N-type and the second conductivity type can be P-type; or the first conductivity type can be P-type and the second conductivity type can be N-type.

[0125] For example, please refer to Figure 3 In step S100, the first conductivity type substrate 10 provided can be an N-type substrate; specifically, the first conductivity type substrate 10 can be a single-crystal silicon wafer with high concentration of N-type ion doping (as a field stop, FS).

[0126] As an example, in step S101, forming a drift region on the front side of the substrate 10 of the first conductivity type may include the following steps:

[0127] S1011: An initial drift region 11 is formed on one side of the substrate 10 of the first conductivity type, such as... Figure 4 As shown. Specifically, the initial drift region 11 can be grown using an epitaxial process, and the initial drift region 11 can be a region of the first conductivity type. The thickness of the initial drift region 11 can be greater than the thickness of the substrate 10; specifically, the thickness of the initial drift region 11 can be 1.5 times, 2 times, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times, 10 times or more than the thickness of the substrate 10.

[0128] S1012: A second conductivity type pillar trench (not shown) is formed within the initial drift region 11; a first conductivity type pillar 111 is formed between the second conductivity type pillar trenches in the initial drift region 11, and the first conductivity type pillar 111 and the second conductivity type pillar trench are alternately arranged in a direction parallel to the surface of the substrate 10. Specifically, a first patterned mask layer (not shown) can be formed first on the side of the initial drift region 11 away from the substrate 10, and the first patterned mask layer defines the shape and position of the second conductivity type pillar trench; then, the initial drift region 11 is etched based on the first patterned mask layer, specifically by, but not limited to, dry etching, to form the second conductivity type pillar trench. The second conductivity type pillar trench can penetrate the initial drift region 11 along the thickness direction. After the second conductivity type pillar trench is formed, the remaining initial drift region 11 forms the first conductivity type pillar 111.

[0129] S1013: Fill the trench of the second conductivity type pillar with a second conductivity type doped material to form the second conductivity type pillar 112, such as... Figure 5 As shown. Specifically, the second conductivity type doped material can be backfilled first. At this time, the second conductivity type doped material not only fills the second conductivity type pillar trench, but also covers the surface of the first patterned mask layer away from the initial drift region 11. Then, the second conductivity type pillar trench and the first patterned mask layer outside the second conductivity type pillar trench are removed, and the second conductivity type doped material remaining in the second conductivity type pillar trench forms the second conductivity type pillar 112.

[0130] Specifically, the second conductivity type doped material may include, but is not limited to, second conductivity type doped silicon.

[0131] Specifically, in step S1013, chemical mechanical polishing can be used, but is not limited to, to remove the second conductive type pillar trench and the first patterned mask layer, in addition to the second conductive type pillar trench.

[0132] As an example, in step S102, an epitaxial process can be used to form a carrier storage layer 12 of the first conductivity type on the side of the drift region away from the substrate 10, such as... Figure 6 As shown.

[0133] Specifically, the doping concentration of the first conductivity type ions in the charge carrier storage layer 12 can be higher than the doping concentration of the first conductivity type ions in the first conductivity type pillar; more specifically, the doping concentration of the first conductivity type ions in the charge carrier storage layer 12 can be at least one order of magnitude higher than the doping concentration of the first conductivity type ions in the first conductivity type pillar.

[0134] As an example, the thickness of the carrier storage layer 12 can be less than the thickness of the drift region and greater than the thickness of the substrate 10.

[0135] As an example, step S103 may include the following steps: S1031~S1033.

[0136] S1031: A first gate trench 131 is formed, which penetrates the carrier storage layer 12 along the thickness direction and extends into the second conductivity type pillar 112, such as... Figure 7 As shown. Specifically, a second patterned mask layer (not shown) can be formed first on the side of the carrier storage layer 12 away from the drift region. The second patterned mask layer at least defines the position and shape of the first gate trench 131. Then, based on the second patterned mask layer, a dry etching process is used to etch the carrier storage layer 12 and the second conductivity type pillar 112. Finally, a polishing or etching process can be used to remove the second patterned mask layer. Specifically, the depth of the first gate trench 131 can be set according to actual needs. In this embodiment, the depth of the first gate trench 131 can be 4μm to 6μm, for example, the depth of the first gate trench 131 can be 4μm, 5μm, or 6μm, etc.

[0137] S1032: A first gate oxide layer 132 is formed within the first gate trench 131, such as Figure 8 As shown, forming a first gate oxide layer 132 within a first gate trench 131 may include the following: forming a first sub-gate oxide layer (not shown) within the first gate trench 131; depositing a gate oxide material layer (not shown) within the first gate trench 131, the gate oxide material layer filling the first gate trench 131; etching back to remove part of the gate oxide material layer to obtain a second sub-gate oxide layer (not shown) located at the bottom of the first gate trench 131, the second sub-gate oxide layer and the first sub-gate oxide layer together constituting the first gate oxide layer 132; the thickness of the first gate oxide layer 132 covering the bottom of the first gate trench 131 is greater than the thickness of the first gate oxide layer 132 covering the sidewalls of the first gate trench 131.

[0138] S1033: A first gate 133 is formed within the first gate trench 131, such as Figure 9 As shown, forming a first gate 133 within a first gate trench 131 may include the following: First, a first gate material layer (not shown) may be formed using a deposition process, but not limited to, a first gate material layer. The material of the first gate material layer may include, but is not limited to, polysilicon of a first doped type. The first gate material layer fills the first gate trench 131 and covers the surface of the carrier storage layer 12 away from the drift region. Then, the first gate material layer covering the surface of the carrier storage layer 12 away from the drift region is removed, and the first gate material layer remaining in the first gate trench 131 is the first gate 133, which fills the first gate trench 131. A first gate oxide layer 132 is located between the first gate 133 and the first gate trench 131.

[0139] As an example, please continue reading Figures 7 to 9 In step S103, while forming the first gate trench structure 13, a second gate trench structure 15 and an emitter trench structure (not shown) are also formed.

[0140] As an example, please continue reading Figure 7 Simultaneously with forming the first gate trench 131, a second gate trench 151 and an emitter trench (not shown) are also formed. The second gate trench 151 penetrates the carrier storage layer 12 along the thickness direction and extends into the first conductivity type pillar 111. The emitter trench penetrates the carrier storage layer 12 along the thickness direction and extends into the first conductivity type pillar 111. The second gate trench 151 and the emitter trench are formed synchronously with the first gate trench 131 using the same process.

[0141] It should be noted that after forming the first gate trench 131, the second gate trench 151, and the emitter trench, the following steps may be included: forming a sacrificial oxide layer in the first gate trench 131, the second gate trench 151, and the emitter trench through a thermal oxidation process; removing the sacrificial oxide layer, specifically, but not limited to, a wet etching process. Through the above-described process of forming and removing the sacrificial oxide layer, defects introduced by dry etching in the first gate trench 131, the second gate trench 151, and the emitter trench can be removed.

[0142] As an example, please continue reading Figure 8 While forming a first sub-gate oxide layer in the first gate trench 131, a second gate oxide layer 152 is also formed in the second gate trench 151, and a third gate oxide layer (not shown) is formed in the emitter trench. The second gate oxide layer 152 covers the sidewalls and bottom of the second gate trench 151, and its thickness is less than the thickness of the first gate oxide layer 132 covering the bottom of the first gate trench 131. The third gate oxide layer covers the sidewalls and bottom of the emitter trench, and its thickness is less than the thickness of the first gate oxide layer 132 covering the bottom of the first gate trench 131. The second gate oxide layer 152 and the third gate oxide layer are formed synchronously with the first sub-gate oxide layer using the same process, and the materials of the second gate oxide layer 152 and the third gate oxide layer are the same as those of the first sub-gate oxide layer.

[0143] As an example, please continue reading Figure 9 While forming the first gate 133 in the first gate trench 131, a second gate 153 is also formed in the second gate trench 151, and an emitter (not shown) is formed in the emitter trench. The second gate 153 and the emitter are formed synchronously with the first gate 133 based on the same process, and the second gate 153 and the emitter are made of the same material as the first gate 133.

[0144] As an example, after the formation of the first gate trench structure 13, the second gate trench structure 15 and the emitter trench structure, and before the formation of the first injection region 14 of the second conductivity type in the carrier storage layer 12, that is, between step S103 and step S110, the following steps may also be included: S104~S109.

[0145] S104: A body region 17 of a second conductivity type is formed within the carrier storage layer 12. The body region 17 is located on opposite sides of the second gate trench structure 15, such as... Figure 10 As shown. Specifically, a protective layer (not shown) and a photoresist layer (not shown) can be formed on the surface of the carrier storage layer 12 away from the drift region. Ion implantation of the carrier storage layer 12 with a second conductivity type is performed using a mask to form a body region 17 within the carrier storage layer 12. The thickness of the body region 17 is less than the thickness of the carrier storage layer 12, i.e., there is a gap between the bottom of the body region 17 and the bottom of the carrier storage layer 12. It should be noted that no body region 17 is formed within the carrier storage layer 12 between the first gate trench structures 13; that is, the mask used in this step allows the region between the first gate trench structures 13 to be avoided during ion implantation.

[0146] S105: An active region 18 of a first conductivity type is formed within the body region 17. The active region 18 is located between the second gate trench structure 15 and the first gate trench structure 13. Figure 11 As shown. Specifically, selective ion implantation can be performed on the body region 17 using a mask to form the active region 18. Specifically, the active region 18 can be in contact with the second gate trench structure 15, but has a gap between it and the first gate trench structure 13.

[0147] S106: A dielectric layer 16 is formed on the side of the carrier storage layer 12 away from the drift region, such as... Figure 12 As shown. Specifically, a dielectric layer 16 can be formed on the side of the carrier storage layer 12 away from the drift region using a deposition process, but not limited to this one. The material of the dielectric layer 16 can include, but is not limited to, a silicon dioxide layer. The thickness of the dielectric layer 16 can be very thin, much thinner than the thickness of the carrier storage layer 12.

[0148] S107: Please continue reading Figure 12 This forms a first contact hole 19 and a third contact hole (not shown); the first contact hole 19 is located between the second gate trench structure 15 and the first gate trench structure 13, penetrates the dielectric layer 16 and the active region 18 along the thickness direction, and extends into the body region 17 (near the silicon surface, at 10... -7The depth of the first contact hole 19 is on the order of magnitude, i.e., a few tenths of a micrometer, for example, the depth of the first contact hole 19 can be 0.2 μm to 0.6 μm; in this example, the depth of the first contact hole 19 can be 0.4 μm). The third contact hole penetrates the dielectric layer 16 along the thickness direction, exposing the second gate 153. Specifically, the first contact hole 19 and the third contact hole can be formed using photolithography and dry etching processes. The shapes of the first contact hole 19 and the third contact hole can be the same or different. The depths of the first contact hole 19 and the third contact hole can be the same or different.

[0149] S108: Ion implantation of a second conductivity type is performed within the body region 17 based on the first contact hole 19 to form a second implantation region (not shown) of the second conductivity type at the bottom of the first contact hole 19; the doping concentration of the second conductivity type ions in the second implantation region is greater than the doping concentration of the second conductivity type ions in the first implantation region. The second implantation region can prevent latch-up during application.

[0150] S109: Form a second contact hole 20. The second contact hole 20 is located between adjacent first gate trench structures 13 extending into the same second conductivity type pillar 112, penetrates the dielectric layer 16 along the thickness direction, and extends into the carrier storage layer 12, such as... Figure 13 As shown. Specifically, the second contact hole 20 can be formed using photolithography etching; the shape and depth of the second contact hole 20 can be set according to actual needs; in this embodiment, the depth of the second contact hole 20 can be greater than the depth of the first contact hole 19.

[0151] As an example, in step S110, please refer to... Figure 13 Ions of a second conductivity type can be implanted into the carrier storage layer 12 via the second contact hole 20 to form the first implantation region 14.

[0152] As an example, the concentration of second conductivity type ions in the first injection region 14 is significantly lower than the concentration of second conductivity type ions in the second injection region; specifically, the concentration of second conductivity type ions in the first injection region 14 is at least two orders of magnitude lower than the concentration of second conductivity type ions in the second injection region.

[0153] As an example, the depth of the first injection region 14 can be set according to actual needs. In this embodiment, along the thickness direction of the carrier storage layer 12 (i.e., perpendicular to the surface of the carrier storage layer 12 away from the drift region), the first injection region 14 can be located in the middle of the carrier storage layer 12. Specifically, the distance from the center of the first injection region 14 to the surface of the carrier storage layer 12 away from the drift region is the same as the distance from the center of the first injection region 14 to the surface of the carrier storage layer 12 adjacent to the drift region. With the above design, when a positive voltage is applied to the first gate trench structure 13, the second conductivity type can be depleted at the fastest speed, preventing carrier outflow.

[0154] As an example, after forming the first injection region 14 of the second conductivity type in the carrier storage layer 12, that is, after step S110, the following steps may also be included: S111~S114.

[0155] S111: Forming emitter metal 21 and gate metal (not shown); emitter metal 21 extends from the first contact hole 19 and the second contact hole 20 to the side of dielectric layer 16 away from carrier storage layer 12; gate metal extends from the third contact hole to the side of dielectric layer 16 away from carrier storage layer 12, and has a gap with emitter metal, such as... Figure 14 As shown. Specifically, the emitter metal 21 and gate metal can be formed using electroplating or other deposition processes. The emitter metal 21 fills the first contact hole 19 and the second contact hole 20, and extends to the side of the dielectric layer 16 away from the carrier storage layer 12. The gate metal fills the third contact hole and extends to the side of the dielectric layer 16 away from the carrier storage layer 12. More specifically, a metal material layer can be formed in the first contact hole 19, the second contact hole 20, the third contact hole, and on the surface of the dielectric layer 16 away from the carrier storage layer 12 using electroplating or other deposition processes. The metal material layer is then photolithographically etched to form the emitter metal 21 and the gate metal.

[0156] S112: Thinning process is performed on the back side of substrate 10. Specifically, a thinning process can be used to thin the back side of substrate 10. The thinning process can include, but is not limited to, polishing process (e.g., chemical mechanical polishing, i.e., CMP) or etching process.

[0157] S113: Ion implantation of a second conductivity type is performed on the back side of the self-thinned substrate 10 to form a collector 22, such as... Figure 15 As shown. Specifically, ion implantation can be performed on the entire back side of the thinned substrate 10. It should be noted that after ion implantation, the resulting structure can also be subjected to rapid laser annealing, which forms the collector 22. Any existing rapid laser annealing process can be used to perform rapid laser annealing on the structure obtained after ion implantation in this step.

[0158] S114: A collector metal 23 is formed on the side of the collector 22 away from the substrate 10, such as... Figure 1 As shown. Specifically, electroplating or other deposition processes can be used to form the current collector metal 23.

[0159] Unless otherwise expressly stated herein, the execution order of these steps in the semiconductor device structure fabrication method of the above embodiments is not strictly limited, and these steps can be executed in other orders. Moreover, at least some steps in the method may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0160] The methods for fabricating the semiconductor device structures in the above embodiments are intended to illustrate the formation principle of the semiconductor device structures in this application and are not intended to limit the specific semiconductor device structures in this application. Other fabrication methods can also be used to fabricate the semiconductor device structures in this application.

[0161] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0162] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0163] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0164] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor device structure, characterized in that, include: Substrate of the first conductivity type; The drift region, located on one side of the front side of the substrate, includes: a first conductivity type pillar and a second conductivity type pillar; the second conductivity type pillar and the first conductivity type pillar are alternately arranged in a direction parallel to the surface of the substrate; A carrier storage layer of the first conductivity type is located on the side of the drift region away from the substrate; Multiple spaced-apart first gate trench structures penetrate the carrier storage layer along the thickness direction and extend into the second conductivity type pillar; The first injection region of the second conductivity type is located within the carrier storage layer and between adjacent first gate trench structures extending into the same second conductivity type pillar.

2. The semiconductor device structure according to claim 1, characterized in that, The first gate trench structure includes: The first gate trench penetrates the carrier storage layer along the thickness direction and extends into the second conductivity type pillar; A first gate oxide layer covers the sidewalls and bottom of the first gate trench; the thickness of the first gate oxide layer covering the bottom of the first gate trench is greater than the thickness of the first gate oxide layer covering the sidewalls of the first gate trench. The first gate is located within the first gate trench.

3. The semiconductor device structure according to claim 2, characterized in that, Also includes: The second gate trench structure includes a second gate trench, a second gate oxide layer, and a second gate; the second gate trench penetrates the carrier storage layer along the thickness direction and extends into the first conductivity type pillar; the second gate oxide layer covers the sidewalls and bottom of the second gate trench, and the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer covering the bottom of the first gate trench; the second gate is located within the second gate trench. An emitter trench structure includes: an emitter trench, a third gate oxide layer, and an emitter; the emitter trench penetrates the carrier storage layer along its thickness direction and extends into the first conductivity type pillar; the third gate oxide layer covers the sidewalls and bottom of the emitter trench, and the thickness of the third gate oxide layer is less than the thickness of the first gate oxide layer covering the bottom of the first gate trench; the emitter is located within the emitter trench.

4. The semiconductor device structure according to claim 3, characterized in that, Also includes: The dielectric layer is located on the side of the carrier storage layer away from the drift region; The body region of the second conductivity type is located within the carrier storage layer and on opposite sides of the second gate trench structure; The active region of the first conductivity type is located within the body region and between the second gate trench structure and the first gate trench structure; The first contact hole is located between the second gate trench structure and the first gate trench structure, penetrates the dielectric layer and the active region along the thickness direction, and extends into the body region; The second injection region of the second conductivity type is located within the body region and at the bottom of the first contact hole; The second contact hole is located between adjacent first gate trench structures extending into the same second conductivity type pillar, penetrates the dielectric layer in the thickness direction, and extends into the carrier storage layer; the first injection region is located at the bottom of the second contact hole; The third contact hole penetrates the dielectric layer along the thickness direction, exposing the second gate.

5. The semiconductor device structure according to claim 4, characterized in that, The doping dose of the second conductivity type ions in the first implantation region is less than the doping dose of the second conductivity type ions in the second implantation region.

6. The semiconductor device structure according to claim 4, characterized in that, Also includes: Emitter metal extends from the first contact hole and the second contact hole to the side of the dielectric layer away from the carrier storage layer; The gate metal extends from the third contact hole to the side of the dielectric layer away from the carrier storage layer and is spaced from the emitter metal. The collector is located on the back side of the substrate; The collector metal is located on the side of the collector away from the substrate.

7. A method for fabricating a semiconductor device structure, characterized in that, include: Provide a substrate of the first conductivity type; A drift region is formed on one side of the front side of the substrate of the first conductivity type. The drift region includes a first conductivity type pillar and a second conductivity type pillar. The second conductivity type pillar and the first conductivity type pillar are arranged alternately in a direction parallel to the surface of the substrate. A carrier storage layer of a first conductivity type is formed on the side of the drift region away from the substrate; Multiple first gate trench structures are formed at intervals, the first gate trench structures penetrate the carrier storage layer along the thickness direction and extend into the second conductivity type pillar; A first injection region of a second conductivity type is formed within the carrier storage layer, the first injection region being located between adjacent first gate trench structures extending into the same second conductivity type pillar.

8. The method for fabricating a semiconductor device structure according to claim 7, characterized in that, The formation of a drift region on one side of the front side of the substrate of the first conductivity type includes: An initial drift region is formed on one side of the substrate of the first conductivity type; A second type of conductive pillar trench is formed in the initial drift region; a first type of conductive pillar is formed in the initial drift region between the second type of conductive pillar trenches; the first type of conductive pillar and the second type of conductive pillar trench are alternately arranged in a direction parallel to the surface of the substrate. The second conductivity type pillar is formed by filling the trench of the second conductivity type pillar with a second conductivity type doped material.

9. The method for fabricating a semiconductor device structure according to claim 7, characterized in that, The formation of a plurality of spaced-apart first gate trench structures includes: A first gate trench is formed, which penetrates the carrier storage layer along the thickness direction and extends into the second conductivity type pillar; Forming a first gate oxide layer within the first gate trench includes: forming a first sub-gate oxide layer within the first gate trench; depositing a gate oxide material layer within the first gate trench; and etching back to remove a portion of the gate oxide material layer to obtain a second sub-gate oxide layer located at the bottom of the first gate trench, wherein the second sub-gate oxide layer and the first sub-gate oxide layer together constitute the first gate oxide layer; the thickness of the first gate oxide layer covering the bottom of the first gate trench is greater than the thickness of the first gate oxide layer covering the sidewalls of the first gate trench. A first gate is formed within the first gate trench.

10. The method for fabricating a semiconductor device structure according to claim 9, characterized in that, While forming the first gate trench structure, a second gate trench structure and an emitter trench structure are also formed, including: While forming the first gate trench, a second gate trench and an emitter trench are also formed; the second gate trench penetrates the carrier storage layer along the thickness direction and extends into the first conductivity type pillar; the emitter trench penetrates the carrier storage layer along the thickness direction and extends into the first conductivity type pillar. While forming a first sub-gate oxide layer in the first gate trench, a second gate oxide layer is also formed in the second gate trench, and a third gate oxide layer is formed in the emitter trench; the second gate oxide layer covers the sidewalls and bottom of the second gate trench, and the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer covering the bottom of the first gate trench; the third gate oxide layer covers the sidewalls and bottom of the emitter trench, and the thickness of the third gate oxide layer is less than the thickness of the first gate oxide layer covering the bottom of the first gate trench; While forming a first gate in the first gate trench, a second gate is also formed in the second gate trench, and an emitter is formed in the emitter trench.

11. The method for fabricating a semiconductor device structure according to claim 10, characterized in that, After forming the first gate trench structure, the second gate trench structure, and the emitter trench structure, and before forming the first injection region of the second conductivity type within the carrier storage layer, the method further includes: A body region of a second conductivity type is formed within the carrier storage layer, the body region being located on opposite sides of the second gate trench structure; An active region of a first conductivity type is formed within the body region, the active region being located between the second gate trench structure and the first gate trench structure; A dielectric layer is formed on the side of the carrier storage layer away from the drift region; A first contact hole and a third contact hole are formed; the first contact hole is located between the second gate trench structure and the first gate trench structure, penetrates the dielectric layer and the active region along the thickness direction, and extends into the body region; the third contact hole penetrates the dielectric layer along the thickness direction and exposes the second gate. Based on the first contact hole, ion implantation of a second conductivity type is performed in the body region to form a second implantation region of the second conductivity type at the bottom of the first contact hole; A second contact hole is formed between adjacent first gate trench structures extending into the same second conductivity type pillar, penetrating the dielectric layer in the thickness direction, and extending into the carrier storage layer; the first implantation region is formed by second conductivity type ion implantation in the carrier storage layer via the second contact hole.

12. The method for fabricating a semiconductor device structure according to claim 11, characterized in that, After forming a first injection region of the second conductivity type within the carrier storage layer, the method further includes: An emitter metal and a gate metal are formed; the emitter metal extends from the first contact hole and the second contact hole to the side of the dielectric layer away from the carrier storage layer; the gate metal extends from the third contact hole to the side of the dielectric layer away from the carrier storage layer and has a gap with the emitter metal; The back side of the substrate is thinned. Ion implantation of a second conductivity type is performed on the back side of the self-thinned substrate to form a collector electrode; A collector metal is formed on the side of the collector electrode away from the substrate.

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