Semiconductor device, method of manufacturing the same, and layout structure

Abstract

This invention provides a semiconductor device, its manufacturing method, and layout structure. A shielded gate trench transistor and a trench Schottky diode are formed in a semiconductor substrate. The trench Schottky diode's blocking effect on minority carriers reduces the overall reverse bias extraction of minority carriers in the semiconductor device, thereby reducing parameters characterizing reverse recovery performance, such as reverse charge (Qrr) and reverse current (Irr). Simultaneously, self-aligned ion implantation can be used to form the well and source regions of the shielded gate trench transistor, avoiding increased manufacturing costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device, its manufacturing method, and its layout structure. Background Technology

[0002] Since the introduction of the Shielded Gate Trench (SGT) transistor, it has rapidly captured the low- and medium-voltage power device market due to its advantages such as low specific on-resistance, low Miller capacitance, low power loss, small parasitic capacitance, high switching speed, and good high-frequency characteristics. With the continuous expansion of SGT transistor applications, especially when used as a switch in various complex switching power supply circuit environments, the reverse recovery performance of the device itself becomes particularly important. When the parasitic freewheeling diode in the SGT transistor transitions from the on-state to the off-state, the current does not immediately reset to zero. Instead, a reverse current (Irr) is generated due to minority carriers, and then gradually recovers to zero. The presence of the parasitic freewheeling diode causes current overshoot during the transition from the off-state to the on-state, which is the sum of the transistor's on-current and the parasitic freewheeling diode's reverse current (Irr), resulting in significant switching losses. This reverse current not only affects the transistor's switching efficiency but also generates unnecessary switching power consumption, limiting the application of SGT transistors to some extent. Therefore, those skilled in the art have been working to improve the reverse recovery performance of transistors. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device, its manufacturing method and layout structure to improve the reverse recovery performance of shielded gate trench transistors.

[0004] Therefore, the present invention provides a semiconductor device, the semiconductor device comprising:

[0005] Semiconductor substrate;

[0006] A shielded gate trench transistor group located in the semiconductor substrate, the shielded gate trench transistor group comprising two shielded gate trench transistors, each shielded gate trench transistor including a source region; and,

[0007] A trench Schottky diode located in the semiconductor substrate of the shielded gate trench transistor group, the trench Schottky diode including a trench gate electrode and a Schottky contact structure located on the side of the trench gate electrode;

[0008] The Schottky contact structure, the trench gate electrode, and the source region are equipotentially connected.

[0009] Optionally, in the semiconductor device, the shielded gate trench transistor includes:

[0010] The first trench is located in the semiconductor substrate;

[0011] The first trench dielectric layer located in the first trench;

[0012] A shielding gate electrode located in the first trench and on the dielectric layer of the first trench;

[0013] An inter-gate dielectric layer located in the first trench and covering the shielding gate electrode;

[0014] The control gate electrode is located in the first trench and on the inter-gate dielectric layer; and,

[0015] The well region and the source region are located in the semiconductor substrate on the side of the first trench.

[0016] Optionally, in the semiconductor device, the first trench dielectric layer includes a stacked first oxide layer, a nitride layer, and a second oxide layer, wherein the second oxide layer covers the nitride layer, and the nitride layer covers a portion of the first oxide layer and exposes the first oxide layer located at the opening of the first trench.

[0017] Optionally, in the semiconductor device, the trench-type Schottky diode includes:

[0018] A second trench group located in the semiconductor substrate, the second trench group comprising two second trenches;

[0019] A trench gate structure located in the second trench, the trench gate structure including a second trench dielectric layer and the trench gate electrode located on the second trench dielectric layer; and,

[0020] The Schottky contact structure located on the surface of the semiconductor substrate in the second trench group.

[0021] Optionally, in the semiconductor device, the surface of the Schottky contact structure is lower than the surface of the trench gate electrode, or flush with the surface of the trench gate electrode.

[0022] Optionally, in the semiconductor device, the second trench dielectric layer includes a stacked first oxide layer, a nitride layer, and a second oxide layer, wherein the second oxide layer covers the nitride layer, and the nitride layer covers the first oxide layer.

[0023] Optionally, in the semiconductor device, the semiconductor structure further includes a metal layer that connects the Schottky contact structure, the trench gate electrode, and the source region.

[0024] The present invention also provides a method for manufacturing a semiconductor device, the method comprising:

[0025] Provide semiconductor substrates; and,

[0026] A shielded gate trench transistor group and a trench Schottky diode are formed in the semiconductor substrate; the shielded gate trench transistor group includes two shielded gate trench transistors, each shielded gate trench transistor including a source region; the trench Schottky diode is located in the semiconductor substrate within the shielded gate trench transistor group, and the trench Schottky diode includes a trench gate electrode and a Schottky contact structure located on the side of the trench gate electrode;

[0027] The Schottky contact structure, the trench gate electrode, and the source region are equipotentially connected.

[0028] Optionally, in the method for manufacturing the semiconductor device, forming a shielded gate trench transistor group and a trench Schottky diode in the semiconductor substrate includes:

[0029] A first trench group and a second trench group are formed in the semiconductor substrate. The first trench group includes two first trenches, and the second trench group includes two second trenches. The second trench group is located in the semiconductor substrate within the first trench group.

[0030] A dielectric material layer is formed, the dielectric material layer covering the first trench, the second trench and the surface of the semiconductor substrate, so as to form a second trench dielectric layer in the second trench;

[0031] A polycrystalline silicon material layer is filled in the first trench and the second trench to form a trench gate electrode in the second trench;

[0032] A patterned masking layer is formed, which covers the second trench group and the semiconductor substrate located in the second trench group, and exposes the first trench group;

[0033] The polysilicon material layer in the first trench is etched to form a shielding gate electrode in the first trench;

[0034] An inter-gate dielectric layer covering the shielding gate electrode and a control gate electrode located on the inter-gate dielectric layer are formed in the first trench;

[0035] A well region and a source region are formed in the semiconductor substrate on the first trench side by means of an ion implantation process;

[0036] Remove the graphical masking layer;

[0037] An interlayer dielectric layer is formed on the semiconductor substrate, and a first opening, a second opening, and a third opening are formed in the interlayer dielectric layer. The first opening penetrates the interlayer dielectric layer and extends into the well region; the second opening penetrates the interlayer dielectric layer and extends into the semiconductor substrate in the second trench group; and the third opening penetrates the interlayer dielectric layer and extends into the trench gate electrode.

[0038] A metal layer is formed on the interlayer dielectric layer, the metal layer extending to cover the surfaces of the first opening, the second opening and the third opening, the metal layer forming a Schottky contact structure on the surface of the semiconductor substrate in the second trench group and connecting the Schottky contact structure, the trench gate electrode and the source region.

[0039] Optionally, in the semiconductor device manufacturing method, the first opening, the second opening, and the third opening are each independent, and the surface of the Schottky contact structure is lower than the surface of the trench gate electrode.

[0040] Optionally, in the semiconductor device manufacturing method, the first opening is independent of the second opening and the third opening, the second opening and the third opening are connected, and the surface of the Schottky contact structure is flush with the surface of the trench gate electrode.

[0041] Optionally, in the semiconductor device manufacturing method, the dielectric material layer includes a stacked first oxide layer, a nitride layer, and a second oxide layer. After etching the polysilicon material layer in the first trench to form a shielded gate electrode in the first trench, forming a shielded gate trench transistor group and a trench Schottky diode in the semiconductor substrate further includes:

[0042] A portion of the second oxide layer and a portion of the nitride layer in the first trench are etched to expose the first oxide layer located at the opening of the first trench, and a first trench dielectric layer is formed in the first trench.

[0043] The present invention also provides a layout structure, the layout structure comprising:

[0044] A first mask structure is used to form a first trench group and a second trench group;

[0045] A second mask structure, the second mask structure being used to form a masking layer; and...

[0046] A third mask structure is used to form a first opening, a second opening, and a third opening.

[0047] Optionally, in the layout structure, the first opening is independent of the second opening and the third opening, and the second opening is independent of the third opening or connected to the third opening.

[0048] In the semiconductor device, its manufacturing method, and layout structure provided by this invention, a shielded-gate trench transistor group and a trench Schottky diode are formed in a semiconductor substrate. The shielded-gate trench transistor group includes two shielded-gate trench transistors. The trench Schottky diode is located in the semiconductor substrate within the shielded-gate trench transistor group. The Schottky contact structure, trench gate electrode, and source region of the trench Schottky diode are equipotentially connected. When the trench Schottky diode is turned on, it only allows majority carriers to flow, which largely suppresses minority carrier injection, thus exhibiting superior fast recovery characteristics. By integrating the trench Schottky diode and the shielded-gate trench transistor together, the blocking effect of the trench Schottky diode on minority carriers reduces the overall reverse bias extraction of minority carriers in the semiconductor device, thereby reducing parameters characterizing reverse recovery performance, such as reverse charge (Qrr) and reverse current (Irr). When the shielded gate trench transistor is turned off, the Schottky contact structure and the source region are at a high potential, the trench Schottky diode is turned on and majority carriers are injected, the minority carriers are suppressed in the shielded gate trench transistor, and the overall reverse recovery capability of the semiconductor device is improved. Attached Figure Description

[0049] Figures 1 to 10 This is a cross-sectional schematic diagram of the structure formed by the manufacturing method of the semiconductor device according to the embodiments of the present invention.

[0050] Figure 11 This is a schematic diagram comparing the conduction curves of the parasitic diodes of the trench Schottky diode and the shielded gate trench transistor according to an embodiment of the present invention.

[0051] Figure 12 This is a schematic diagram comparing the reverse recovery curves of the semiconductor device according to an embodiment of the present invention and the existing shielded gate trench transistor.

[0052] Figure 13 This is a partial schematic diagram of the layout structure of an embodiment of the present invention.

[0053] Figure 14 It is to utilize Figure 13 The schematic diagram of the semiconductor device formed by the layout structure shown is shown, and its corresponding Figure 13 The position of AA' in the diagram.

[0054] Figure 15 It is to utilize Figure 13The schematic diagram of the semiconductor device formed by the layout structure shown is shown, and its corresponding Figure 13 The position of BB' in the middle.

[0055] The reference numerals in the attached figures are explained as follows:

[0056] 1, 1' - Semiconductor device; 10, 10' - Semiconductor substrate; 20S - Shielded gate trench transistor group; 20 - Shielded gate trench transistor; 21 - Shielded gate electrode; 22 - Inter-gate dielectric layer; 23 - First trench dielectric layer; 24, 24' - Control gate electrode; 25, 25' - Well region; 26, 26' - Source region; 40 - Trench Schottky diode; 41 - Second trench dielectric layer; 42, 42' - Trench gate electrode; 43 - Trench gate structure; 44, 44' - Schottky contact structure.

[0057] 100 - Silicon substrate; 101 - Silicon epitaxial layer; 110S, 110S' - First trench group; 110 - First trench; 111S, 111S' - Second trench group; 111, 111' - Second trench; 120 - Dielectric material layer; 121 - First oxide layer; 122 - Nitride layer; 123 - Second oxide layer; 130 - Polycrystalline silicon material layer; 140 - Patterned masking layer; 141 - Patterned photoresist layer; 150 - Interlayer dielectric layer; 151, 151' - First opening; 152, 152' - Second opening; 160, 160' - Metal layer.

[0058] 200, 210, 300, 310 - curves.

[0059] 400 - Layout structure; 410 - First mask structure; 411 - First pattern; 420 - Second mask structure; 421 - Second pattern; 430 - Third mask structure; 431 - Third pattern. Detailed Implementation

[0060] The reverse recovery performance of a transistor is directly related to minority carrier injection during parasitic diode conduction. Therefore, to optimize the reverse recovery performance of a device, it is necessary to reduce the degree of minority carrier injection during parasitic diode conduction. Schottky contact structures are widely used in fast recovery diode devices. This structure allows only majority carriers to flow during conduction, largely suppressing minority carrier injection and enabling the device to exhibit fast recovery characteristics. However, due to factors such as image forces, Schottky diodes have a large reverse leakage current. Therefore, the trench MOS barrier Schottky diode (TMBS) was further proposed. In forward conduction, the trench Schottky diode isolates minority carrier flow through the Schottky contact structure; in reverse bias, it achieves a two-dimensional charge coupling effect through the trench gate structure, changing the electric field distribution in the drift region. This shifts the maximum electric field strength in the drift region from the Schottky contact structure interface to the corner of the trench dielectric layer inside the drift region, effectively weakening the effective barrier height reduction effect caused by the image charge of the Schottky contact structure, thus significantly reducing reverse leakage current. The electric field in the drift region changes from a one-dimensional linear distribution to a non-linear distribution, which can obtain a higher blocking voltage and thus have better fast recovery characteristics.

[0061] Therefore, in the semiconductor device, its manufacturing method, and layout structure provided by this invention, a shielded gate trench transistor group and a trench Schottky diode are formed in the semiconductor substrate. The shielded gate trench transistor group includes two shielded gate trench transistors, and the trench Schottky diode is located in the semiconductor substrate within the shielded gate trench transistor group. The Schottky contact structure, trench gate electrode, and source region of the trench Schottky diode are equipotentially connected. When the trench Schottky diode is turned on, it only allows majority carriers to flow, which largely suppresses minority carrier injection, thus exhibiting superior fast recovery characteristics. By integrating the trench Schottky diode and the shielded gate trench transistor together, the blocking effect of the trench Schottky diode on minority carriers reduces the overall reverse bias extraction of minority carriers in the semiconductor device, thereby reducing parameters characterizing reverse recovery performance, such as reverse charge (Qrr) and reverse current (Irr). When the shielded gate trench transistor is turned off, the Schottky contact structure and the source region are at a high potential, the trench Schottky diode is turned on and majority carriers are injected, the minority carriers are suppressed in the shielded gate trench transistor, and the overall reverse recovery capability of the semiconductor device is improved.

[0062] The semiconductor device, its manufacturing method, and layout structure proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0063] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined in this application, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise indicated, terms such as "upper / upper layer," "lower / lower layer," and similar terms are for ease of description only and are not limited to a location or spatial orientation. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed following "comprising" or "including" and its equivalents, and does not exclude other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0064] First, please refer to Figure 10 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 10 As shown, the semiconductor device 1 includes: a semiconductor substrate 10; a shielded gate trench transistor group 20S located in the semiconductor substrate 10, the shielded gate trench transistor group 20S including two shielded gate trench transistors 20, each shielded gate trench transistor 20 including a source region 26; and a trench Schottky diode 40 located in the semiconductor substrate 10 within the shielded gate trench transistor group 20S, the trench Schottky diode 40 including a trench gate electrode 42 and a Schottky contact structure 44 located on the side of the trench gate electrode 42; wherein the Schottky contact structure 44, the trench gate electrode 42, and the source region 26 of the shielded gate trench transistor 20 are equipotentially connected.

[0065] The semiconductor device and its manufacturing method will now be described in detail. For specific details, please refer to [link / reference needed]. Figures 1 to 10 It is a cross-sectional schematic diagram of the structure formed by the manufacturing method of the semiconductor device according to the embodiments of the present invention.

[0066] like Figure 1 As shown, firstly, a semiconductor substrate 10 is provided, wherein the semiconductor substrate 10 can be made of silicon, germanium silicon, silicon carbon, etc. In this embodiment, the semiconductor substrate 10 includes a silicon substrate 100 and a silicon epitaxial layer 101 located on the silicon substrate 100. Further, the silicon substrate 100 and the silicon epitaxial layer 101 can be subjected to an ion implantation process; for example, in this embodiment, the silicon substrate 100 and the silicon epitaxial layer 101 are N-type doped.

[0067] Next, the shielded gate trench transistor 20 and the trench Schottky diode 40 are formed in the semiconductor substrate 10.

[0068] For details, please continue to refer to [the website / information]. Figure 1 A first trench group 110S and a second trench group 111S are formed in the semiconductor substrate 10. The first trench group 110S includes two first trenches 110, and the second trench group 111S includes two second trenches 111. The second trench group 111S is located within the semiconductor substrate 110 of the first trench group 110S, specifically, within the semiconductor substrate 110 between the two first trenches 110 in the first trench group 110S. Specifically, the first trench group 110S and the second trench group 111S are formed by performing an etching process on the semiconductor substrate 10. In this embodiment, both the first trenches 110 and the second trenches 111 extend from the surface of the silicon epitaxial layer 101 into the silicon epitaxial layer 101, and the depths of the first trenches 110 and the second trenches 111 are the same.

[0069] Next, as Figure 2 As shown, a dielectric material layer 120 is formed, which covers the first trench 110, the second trench 111, and the surface of the semiconductor substrate 10 to form a second trench dielectric layer 41 in the second trench 111. Here, the dielectric material layer 120 is in a continuous state, covering the surface of the first trench 110, the surface of the second trench 111, and the surface of the semiconductor substrate 10, wherein the portion of the dielectric material layer 120 covering the surface of the second trench 111 forms the second trench dielectric layer 41.

[0070] The dielectric material layer 120 can be a single-layer structure or a multi-layer structure. In this embodiment, the dielectric material layer 120 includes a stacked first oxide layer 121, a nitride layer 122, and a second oxide layer 123. The nitride layer 122 can be, for example, silicon nitride (Si3N4), which can serve as a barrier layer for subsequent oxidation processes. That is, in this embodiment, the second trench dielectric layer 41 includes a stacked first oxide layer 121, a nitride layer 122, and a second oxide layer 123, wherein the second oxide layer 123 covers the nitride layer 122, and the nitride layer 122 covers the first oxide layer 121.

[0071] Next, as Figure 3 As shown, a polysilicon material layer 130 is filled in the first trench 110 and the second trench 111 to form a trench gate electrode 42 in the second trench 111. Specifically, the polysilicon material layer 130 can be deposited, filling the first trench 110 and the second trench 111 and extending to cover the dielectric material layer 120 on the surface of the semiconductor substrate 10; then, the polysilicon material layer 130 outside the first trench 110 and the second trench 111 can be removed by a polishing process to fill the first trench 110 and the second trench 111 with the polysilicon material layer 130. The polysilicon material layer 130 filling the second trench 111 forms the trench gate electrode 42. The trench gate electrode 42 is located in the second trench 111 and on the second trench dielectric layer 41, and the trench gate electrode 42 and the second trench dielectric layer 41 form a trench gate structure 43.

[0072] Next, as Figure 4 As shown, a patterned masking layer 140 is formed, which covers the second trench group 111S and the semiconductor substrate 10 located in the second trench group 111S, and exposes the first trench group 110S. Specifically, the patterned masking layer 140 covers the second trench 111 and the trench gate structure 43 in the second trench 111, and also extends to cover the surface of the semiconductor substrate 10 between the two second trenches 111 of the second trench group 111S, more specifically covering the dielectric material layer 120 between the two second trenches 111 of the second trench group 111S. Simultaneously, the first trench group 110S and the dielectric material layer 120 between the first trench 110 and the second trench 111 are exposed. The patterned masking layer 140 can be made of silicon nitride (Si3N4) and / or silicon oxide (SiO2), etc.

[0073] Specifically, a masking material layer (not shown in the figure) can be formed first, covering the device surface, including the surfaces of the dielectric material layer 120 and the polysilicon material layer 130, specifically involving the dielectric material layer 120 and the dielectric material layer 120 and polysilicon material layer 130 in the first trench 110 and the second trench 111 on the semiconductor substrate 10; next, a photoresist layer (not shown in the figure) is formed on the masking material layer, and a photolithography process is performed on the photoresist layer to form a patterned photoresist layer 141; then, the masking material layer can be etched using the patterned photoresist layer 141 to form the patterned masking layer 140, and the patterned photoresist layer 141 can be removed, such as... Figure 5 As shown.

[0074] Please refer to Figure 5 In this embodiment, the polysilicon material layer 130 in the first trench 110 is then etched to form a shielding gate electrode 21 in the first trench 110. Specifically, the polysilicon material layer 130 in the first trench 110 is etched to remove a portion of the thickness of the polysilicon material layer 130 in the first trench 110, and the remaining polysilicon material layer 130 in the first trench 110 forms the shielding gate electrode 21.

[0075] In this embodiment, a portion of the second oxide layer 123 in the first trench 110 is further etched to expose the nitride layer 122 located at the opening of the first trench 110. In the first trench 110, the surface of the shielding gate electrode 21 and the surface of the second oxide layer 123 are flush. Furthermore, the second oxide layer 123 covering the surface of the semiconductor substrate 10 is also etched away. That is, the exposed second oxide layer 123 is etched away.

[0076] like Figure 6 As shown, an inter-gate dielectric layer 22 covering the shielding gate electrode 21 is then formed in the first trench 110. In this embodiment, the inter-gate dielectric layer 22 is formed by a thermal oxidation process; in other embodiments of this application, the inter-gate dielectric layer 22 can also be formed by a deposition process.

[0077] In this embodiment, after forming the inter-gate dielectric layer 22, a portion of the nitride layer 122 in the first trench 110 is further etched to expose the first oxide layer 121 located at the opening of the first trench 110. Furthermore, the nitride layer 122 covering the surface of the semiconductor substrate 10 is also etched away. That is, the exposed nitride layer 122 is etched away.

[0078] Here, a first trench dielectric layer 23 is formed in the first trench 110. The first trench dielectric layer 23 includes a first oxide layer 121, a nitride layer 122, and a second oxide layer 123 stacked together. The second oxide layer 123 covers the nitride layer 122, and the nitride layer 122 covers a portion of the first oxide layer 121, exposing the first oxide layer 121 located at the opening of the first trench 110. That is, in this embodiment, the thickness of the first trench dielectric layer 23 at the bottom of the first trench 110 is greater than the thickness at the opening of the first trench 110.

[0079] Next, as Figure 7 As shown, a control gate electrode 24 is formed in the first trench 110, and the control gate electrode 24 is located on the inter-gate dielectric layer 22. In this embodiment, the control gate electrode 24 is made of polysilicon. Specifically, a polysilicon layer (not shown in the figure) can be formed first; then, the control gate electrode 24 is formed by etching back the polysilicon layer.

[0080] Please continue to refer to this. Figure 7 In this embodiment, a well region 25 and a source region 26 are then formed in the semiconductor substrate 10 on the side of the first trench 110 using an ion implantation process. Specifically, the well region 25 can be formed in the semiconductor substrate 10 first using a first ion implantation process. Here, the first ion implantation process is a P-type ion implantation process, and further, the first ion implantation process can be a maskless ion implantation process. Next, the source region 26 is formed in the well region 25 using a second ion implantation process. Here, the second ion implantation process is an N-type ion implantation process, and further, the second ion implantation process can also be a maskless ion implantation process. Furthermore, after performing the first and second ion implantation processes, an annealing process is also performed to activate the implanted ions.

[0081] Thus, the shielded gate trench transistor 20 is formed. Specifically, the shielded gate trench transistor 20 includes: a first trench 110 located in the semiconductor substrate 10; a first trench dielectric layer 23 located in the first trench 110; a shielded gate electrode 21 located in the first trench 110 and on the first trench dielectric layer 23; an inter-gate dielectric layer 22 located in the first trench 110 and covering the shielded gate electrode 21; a control gate electrode 24 located in the first trench 110 and on the inter-gate dielectric layer 22; and a well region 25 and a source region 26 located in the semiconductor substrate 10 on the side of the first trench 110.

[0082] Next, as Figure 8As shown, the patterned masking layer 140 is removed, exposing the second trench group 111S and the dielectric material layer 120 located in the second trench group 111S. In this embodiment, the exposed second oxide layer 123 is further removed to expose the nitride layer 122, and the exposed nitride layer 122 is further removed to expose the first oxide layer 121. For example, the patterned masking layer 140, the second oxide layer 123, and the nitride layer 122 can be removed by a plasma process.

[0083] Next, please refer to Figure 9 An interlayer dielectric layer 150 is formed on the semiconductor substrate 10. Specifically, the interlayer dielectric layer 150 can be formed by a deposition process, where the interlayer dielectric layer 150 covers the first trench 110, the second trench 111, and the first oxide layer 121. Next, a first opening 151, a second opening 152, and a third opening (not shown in the figure) are formed in the interlayer dielectric layer 150 by an etching process. The first opening 151 penetrates the interlayer dielectric layer 150 and the source region 26 and extends into the well region 25. The second opening 152 penetrates the interlayer dielectric layer 150 and extends into the semiconductor substrate 10 in the second trench group 111S. The third opening penetrates the interlayer dielectric layer 150 and extends into the trench gate electrode 42. In this embodiment, the third opening exposes a portion of the trench gate electrode 42, meaning that a portion of the trench gate electrode 42 is still covered by the interlayer dielectric layer 150. In other embodiments of this application, the third opening may also expose the entire trench gate electrode 42, as can be referred to accordingly. Figures 13 to 15 In this embodiment, the bottom of the second opening 152 is lower than the surface of the trench gate electrode 42; in other embodiments, the bottom of the second opening 152 may be flush with the surface of the trench gate electrode 42. The first opening 151, the second opening 152, and the third opening may each be independent; alternatively, the first opening 151 may be independent of the second opening 152 and the third opening, with the second opening 152 and the third opening connected; or the first opening 151, the second opening 152, and the third opening may be interconnected.

[0084] In this embodiment, the cross-sectional width of the second opening 152 is wider than the cross-sectional width of the first opening 151, and the depth of the second opening 152 is the same as the depth of the first opening 151. The second opening 152 and the first opening 151 can be formed simultaneously by a one-step etching process. In this embodiment, the depth of the third opening can be shallower than the depths of the first opening 151 and the second opening 152; or the depth of the third opening can be the same as the depths of the first opening 151 and the second opening 152.

[0085] Next, as Figure 10 As shown, a metal layer 160 is formed, which covers the surface of the interlayer dielectric layer 150 and extends to cover the first opening 151, the second opening 152, and the third opening. The metal layer 160 forms a Schottky contact structure 44 on the surface of the semiconductor substrate 10 in the second trench group 111S; that is, the metal layer 160 and the semiconductor substrate 10 exposed by the second opening 152 react to form the Schottky contact structure 44.

[0086] Thus, the trench-type Schottky diode 40 is formed. Specifically, the trench-type Schottky diode 40 includes: a second trench group 111S located in the semiconductor substrate 10, the second trench group 111S including two second trenches 111; a second trench dielectric layer 41 located in the second trenches 111; a trench gate electrode 42 located in the second trenches 111 and on the second trench dielectric layer 41; and the Schottky contact structure 44 located on the surface of the semiconductor substrate 10 in the second trench group 111S.

[0087] Please continue to refer to this. Figure 10 In this embodiment, the bottom of the second opening 152 is lower than the surface of the trench gate electrode 42. Furthermore, the surface of the Schottky contact structure 44 formed on the surface of the semiconductor substrate 10 exposed by the second opening 152 is also lower than the surface of the trench gate electrode 42.

[0088] The metal layer 160 may include a multilayer structure. In this embodiment, the metal layer 160 includes a stacked titanium nitride layer (not shown) and an aluminum metal layer (not shown). In other embodiments of this application, the metal layer 160 may also include other metal material layers, such as titanium layers, nickel layers, etc.

[0089] Simultaneously, the metal layer 160 also connects the Schottky contact structure 44, the trench gate electrode 42, and the source region 26. Specifically, the metal layer 160 is electrically connected to the Schottky contact structure 44 through the second opening 152, electrically connected to the trench gate electrode 42 through the third opening, and electrically connected to the source region 26 through the first opening 151, thereby making the Schottky contact structure 44, the trench gate electrode 42, and the source region 26 equipotentially connected.

[0090] like Figure 10 As shown in this embodiment, a shielded gate trench transistor group 20S and a trench Schottky diode 40 are formed in the semiconductor substrate 10. The shielded gate trench transistor group 20S includes two shielded gate trench transistors 20. The trench Schottky diode 40 is located in the semiconductor substrate 10 within the shielded gate trench transistor group 20S. The Schottky contact structure 44, the trench gate electrode 42 of the trench Schottky diode 40, and the source region 26 of the shielded gate trench transistor 20 are equipotentially connected. When the trench Schottky diode 40 is turned on, it only allows majority carriers to flow, which largely suppresses minority carrier injection, thus exhibiting superior fast recovery characteristics. By integrating the trench Schottky diode 40 and the shielded gate trench transistor 20, the trench Schottky diode 40 reduces the degree to which the semiconductor device 1 extracts minority carriers under reverse bias, thereby reducing parameters characterizing reverse recovery performance, such as reverse charge (Qrr) and reverse current (Irr). When the shielded gate trench transistor 20 is turned off, the Schottky contact structure 44 and the source region 26 are at a high potential, and the trench Schottky diode 40 is turned on, enabling majority carrier injection. This suppresses minority carrier injection in the shielded gate trench transistor 20 and improves the overall reverse recovery capability of the semiconductor device 1.

[0091] For further details, please refer to... Figure 11 and Figure 12 ,in, Figure 11 This is a schematic diagram comparing the conduction curves of the parasitic diodes of the trench Schottky diode and the shielded gate trench transistor according to an embodiment of the present invention. Figure 12 This is a schematic diagram comparing the reverse recovery curves of a semiconductor device and a shielded gate trench transistor according to an embodiment of the present invention.

[0092] like Figure 11As shown, curve 200 is the conduction curve of the trench Schottky diode, and curve 210 is the conduction curve of the parasitic diode. Taking the voltage corresponding to 11A (amperes) as the turn-on voltage, the forward voltage Vf of the trench Schottky diode is approximately 0.435V, while the forward voltage Vf of the parasitic diode is approximately 0.762V. This ensures that the trench Schottky diode conducts first and injects majority carriers, thereby suppressing minority carrier injection when the parasitic diode conducts.

[0093] like Figure 12 As shown, curve 300 is the reverse recovery curve of semiconductor device 1 according to an embodiment of the present invention, and curve 310 is the reverse recovery curve of a conventional shielded gate trench transistor. Comparing curves 300 and 310, it can be seen that semiconductor device 1 according to an embodiment of the present invention has smaller reverse charge (Qrr) and reverse current (Irr), and exhibits better reverse recovery performance.

[0094] Furthermore, embodiments of this application also provide a layout structure for forming the aforementioned semiconductor device 1. For example... Figure 13 As shown, the layout structure 400 includes:

[0095] A first mask structure 410 is used to form a first trench group and a second trench group.

[0096] A second mask structure 420 is used to form a masking layer; and...

[0097] A third mask structure 430 is used to form a first opening, a second opening, and a third opening.

[0098] like Figure 13 As shown, the first mask structure 410 includes a plurality of first patterns 411, which are used to expose the semiconductor substrate. In this embodiment, the plurality of first patterns 411 are rectangles of the same shape, which are used to form a first trench group and a second trench group of the same shape.

[0099] The second mask structure 420 includes a plurality of second patterns 421. In this embodiment, the plurality of second patterns 421 are rectangles of the same shape. Figure 13 As shown, the second mask structure 420 and the first mask structure 410 are aligned, and a plurality of second patterns 421 are respectively aligned with a plurality of first patterns 411. Here, the second patterns 421 are used to expose part of the first trench, and two second patterns 421 respectively expose part of the first trench group.

[0100] The third mask structure 430 includes a plurality of third patterns 431. In this embodiment, the plurality of third patterns 431 are not all the same. Figure 13 As shown, the third mask structure 430 and the first mask structure 410 are aligned. In this embodiment, a plurality of third patterns 431 are used to expose the second trench group and the semiconductor substrate in the second trench group, as well as a portion of the first trench. The patterns of the third patterns 431 used to expose the semiconductor substrate in the second trench group and the third patterns 431 used to expose a portion of the first trench are different. In this embodiment, the third pattern 431 exposes all of the second trench group and the semiconductor substrate in the second trench group; in other embodiments of this application, the third pattern 431 may also expose a portion of the second trench group and the semiconductor substrate in the second trench group, or only expose the semiconductor substrate in the second trench group.

[0101] For further details, please refer to... Figure 14 and Figure 15 ,in, Figure 14 It is to utilize Figure 13 The schematic diagram of the semiconductor device formed by the layout structure shown is shown, and its corresponding Figure 13 The position of AA' in the middle; Figure 15 It is to utilize Figure 13 The schematic diagram of the semiconductor device formed by the layout structure shown is shown, and its corresponding Figure 13 The position of BB' in the middle.

[0102] like Figure 14 and Figure 15 As shown, in this embodiment, a semiconductor device 1' is formed using the layout structure 400. Specifically, a first trench group 110S' and a second trench group 111S' are formed using the first mask structure 410; a control gate electrode 24', a well region 25', and a source region 26' are formed using the second mask structure 420, while simultaneously masking the semiconductor substrate 10' between the trench gate electrode 42' in the second trench 111' and the second trench group 111S'; and a third mask structure 430 is used to form a first opening 151' for connecting the source region 26', a second opening 152' for connecting the Schottky contact structure 44', and a third opening for connecting the trench gate electrode 42' (in this embodiment, the third opening and the second opening are connected and are not shown separately in the figure). The difference between this embodiment and the previous embodiment is that... Figure 10In the illustrated embodiment, the second opening 152 and the third opening are independent of each other. The second opening 152 exposes the semiconductor substrate 10 between the second trench groups 111S, and the third opening exposes a portion of the trench gate electrode 42; while... Figure 14 and Figure 15 In the illustrated embodiment, the second opening 152' and the third opening are connected, exposing the semiconductor substrate 10' between the second trench group 111S' and the second trench group 111S'.

[0103] In this embodiment, the control gate electrode 24', well region 25', and source region 26' are formed using the second mask structure 420. Simultaneously, the semiconductor substrate 10' between the trench gate electrode 42' in the second trench 111' and the second trench group 111S' is masked. That is, the second mask structure 420, which forms the control gate electrode 24', well region 25', and source region 26', is used to mask the semiconductor substrate 10' between the trench gate electrode 42' in the second trench 111' and the second trench group 111S'. No additional mask structure is added to mask the semiconductor substrate 10' between the trench gate electrode 42' in the second trench 111' and the second trench group 111S'. In other words, in this embodiment, ion implantation is performed using a self-aligned process to form the well region and source region of the shielded gate trench transistor, thereby avoiding an increase in manufacturing costs.

[0104] In summary, in the semiconductor device, its manufacturing method, and layout structure provided in the embodiments of the present invention, a shielded gate trench transistor and a trench Schottky diode are formed in the semiconductor substrate. The barrier effect of the trench Schottky diode on minority carriers reduces the degree of minority carrier extraction by the overall reverse bias of the semiconductor device, thereby reducing parameters characterizing the reverse recovery performance of the semiconductor device, such as reverse charge (Qrr) and reverse current (Irr). Simultaneously, the well and source regions of the shielded gate trench transistor can be formed by self-aligned ion implantation, avoiding an increase in manufacturing costs.

[0105] In this application, references to "one embodiment" or "some embodiments" mean that a feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment or at least some embodiments of this application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" throughout this application does not necessarily refer to the same or the same embodiments. Furthermore, in one or more embodiments, features, structures, or characteristics can be combined in any suitable combination and / or sub-combination.

[0106] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this application. The embodiments of this application can be combined in any way without departing from the spirit and scope of this application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Semiconductor substrate; A shielded gate trench transistor group located in the semiconductor substrate, the shielded gate trench transistor group comprising two shielded gate trench transistors, each shielded gate trench transistor including a source region; and, A trench Schottky diode located in the semiconductor substrate of the shielded gate trench transistor group, the trench Schottky diode including a trench gate electrode and a Schottky contact structure located on the side of the trench gate electrode; The Schottky contact structure, the trench gate electrode, and the source region are equipotentially connected.

2. The semiconductor device as claimed in claim 1, characterized in that, The shielded gate trench transistor includes: The first trench is located in the semiconductor substrate; The first trench dielectric layer located in the first trench; A shielding gate electrode located in the first trench and on the dielectric layer of the first trench; An inter-gate dielectric layer located in the first trench and covering the shielding gate electrode; The control gate electrode is located in the first trench and on the inter-gate dielectric layer; and, The well region and the source region are located in the semiconductor substrate on the side of the first trench.

3. The semiconductor device as described in claim 2, characterized in that, The first trench dielectric layer includes a stacked first oxide layer, a nitride layer, and a second oxide layer, wherein the second oxide layer covers the nitride layer, and the nitride layer covers a portion of the first oxide layer and exposes the first oxide layer located at the opening of the first trench.

4. The semiconductor device as claimed in claim 1, characterized in that, The trench-type Schottky diode includes: A second trench group located in the semiconductor substrate, the second trench group comprising two second trenches; A trench gate structure located in the second trench, the trench gate structure including a second trench dielectric layer and the trench gate electrode located on the second trench dielectric layer; and, The Schottky contact structure located on the surface of the semiconductor substrate in the second trench group.

5. The semiconductor device as claimed in claim 4, characterized in that, The surface of the Schottky contact structure is lower than the surface of the slot gate electrode, or flush with the surface of the slot gate electrode.

6. The semiconductor device as claimed in claim 4, characterized in that, The second trench dielectric layer includes a first oxide layer, a nitride layer, and a second oxide layer stacked together, wherein the second oxide layer covers the nitride layer, and the nitride layer covers the first oxide layer.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The semiconductor structure further includes a metal layer that connects the Schottky contact structure, the trench gate electrode, and the source region.

8. A method for manufacturing a semiconductor device, characterized in that, The method for manufacturing the semiconductor device includes: Provide semiconductor substrates; and, A shielded gate trench transistor group and a trench Schottky diode are formed in the semiconductor substrate; the shielded gate trench transistor group includes two shielded gate trench transistors, each shielded gate trench transistor including a source region; the trench Schottky diode is located in the semiconductor substrate within the shielded gate trench transistor group, and the trench Schottky diode includes a trench gate electrode and a Schottky contact structure located on the side of the trench gate electrode; The Schottky contact structure, the trench gate electrode, and the source region are equipotentially connected.

9. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, Forming a shielded gate trench transistor array and a trench Schottky diode in the semiconductor substrate includes: A first trench group and a second trench group are formed in the semiconductor substrate. The first trench group includes two first trenches, and the second trench group includes two second trenches. The second trench group is located in the semiconductor substrate within the first trench group. A dielectric material layer is formed, the dielectric material layer covering the first trench, the second trench and the surface of the semiconductor substrate, so as to form a second trench dielectric layer in the second trench; A polycrystalline silicon material layer is filled in the first trench and the second trench to form a trench gate electrode in the second trench; A patterned masking layer is formed, which covers the second trench group and the semiconductor substrate located in the second trench group, and exposes the first trench group; The polysilicon material layer in the first trench is etched to form a shielding gate electrode in the first trench; An inter-gate dielectric layer covering the shielding gate electrode and a control gate electrode located on the inter-gate dielectric layer are formed in the first trench; A well region and a source region are formed in the semiconductor substrate on the first trench side by means of an ion implantation process; Remove the graphical masking layer; An interlayer dielectric layer is formed on the semiconductor substrate, and a first opening, a second opening, and a third opening are formed in the interlayer dielectric layer. The first opening penetrates the interlayer dielectric layer and extends into the well region; the second opening penetrates the interlayer dielectric layer and extends into the semiconductor substrate in the second trench group; and the third opening penetrates the interlayer dielectric layer and extends into the trench gate electrode. A metal layer is formed on the interlayer dielectric layer, the metal layer extending to cover the surfaces of the first opening, the second opening and the third opening, the metal layer forming a Schottky contact structure on the surface of the semiconductor substrate in the second trench group and connecting the Schottky contact structure, the trench gate electrode and the source region.

10. The method for manufacturing a semiconductor device as described in claim 9, characterized in that, The first opening, the second opening, and the third opening are each independent, and the surface of the Schottky contact structure is lower than the surface of the trench gate electrode.

11. The method for manufacturing a semiconductor device as described in claim 9, characterized in that, The first opening is independent of the second opening and the third opening, the second opening and the third opening are connected, and the surface of the Schottky contact structure is flush with the surface of the slot gate electrode.

12. The method for manufacturing a semiconductor device as described in claim 9, characterized in that, The dielectric material layer includes a stacked first oxide layer, a nitride layer, and a second oxide layer. After etching the polysilicon material layer in the first trench to form a shielded gate electrode in the first trench, forming a shielded gate trench transistor group and a trench Schottky diode in the semiconductor substrate further includes: A portion of the second oxide layer and a portion of the nitride layer in the first trench are etched to expose the first oxide layer located at the opening of the first trench, and a first trench dielectric layer is formed in the first trench.

13. A layout structure, characterized in that, The layout structure includes: A first mask structure is used to form a first trench group and a second trench group; A second mask structure, the second mask structure being used to form a masking layer; and... A third mask structure is used to form a first opening, a second opening, and a third opening.

14. The layout structure as described in claim 13, characterized in that, The first opening is independent of the second opening and the third opening, and the second opening is independent of the third opening or connected to the third opening.

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