Diamond-3c-sic heterostructure and method of preparation

Abstract

This invention provides a diamond-3C-SiC heterostructure and its fabrication method, relating to the technical field of wide-bandgap semiconductor fabrication. The diamond-3C-SiC heterostructure comprises, from bottom to top, a 0.5-1.0 mm thick diamond substrate, a 5-10 nm thick SiC transition layer, a 2-5 nm thick single-crystal silicon transition layer, and a 5-10 μm thick 3C-SiC layer. This invention utilizes an innovative "magnetron sputtering silicon layer + in-situ solid-state reactive annealing" process to construct a composite transition layer on the diamond surface consisting of an "in-situ reactive SiC layer + recrystallized silicon layer." This transition layer achieves a "gradual buffer" from diamond to 3C-SiC in terms of chemical bonding and crystal structure, significantly reducing interface energy and effectively relaxing mismatch stress. This lays a reliable interface foundation for subsequently obtaining a single-crystal 3C-SiC epitaxial layer with low defect density and high crystallinity, overcoming a core obstacle in heterogeneous integration.

Description

Technical Field

[0001] This invention relates to the technical field of wide bandgap semiconductor fabrication, and in particular to a diamond-3C-SiC heterostructure and its fabrication method. Background Technology

[0002] Cubic silicon carbide (3C-SiC) is a promising third-generation wide-bandgap semiconductor material. Compared to mainstream hexagonal silicon carbide (such as 4H-SiC and 6H-SiC), 3C-SiC possesses higher electron mobility, lower interface state density, and its cubic symmetry is similar to that of silicon (Si) crystal structure, theoretically offering better compatibility with silicon-based microelectronic processes. These properties give 3C-SiC unique advantages in manufacturing high-frequency metal-oxide-semiconductor field-effect transistors (MOSFETs), high-sensitivity sensors, and certain specialized optoelectronic devices.

[0003] However, the large-scale application of 3C-SiC materials has been limited by the availability of high-quality single-crystal substrates. Currently, 3C-SiC epitaxial growth mainly uses inexpensive silicon (Si) substrates. However, due to the significant lattice mismatch (approximately 20%) and difference in thermal expansion coefficients between Si and 3C-SiC, 3C-SiC films epitaxially grown on Si exhibit high-density crystal defects (such as stacking faults and micropipes), severe biaxial tensile stress, and significant wafer warping. These material quality issues severely degrade the electrical performance, stability, and reliability of devices fabricated based on them, preventing the full realization of the theoretical advantages of 3C-SiC.

[0004] Chinese patent CN117418309A discloses a method for preparing 3C-SiC single crystals. This method involves growing an initial 3C-SiC single crystal layer on a Si single crystal substrate using chemical vapor deposition (CVD), then bonding the initial 3C-SiC single crystal layer to a 4H-SiC single crystal substrate, removing the Si single crystal substrate, and further rapidly growing a 3C-SiC single crystal thickening layer on the initial 3C-SiC single crystal layer using CVD at a temperature higher than the melting point of Si. However, this method suffers from defects in the bonding interface quality, such as defects in the initial 3C-SiC layer being directly transferred to the thickening layer, and defects arising during the high-temperature thickening growth process.

[0005] Chinese patent CN121023637A discloses a 3C-SiC epitaxial layer and its preparation method. This method introduces a sacrificial layer of C or Si material on the surface of a 4H-SiC substrate. The sacrificial layer plays a key role in passivating the activity of atomic steps on the 4H-SiC surface, thereby reducing polymorphic mixing from the source and improving the growth quality and yield of the 3C-SiC epitaxial layer. However, this method has technical defects such as the defects caused by the introduction and removal of the sacrificial layer, and the uncertainty and limitations of the passivation effect.

[0006] Chinese patent CN119753832A discloses a 3C-SiC epitaxial wafer and its preparation method. The method includes the following steps: (1) etching a silicon substrate; (2) forming a first carbonization buffer layer on the surface of the etched silicon substrate; (3) performing heteroepitaxial growth on the first carbonization buffer layer in the presence of a first process gas. However, this method has technical defects such as poor low-temperature compatibility, single crystal growth purity and defect control depending on the gas ratio, weaker stability than the transition layer-mediated method, poor flexibility in transition layer preparation, and insufficient adaptability.

[0007] Chinese patent CN119710914A discloses a 3C-SiC epitaxial layer and its preparation method. This method has technical defects such as high dependence on multiple stages for defect control, significant disadvantages in substrate compatibility and cost.

[0008] On the other hand, in the pursuit of higher power density and higher frequency semiconductor devices, heat dissipation has become a core bottleneck restricting performance improvement. Diamond, as the material with the highest known thermal conductivity in nature (>2000 W / mK at room temperature), is an ideal heat dissipation substrate for solving this bottleneck. However, diamond has high surface chemical inertness and its lattice constant differs greatly from most functional semiconductor materials, making it difficult to directly epitaxially grow high-quality, large-area single-crystal semiconductor functional layers on it. Currently, the application of diamond in semiconductors is mostly limited to its use as a heat dissipation material for device packaging after completion or as an electrical material for polycrystalline / nanocrystalline thin films; its potential as a single-crystal epitaxial substrate remains largely untapped.

[0009] Therefore, how to combine the excellent electrical properties of 3C-SiC with the unparalleled heat dissipation capabilities of diamond to create a novel heterostructure with both excellent electrical and thermal properties is a technical challenge that urgently needs to be overcome in this field. Summary of the Invention

[0010] The main objective of this invention is to address the technical challenges in existing cubic silicon carbide (3C-SiC) fabrication techniques, including the difficulty in obtaining high-quality single-crystal substrates, the quality and performance defects of 3C-SiC films epitaxially grown on silicon substrates, the inability to directly grow 3C-SiC films on diamond substrates, and the poor epitaxial quality and high stress in 3C-SiC / Si structures due to lattice and thermal mismatch. Therefore, this invention proposes a diamond-3C-SiC heterostructure and its fabrication method that can solve the aforementioned problems.

[0011] The technical solution is as follows:

[0012] A diamond-3C-SiC heterostructure, wherein the diamond-3C-SiC heterostructure comprises, from bottom to top, a diamond substrate with a thickness of 0.5-1.0 mm, a SiC transition layer with a thickness of 5-10 nm, a single-crystal silicon transition layer with a thickness of 2-5 nm, and a 3C-SiC layer with a thickness of 5-10 μm.

[0013] Optionally, in the diamond-3C-SiC heterostructure, the average particle size of the SiC transition layer is 1-10 μm, the average particle size of the single-crystal silicon transition layer is 30-300 nm, and the 3C-SiC layer is single-crystal 3C-SiC.

[0014] Optionally, the diamond-3C-SiC heterostructure exhibits the following properties: microtube density ≤ 10 cm³. -2 Surface roughness ≤ 1 nm, residual stress ≤ 0.1 GPa, electron mobility ≥ 800 cm⁻¹ 2 / V·s, effective thermal conductivity ≥1500W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 1-10kW / cm, high frequency of 26-40GHz, and high reliability under extreme environments.

[0015] A method for preparing the diamond-3C-SiC heterostructure, comprising the following steps:

[0016] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirements are screened as substrate materials, and the impurity content is controlled to obtain screened single-crystal diamond substrates.

[0017] S2, Chemical mechanical polishing of single crystal diamond substrate: The screened single crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain polished single crystal diamond substrate.

[0018] S3, which facilitates the pretreatment of substrate epitaxy 3C-SiC: The polished single crystal diamond substrate of S2 is boiled and acid-washed with a mixed acid solution, and then ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence to obtain the pretreated-polished single crystal diamond substrate.

[0019] S4. Preparation of silicon layer: Using silicon target material as silicon source, a silicon layer is deposited by magnetron sputtering on the pretreated-polished single crystal diamond substrate surface in S3 to obtain a non-single crystal silicon layer-single crystal diamond substrate.

[0020] S5, Synergistic preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 is subjected to high-temperature annealing treatment, a thin SiC transition layer is formed at the interface, and the non-single-crystal silicon is recrystallized to form single-crystal silicon, thus obtaining single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0021] S6. Growth of a single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer is grown on the surface of the single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate in S5 using a chemical vapor deposition equipment, resulting in a heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0022] Optionally, the high-quality single-crystal diamond in S1 meets the product size requirements of 5×5mm and above, and controls the impurity content to be less than 1ppb.

[0023] Optionally, the roughness of the polished single-crystal diamond substrate in S2 is below 0.3 nm.

[0024] Optionally, in S3, the mixed acid solution is a 3:1 ratio of 95-98% H2SO4 and 96-99.7% HNO3, and the boiling pickling time is 25-35 min; the ultrasonic cleaning frequency is 40-200 Hz and the time is 10-20 min.

[0025] Optionally, in S4, the substrate temperature is controlled at 150-200℃, the sputtering power is 150-250W, the sputtering time is 160-200s, and the applied bias voltage is 100-150V.

[0026] Optionally, the high-temperature annealing treatment in S5 is carried out at a temperature of 1000-1300℃ for 1-5 minutes; the thickness of the thin SiC transition layer is 5-10 mm.

[0027] Optionally, hydrogen is used as the carrier gas in S6, with a heating rate of 20-30℃ / min, heating to 830-860℃ and stabilizing for 5-10 min for in-situ etching with hydrogen; the growth process of the single crystal 3C-SiC layer: the growth temperature is 1400-1550℃, the C raw materials include CH4, C2H4, and C3H8, and the Si raw materials can be SiH4, SiH3Cl, SiH2Cl2, SiHCl3, and SiCl4; the C / Si ratio of the C raw materials and Si raw materials is 0.1-10, and the growth rate is 1-30μm / h.

[0028] Technical principle of the invention:

[0029] In existing technologies, 3C-SiC possesses excellent electrical properties, but its epitaxial quality and stress issues are prominent. Diamond has unparalleled heat dissipation capabilities, but it cannot be effectively used as an epitaxial substrate. Therefore, the core technical challenge that the industry urgently needs to overcome is: how to combine the excellent electrical properties of 3C-SiC with the ultra-high heat dissipation capabilities of diamond to construct a novel heterostructure that simultaneously possesses excellent electrical and thermal properties. This would solve both the quality and stress problems of epitaxy of 3C-SiC on Si substrates and overcome the technical obstacle of growing high-quality single-crystal semiconductor layers on diamond surfaces, providing an ideal material platform for next-generation ultra-high power density, high frequency, and high reliability semiconductor devices.

[0030] The core technical principle of this invention is to achieve efficient heterogeneous integration of diamond and 3C-SiC through "composite transition layer mediation + multi-stage precise control". This combines the excellent electrical properties of 3C-SiC with the ultra-high heat dissipation capacity of diamond, and solves the core problems of lattice mismatch and interface compatibility between the two.

[0031] In existing technologies, 3C-SiC possesses excellent electrical properties, but its epitaxial quality and stress issues are prominent. Diamond has unparalleled heat dissipation capabilities, but it cannot be effectively used as an epitaxial substrate. Therefore, the core technical challenge that the industry urgently needs to overcome is: how to combine the excellent electrical properties of 3C-SiC with the ultra-high heat dissipation capabilities of diamond to construct a novel heterostructure that simultaneously possesses excellent electrical and thermal properties. This would solve both the quality and stress problems of epitaxy of 3C-SiC on Si substrates and overcome the technical obstacle of growing high-quality single-crystal semiconductor layers on diamond surfaces, providing an ideal material platform for next-generation ultra-high power density, high frequency, and high reliability semiconductor devices.

[0032] In existing technologies, epitaxial growth of 3C-SiC on silicon substrates faces approximately 20% lattice mismatch and significant differences in thermal expansion coefficients, resulting in high-density stacking faults, micropipes, and severe biaxial tensile stress in the thin films. This invention solves this problem at its root through precise control of multiple stages.

[0033] The key to the implementation of this invention lies in:

[0034] 1. A high-purity single-crystal diamond substrate is used via CVD, and the surface roughness is reduced to less than 0.3 nm by CMP polishing. This provides a near-perfect crystal template for subsequent heteroepitaxial growth. The extremely low roughness is fundamental to reducing heteronucleation defects and achieving two-dimensional layered growth.

[0035] 2. By depositing an amorphous silicon layer of a specific thickness (controlled by a deposition time of 160-200s) through magnetron sputtering, and heating the substrate, the deposited silicon layer can be made more dense and uniform, but the temperature should not be too high.

[0036] 3. The annealing temperature is above 1000℃ to ensure the formation of a uniform silicon carbide layer, while the remaining silicon layer is recrystallized, ultimately forming a composite buffer structure of "diamond / in-situ SiC / crystalline silicon".

[0037] 4. Dynamic and precise control of the C / Si ratio. Although a wide range of C / Si ratios (0.1-10) is given, successful implementation hinges on finding and stabilizing an extremely narrow process window of "slightly silicon-rich" on specific equipment and substrates. This suppresses the formation of vapor phase and surface free carbon (graphite), helps to obtain a smooth surface morphology, and maintains a reasonable growth rate.

[0038] This invention utilizes an innovative "magnetron sputtering silicon layer + in-situ solid-state reactive annealing" process to construct a composite transition layer on the diamond surface, consisting of an "in-situ reactive SiC layer + recrystallized silicon layer." This transition layer achieves a "gradual buffer" in chemical bonding and crystal structure from diamond to 3C-SiC, significantly reducing interface energy and effectively relaxing mismatch stress. This lays a reliable interface foundation for subsequently obtaining single-crystal 3C-SiC epitaxial layers with low defect density and high crystallinity, overcoming a core obstacle in heterogeneous integration. It achieves synergistic optimization of process controllability and crystal quality, providing an ideal material platform for high-performance composite functional devices.

[0039] The above technical solution has at least the following advantages compared with the existing technology:

[0040] The above-mentioned solution proposes a diamond-3C-SiC heterostructure and its preparation method, which can solve the technical problems in the existing cubic silicon carbide (3C-SiC) preparation technology, such as the difficulty in obtaining high-quality single crystal substrates, especially the quality and performance defects of 3C-SiC films epitaxially grown on silicon substrates, the inability to directly grow 3C-SiC films on diamond substrates, and the poor epitaxial quality and high stress in 3C-SiC / Si structures caused by lattice and thermal mismatch.

[0041] The method of this invention, through the screening and chemical mechanical polishing of single-crystal diamond substrates, can reduce the surface roughness of the diamond substrates to an atomically smooth and damage-free surface, ensuring the orientation and consistency of single-crystal epitaxial growth.

[0042] The method of the present invention, by taking advantage of the pretreatment of the 3C-SiC substrate, enables chemical cleaning and surface terminalization, improves the uniformity and adhesion of the nucleation layer, reduces interface defects and amorphous phases, thereby improving the crystallization quality of the thin film.

[0043] The method of the present invention can alleviate lattice mismatch and provide a suitable chemical nucleation surface by preparing a silicon layer.

[0044] The method of this invention enables the synergistic preparation of a single-crystal silicon layer transition layer and a SiC transition layer, thereby achieving a gradient transition in lattice constant and thermal expansion coefficient, as well as "functional stratification" that filters and blocks defects.

[0045] The method of the present invention can control the growth mode and step flow surface morphology of the sample by adjusting the carbon-silicon ratio and process parameters during the growth of single crystal 3C-SiC layer, and can also suppress the generation of specific defects.

[0046] In summary, compared with traditional 3C-SiC preparation methods, the method of this invention constructs a composite transition layer on the diamond surface consisting of an in-situ reactive SiC layer and a recrystallized silicon layer through an innovative "magnetron sputtering silicon layer + in-situ solid-state reaction annealing" process. A 3C-SiC layer is then grown on this composite transition layer. This method can effectively reduce interface energy and effectively relax mismatch stress, solving the core obstacle of heterogeneous integration. It is simple to operate, low in cost, low in energy consumption, and high in efficiency, which is conducive to large-scale industrial production and promotion. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the process flow for preparing a diamond-3C-SiC heterostructure according to the present invention;

[0049] Figure 2 This is an XRD pattern of a single-crystal 3C-SiC layer in a diamond-3C-SiC heterostructure according to Embodiment 1 of the present invention;

[0050] Figure 3This is a SEM image of the surface of a single-crystal 3C-SiC layer in a diamond-3C-SiC heterostructure according to Embodiment 1 of the present invention. Detailed Implementation

[0051] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0052] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0053] In the embodiments of the present invention, the terms "image" and "picture" may sometimes be used interchangeably. It should be noted that when the distinction is not emphasized, their intended meanings are consistent.

[0054] In this embodiment of the invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When the difference is not emphasized, the meaning they express is the same.

[0055] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0056] A diamond-3C-SiC heterostructure, wherein the diamond-3C-SiC heterostructure comprises, from bottom to top, a diamond substrate with a thickness of 0.5-1.0 mm, a SiC transition layer with a thickness of 5-10 nm, a single-crystal silicon transition layer with a thickness of 2-5 nm, and a 3C-SiC layer with a thickness of 5-10 μm.

[0057] Specifically, in the diamond-3C-SiC heterostructure, the average particle size of the SiC transition layer is 1-10 μm, the average particle size of the single-crystal silicon transition layer is 30-300 nm, and the 3C-SiC layer is single-crystal 3C-SiC.

[0058] In particular, the diamond-3C-SiC heterostructure exhibits the following properties: microtube density ≤ 10 cm³. -2 Surface roughness ≤ 1 nm, residual stress ≤ 0.1 GPa, electron mobility ≥ 800 cm⁻¹ 2 / V·s, effective thermal conductivity ≥1500W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 1-10kW / cm, high frequency of 26-40GHz, and high reliability under extreme environments.

[0059] A method for preparing the diamond-3C-SiC heterostructure, wherein the method for preparing the diamond-3C-SiC heterostructure is combined with... Figure 1 Includes the following steps:

[0060] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirements are screened as substrate materials, and the impurity content is controlled to obtain screened single-crystal diamond substrates.

[0061] S2, Chemical mechanical polishing of single crystal diamond substrate: The screened single crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain polished single crystal diamond substrate.

[0062] S3, which facilitates the pretreatment of substrate epitaxy 3C-SiC: The polished single crystal diamond substrate of S2 is boiled and acid-washed with a mixed acid solution, and then ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence to obtain the pretreated-polished single crystal diamond substrate.

[0063] S4. Preparation of silicon layer: Using silicon target material as silicon source, a silicon layer is deposited by magnetron sputtering on the pretreated-polished single crystal diamond substrate surface in S3 to obtain a non-single crystal silicon layer-single crystal diamond substrate.

[0064] S5, Synergistic preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 is subjected to high-temperature annealing treatment, a thin SiC transition layer is formed at the interface, and the non-single-crystal silicon is recrystallized to form single-crystal silicon, thus obtaining single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0065] S6. Growth of a single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer is grown on the surface of the single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate in S5 using a chemical vapor deposition equipment, resulting in a heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0066] Specifically, the high-quality single-crystal diamonds in S1 meet the product size requirements of 5×5mm and above, and the impurity content is controlled to be less than 1ppb.

[0067] Specifically, the roughness of the polished single-crystal diamond substrate in S2 is below 0.3 nm.

[0068] Specifically, in S3, the mixed acid solution is 95-98% H2SO4 and 96-99.7% HNO3 in a 3:1 ratio, and the boiling acid washing time is 25-35 min; the ultrasonic cleaning frequency is 40-200 Hz and the time is 10-20 min.

[0069] Specifically, in S4, the substrate temperature is controlled at 150-200℃, the sputtering power is 150-250W, the sputtering time is 160-200s, and the applied bias voltage is 100-150V.

[0070] Specifically, the high-temperature annealing treatment in S5 is carried out at a temperature of 1000-1300℃ for 1-5 minutes; the thickness of the thin SiC transition layer is 5-10 mm.

[0071] Specifically, in S6, hydrogen is used as the carrier gas, with a heating rate of 20-30℃ / min, and the temperature is raised to 830-860℃ and stabilized for 5-10 min for in-situ etching with hydrogen. The growth process of the single crystal 3C-SiC layer is as follows: the growth temperature is 1400-1550℃, the C raw materials include CH4, C2H4, and C3H8, and the Si raw materials can be SiH4, SiH3Cl, SiH2Cl2, SiHCl3, and SiCl4; the C / Si ratio of the C raw materials and Si raw materials is 0.1-10, and the growth rate is 1-30μm / h.

[0072] Example 1

[0073] This embodiment describes a diamond-3C-SiC heterostructure, which consists of a 0.957 mm thick diamond substrate, a 5 nm thick SiC transition layer, a 2 nm thick single-crystal silicon transition layer, and a 5 μm thick 3C-SiC layer, from bottom to top.

[0074] A method for preparing the diamond-3C-SiC heterostructure, wherein the method for preparing the diamond-3C-SiC heterostructure is combined with... Figure 1 Includes the following steps:

[0075] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirement of 5.0×5.0mm are screened as substrate materials, and the impurity content is controlled to be less than 1ppb to obtain screened single-crystal diamond substrates.

[0076] S2. Chemical mechanical polishing of single-crystal diamond substrate: The screened single-crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain a polished single-crystal diamond substrate with a roughness of less than 0.3 nm.

[0077] S3. Pretreatment for substrate epitaxy of 3C-SiC: The polished single-crystal diamond substrate of S2 is boiled and acid-washed using a mixed acid solution. The mixed acid solution is 98% H2SO4 and 99.7% HNO3 in a ratio of 3:1, and the boiling and acid washing time is 25-35 min. After that, it is ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence. The ultrasonic cleaning frequency of each is 100 Hz and the time is 15 min, to obtain the pretreated-polished single-crystal diamond substrate.

[0078] S4. Preparation of silicon layer: Using silicon target as silicon source, a silicon layer is deposited by magnetron sputtering on the surface of pretreated-polished single crystal diamond substrate in S3. The substrate temperature is controlled at 150℃, the sputtering power is 150W, the sputtering time is 160s, and the applied bias voltage is 100V to obtain non-single crystal silicon layer-single crystal diamond substrate.

[0079] S5, Synergistic preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 is subjected to high-temperature annealing treatment at a temperature of 1000℃ for 1 min; a thin SiC transition layer is formed at the interface, and the non-single-crystal silicon is recrystallized to form single-crystal silicon, thus obtaining a single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0080] S6. Growth of the single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer was grown on the surface of the single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate in S5 using chemical vapor deposition equipment. Hydrogen was used as the carrier gas, and the heating rate was 25℃ / min. The temperature was raised to 830℃ and stabilized for 10 min for in-situ etching with hydrogen. The growth process of the single-crystal 3C-SiC layer: The growth temperature was 1400℃, the C material was CH4, and the Si material could be SiH4. The C / Si ratio of the C material and the Si material was 0.5, and the growth rate was 5μm / h. A heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate was obtained.

[0081] In the diamond-3C-SiC heterostructure prepared in this embodiment, the average particle size of the SiC transition layer is 1 μm, the average particle size of the single-crystal silicon transition layer is 30 nm, and the 3C-SiC layer is single-crystal.

[0082] The diamond-3C-SiC heterostructure prepared in this embodiment exhibits the following properties: microtube density 9 cm⁻¹ -2 Surface roughness 1 nm, residual stress 0.1 GPa, electron mobility 910 cm⁻¹ 2 / V·s, effective thermal conductivity 1580W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 10kW / cm, high frequency of 26GHz, and ultra-high reliability under extreme environments.

[0083] Example 2

[0084] This embodiment presents a diamond-3C-SiC heterostructure, which consists of a 0.9 mm thick diamond substrate, a 10 nm thick SiC transition layer, a 5 nm thick single-crystal silicon transition layer, and a 10 μm thick 3C-SiC layer from bottom to top.

[0085] A method for preparing the diamond-3C-SiC heterostructure, wherein the method for preparing the diamond-3C-SiC heterostructure is combined with... Figure 1 Includes the following steps:

[0086] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirement of 5.0×5.0mm are screened as substrate materials, and the impurity content is controlled to be less than 1ppb to obtain screened single-crystal diamond substrates.

[0087] S2. Chemical mechanical polishing of single-crystal diamond substrate: The screened single-crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain a polished single-crystal diamond substrate with a roughness of less than 0.3 nm.

[0088] S3. Pretreatment for substrate epitaxy of 3C-SiC: The polished single-crystal diamond substrate of S2 is boiled and acid-washed using a mixed acid solution. The mixed acid solution is composed of 98% H2SO4 and 99.7% HNO3 in a 3:1 ratio, and the boiling and acid washing time is 35 min. After that, it is ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence. The ultrasonic cleaning frequency of each is 200 Hz and the time is 20 min, to obtain the pretreated-polished single-crystal diamond substrate.

[0089] S4. Preparation of silicon layer: Using silicon target as silicon source, a silicon layer is deposited by magnetron sputtering on the surface of pretreated-polished single crystal diamond substrate in S3. The substrate temperature is controlled at 200℃, the sputtering power is 250W, the sputtering time is 200s, and the applied bias voltage is 150V to obtain non-single crystal silicon layer-single crystal diamond substrate.

[0090] S5, Synergistic preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 is subjected to high-temperature annealing treatment at a temperature of 1300℃ for 10min; a thin SiC transition layer is formed at the interface, and the non-single-crystal silicon is recrystallized to form single-crystal silicon, thus obtaining a single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0091] S6. Growth of the single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer is grown on the surface of the single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate in S5 using chemical vapor deposition equipment. Hydrogen is used as the carrier gas, the heating rate is 30℃ / min, the temperature is raised to the growth temperature of 860℃ and stabilized for 10min, and in-situ etching is performed using hydrogen. The growth process of the single-crystal 3C-SiC layer: the growth temperature is 1550℃, the C raw material includes C2H4, and the Si raw material can be SiH3Cl; the C / Si ratio of the C raw material and the Si raw material is 7, and the growth rate is 6μm / h; a heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate is obtained.

[0092] In the diamond-3C-SiC heterostructure prepared in this embodiment, the average particle size of the SiC transition layer is 1 μm, the average particle size of the single-crystal silicon transition layer is 50 nm, and the 3C-SiC layer is single-crystal.

[0093] The properties of the diamond-3C-SiC heterostructure prepared in this embodiment are as follows: microtube density 6 cm⁻¹ -2 Surface roughness 0.5 nm, residual stress 0.1 GPa, electron mobility 950 cm⁻¹ 2 / V·s, effective thermal conductivity 1550W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 10kW / cm, high frequency of 40GHz, and ultra-high reliability under extreme environments.

[0094] Example 3

[0095] This embodiment describes a diamond-3C-SiC heterostructure, which consists of a 0.93 mm thick diamond substrate, a 7 nm thick SiC transition layer, a 3 nm thick single-crystal silicon transition layer, and an 8 μm thick 3C-SiC layer, from bottom to top.

[0096] A method for preparing the diamond-3C-SiC heterostructure, wherein the method for preparing the diamond-3C-SiC heterostructure is combined with... Figure 1 Includes the following steps:

[0097] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirement of 5.0×5.0mm are screened as substrate materials, and the impurity content is controlled to be less than 1ppb to obtain screened single-crystal diamond substrates.

[0098] S2. Chemical mechanical polishing of single-crystal diamond substrate: The screened single-crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain a polished single-crystal diamond substrate with a roughness of less than 0.3 nm.

[0099] S3. Pretreatment of substrate for epitaxial 3C-SiC: The polished single-crystal diamond substrate of S2 is boiled and acid-washed using a mixed acid solution. The mixed acid solution is composed of 98% H2SO4 and 99.7% HNO3 in a 3:1 ratio, and the boiling and acid washing time is 30 min. After that, it is ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence. The ultrasonic cleaning frequency of each is 100 Hz and the time is 15 min, to obtain the pretreated-polished single-crystal diamond substrate.

[0100] S4. Preparation of silicon layer: Using silicon target as silicon source, a silicon layer is deposited by magnetron sputtering on the surface of pretreated-polished single crystal diamond substrate in S3. The substrate temperature is controlled at 170℃, the sputtering power is 200W, the sputtering time is 180s, and the applied bias voltage is 120V to obtain non-single crystal silicon layer-single crystal diamond substrate.

[0101] S5, Synergistic preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 is subjected to high-temperature annealing treatment at a temperature of 1100℃ for 2 minutes; a thin SiC transition layer is formed at the interface, and the non-single-crystal silicon is recrystallized to form single-crystal silicon, thus obtaining a single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0102] S6. Growth of the single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer was grown on the surface of the single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate in S5 using chemical vapor deposition equipment. Hydrogen was used as the carrier gas, and the heating rate was 27℃ / min. The temperature was raised to 850℃ and stabilized for 7 min for in-situ etching with hydrogen. Growth process of the single-crystal 3C-SiC layer: The growth temperature was 1450℃. The C raw material included C3H8, and the Si raw material could be SiH2Cl2. The C / Si ratio of the C raw material and the Si raw material was 8, and the growth rate was 11μm / h. A heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate was obtained.

[0103] In the diamond-3C-SiC heterostructure prepared in this embodiment, the average particle size of the SiC transition layer is 3 μm, the average particle size of the single-crystal silicon transition layer is 100 nm, and the 3C-SiC layer is single-crystal.

[0104] The properties of the diamond-3C-SiC heterostructure prepared in this embodiment are as follows: microtube density 6 cm⁻¹ -2 Surface roughness 0.6 nm, residual stress 0.1 GPa, electron mobility 960 cm⁻¹ 2 / V·s, effective thermal conductivity 1730W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 10kW / cm, high frequency of 35GHz, and ultra-high reliability under extreme environments.

[0105] Example 4

[0106] This embodiment presents a diamond-3C-SiC heterostructure, which consists of a 0.96 mm thick diamond substrate, a 9 nm thick SiC transition layer, a 4 nm thick single-crystal silicon transition layer, and a 9 μm thick 3C-SiC layer from bottom to top.

[0107] A method for preparing the diamond-3C-SiC heterostructure, wherein the method for preparing the diamond-3C-SiC heterostructure is combined with... Figure 1 Includes the following steps:

[0108] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirement of 5.0×5.0mm are screened as substrate materials, and the impurity content is controlled to be less than 1ppb to obtain screened single-crystal diamond substrates.

[0109] S2. Chemical mechanical polishing of single-crystal diamond substrate: The screened single-crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain a polished single-crystal diamond substrate with a roughness of less than 0.3 nm.

[0110] S3. Pretreatment for substrate epitaxy of 3C-SiC: The polished single-crystal diamond substrate of S2 was boiled and acid-washed using a mixed acid solution. The mixed acid solution was composed of 98% H2SO4 and 99.7% HNO3 in a 3:1 ratio, and the boiling and acid washing time was 33 min. Afterwards, it was ultrasonically cleaned in acetone, anhydrous ethanol, and deionized water in sequence. The ultrasonic cleaning frequency of each was 150 Hz, and the time was 18 min, to obtain the pretreated-polished single-crystal diamond substrate.

[0111] S4. Preparation of silicon layer: Using silicon target as silicon source, a silicon layer is deposited by magnetron sputtering on the surface of pretreated-polished single crystal diamond substrate in S3. The substrate temperature is controlled at 180℃, the sputtering power is 230W, the sputtering time is 180s, and the applied bias voltage is 130V to obtain non-single crystal silicon layer-single crystal diamond substrate.

[0112] S5, Synergistic preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 is subjected to high-temperature annealing treatment at a temperature of 1200℃ for 9 minutes; a thin SiC transition layer is formed at the interface, and the non-single-crystal silicon is recrystallized to form single-crystal silicon, thus obtaining a single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0113] S6. Growth of the single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer was grown on the surface of the single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate in S5 using chemical vapor deposition equipment. Hydrogen was used as the carrier gas, and the heating rate was 29℃ / min. The temperature was raised to 855℃ and stabilized for 9 min for in-situ etching with hydrogen. Growth process of the single-crystal 3C-SiC layer: The growth temperature was 1500℃. The C material included CH4, and the Si material could be SiHCl3. The C / Si ratio of the C material and the Si material was 7, and the growth rate was 18μm / h. A heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate was obtained.

[0114] In the diamond-3C-SiC heterostructure prepared in this embodiment, the average particle size of the SiC transition layer is 1 μm, the average particle size of the single-crystal silicon transition layer is 150 nm, and the 3C-SiC layer is single-crystal.

[0115] The properties of the diamond-3C-SiC heterostructure prepared in this embodiment are: microtube density 7 cm⁻¹ -2 Surface roughness 0.6 nm, residual stress 0.1 GPa, electron mobility 1000 cm⁻¹ 2 / V·s, effective thermal conductivity 1750W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 10kW / cm, high frequency of 28GHz, and ultra-high reliability under extreme environments.

[0116] Example 5

[0117] This embodiment provides a diamond-3C-SiC heterostructure, which consists of a 1.0 mm thick diamond substrate, a 6 nm thick SiC transition layer, a 3 nm thick single-crystal silicon transition layer, and a 6 μm thick 3C-SiC layer, from bottom to top.

[0118] A method for preparing the diamond-3C-SiC heterostructure, wherein the method for preparing the diamond-3C-SiC heterostructure is combined with... Figure 1 Includes the following steps:

[0119] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirement of 5.0×5.0mm are screened as substrate materials, and the impurity content is controlled to be less than 1ppb to obtain screened single-crystal diamond substrates.

[0120] S2. Chemical mechanical polishing of single-crystal diamond substrate: The screened single-crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain a polished single-crystal diamond substrate with a roughness of less than 0.3 nm.

[0121] S3. Pretreatment of substrate for epitaxial 3C-SiC: The polished single-crystal diamond substrate of S2 is boiled and acid-washed using a mixed acid solution. The mixed acid solution is composed of 98% H2SO4 and 99.7% HNO3 in a 3:1 ratio, and the boiling and acid washing time is 27 min. After that, it is ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence. The ultrasonic cleaning frequency of each is 100 Hz and the time is 12 min, to obtain the pretreated-polished single-crystal diamond substrate.

[0122] S4. Preparation of silicon layer: Using silicon target material as silicon source, a silicon layer is deposited by magnetron sputtering on the surface of pretreated-polished single crystal diamond substrate in S3. The substrate temperature is controlled at 160℃, the sputtering power is 170W, the sputtering time is 175s, and the applied bias voltage is 125V to obtain non-single crystal silicon layer-single crystal diamond substrate.

[0123] S5, Co-preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 was subjected to high-temperature annealing at 1150℃ for 1.5 min; a thin SiC transition layer was formed at the interface, and the non-single-crystal silicon was recrystallized to form single-crystal silicon, thus obtaining the single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0124] S6. Growth of the single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer was grown on the surface of the single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate in S5 using chemical vapor deposition equipment. Hydrogen was used as the carrier gas, and the heating rate was 28℃ / min. The temperature was raised to 835℃ and stabilized for 6 min for in-situ etching with hydrogen. Growth process of the single-crystal 3C-SiC layer: The growth temperature was 1450℃. The C material included CH4, and the Si material could be SiCl4. The C / Si ratio of the C material and the Si material was 8, and the growth rate was 20μm / h. A heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate was obtained.

[0125] In the diamond-3C-SiC heterostructure prepared in this embodiment, the average particle size of the SiC transition layer is 3 μm, the average particle size of the single-crystal silicon transition layer is 300 nm, and the 3C-SiC layer is single-crystal.

[0126] The diamond-3C-SiC heterostructure prepared in this embodiment exhibits the following properties: microtube density 7.5 cm³. -2Surface roughness 0.5 nm, residual stress 0.08 GPa, electron mobility 930 cm⁻¹ 2 / V·s, effective thermal conductivity 1600W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 10kW / cm, high frequency of 32GHz, and ultra-high reliability under extreme environments.

[0127] Example 6

[0128] This embodiment describes a diamond-3C-SiC heterostructure, which consists of a 0.6 mm thick diamond substrate, a 9 nm thick SiC transition layer, a 4 nm thick single-crystal silicon transition layer, and an 8 μm thick 3C-SiC layer, from bottom to top.

[0129] A method for preparing the diamond-3C-SiC heterostructure, wherein the method for preparing the diamond-3C-SiC heterostructure is combined with... Figure 1 Includes the following steps:

[0130] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirement of 5.0×5.0mm are screened as substrate materials, and the impurity content is controlled to be less than 1ppb to obtain screened single-crystal diamond substrates.

[0131] S2. Chemical mechanical polishing of single-crystal diamond substrate: The screened single-crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain a polished single-crystal diamond substrate with a roughness of less than 0.3 nm.

[0132] S3. Pretreatment of substrate for epitaxial 3C-SiC: The polished single-crystal diamond substrate of S2 is boiled and acid-washed with a mixed acid solution. The mixed acid solution is 95% H2SO4 and 96% HNO3 in a ratio of 3:1, and the boiling and acid washing time is 32 min. Then, it is ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence. The ultrasonic cleaning frequency of each is 100 Hz and the time is 17 min, to obtain the pretreated-polished single-crystal diamond substrate.

[0133] S4. Preparation of silicon layer: Using silicon target as silicon source, a silicon layer is deposited by magnetron sputtering on the surface of pretreated-polished single crystal diamond substrate in S3. The substrate temperature is controlled at 190℃, the sputtering power is 240W, the sputtering time is 190s, and the applied bias voltage is 130V to obtain non-single crystal silicon layer-single crystal diamond substrate.

[0134] S5, Synergistic preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 is subjected to high-temperature annealing treatment at a temperature of 1250℃ for 3 minutes; a thin SiC transition layer is formed at the interface, and the non-single-crystal silicon is recrystallized to form single-crystal silicon, thus obtaining a single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0135] S6. Growth of the single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer was grown on the surface of the single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate in S5 using chemical vapor deposition equipment. Hydrogen was used as the carrier gas, and the heating rate was 29℃ / min. The temperature was raised to 845℃ and stabilized for 9 min for in-situ etching with hydrogen. Growth process of the single-crystal 3C-SiC layer: The growth temperature was 1470℃. The C raw material included C2H4, and the Si raw material could be SiCl4. The C / Si ratio of the C raw material and the Si raw material was 9, and the growth rate was 25μm / h. A heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate was obtained.

[0136] In the diamond-3C-SiC heterostructure prepared in this embodiment, the average particle size of the SiC transition layer is 2 μm, the average particle size of the single-crystal silicon transition layer is 200 nm, and the 3C-SiC layer is single-crystal.

[0137] The diamond-3C-SiC heterostructure prepared in this embodiment exhibits the following properties: microtube density 8.5 cm³. -2 Surface roughness 0.65 nm, residual stress 0.1 GPa, electron mobility 900 cm⁻¹ 2 / V·s, effective thermal conductivity 1650W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 10kW / cm, high frequency of 35GHz, and ultra-high reliability under extreme environments.

[0138] Example 7

[0139] This embodiment provides a diamond-3C-SiC heterostructure, which consists of a 0.65 mm thick diamond substrate, a 9.5 nm thick SiC transition layer, a 5 nm thick single-crystal silicon transition layer, and a 7 μm thick 3C-SiC layer from bottom to top.

[0140] A method for preparing the diamond-3C-SiC heterostructure, wherein the method for preparing the diamond-3C-SiC heterostructure is combined with... Figure 1 Includes the following steps:

[0141] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirement of 5.0×5.0mm are screened as substrate materials, and the impurity content is controlled to be less than 1ppb to obtain screened single-crystal diamond substrates.

[0142] S2. Chemical mechanical polishing of single-crystal diamond substrate: The screened single-crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain a polished single-crystal diamond substrate with a roughness of less than 0.3 nm.

[0143] S3. Pretreatment of substrate for epitaxial 3C-SiC: The polished single-crystal diamond substrate of S2 is boiled and acid-washed using a mixed acid solution. The mixed acid solution is composed of 98% H2SO4 and 99.7% HNO3 in a 3:1 ratio, and the boiling and acid washing time is 30 min. After that, it is ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence. The ultrasonic cleaning frequency of each is 100 Hz and the time is 18 min, to obtain the pretreated-polished single-crystal diamond substrate.

[0144] S4. Preparation of silicon layer: Using silicon target as silicon source, a silicon layer is deposited by magnetron sputtering on the surface of pretreated-polished single crystal diamond substrate in S3. The substrate temperature is controlled at 150℃, the sputtering power is 230W, the sputtering time is 200s, and the applied bias voltage is 125V to obtain non-single crystal silicon layer-single crystal diamond substrate.

[0145] S5, Co-preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 was subjected to high-temperature annealing treatment at a temperature of 1240℃ for 2.5 min; a thin SiC transition layer was formed at the interface, and the non-single-crystal silicon was recrystallized to form single-crystal silicon, thus obtaining a single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0146] S6. Growth of the single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer was grown on the surface of the single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate in S5 using chemical vapor deposition equipment. Hydrogen was used as the carrier gas, and the heating rate was 28℃ / min. The temperature was raised to 850℃ and stabilized for 8min for in-situ etching with hydrogen. Growth process of the single-crystal 3C-SiC layer: The growth temperature was 1440℃. The C raw material included C2H4, and the Si raw material could be SiCl4. The C / Si ratio of the C raw material and the Si raw material was 8, and the growth rate was 23μm / h. A heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate was obtained.

[0147] In the diamond-3C-SiC heterostructure prepared in this embodiment, the average particle size of the SiC transition layer is 1 μm, the average particle size of the single-crystal silicon transition layer is 100 nm, and the 3C-SiC layer is single-crystal.

[0148] The diamond-3C-SiC heterostructure prepared in this embodiment exhibits the following properties: microtube density 7.5 cm³. -2 Surface roughness 0.08 nm, residual stress 0.1 GPa, electron mobility 900 cm⁻¹ 2 / V·s, effective thermal conductivity 1600W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 10kW / cm, high frequency of 30GHz, and ultra-high reliability under extreme environments.

[0149] Example 8

[0150] This embodiment provides a diamond-3C-SiC heterostructure, which consists of a 0.75 mm thick diamond substrate, a 7 nm thick SiC transition layer, a 2 nm thick single-crystal silicon transition layer, and a 6 μm thick 3C-SiC layer from bottom to top.

[0151] A method for preparing the diamond-3C-SiC heterostructure, wherein the method for preparing the diamond-3C-SiC heterostructure is combined with... Figure 1 Includes the following steps:

[0152] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirement of 5.0×5.0mm are screened as substrate materials, and the impurity content is controlled to be less than 1ppb to obtain screened single-crystal diamond substrates.

[0153] S2. Chemical mechanical polishing of single-crystal diamond substrate: The screened single-crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain a polished single-crystal diamond substrate with a roughness of less than 0.3 nm.

[0154] S3. Pretreatment for substrate epitaxy of 3C-SiC: The polished single-crystal diamond substrate of S2 is boiled and acid-washed using a mixed acid solution. The mixed acid solution is composed of 96% H2SO4 and 99.7% HNO3 in a 3:1 ratio, and the boiling and acid washing time is 32 min. After that, it is ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence. The ultrasonic cleaning frequency of each is 100 Hz and the time is 20 min, to obtain the pretreated-polished single-crystal diamond substrate.

[0155] S4. Preparation of silicon layer: Using silicon target as silicon source, a silicon layer is deposited by magnetron sputtering on the surface of pretreated-polished single crystal diamond substrate in S3. The substrate temperature is controlled at 185℃, the sputtering power is 230W, the sputtering time is 180s, and the applied bias voltage is 120V to obtain non-single crystal silicon layer-single crystal diamond substrate.

[0156] S5, Synergistic preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 is subjected to high-temperature annealing treatment at a temperature of 1220℃ for 4 minutes; a thin SiC transition layer is formed at the interface, and the non-single-crystal silicon is recrystallized to form single-crystal silicon, thus obtaining a single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0157] S6. Growth of the single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer was grown on the surface of the single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate in S5 using chemical vapor deposition equipment. Hydrogen was used as the carrier gas, and the heating rate was 26℃ / min. The temperature was raised to 850℃ and stabilized for 7 min for in-situ etching with hydrogen. Growth process of the single-crystal 3C-SiC layer: The growth temperature was 1520℃. The C material included CH4, and the Si material could be SiCl4. The C / Si ratio of the C material and the Si material was 7, and the growth rate was 20μm / h. A heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate was obtained.

[0158] In the diamond-3C-SiC heterostructure prepared in this embodiment, the average particle size of the SiC transition layer is 1 μm, the average particle size of the single-crystal silicon transition layer is 150 nm, and the 3C-SiC layer is single-crystal.

[0159] The diamond-3C-SiC heterostructure prepared in this embodiment exhibits the following properties: microtube density 6.5 cm³. -2 Surface roughness 0.7 nm, residual stress 0.1 GPa, electron mobility 940 cm⁻¹ 2 / V·s, effective thermal conductivity 1700W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 10kW / cm, high frequency of 35GHz, and ultra-high reliability under extreme environments.

[0160] Example 9

[0161] This embodiment describes a diamond-3C-SiC heterostructure, which consists of a 0.75 mm thick diamond substrate, a 9 nm thick SiC transition layer, a 4 nm thick single-crystal silicon transition layer, and an 8 μm thick 3C-SiC layer, from bottom to top.

[0162] A method for preparing the diamond-3C-SiC heterostructure, wherein the method for preparing the diamond-3C-SiC heterostructure is combined with... Figure 1 Includes the following steps:

[0163] S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirement of 5.0×5.0mm are screened as substrate materials, and the impurity content is controlled to be less than 1ppb to obtain screened single-crystal diamond substrates.

[0164] S2. Chemical mechanical polishing of single-crystal diamond substrate: The screened single-crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain a polished single-crystal diamond substrate with a roughness of less than 0.3 nm.

[0165] S3. Pretreatment for substrate epitaxy of 3C-SiC: The polished single-crystal diamond substrate of S2 is boiled and acid-washed using a mixed acid solution. The mixed acid solution is composed of 98% H2SO4 and 99.7% HNO3 in a 3:1 ratio, and the boiling and acid washing time is 32 min. After that, it is ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence. The ultrasonic cleaning frequency of each is 100 Hz and the time is 15 min, to obtain the pretreated-polished single-crystal diamond substrate.

[0166] S4. Preparation of silicon layer: Using silicon target as silicon source, a silicon layer is deposited by magnetron sputtering on the surface of pretreated-polished single crystal diamond substrate in S3. The substrate temperature is controlled at 200℃, the sputtering power is 240W, the sputtering time is 200s, and the applied bias voltage is 130V to obtain non-single crystal silicon layer-single crystal diamond substrate.

[0167] S5, Synergistic preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 is subjected to high-temperature annealing treatment at a temperature of 1200℃ for 3 minutes; a thin SiC transition layer is formed at the interface, and the non-single-crystal silicon is recrystallized to form single-crystal silicon, thus obtaining a single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

[0168] S6. Growth of the single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer is grown on the surface of the single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate in S5 using chemical vapor deposition equipment. Hydrogen is used as the carrier gas, the heating rate is 30℃ / min, the temperature is raised to 845℃ and stabilized for 10min, and in-situ etching is performed using hydrogen. Growth process of the single-crystal 3C-SiC layer: The growth temperature is 1550℃, the C material includes CH4, and the Si material can be SiH4; the C / Si ratio of the C material and the Si material is 10, and the growth rate is 29μm / h. A heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon transition layer-SiC transition layer-single-crystal diamond substrate is obtained.

[0169] In the diamond-3C-SiC heterostructure prepared in this embodiment, the average particle size of the SiC transition layer is 1 μm, the average particle size of the single-crystal silicon transition layer is 120 nm, and the 3C-SiC layer is single-crystal.

[0170] The diamond-3C-SiC heterostructure prepared in this embodiment exhibits the following properties: microtube density 8.5 cm³. -2 Surface roughness 0.8 nm, residual stress 0.1 GPa, electron mobility 880 cm⁻¹ 2 / V·s, effective thermal conductivity 1590W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 10kW / cm, high frequency of 35GHz, and ultra-high reliability under extreme environments.

[0171] The above-mentioned solution proposes a diamond-3C-SiC heterostructure and its preparation method, which can solve the technical problems in the existing cubic silicon carbide (3C-SiC) preparation technology, such as the difficulty in obtaining high-quality single crystal substrates, especially the quality and performance defects of 3C-SiC films epitaxially grown on silicon substrates, the inability to directly grow 3C-SiC films on diamond substrates, and the poor epitaxial quality and high stress in 3C-SiC / Si structures caused by lattice and thermal mismatch.

[0172] The method of this invention, through the screening and chemical mechanical polishing of single-crystal diamond substrates, can reduce the surface roughness of the diamond substrates to an atomically smooth and damage-free surface, ensuring the orientation and consistency of single-crystal epitaxial growth.

[0173] The method of the present invention, by taking advantage of the pretreatment of the 3C-SiC substrate, enables chemical cleaning and surface terminalization, improves the uniformity and adhesion of the nucleation layer, reduces interface defects and amorphous phases, thereby improving the crystallization quality of the thin film.

[0174] The method of the present invention can alleviate lattice mismatch and provide a suitable chemical nucleation surface by preparing a silicon layer.

[0175] The method of this invention enables the synergistic preparation of a single-crystal silicon layer transition layer and a SiC transition layer, thereby achieving a gradient transition in lattice constant and thermal expansion coefficient, as well as "functional stratification" that filters and blocks defects.

[0176] The method of the present invention can control the growth mode and step flow surface morphology of the sample by adjusting the carbon-silicon ratio and process parameters during the growth of single crystal 3C-SiC layer, and can also suppress the generation of specific defects.

[0177] In summary, compared with traditional 3C-SiC preparation methods, the method of this invention constructs a composite transition layer on the diamond surface consisting of an in-situ reactive SiC layer and a recrystallized silicon layer through an innovative "magnetron sputtering silicon layer + in-situ solid-state reaction annealing" process. A 3C-SiC layer is then grown on this composite transition layer. This method can effectively reduce interface energy and effectively relax mismatch stress, solving the core obstacle of heterogeneous integration. It is simple to operate, low in cost, low in energy consumption, and high in efficiency, which is conducive to large-scale industrial production and promotion.

[0178] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0179] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0180] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0181] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A diamond-3C-SiC heterostructure, characterized in that, The diamond-3C-SiC heterostructure consists of a 0.5-1.0 mm thick diamond substrate, a 5-10 nm thick SiC transition layer, a 2-5 nm thick single-crystal silicon transition layer, and a 5-10 μm thick 3C-SiC layer, from bottom to top.

2. The diamond-3C-SiC heterostructure according to claim 1, characterized in that, In the diamond-3C-SiC heterostructure, the average particle size of the SiC transition layer is 1-10 μm, the average particle size of the single-crystal silicon transition layer is 30-300 nm, and the 3C-SiC layer is single-crystal 3C-SiC.

3. The diamond-3C-SiC heterostructure according to claim 1, characterized in that, The properties of the diamond-3C-SiC heterostructure are: microtube density ≤10 cm⁻¹ -2 Surface roughness ≤ 1 nm, residual stress ≤ 0.1 GPa, electron mobility ≥ 800 cm⁻¹ 2 / V·s, effective thermal conductivity ≥1500W / mK; the diamond-3C-SiC heterostructure is suitable for semiconductor devices with ultra-high power density of 1-10kW / cm, high frequency of 26-40GHz, and high reliability under extreme environments.

4. A method for preparing a diamond-3C-SiC heterostructure based on claim 1, characterized in that, The preparation method of the diamond-3C-SiC heterostructure includes the following steps: S1. Screening of single-crystal diamond substrates: High-quality single-crystal diamonds that meet the product size requirements are screened as substrate materials, and the impurity content is controlled to obtain screened single-crystal diamond substrates. S2, Chemical mechanical polishing of single crystal diamond substrate: The screened single crystal diamond substrate of S1 is chemically mechanically polished with silicon dioxide / silicon powder polishing slurry to obtain polished single crystal diamond substrate. S3, which facilitates the pretreatment of substrate epitaxy 3C-SiC: The polished single crystal diamond substrate of S2 is boiled and acid-washed with a mixed acid solution, and then ultrasonically cleaned in acetone, anhydrous ethanol and deionized water in sequence to obtain the pretreated-polished single crystal diamond substrate. S4. Preparation of silicon layer: Using silicon target material as silicon source, a silicon layer is deposited by magnetron sputtering on the pretreated-polished single crystal diamond substrate surface in S3 to obtain a non-single crystal silicon layer-single crystal diamond substrate. S5, Synergistic preparation of single-crystal silicon layer transition layer-SiC transition layer: The non-single-crystal silicon layer-single-crystal diamond substrate of S4 is subjected to high-temperature annealing treatment, a thin SiC transition layer is formed at the interface, and the non-single-crystal silicon is recrystallized to form single-crystal silicon, thus obtaining single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate. S6. Growth of a single-crystal 3C-SiC layer: A single-crystal 3C-SiC layer is grown on the surface of the single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate in S5 using a chemical vapor deposition equipment, resulting in a heterostructure product of single-crystal 3C-SiC layer-single-crystal silicon layer transition layer-SiC transition layer-single-crystal diamond substrate.

5. The method for preparing the diamond-3C-SiC heterostructure according to claim 4, characterized in that, The high-quality single-crystal diamond in S1 meets the product size requirements of 5×5mm and above, and the impurity content is controlled to be less than 1ppb.

6. The method for preparing the diamond-3C-SiC heterostructure according to claim 4, characterized in that, The roughness of the polished single-crystal diamond substrate in S2 is below 0.3 nm.

7. The method for preparing the diamond-3C-SiC heterostructure according to claim 4, characterized in that, In S3, the mixed acid solution consists of 95-98% H2SO4 and 96-99.7% HNO3 in a 3:1 ratio, with a boiling pickling time of 25-35 minutes; the ultrasonic cleaning frequency is 40-200 Hz, and the time is 10-20 minutes.

8. The method for preparing the diamond-3C-SiC heterostructure according to claim 4, characterized in that, In S4, the substrate temperature is controlled at 150-200℃, the sputtering power is 150-250W, the sputtering time is 160-200s, and the applied bias voltage is 100-150V.

9. The method for preparing the diamond-3C-SiC heterostructure according to claim 4, characterized in that, The high-temperature annealing treatment in S5 is carried out at a temperature of 1000-1300℃ for 1-5 minutes; the thickness of the thin SiC transition layer is 5-10 mm.

10. The method for preparing the diamond-3C-SiC heterostructure according to claim 4, characterized in that, In S6, hydrogen is used as the carrier gas, and the heating rate is 20-30℃ / min. The temperature is raised to 830-860℃ and stabilized for 5-10 min for in-situ etching with hydrogen. The growth process of the single crystal 3C-SiC layer is as follows: the growth temperature is 1400-1550℃, the C raw materials include CH4, C2H4, and C3H8, and the Si raw materials can be SiH4, SiH3Cl, SiH2Cl2, SiHCl3, and SiCl4. The C / Si ratio of the C raw materials and Si raw materials is 0.1-10, and the growth rate is 1-30μm / h.

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