Inverters and methods of making the same

Abstract

This invention discloses an inverter and its fabrication method. The inverter includes: a substrate; a gate, including a first gate and a second gate disposed on the substrate and spaced apart; a gate dielectric layer, including a first gate dielectric layer stacked on the substrate, the first gate, and the second gate, and a second gate dielectric layer stacked on the first gate dielectric layer, wherein the second gate dielectric layer is at least partially located in the region directly above the second gate; a channel layer, including a first channel layer stacked on the first gate dielectric layer and a second channel layer stacked on the second gate dielectric layer; a first source, a first drain, a second source, and a second drain stacked on the first gate dielectric layer, wherein the second source is electrically connected to the second gate. This invention fabricates a second gate dielectric layer on the first gate dielectric layer on the second gate, utilizing the electronegativity of F ions in the second gate dielectric layer to achieve region-selective doping of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to an inverter and its fabrication method. Background Technology

[0002] Two-dimensional materials have broad application prospects in optics, electronics and other fields due to their excellent properties. Compared with traditional channel materials, two-dimensional materials can achieve excellent electrostatic gate control capabilities, suppress short-channel effects, and maintain good semiconductor properties and electromigration properties.

[0003] CMOS inverters using two-dimensional material layers as channel layers still face several challenges and limitations in design and fabrication. N-type devices typically use MoS2 as the channel layer, while other materials, such as WSe2, MoTe2, and BP, serve as P-type channel layers. While integrating these two materials can effectively achieve inverter functionality, this undoubtedly increases transmission and processing time, experimental complexity, and makes it difficult to match the performance of N-type and P-type devices. A good approach is to achieve the corresponding functionality through in-situ controlled selective doping during growth, but yield and performance are difficult to control.

[0004] Metal fluorides possess excellent properties such as high dielectric constant and large bandgap, making them promising candidates for applications in semiconductor device technology. Calcium fluoride (CaF2) is one of the most distinctive metal fluorides, capable of serving as an ion-gate dielectric. Compared to traditional oxide gate dielectrics, calcium fluoride exhibits… <111> The crystal plane terminates with inert F, allowing for the formation of clean quasi-van der Waals interfaces with two-dimensional materials. Furthermore, CaF₂ possesses a high dielectric constant (~6.8) and a large band gap (12.1 eV), enabling large-scale fabrication. Because the material terminates with F, and F has strong electronegativity, significant charge accumulation occurs at the interface with the channel layer, inducing further charge generation within the channel layer.

[0005] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide an inverter and its fabrication method. Summary of the Invention

[0006] The purpose of this invention is to provide an inverter and its manufacturing method, which can obtain an inverter with excellent performance and better stability.

[0007] To achieve the above objectives, an embodiment of the present invention provides the following technical solution:

[0008] An inverter, the inverter comprising:

[0009] Substrate;

[0010] The gate includes a first gate and a second gate located on the substrate and spaced apart from each other;

[0011] The gate dielectric layer includes a first gate dielectric layer stacked on the substrate, the first gate, and the second gate, and a second gate dielectric layer stacked on the first gate dielectric layer, wherein the second gate dielectric layer is at least partially located in the region directly above the second gate.

[0012] The channel layer includes a first channel layer stacked on a first gate dielectric layer and a second channel layer stacked on a second gate dielectric layer, wherein the first channel layer is at least partially located in the region directly above the first gate, and the second channel layer is at least partially located in the region directly above the second gate.

[0013] A first source, a first drain, a second source, and a second drain are stacked on the first gate dielectric layer. The first drain and the second source are located on the first gate dielectric layer between the first channel layer and the second channel layer and are electrically connected to the first channel layer and the second channel layer, respectively. The first source is located on the side of the first channel layer away from the first drain and is electrically connected to the first channel layer. The second drain is located on the side of the second channel layer away from the second source and is electrically connected to the second channel layer. The second source is electrically connected to the second gate.

[0014] In one embodiment, the first drain and the second source are connected to form a common electrode. Along the extension direction of the common electrode, one end of the common electrode is connected to one end of the second gate through a conductive portion, and the second source and the second gate are electrically connected through the conductive portion.

[0015] In one embodiment, the upper surface of the first gate dielectric layer is stepped.

[0016] In one embodiment, the upper surface of the first gate dielectric layer is planar.

[0017] In one embodiment, the first source and the first drain are partially covered on the first channel layer, and the second source and the second drain are partially covered on the second channel layer.

[0018] In one embodiment, the first channel layer and the second channel layer are N-type two-dimensional material layers or the first channel layer and the second channel layer are P-type two-dimensional material layers, and a quasi-van der Waals interface is formed between the second gate dielectric layer and the second channel layer.

[0019] In one embodiment, the first gate dielectric layer is one or more of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer; and / or,

[0020] The second gate dielectric layer is one or more of a strontium fluoride layer, a barium fluoride layer, or a calcium fluoride layer.

[0021] In one embodiment, the first gate serves as the input terminal of the inverter, the second source is connected to the second gate and serves as the output terminal of the inverter, the second drain is connected to an external power supply, and the first source is grounded.

[0022] Another embodiment of the present invention provides the following technical solution:

[0023] A method for fabricating an inverter, the method comprising the following steps:

[0024] A substrate is provided, and a first gate and a second gate spaced apart are formed on the substrate;

[0025] A first gate dielectric layer is fabricated on the substrate, the first gate, and the second gate;

[0026] A second gate dielectric layer is fabricated on the first gate dielectric layer, wherein the second gate dielectric layer is at least partially located in the region directly above the second gate.

[0027] A first channel layer and a second channel layer are fabricated, wherein the first channel layer is at least partially located in the region directly above the first gate, and the second channel layer is at least partially located in the region directly above the second gate.

[0028] A first source, a first drain, a second source, and a second drain are fabricated on a first gate dielectric layer. The first drain and the second source are located on the first gate dielectric layer between the first channel layer and the second channel layer and are electrically connected to the first channel layer and the second channel layer, respectively. The first source is located on the side of the first channel layer away from the first drain and is electrically connected to the first channel layer. The second drain is located on the side of the second channel layer away from the second source and is electrically connected to the second channel layer. The second source is electrically connected to the second gate.

[0029] In one embodiment, fabricating a second gate dielectric layer on a first gate dielectric layer includes the following steps:

[0030] A patterned photoresist layer is prepared on the first gate dielectric layer to expose at least the region of the first gate dielectric layer directly above the second gate.

[0031] A second gate dielectric layer is deposited on the photoresist layer and the first gate dielectric layer;

[0032] Remove the photoresist layer and the second gate dielectric layer on the photoresist layer.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] This invention fabricates a second gate dielectric layer on the first gate dielectric layer on the second gate. By utilizing the electronegativity of F ions in the second gate dielectric layer, region-selective doping of the device is achieved, resulting in an inverter with a larger on / off ratio. It can maintain the original off-state current and has a significant shift in threshold voltage, providing a simple and effective method for improving the performance of large-size transistors. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the inverter structure in Embodiment 1 of the present invention;

[0037] Figure 2 This is a circuit diagram of the inverter in Embodiment 1 of the present invention;

[0038] Figures 3a-3e This is a process flow diagram of the method for preparing the inverter in Embodiment 1 of the present invention;

[0039] Figure 4 This is a graph showing the output characteristic curve of the inverter in Embodiment 1 of the present invention;

[0040] Figure 5 This is a graph showing the transfer characteristics of the inverter in Embodiment 1 of the present invention;

[0041] Figure 6 This is a cross-sectional TEM image of the CaF2 selected region of the inverter in Embodiment 1 of the present invention;

[0042] Figure 7 This is a schematic diagram of the inverter in Embodiment 2 of the present invention.

[0043] Explanation of key figure labels:

[0044] 10 - Substrate, 201 - First gate dielectric layer, 202 - Second gate dielectric layer, 301 - First channel layer, 302 - Second channel layer, 4011 - First gate, 4012 - Second gate, 4021 - First source, 4022 - First drain, 4031 - Second source, 4032 - Second drain, 404 - Common electrode. Detailed Implementation

[0045] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0046] This invention discloses an inverter, comprising:

[0047] Substrate;

[0048] The gate includes a first gate and a second gate located on the substrate and spaced apart from each other;

[0049] The gate dielectric layer includes a first gate dielectric layer stacked on the substrate, the first gate, and the second gate, and a second gate dielectric layer stacked on the first gate dielectric layer, wherein the second gate dielectric layer is at least partially located in the region directly above the second gate.

[0050] The channel layer includes a first channel layer stacked on a first gate dielectric layer and a second channel layer stacked on a second gate dielectric layer, wherein the first channel layer is at least partially located in the region directly above the first gate and the second channel layer is at least partially located in the region directly above the second gate.

[0051] A first source, a first drain, a second source, and a second drain are stacked on the first gate dielectric layer. The first drain and the second source are located on the first gate dielectric layer between the first channel layer and the second channel layer and are electrically connected to the first channel layer and the second channel layer, respectively. The first source is located on the side of the first channel layer away from the first drain and is electrically connected to the first channel layer. The second drain is located on the side of the second channel layer away from the second source and is electrically connected to the second channel layer. The second source is electrically connected to the second gate.

[0052] This invention also discloses a method for fabricating an inverter, comprising the following steps:

[0053] A substrate is provided, and a first gate and a second gate spaced apart are formed on the substrate;

[0054] A first gate dielectric layer is fabricated on the substrate, the first gate, and the second gate;

[0055] A second gate dielectric layer is fabricated on the first gate dielectric layer, wherein the second gate dielectric layer is at least partially located in the region directly above the second gate.

[0056] A first channel layer and a second channel layer are fabricated, wherein the first channel layer is at least partially located in the region directly above the first gate, and the second channel layer is at least partially located in the region directly above the second gate;

[0057] The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are formed on the first gate dielectric layer. The first drain electrode and the second source electrode are located on the first gate dielectric layer between the first channel layer and the second channel layer and are electrically connected to the first channel layer and the second channel layer respectively. The first source electrode is located on a side of the first channel layer away from the first drain electrode and is electrically connected to the first channel layer. The second drain electrode is located on a side of the second channel layer away from the second source electrode and is electrically connected to the second channel layer. The second source electrode is electrically connected to the second gate electrode.

[0058] Example 1:

[0059] Refer Figure 1 As shown, the inverter in this embodiment includes:

[0060] Substrate 10;

[0061] Gate electrodes, including a first gate electrode 4011 and a second gate electrode 401 which are located on the substrate and arranged at intervals;

[0062] Gate dielectric layers, including a first gate dielectric layer 201 laminated on the substrate 10, the first gate electrode 4011, and the second gate electrode 4012, and a second gate dielectric layer 202 laminated on the first gate dielectric layer 201. The second gate dielectric layer 202 is at least partially located in the region directly above the second gate electrode 4012;

[0063] Channel layers, including a first channel layer 301 laminated on the first gate dielectric layer 201, and a second channel layer 302 laminated on the second gate dielectric layer 202. The first channel layer 301 is at least partially located in the region directly above the first gate electrode 4011, and the second channel layer 302 is at least partially located in the region directly above the second gate electrode 4012;

[0064] A first source electrode 4021, a first drain electrode 4022, a second source electrode 4031, and a second drain electrode 4032 laminated on the first gate dielectric layer 201. The first drain electrode 4022 and the second source electrode 4031 are located on the first gate dielectric layer 201 between the first channel layer 301 and the second channel layer 302 and are electrically connected to the first channel layer 301 and the second channel layer 302 respectively. The first source electrode 4021 is located on a side of the first channel layer 301 away from the first drain electrode 4022 and is electrically connected to the first channel layer 301. The second drain electrode 4032 is located on a side of the second channel layer 302 away from the second source electrode 4031 and is electrically connected to the second channel layer 302. The second source electrode 4031 is electrically connected to the second gate electrode 4012.

[0065] Preferably, the substrate 10 in this embodiment is a silicon oxide substrate.

[0066] Exemplarily, the thicknesses of the first gate electrode 4011 and the second gate electrode 4012 in this embodiment are equal.

[0067] In this embodiment, the upper surface of the first gate dielectric layer 201 is stepped. The thickness of the first gate dielectric layer 201 on the surface of the substrate 10 is equal to the thickness of the first gate dielectric layer 201 on the surface of the first gate 4011 and the second gate 4012. The second gate dielectric layer 202 covers the first gate dielectric layer 201 on the upper surface and sidewall of the second gate 4012.

[0068] The first gate dielectric layer 201 is one or more of the insulating dielectric layers such as silicon oxide, silicon nitride, aluminum oxide, or hafnium oxide, preferably a hafnium oxide (HfO2) layer. Hafnium oxide, as a high-k material, has a higher dielectric constant and superior electrical properties, which can increase the thickness of the dielectric layer while maintaining capacitance, effectively improving gate leakage current. The second gate dielectric layer 202 is one or more of the fluoride insulating dielectric layers such as strontium fluoride, barium fluoride, or calcium fluoride, preferably a calcium fluoride (CaF2) layer.

[0069] Furthermore, the channel layer is an N-type two-dimensional material layer or a P-type two-dimensional material layer, and a quasi-van der Waals cross section is formed between the second gate dielectric layer 202 and the second channel layer 302.

[0070] Specifically, in this embodiment, both the first channel layer 301 and the second channel layer 302 are N-type two-dimensional material layers, preferably molybdenum disulfide (MoS2) layers. The first channel layer 301 and the second channel layer 302 partially cover the first gate dielectric layer 201 above the first gate 4011 and the second gate dielectric layer 202 above the second gate 4012, respectively. In this embodiment, the projections of the first channel layer 301 and the second channel layer 302 onto the gate dielectric layer are both rectangles, with a length greater than or equal to 2 μm and a width greater than or equal to 2 μm.

[0071] In this embodiment, the first source 4021 and the first drain 4022 partially cover the first channel layer 301, and the second source 4031 and the second drain 4032 partially cover the second channel layer 302. Due to the influence of the fabrication process, in this embodiment, the first source 4021 and the first drain 4022 do not cover the first gate dielectric layer 201 on the sidewall of the first gate 4011, and the second source 4031 and the second drain 4032 do not cover the second gate dielectric layer 202 on the sidewall of the second gate 4012 on the first gate dielectric layer 201. The connection between the top and bottom of the first source 4021, the first drain 4022, the second source 4031, and the second drain 4032 forms an obtuse angle with the bottom.

[0072] It should be understood that there are no specific requirements for the shapes of the first source electrode 4021, the first drain electrode 4022, the second source electrode 4031, and the second drain electrode 4032, as long as they can achieve the function of electrical connection with the corresponding channel layer. The gate electrode, the first source electrode 4021, the first drain electrode 4022, the second source electrode 4031, and the second drain electrode 4032 in this embodiment are conventional conductive electrodes, which will not be elaborated here.

[0073] Furthermore, as shown in Figure 2 , in this embodiment, the first drain electrode 4022 is connected to the second source electrode 4031 to form a common electrode 404. Along the extension direction of the common electrode 404, one end of the common electrode 404 is connected to one end of the second gate electrode 4012 through a conductive portion, and the second source electrode 4031 and the second gate electrode 4012 are electrically connected through a conductive portion.

[0074] Referring to Figure 2 , in this embodiment, the first gate electrode 4011 serves as the input terminal of the inverter. The first gate electrode 4011 is led out through a lead electrode for convenient connection with the outside. The second source electrode 4031 and the second gate electrode 4012 are connected through a conductive portion and serve as the output terminal of the inverter. The second drain electrode 4032 is connected to an external power supply, and the first source electrode 4021 is grounded.

[0075] The preparation method of the inverter in this embodiment includes the following steps:

[0076] S1, as shown in Figure 3a , provide a substrate 10 and prepare the spaced-apart first gate electrode 4011 and second gate electrode 4012 on the substrate 10.

[0077] The substrate 10 in this embodiment is a silicon oxide substrate. The preparation processes of the first gate electrode 4011 and the second gate electrode 4012 are conventional processes, which will not be elaborated here.

[0078] S2, as shown in Figure 3b , prepare a first gate dielectric layer 201 on the substrate 10, the first gate electrode 4011, and the second gate electrode 4012.

[0079] Specifically, the first gate dielectric layer 201 in this embodiment is preferably a hafnium oxide layer, and a dense hafnium oxide thin film is deposited on the substrate 10, the first gate electrode 4011, and the second gate electrode 4012 by using a plasma-enhanced atomic layer deposition (PEALD) process.

[0080] S3, as shown in Figure 3c , prepare a second gate dielectric layer 202 on the first gate dielectric layer 201. The second gate dielectric layer 202 is at least partially located in the region directly above the second gate electrode 4012.

[0081] Specifically, this step includes:

[0082] 1. A patterned photoresist layer is prepared on the surface of the first gate dielectric layer 201 to expose at least the area of ​​the first gate dielectric layer 201 located directly above the second gate 4012.

[0083] For example, in this embodiment, a patterned photoresist layer is prepared using photolithography, and the photoresist is a negative photoresist. During photolithography, a larger pattern is used, that is, the width is greater than the width of the first gate dielectric layer 201 on the second gate 4012 for exposure. After development, the photoresist layer on the first gate dielectric layer 201 on the sidewall of the second gate 4012 is removed.

[0084] 2. Deposit a second gate dielectric layer 202 on the photoresist layer and the first gate dielectric layer 201.

[0085] Specifically, in this embodiment, the second gate dielectric layer 202 is preferably a calcium fluoride layer, which is deposited by magnetron sputtering.

[0086] 3. Remove the photoresist layer and the second gate dielectric layer 202 on the photoresist layer.

[0087] S4, Reference Figure 3d As shown, a first channel layer 301 and a second channel layer 302 are fabricated. The first channel layer 301 is at least partially located in the region directly above the first gate 4011, and the second channel layer 302 is at least partially located in the region directly above the second gate 4012.

[0088] In this embodiment, the first channel layer 301 and the second channel layer 302 are molybdenum disulfide layers.

[0089] Specifically, after the fabrication of the second gate dielectric layer 202 is completed, the wafer-level molybdenum disulfide layer grown on the substrate by chemical vapor deposition (CVD) is first transferred to the gate dielectric layer by a wet transfer process; then the molybdenum disulfide layer is patterned by photolithography and reactive ion etching (RIE) processes to form a first channel layer 301 stacked on the first gate dielectric layer 201 and a second channel layer 302 stacked on the second gate dielectric layer 202.

[0090] S5, Participant Figure 3eAs shown, a first source electrode 4021, a first drain electrode 4022, a second source electrode 4031, and a second drain electrode 4032 are formed on a first gate dielectric layer 201. The first drain electrode 4022 and the second source electrode 4031 are located on the first gate dielectric layer 201 between the first channel layer 301 and the second channel layer 302 and are electrically connected to the first channel layer 301 and the second channel layer 302 respectively. The first source electrode 4021 is located on a side of the first channel layer 301 away from the first drain electrode 4022 and is electrically connected to the first channel layer 301. The second drain electrode 4032 is located on a side of the second channel layer 302 away from the second source electrode 4031 and is electrically connected to the second channel layer 302. The second source electrode 4031 is electrically connected to the second gate electrode 4012.

[0091] In this embodiment, the first drain electrode 4021 and the second source electrode 4031 are connected to form a common electrode 404.

[0092] In this embodiment, the preparation processes of the first source electrode 4021, the first drain electrode 4022, the second source electrode 4031, and the second drain electrode 4032 are conventional processes and will not be elaborated here. <x

[0093] Refer Figure 4 As shown, the output characteristic curve of the inverter in this embodiment indicates that the device has good contact.

[0094] Refer Figure 5 As shown, the transfer characteristic curve 1 is the transfer characteristic curve of the MoS2 layer on the HfO2 layer, showing the conductive characteristics of an intrinsic MoS2 and turning on near 0V. The transfer characteristic curve 2 is the transfer characteristic curve of the MoS2 layer in direct contact with the CaF2 layer. Compared with the intrinsic performance, it has a more negative turn-on voltage. While maintaining the same order of magnitude of the off-state current, the MoS2 layer on the CaF2 layer has a larger on-state current.

[0095] Refer Figure 6 As shown, after the electrical tests are completed, the cross-sectional TEM image of the CaF2 selected area of the inverter in this embodiment shows that a clean quasi-van der Waals interface is formed between the MoS2 layer and the CaF2 layer, avoiding the influence brought by the impurities and defects of the interface during the electrical test process.

[0096] Embodiment 2:

[0097] Refer Figure 7 As shown, the structure and preparation method of the inverter in this embodiment are substantially the same as those in Embodiment 1, except that the upper surface of the first gate dielectric layer 201 is flat, and the thickness of the first gate dielectric layer 201 on the surface of the substrate 10 is greater than the thickness of the first gate dielectric layer 201 on the surfaces of the first gate electrode 4011 and the second gate electrode 4012. <00x00218>

[0098] As can be seen from the above technical solution, the present invention has the following beneficial effects:

[0099] This invention fabricates a second gate dielectric layer on the first gate dielectric layer on the second gate. By utilizing the electronegativity of F ions in the second gate dielectric layer, region-selective doping of the device is achieved, resulting in an inverter with a larger on / off ratio. It can maintain the original off-state current and has a significant shift in threshold voltage, providing a simple and effective method for improving the performance of large-size transistors.

[0100] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0101] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An inverter, characterized in that, The inverter includes: Substrate; The gate includes a first gate and a second gate located on the substrate and spaced apart from each other; The gate dielectric layer includes a first gate dielectric layer stacked on the substrate, the first gate, and the second gate, and a second gate dielectric layer stacked on the first gate dielectric layer, wherein the second gate dielectric layer is at least partially located in the region directly above the second gate. The channel layer includes a first channel layer stacked on a first gate dielectric layer and a second channel layer stacked on a second gate dielectric layer, wherein the first channel layer is at least partially located in the region directly above the first gate, and the second channel layer is at least partially located in the region directly above the second gate. A first source, a first drain, a second source, and a second drain are stacked on the first gate dielectric layer. The first drain and the second source are located on the first gate dielectric layer between the first channel layer and the second channel layer and are electrically connected to the first channel layer and the second channel layer, respectively. The first source is located on the side of the first channel layer away from the first drain and is electrically connected to the first channel layer. The second drain is located on the side of the second channel layer away from the second source and is electrically connected to the second channel layer. The second source is electrically connected to the second gate.

2. The inverter according to claim 1, characterized in that, The first drain and the second source are connected to form a common electrode. Along the extension direction of the common electrode, one end of the common electrode is connected to one end of the second gate through a conductive part. The second source and the second gate are electrically connected through the conductive part.

3. The inverter according to claim 1, characterized in that, The upper surface of the first gate dielectric layer is stepped.

4. The inverter according to claim 1, characterized in that, The upper surface of the first gate dielectric layer is planar.

5. The inverter according to claim 1, characterized in that, The first source and the first drain are partially covered on the first channel layer, and the second source and the second drain are partially covered on the second channel layer.

6. The inverter according to claim 1, characterized in that, The first channel layer and the second channel layer are either N-type two-dimensional material layers or P-type two-dimensional material layers, and a quasi-van der Waals interface is formed between the second gate dielectric layer and the second channel layer.

7. The inverter according to claim 1, characterized in that, The first gate dielectric layer is one or more of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, or a hafnium oxide layer; and / or, The second gate dielectric layer is one or more of a strontium fluoride layer, a barium fluoride layer, or a calcium fluoride layer.

8. The inverter according to claim 1, characterized in that, The first gate serves as the input terminal of the inverter, the second source is connected to the second gate and serves as the output terminal of the inverter, the second drain is connected to the external power supply, and the first source is grounded.

9. A method for manufacturing an inverter, characterized in that, The preparation method includes the following steps: A substrate is provided, and a first gate and a second gate spaced apart are formed on the substrate; A first gate dielectric layer is fabricated on the substrate, the first gate, and the second gate; A second gate dielectric layer is fabricated on the first gate dielectric layer, wherein the second gate dielectric layer is at least partially located in the region directly above the second gate. A first channel layer and a second channel layer are fabricated, wherein the first channel layer is at least partially located in the region directly above the first gate, and the second channel layer is at least partially located in the region directly above the second gate. A first source, a first drain, a second source, and a second drain are fabricated on a first gate dielectric layer. The first drain and the second source are located on the first gate dielectric layer between the first channel layer and the second channel layer and are electrically connected to the first channel layer and the second channel layer, respectively. The first source is located on the side of the first channel layer away from the first drain and is electrically connected to the first channel layer. The second drain is located on the side of the second channel layer away from the second source and is electrically connected to the second channel layer. The second source is electrically connected to the second gate.

10. The method for preparing an inverter according to claim 9, characterized in that, Fabricating a second gate dielectric layer on a first gate dielectric layer includes the following steps: A patterned photoresist layer is prepared on the first gate dielectric layer to expose at least the region of the first gate dielectric layer directly above the second gate. A second gate dielectric layer is deposited on the photoresist layer and the first gate dielectric layer; Remove the photoresist layer and the second gate dielectric layer on the photoresist layer.

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