N-type topcon cell and related apparatus

Abstract

This application provides an N-type TOPCON cell, belonging to the field of solar cells. The cell includes: an N-type crystalline silicon substrate, a P+ layer, and an N+ layer; the P+ layer is disposed on the front side of the N-type crystalline silicon substrate, and the N+ layer is disposed on the back side of the N-type crystalline silicon substrate; the P+ layer includes at least one antireflection layer, at least six passivation layers, a boron-doped layer, and a P+ passivated emitter; the N+ layer includes a passivation layer, a phosphorus-doped layer, and the passivation layer. The N-type TOPCON cell provided by this application can achieve good chemical passivation and field-effect passivation of the surface of the doped polycrystalline silicon layer, reducing carrier loss due to recombination in the polycrystalline silicon layer and improving the effective output of photogenerated carriers.

Description

Technical Field

[0001] This application relates to the field of solar cells, and more particularly to an N-type TOPCON cell and an electrical device. Background Technology

[0002] N-type TOPCon cells are a type of solar cell technology based on the selective carrier principle using tunnel oxide passivated contact (TOC). Conventional N-type cell modules have poor resistance to ultraviolet (UV) degradation, with a degradation rate of approximately 4% under UV30. In low-latitude or high-altitude regions, where solar UV radiation is strong, the power generation efficiency decreases significantly. Studies on UV degradation have revealed that under UV irradiation, hydrogen bonds in the passivation layer of N-type TOPCon cells may break, leading to changes in the chemical structure. The breakage of hydrogen bonds generates excess hydrogen atom clusters, which may not effectively recombine or passivate defects on the cell surface, thus losing some of the hydrogen passivation function. This loss of passivation function may increase the recombination rate at the cell surface, meaning an increased probability of electron-hole recombination, thereby reducing the cell's conversion efficiency. Therefore, a new cell structure is needed to block the penetration of short-wavelength light and reduce hydrogen bond breakage. Summary of the Invention

[0003] The purpose of this application is to provide an N-type TOPCON battery and an electrical device to solve the above-mentioned problems.

[0004] To achieve the above objectives, this application adopts the following technical solution:

[0005] This application provides an N-type TOPCON battery, comprising:

[0006] An N-type crystalline silicon substrate, a P+ layer, and an N+ layer; the P+ layer is disposed on the front side of the N-type crystalline silicon substrate, and the N+ layer is disposed on the back side of the N-type crystalline silicon substrate;

[0007] The P+ layer includes at least one anti-reflection layer, at least six passivation layers, a boron-doped layer, and a P+ passivated emitter.

[0008] The N+ layer includes a passivation layer, a phosphorus-doped layer, and the passivation layer.

[0009] Optionally, in the P+ layer, the direction extending from the surface of the N-type silicon substrate away from the N-type silicon substrate includes, in sequence: a P+ passivated emitter, a first passivation layer, the boron-doped layer, a second passivation layer, a third passivation layer, a fourth passivation layer, a fifth passivation layer, a first antireflection layer, and a sixth passivation layer.

[0010] Optionally, the third passivation layer, the fourth passivation layer, the fifth passivation layer, and the sixth passivation layer each independently include a silicon oxide layer and / or an aluminum oxide layer.

[0011] Optionally, the first passivation layer comprises one of the following: a mixture film of multiple group IVA elements, an oxide film of group IVA elements, a nitride film of group IVA elements, a oxynitride film of group IVA elements, and a metal oxide film.

[0012] Optionally, the second passivation layer comprises: a mixture film of multiple group IVA elements, an oxide film of group IVA elements, a nitride film of group IVA elements, and an oxide film of group IVA elements.

[0013] Optionally, in the P+ layer, the direction extending from the surface of the N-type silicon substrate away from the N-type silicon substrate includes, in sequence: a P-type emitter, a first silicon oxide layer, a boron doped layer, a first aluminum oxide layer, a second silicon oxide layer, a third silicon oxide layer, a silicon nitride antireflection layer, and a fourth silicon oxide layer.

[0014] Optionally, the thickness of the first silicon oxide layer is 1-3 nm.

[0015] Optionally, the thickness of the boron-doped layer is 30-220 nm.

[0016] Optionally, the thickness of the first alumina layer is 1-10 nm.

[0017] Optionally, the thickness of the second silicon oxide layer is 1-3 nm.

[0018] Optionally, the thickness of the second alumina layer is 1-10 nm.

[0019] Optionally, the thickness of the third silicon oxide layer is 1-3 nm.

[0020] Optionally, the thickness of the silicon nitride antireflection layer is 60-80 nm.

[0021] Optionally, the thickness of the fourth silicon oxide layer is 2-10 nm.

[0022] Optionally, in the N+ layer, the direction in which the surface of the N-type silicon substrate extends away from the N-type silicon substrate includes, in sequence: a seventh passivation layer, the phosphorus doped layer, and a second antireflection layer.

[0023] Optionally, the seventh passivation layer comprises one of the following: a mixture film of multiple group IVA elements, an oxide film of group IVA elements, a nitride film of group IVA elements, and an oxide oxynitride film of group IVA elements.

[0024] Optionally, the second antireflection layer is a silicon nitride antireflection layer.

[0025] Optionally, the seventh passivation layer is a silicon oxide layer with a thickness of 1-3 nm.

[0026] Optionally, the thickness of the phosphorus-doped layer is 30-220 nm.

[0027] Optionally, the thickness of the silicon nitride antireflection layer is 60-80 nm.

[0028] Optionally, the N+ layer may further include a metal crystal.

[0029] Optionally, the metal crystal is in direct contact with or spaced apart from the electrode on the back side of the N-type crystalline silicon substrate.

[0030] Optionally, the metal crystal is located in the region where the electrode on the back side of the N-type crystalline silicon substrate projects onto the substrate.

[0031] This application also provides an electrical device, including the aforementioned N-type TOPCON battery.

[0032] Compared with the prior art, the beneficial effects of this application include:

[0033] The N-type TOPCON cell provided in this application reduces the penetration of ultraviolet light by setting multiple anti-reflection films of different media on the front side of the cell, thereby greatly mitigating the ultraviolet degradation of the solar cell. The front side of the cell adopts a stacked passivation structure, namely a P-type emitter, silicon oxide, a boron doped layer, and an aluminum oxide layer. This application achieves good chemical passivation and field-effect passivation of the surface of the doped polycrystalline silicon layer by introducing a stacked passivation structure, reducing the loss of charge carriers caused by recombination in the polycrystalline silicon layer and improving the effective output of photogenerated charge carriers. Furthermore, the boron doped layers with different doping concentrations are set to generate a potential difference, providing a certain driving force for the output of photogenerated charge carriers to the external circuit, thereby further increasing the effective output of charge carriers and effectively improving the conversion efficiency of the solar cell.

[0034] The electrical equipment provided in this application has excellent electrical performance and exhibits stability and reliability during long-term use. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation on the scope of this application.

[0036] Figure 1 This is a schematic diagram of the structure of the N-type TOPCON battery provided in Example 1.

[0037] Key symbols: 10 - N-type crystalline silicon substrate; 101 - P-type emitter; 102 - First silicon oxide layer; 103 - Boron doped layer; 104 - First aluminum oxide layer; 105 - Second silicon oxide layer; 106 - Second aluminum oxide layer; 107 - Third silicon oxide layer; 108 - First silicon nitride antireflection layer; 109 - Fourth silicon oxide layer; 201 - Fifth silicon oxide layer; 202 - Phosphorus doped layer; 203 - Second silicon nitride antireflection layer; 204 - Metal crystal. Detailed Implementation

[0038] As used in this article:

[0039] "Prepared from" is synonymous with "comprising". The terms "comprising", "including", "having", "containing", or any other variations thereof as used herein are intended to cover non-exclusive inclusion. For example, a composition, step, method, article, or apparatus that includes the listed elements is not necessarily limited to those elements, but may include other elements not expressly listed or elements inherent to such composition, step, method, article, or apparatus.

[0040] The conjunction "composed of..." excludes any unspecified elements, steps, or components. If used in a claim, this phrase makes the claim closed, excluding materials other than those described, except for associated conventional impurities. When the phrase "composed of..." appears in a clause of the body of a claim rather than immediately following it, it limits only the elements described in that clause; other elements are not excluded from the claim as a whole.

[0041] When a quantity, concentration, or other value or parameter is expressed as a range, a preferred range, or a range defined by a series of upper and lower preferred values, this should be understood as specifically disclosing all ranges formed by any pair of any upper or preferred value with any lower or preferred value, regardless of whether the range is disclosed individually. For example, when the range “1–5” is disclosed, the described range should be interpreted as including ranges “1–4”, “1–3”, “1–2”, “1–2 and 4–5”, “1–3 and 5”, etc. When numerical ranges are described herein, unless otherwise stated, the range is intended to include its endpoints and all integers and fractions within that range.

[0042] In these embodiments, unless otherwise specified, the portions and percentages are all by weight.

[0043] "Parts by mass" refers to the basic unit of measurement that expresses the mass ratio of multiple components. One part can represent any unit mass, such as 1g or 2.689g. If we say that component A has "a" parts by mass and component B has "b" parts by mass, it means the ratio of the mass of component A to the mass of component B is a:b. Alternatively, it can mean that the mass of component A is aK and the mass of component B is bK (K is any number representing a multiplier). It is important to understand that, unlike the number of parts by mass, the sum of the mass parts of all components is not limited to 100 parts.

[0044] "And / or" is used to indicate that one or both of the described situations may occur, for example, A and / or B includes (A and B) and (A or B).

[0045] To better illustrate the technical solution provided in this application, the technical solution will be described in its entirety before the embodiments, as follows:

[0046] In a first aspect, this application provides an N-type TOPCON battery, comprising:

[0047] An N-type crystalline silicon substrate, a P+ layer, and an N+ layer; the P+ layer is disposed on the front side of the N-type crystalline silicon substrate, and the N+ layer is disposed on the back side of the N-type crystalline silicon substrate;

[0048] The P+ layer includes at least one anti-reflection layer, at least six passivation layers, a boron-doped layer, and a P+ passivated emitter.

[0049] The N+ layer includes a passivation layer, a phosphorus-doped layer, and the passivation layer.

[0050] In an optional embodiment, the P+ layer, extending from the surface of the N-type silicon substrate away from the N-type silicon substrate, includes, in sequence: a P+ passivated emitter, a first passivation layer, the boron-doped layer, a second passivation layer, a third passivation layer, a fourth passivation layer, a fifth passivation layer, a first antireflection layer, and a sixth passivation layer.

[0051] In an optional implementation, the third passivation layer, the fourth passivation layer, the fifth passivation layer, and the sixth passivation layer each independently include a silicon oxide layer and / or an aluminum oxide layer.

[0052] In an optional embodiment, the first passivation layer comprises one of the following: a mixture film of multiple group IVA elements, an oxide film of group IVA elements, a nitride film of group IVA elements, an oxide nitride film of group IVA elements, and a metal oxide film.

[0053] In an optional embodiment, the second passivation layer comprises: a mixture film of multiple group IVA elements, an oxide film of group IVA elements, a nitride film of group IVA elements, and an oxide film of group IVA elements.

[0054] In an optional embodiment, the P+ layer comprises, in a direction extending away from the N-type silicon substrate from the surface of the N-type silicon substrate, the following layers are sequentially arranged: a P-type emitter, a first silicon oxide layer, a boron doped layer, a first aluminum oxide layer, a second silicon oxide layer, a third silicon oxide layer, a silicon nitride antireflection layer, and a fourth silicon oxide layer.

[0055] The first silicon oxide layer separates the P+ passivated emitter and the boron-doped layer, significantly reducing carrier recombination losses between the P-type emitter and the boron-doped layer. This helps reduce charge loss during transport, thereby improving the photoelectric conversion efficiency of the solar cell. The first aluminum oxide layer provides negative charge, reducing electron-hole recombination caused by electrons transitioning to the front surface of the cell. Furthermore, the abundant hydrogen bonds in aluminum oxide provide sufficient hydrogen passivation to enhance cell efficiency. The second silicon oxide layer weakens the penetration of short-wavelength light, blocks hydrogen accumulation between the two aluminum oxide layers, and reduces ultraviolet decay. It also provides sufficient negative charge to reduce electron migration to the surface and decrease recombination. The third silicon oxide layer, inserted between the aluminum oxide and silicon nitride layers, weakens the penetration of short-wavelength light. The outermost silicon oxide and silicon nitride layers together form a passivation contact structure, which effectively reduces surface and metal-to-metal recombination, providing greater potential for further improvements in cell conversion efficiency.

[0056] In one alternative embodiment, the thickness of the first silicon oxide layer is 1-3 nm.

[0057] Optionally, the thickness of the first silicon oxide layer can be 1 nm, 2 nm, 3 nm, or any value between 1 and 3 nm.

[0058] In one alternative embodiment, the thickness of the boron-doped layer is 30-220 nm.

[0059] Optionally, the thickness of the boron-doped layer can be 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, 155nm, 160nm, 165nm, 170nm, 175nm, 180nm, 185nm, 190nm, 195nm, 200nm, 205nm, 210nm, 215nm, 220nm, or any value between 30nm and 220nm.

[0060] In one optional embodiment, the thickness of the first alumina layer is 1-10 nm.

[0061] Optionally, the thickness of the first alumina layer can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, or any value between 1 and 10nm.

[0062] In one alternative embodiment, the thickness of the second silicon oxide layer is 1-3 nm.

[0063] Optionally, the thickness of the second silicon oxide layer can be 1 nm, 2 nm, 3 nm, or any value between 1 and 3 nm.

[0064] In one optional embodiment, the thickness of the second alumina layer is 1-10 nm.

[0065] Optionally, the thickness of the second alumina layer can be 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, or any value between 1 and 10nm.

[0066] In one optional embodiment, the thickness of the third silicon oxide layer is 1-3 nm.

[0067] Optionally, the thickness of the third silicon oxide layer can be 1 nm, 2 nm, 3 nm, or any value between 1 and 3 nm.

[0068] In one optional embodiment, the thickness of the silicon nitride antireflection layer is 60-80 nm.

[0069] Optionally, the thickness of the silicon nitride antireflection layer can be 60nm, 62nm, 64nm, 66nm, 68nm, 70nm, 72nm, 74nm, 76nm, 78nm, 80nm, or any value between 60 and 80nm.

[0070] In one optional embodiment, the thickness of the fourth silicon oxide layer is 2-10 nm.

[0071] Optionally, the thickness of the fourth silicon oxide layer can be 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, or any value between 2 and 10nm.

[0072] In an optional embodiment, the N+ layer includes, in the direction extending away from the N-type silicon substrate from the surface of the N+ layer, a seventh passivation layer, the phosphorus doped layer, and a second antireflection layer, which are sequentially disposed.

[0073] In an optional embodiment, the seventh passivation layer comprises one of the following: a mixture film of multiple group IVA elements, an oxide film of group IVA elements, a nitride film of group IVA elements, and an oxide nitride film of group IVA elements.

[0074] In one optional embodiment, the second antireflection layer is a silicon nitride antireflection layer.

[0075] In an optional embodiment, the seventh passivation layer is a silicon oxide layer with a thickness of 1-3 nm.

[0076] Optionally, the thickness of the seventh passivation layer, silicon oxide layer, can be 1 nm, 2 nm, 3 nm, or any value between 1 and 3 nm.

[0077] In one optional embodiment, the thickness of the phosphorus-doped layer is 30-220 nm.

[0078] The thickness of the phosphorus doped layer can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 90nm, 200nm, 210nm, 220nm, or any value between 30nm and 220nm.

[0079] In one optional embodiment, the thickness of the silicon nitride antireflection layer is 60-80 nm.

[0080] In an alternative implementation, the N+ layer further includes a metal crystal.

[0081] In an alternative embodiment, the metal crystal is in direct contact with or spaced apart from the electrode on the back side of the N-type silicon substrate.

[0082] In an alternative embodiment, the metal crystal is located in the region where the electrode on the back side of the N-type crystalline silicon substrate projects onto the substrate.

[0083] The method for forming the metal crystal is as follows:

[0084] After silver paste is printed onto the surface of a silicon wafer, it is sintered in a sintering furnace. When the temperature is higher than the silver-silicon eutectic temperature, which is 840°C, silver atoms and silicon atoms diffuse into each other at the silver-silicon interface. Above this temperature, silicon and silver melt, and the interface becomes a silver-silicon melt; below this temperature, cooling forms a silicon solid melt, and some silver precipitates to form a recrystallized layer, which is the metallic crystal.

[0085] During screen printing, the paste can penetrate and be pressed into and formed in the phosphorus doped layer, that is, a metal crystal can be formed in the phosphorus doped layer, in the region where the electrode is projected onto the substrate.

[0086] The method for preparing the N-type TOPCON battery is as follows:

[0087] Step 1: Clean the N-type crystalline silicon substrate, remove the damaged layer, and texturize it to form a random pyramid structure on the silicon wafer surface.

[0088] Step 2: Using a boron diffusion furnace, boron is diffused outwards along the P+ layer of the texturized silicon substrate to form a p-type emitter with a maximum doping concentration of 10. 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0089] Step 3: The front borosilicate glass and the back winding are cleaned using a cleaning machine to obtain the intermediate state of the solar cell.

[0090] Step 4: Using LPCVD, grow a first silicon oxide layer and a first intrinsic amorphous silicon layer in the P+ direction of an N-type crystalline silicon substrate; grow a fifth silicon oxide layer and a second intrinsic amorphous silicon layer in the N+ direction, with the thickness of the first and fifth silicon oxide layers being 1-3 nm and the thickness of the intrinsic amorphous silicon layer being 100 nm.

[0091] Step 5: Deposit the first mask layer in the P+ layer direction of the N-type crystalline silicon substrate using PECVD. The mask layer has a thickness of 80 nm and the deposition process temperature is 330-380℃.

[0092] Step 6: Polycrystalline the intrinsic amorphous silicon along the P+ and N+ directions using a diffusion furnace to form an intrinsic polycrystalline silicon layer. Phosphorus diffusion is then performed on the back side of the intrinsic polycrystalline silicon layer to form an N+-type N-type phosphorus-doped layer with a phosphorus doping concentration of 10%. 22 -10 23 cm-3 At the same time, a second mask layer is formed on the phosphorus-doped layer on the back side.

[0093] Step 7: Remove the first mask layer in the P+ direction using a chain cleaning machine.

[0094] Step 8: Boron doping layer is formed by boron diffusion in the first intrinsic polysilicon layer along the P+ layer direction, with a boron doping concentration of 10. 20 -10 22 cm -3 Simultaneously, a third mask layer of boron-doped silicon oxide is formed on the boron-doped polycrystalline silicon layer.

[0095] Step 9: Remove the third mask layer on the front side using a chain cleaning agent.

[0096] Step 10: Deposit a first alumina passivation layer with a thickness of 5 nm on the P-type boron-doped polysilicon in the P+ layer direction using an ALD device.

[0097] Step 11: Grow a second silicon oxide layer of 1-3 nm on the front side of the silicon wafer. The oxygen atoms in this silicon oxide layer also passivate the dangling bonds of the surface silicon, reducing surface recombination.

[0098] The flow rate of nitrous oxide is 8000-11000 sccm / min, the pressure is 1500-2000 mtorr, the radio frequency power is 7000-12000W, and the time is 100-200s; Radio frequency power: 7000-12000W; Time: 100-200s.

[0099] Step 12: Continue growing a second alumina layer of 1-10 nm, setting the pressure to 1400-1800 mtorr; RF power to 6000-9000 W; trimethylaluminum to 40-70 sccm / min; nitrous oxide flow rate to 4000 sccm / min; and time to 30-90 s.

[0100] Step 13: Continue growing a 1-3nm third silicon oxide layer to weaken the penetration of short-wavelength light, block hydrogen accumulation between the two aluminum oxide layers, and reduce ultraviolet attenuation; set the nitrous oxide flow rate to 8000-11000 sccm / min, pressure to 1500-2000 mtorr, RF power to 7000-12000 W, and time to 100-300 s.

[0101] Step 14: First silicon nitride antireflection layer of 60-80nm, set silane flow rate of 1200-1800sccm / min, ammonia flow rate of 8500-1200sccm / min, pressure of 1500-1800mtorr, time of 600-900s, silicon nitride film thickness of 70nm.

[0102] Step 15: Continue growing a 2-10nm fifth silicon oxide layer to reduce the refractive index of the front surface layer; set the nitrous oxide flow rate to 8000-11000 sccm / min, pressure to 1500-2000 mtorr, RF power to 7000-12000 W, and time to 200-800 s.

[0103] Step 16: Print silver electrodes on local areas of the front and back sides using screen printing, with a maximum sintering temperature of 800℃.

[0104] Step 17: Remove the second mask layer in the N+ direction by chain cleaning.

[0105] Step 18: Deposit an anti-reflection layer, namely a silicon nitride layer, on the phosphorus-doped layer on the back side using a PECVD device. The total thickness of the silicon nitride layer is 70 nm, and the deposition process temperature is 450-500 °C.

[0106] Secondly, this application also provides an electrical device, including the aforementioned N-type TOPCON battery.

[0107] The implementation schemes of this application will be described in detail below with reference to specific embodiments. However, those skilled in the art will understand that the following embodiments are only for illustrating this application and should not be regarded as limiting the scope of the application. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Where the manufacturers of reagents or instruments are not specified, they are all conventional products that can be purchased commercially.

[0108] Example 1

[0109] This embodiment provides an N-type TOPCON battery, the structure of which is shown below:

[0110] like Figure 1 As shown, in the P+ layer, the surface of the N-type silicon substrate extending away from the N-type silicon substrate 10 includes the following sequentially disposed elements:

[0111] P-type emitter 101: Maximum doping concentration is 10. 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0112] The first silicon oxide layer 102 is a flint penetration thin film layer with a thickness of 1.5 nm.

[0113] Boron-doped layer 103: A p-type boron-doped polycrystalline silicon layer with a thickness of 60 nm and a doping concentration of 10. 18 -10 22 cm -3 .

[0114] The first alumina layer 104: on the one hand, it provides negative charge to reduce the electron-hole recombination caused by the transition of electrons to the front surface of the battery; on the other hand, there are a large number of hydrogen bonds in the alumina, which can provide sufficient hydrogen passivation to improve battery efficiency. The thickness is 5nm.

[0115] The second silicon oxide layer 105 is used to weaken the penetration of short-wavelength light, block hydrogen accumulation between the two aluminum oxide layers, and reduce ultraviolet attenuation. Its thickness is 1.5 nm.

[0116] The second alumina layer 106 provides sufficient negative charge to reduce electron migration to the surface and reduce recombination; its thickness is 2 nm.

[0117] The third silicon oxide layer 107: A dielectric material is inserted between aluminum oxide and silicon nitride to weaken the penetration of short-wavelength light, with a thickness of 2nm.

[0118] First silicon nitride antireflection layer 108: The refractive index of silicon nitride is 2.15 and the thickness is 70 nm.

[0119] The fourth silicon oxide layer 109 is used to reduce the refractive index of the front surface layer. When it forms a multilayer antireflection film with silicon nitride, it can achieve a good antireflection effect and improve the photoelectric conversion efficiency of the solar cell. The thickness is 5nm.

[0120] The surface of the N-type silicon substrate in the N+ layer extends away from the N-type silicon substrate, including the following sequentially arranged layers:

[0121] The fifth silicon oxide layer 201 is a flint penetration thin film layer with a thickness of 1.5 nm.

[0122] Phosphorus-doped layer 202: 80 nm thick, with a doping concentration of 10. 22 -10 23 cm -3 .

[0123] Second silicon nitride antireflection layer 203: As a back antireflection layer, the silicon nitride has a refractive index of 2.15 and a thickness of 70nm.

[0124] Metal crystal 204: At the silver-silicon interface, it becomes a silver-silicon melt. After cooling, it forms a silicon solid melt. Some silver precipitates out to form a recrystallized layer, which is the metal crystal.

[0125] The preparation method follows the above procedure, with adjustments made to the corresponding parameters.

[0126] Comparative Example 1

[0127] This comparative example provides an N-type TOPCON battery, the structure of which is shown below:

[0128] In the P+ layer, the surface of the N-type silicon substrate 10 extends away from the N-type silicon substrate and includes the following sequentially disposed layers:

[0129] P-type emitter: Maximum doping concentration is 10 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0130] Silicon oxide layer: a fire-through thin film layer with a thickness of 1.5 nm.

[0131] Boron-doped layer: P-type boron-doped polycrystalline silicon layer, 60 nm thick, with a doping concentration of 10. 18 -10 22 cm -3 .

[0132] Alumina layer: On the one hand, it provides negative charge, reducing the transition of electrons to the front surface of the battery, thus reducing electron-hole recombination; on the other hand, aluminum oxide contains a large number of hydrogen bonds, which can provide sufficient hydrogen passivation to improve battery efficiency. The thickness is 5nm.

[0133] First silicon nitride antireflection layer: The refractive index of silicon nitride is 2.15 and the thickness is 70nm.

[0134] The surface of the N-type silicon substrate 10 in the N+ layer extends away from the N-type silicon substrate and includes the following sequentially arranged layers:

[0135] Silicon oxide layer: a fire-through thin film layer with a thickness of 1.5 nm.

[0136] Phosphorus-doped layer: 80 nm thick, with a doping concentration of 10. 22 -10 23 cm -3 .

[0137] Second silicon nitride antireflection layer 203: As a back antireflection layer, the silicon nitride has a refractive index of 2.15 and a thickness of 70nm.

[0138] Metallic crystals: At the silver-silicon interface, it becomes a silver-silicon melt, which, upon cooling, forms a silicon solid melt. Some silver precipitates out to form a recrystallized layer, which is the metallic crystal.

[0139] The preparation method follows the above procedure, with adjustments made to the corresponding parameters.

[0140] Comparative Example 2

[0141] This comparative example provides a conventional N-type TOPCON battery, the structure of which is shown below:

[0142] In the P+ layer, the surface of the N-type silicon substrate 10 extends away from the N-type silicon substrate and includes the following sequentially disposed layers:

[0143] P-type emitter: Maximum doping concentration is 10 20 cm -3 The boron concentration is 10 17 cm -3 The diffusion junction depth at that location is 0.5 μm.

[0144] Alumina layer: On the one hand, it provides negative charge, reducing the transition of electrons to the front surface of the battery, thus reducing electron-hole recombination; on the other hand, aluminum oxide contains a large number of hydrogen bonds, which can provide sufficient hydrogen passivation to improve battery efficiency. The thickness is 5nm.

[0145] First silicon nitride antireflection layer: The refractive index of silicon nitride is 2.15 and the thickness is 70nm.

[0146] The surface of the N-type silicon substrate 10 in the N+ layer extends away from the N-type silicon substrate and includes the following sequentially arranged layers:

[0147] Silicon oxide layer: a fire-through thin film layer with a thickness of 1.5 nm.

[0148] Phosphorus-doped layer: 80 nm thick, with a doping concentration of 10. 22 -10 23 cm -3 .

[0149] Second silicon nitride antireflection layer 203: As a back antireflection layer, the silicon nitride has a refractive index of 2.15 and a thickness of 70nm.

[0150] Metallic crystals: At the silver-silicon interface, it becomes a silver-silicon melt, which, upon cooling, forms a silicon solid melt. Some silver precipitates out to form a recrystallized layer, which is the metallic crystal.

[0151] The preparation method follows the above procedure, with adjustments made to the corresponding parameters.

[0152] The electrical performance of the N-type TOPCON batteries prepared in the examples and comparative examples was tested, and the results are shown in Table 1:

[0153] Table 1 shows the electrical performance tests of the N-type TOPCON batteries prepared in the examples and comparative examples.

[0154]

[0155] It is evident that by setting multiple anti-reflection coatings with different media on the front side of the cell, the penetration ability of ultraviolet light is reduced, thereby greatly alleviating the ultraviolet degradation of the solar cell. The introduction of a stacked passivation structure on the front side of the cell achieves good chemical passivation and field-effect passivation of the surface of the doped polycrystalline silicon layer, reducing the loss of charge carriers caused by recombination in the polycrystalline silicon layer and improving the effective output of photogenerated charge carriers. Furthermore, the setting of boron doping layers with different doping concentrations creates a potential difference, providing a certain driving force for the output of photogenerated charge carriers to the external circuit, thereby further increasing the effective output of charge carriers and effectively improving the conversion efficiency of the solar cell.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0157] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the foregoing claims, any of the claimed embodiments can be used in any combination. The information disclosed in this background section is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.

Claims

1. An N-type TOPCON battery, characterized in that, include: An N-type crystalline silicon substrate, a P+ layer, and an N+ layer; the P+ layer is disposed on the front side of the N-type crystalline silicon substrate, and the N+ layer is disposed on the back side of the N-type crystalline silicon substrate; The P+ layer includes at least one anti-reflection layer, at least six passivation layers, a boron-doped layer, and a P+ passivated emitter. The N+ layer includes a passivation layer, a phosphorus-doped layer, and the passivation layer.

2. The N-type TOPCON battery according to claim 1, characterized in that, In the P+ layer, the direction extending from the surface of the N-type silicon substrate away from the N-type silicon substrate includes, in sequence: a P+ passivated emitter, a first passivation layer, the boron-doped layer, a second passivation layer, a third passivation layer, a fourth passivation layer, a fifth passivation layer, a first antireflection layer, and a sixth passivation layer.

3. The N-type TOPCON battery according to claim 2, characterized in that, The third passivation layer, the fourth passivation layer, the fifth passivation layer, and the sixth passivation layer each independently include a silicon oxide layer and / or an aluminum oxide layer.

4. The N-type TOPCON battery according to claim 2, characterized in that, At least one of the following conditions must be met: a. The first passivation layer comprises: a mixture film of multiple group IVA elements, an oxide film of group IVA elements, a nitride film of group IVA elements, a nitride film of group IVA elements, or a metal oxide film; b. The second passivation layer comprises: a mixture film of multiple group IVA elements, an oxide film of group IVA elements, a nitride film of group IVA elements, and an oxide film of group IVA elements.

5. The N-type TOPCON battery according to claim 2, characterized in that, In the P+ layer, the direction extending from the surface of the N-type silicon substrate away from the N-type silicon substrate includes, in sequence: a P-type emitter, a first silicon oxide layer, a boron doped layer, a first aluminum oxide layer, a second silicon oxide layer, a third silicon oxide layer, a silicon nitride antireflection layer, and a fourth silicon oxide layer.

6. The N-type TOPCON battery according to claim 5, characterized in that, At least one of the following conditions must be met: c. The thickness of the first silicon oxide layer is 1-3 nm; d. The thickness of the boron-doped layer is 30-220 nm; The thickness of the first alumina layer is 1-10 nm; f. The thickness of the second silicon oxide layer is 1-3 nm; g. The thickness of the second alumina layer is 1-10 nm; h. The thickness of the third silicon oxide layer is 1-3 nm; i. The thickness of the silicon nitride antireflection layer is 60-80 nm; j. The thickness of the fourth silicon oxide layer is 2-10 nm.

7. The N-type TOPCON battery according to claim 1, characterized in that, In the N+ layer, the surface of the N-type silicon substrate extending away from the N-type silicon substrate includes, in sequence: a seventh passivation layer, the phosphorus-doped layer, and a second antireflection layer, wherein at least one of the following conditions is met: k. The seventh passivation layer comprises one of the following: a mixture film of multiple group IVA elements, an oxide film of group IVA elements, a nitride film of group IVA elements, and an oxide nitride film of group IVA elements; l. The second antireflection layer is a silicon nitride antireflection layer.

8. The N-type TOPCON battery according to claim 7, characterized in that, At least one of the following conditions must be met: m. The seventh passivation layer is a silicon oxide layer with a thickness of 1-3 nm; n. The thickness of the phosphorus-doped layer is 30-220 nm; o. The thickness of the silicon nitride antireflection layer is 60-80 nm.

9. The N-type TOPCON battery according to claim 1, characterized in that, The N+ layer further includes a metal crystal and satisfies at least one of the following conditions: p. The metal crystal is in direct contact with or spaced apart from the electrode on the back side of the N-type crystalline silicon substrate; q. The metal crystal is located in the region where the electrode on the back side of the N-type crystalline silicon substrate is projected onto the substrate.

10. An electrical-related device, characterized in that, Includes the N-type TOPCON battery as described in any one of claims 1-9.

Images