Double superlattice obtained by layer transfer, structure and method of manufacture

Abstract

This invention relates to a method (500) for fabricating a stacked structure comprising a superlattice, comprising the steps of: forming (510) on a first substrate. Car First superlattice (Stck1); (520) is formed on the second substrate. Don Seed layer (Init) of the second superlattice (Stck2); formed in the second substrate (550 Don The seed layer (Init) is weakened (560) and assembled (560) onto the first superlattice (Stck1) at the dielectric separation layer, which separates the first superlattice (Stck1) from the seed layer (Init) and keeps them attached to each other; after the assembly step (560), a portion of the second substrate is removed (570A) by splitting the second substrate at the weakened plane (Imp); after the splitting step (570A), the seed layer (Init) is exposed (570B); and a second superlattice (Stck2) is formed (580) on the exposed seed layer (Init).

Description

Technical Field

[0001] The present invention generally relates to superlattices formed by periodic stacking of at least one thin layer, and more particularly to superlattices including semiconductor layers. More specifically, the present invention relates to dual superlattices. Background Technology

[0002] Superlattices have attracted attention due to their mechanical and semiconductor properties, as well as their potential for forming quantum dots.

[0003] They have also been used to develop so-called nanosheet transistors, or gate-all-around field-effect transistors (GAAFETs), whose conductive channels are formed by stacking layers of nanometer-thickness, each surrounded by a gate metal, as described in patents US 10,249,739B2 and US 11,018,222B1. These semiconductor structures have gates surrounding the channels and are therefore called "gate-all-around."

[0004] This principle has been applied to the formation of complementary field-effect transistors (CFETs) with a three-dimensional structure formed using a pair of stacked superlattices: a first superlattice formed on a substrate is used to form an n-type transistor, while a second superlattice formed on the first superlattice is used to form a p-type transistor, and vice versa. This three-dimensional structure offers advantages in integration density compared to conventional methods for implementing CMOS technology, which typically employ p-type and n-type transistors fabricated side-by-side in the same plane. In particular, the CFET method can, in principle, halve the footprint of a pair of p-type and n-type transistors, or shorten the connection between the two transistors, and thus reduce the resistance of the corresponding connection. This method is described, for example, in documents US 2019 / 0319095A1, US 2021 / 0104523A1, and US 2023 / 0326925A1.

[0005] Whether it's a nanosheet transistor or a CFET, the manufacturing methods discussed involve creating a superlattice, which consists of a stack of two types of alternating materials: one designed to form the channel region of the transistor, and another used to form a sacrificial layer, which is removed and replaced by a gate dielectric structure and a gate metal structure during transistor manufacturing.

[0006] Document US 2021 / 082901A1 discloses a method for fabricating high-density logic and memory, which includes stacking superlattice products.

[0007] Document US 2023 / 197721A1 discloses a method for manufacturing stacked transistors.

[0008] Document WO 20181 / 30781A1 discloses a method for manufacturing an image sensor.

[0009] Manufacturing a CFET requires two types of transistors, an n-type and a p-type, which are stacked on top of each other. There are two possible methods.

[0010] The first method is called the "sequential" method, meaning that the two types of transistors are formed sequentially in separate steps. In this method, a semiconductor structure made of silicon or another semiconductor, or in fact a superlattice designed to form the second nanosheet transistor, is transferred onto a semiconductor substrate that already, for example, hosts the first nanosheet transistor. First, the first transistor is formed on the substrate, then the semiconductor structure is transferred onto it, and subsequently the second transistor is formed within that semiconductor structure. The thermal budget for the method of transferring the semiconductor structure and forming the second transistor is limited by the need to avoid degrading the first transistor. Furthermore, the alignment of the second transistor with the first transistor must be extremely precise, and specific electrical contact structures must be established between the two layers.

[0011] The second method is called the "monolithic" method, which means that the first and second transistors are formed on the same substrate, and at least some manufacturing steps are applied simultaneously to all layers on which the first and second transistors are formed. See US 2019 / 0319095A1. One of the main advantages of this method is the self-alignment of the second transistor with the first transistor, which allows for a higher density of transistors on the substrate and reduces the parasitic capacitance and resistance between the first and second transistors.

[0012] Compared to sequential methods, monolithic methods require thicker superlattices as the starting structure because these superlattices form the basic structure of two simultaneously fabricated superimposed transistors. Superlattices are typically fabricated epitaxially. However, the number of layers that can be stacked to form these superlattices is limited by a critical epitaxial thickness, beyond which the quality of the deposited layers degrades due to elastic and / or plastic relaxation. Monolithic methods approach, and may require exceeding, this critical epitaxial thickness.

[0013] Furthermore, the monolithic method is technically more complex to implement than the sequential method, especially when a dielectric separator layer needs to be formed between the first and second transistors. Such a layer makes it easier to integrate internal space into the structure and form metal layers for the source and drain of the transistors. The vertical distance between the first and second transistors can be reduced to the thickness of the dielectric layer, which has a positive impact on reducing parasitic capacitance and resistance between the first and second transistors. However, obtaining such a dielectric layer requires complex processes and the use of a sacrificial layer, which is removed to make room for the dielectric layer. This sacrificial layer associated with the dielectric separator layer must be compatible with the sacrificial layer intended to form the space accommodating the gate dielectric layer and the metal layer. Therefore, both sacrificial layers used must be able to be selectively etched relative to each other and relative to the semiconductor forming the conductive channel of the transistor. Silicon is used, for example, for the channel, and silicon alloys with various percentages of germanium are used, for example, for the sacrificial layers. From a technical standpoint, while such structures are possible, obtaining them remains complex and challenging.

[0014] One approach involves forming two superlattices independently on two separate substrates, and then transferring one onto the other using a layer transfer technique, such as a so-called "smart dicing" method. One possible implementation of this approach includes: (a) seeding ions through the superlattice formed on one of the two substrates to create a weakening plane within that substrate; (b) bonding the two superlattices together using a direct bonding method, such as molecular bonding; and then (c) splitting the implanted substrate within the weakening layer. A disadvantage of this approach is that it typically requires at least one heat treatment to repair the transfer layer damaged by the transfer process, particularly the ion implantation step. This heat treatment has a detrimental effect on the superlattice because it causes germanium ions to diffuse into the silicon.

[0015] Therefore, there is a need for a method for fabricating or bonding superlattices that allows for exceeding the critical epitaxial thickness while limiting the damage to the layers forming the superlattice. Summary of the Invention

[0016] The applicant's objective is to provide a method for fabricating structures that facilitate the integration and production of nanosheet transistors, and more specifically, CFETs (i.e., stacked p-type and n-type transistors). This fabrication method should preferably be a monolithic approach particularly suited for CFET fabrication.

[0017] To achieve this objective, one aspect of the present invention is a method for fabricating a structure comprising a superlattice stack, the method comprising the steps of: forming a first superlattice on a first substrate by alternately stacking a plurality of first channel layers and a plurality of first sacrificial layers; forming a seed layer of a second superlattice by adding material to a second substrate; forming a weakening plane in the second substrate by implanting light-seed ions into the second substrate; forming an assembly by bonding the seed layer to the first superlattice via a dielectric separation layer, the dielectric separation layer separating the first superlattice from the seed layer and holding them fixed to each other; after the bonding step, removing a first portion of the second substrate by splitting the second substrate at the weakening plane, and removing that portion of the second substrate; after the splitting step of the second substrate, exposing the seed layer such that the exposed seed layer forms the outer side of the assembly, the exposure step comprising: after the step of removing the first portion of the second substrate, removing a second portion of the second substrate held in bond with the seed layer (Don). a ); and by alternately stacking multiple second channel layers and multiple second sacrificial layers, a second superlattice is formed on the outside of the exposed seed layer and in direct contact with the outside.

[0018] The first advantage of this method is that it provides a superlattice stack that can be the same or different in composition and / or orientation.

[0019] The second advantage of this method is that the resulting structures can exceed the critical epitaxial thickness, which limits the number and thickness of layers that can be epitaxially grown on top of each other without sacrificing the quality of the crystal structure of these layers.

[0020] A third advantage of this method is that it provides a separation layer between the two superlattices within the stack itself, which potentially possesses structural properties incompatible with conventional superlattice formation methods. Specifically, superlattices are conventionally formed by epitaxially depositing layers sequentially. However, using this method, the separation layer can be made of a dielectric, such as a nitride or oxide, which can be amorphous, incompatible with forming a semiconductor layer with good crystal quality on the surface of this amorphous layer via epitaxy; conversely, epitaxial deposition requires a crystalline substrate layer. This invention therefore allows the use of any type of dielectric, such as SiN, SiCN, or SiO2, which can be selected based on its inherent dielectric properties and compatibility with the steps used to fabricate transistors based on stacked superlattices.

[0021] A fourth advantage of this method is its relative advantage over methods involving transferring a second superlattice from a substrate independently formed thereon to a first lattice via a smart cutting method. In such cases, a heat treatment might be necessary to repair the transfer layer, but this is irrelevant in this method. Therefore, the method of the present invention limits the potential negative impact of heat treatment on the superlattice and / or the structure accompanying it.

[0022] The fifth advantage stems from the anticipated application of superlattice stacking, namely the formation of CFETs. The dielectric separation layer can be configured to perform the function of providing electrical isolation between stacked transistors, but it can also be used as an etch stop layer, allowing for transistor differentiation or integration, for example, into structures on the back side of a carrier substrate.

[0023] Therefore, the manufacturing method according to the invention is suitable for producing structures that can be used as the basis for a monolithic method for producing electronic circuits with integrated CFETs.

[0024] Further non-limiting features of the method according to the invention (these features may be implemented individually or in any technically feasible combination): - The weakening plane of the second substrate is formed by implanting light seed ions into the second substrate through the seed layer; - The separation layer can be continuously formed in a plane parallel to the surface of the first substrate on which the first superlattice is formed; - The first channel layer and the second channel layer may each be formed from semiconductor materials, and the first sacrificial layer and the second sacrificial layer may each be formed from materials capable of having a faster etching rate than the first channel layer and the second channel layer, respectively; - The first channel layer and the second channel layer may each be formed of silicon, and the first sacrificial layer and the second sacrificial layer may each be formed of silicon-germanium alloy; - The method may include the following steps: forming a first capping layer covering the first superlattice before the fixing step, and forming a second capping layer covering the seed crystal layer before the fixing step; in the method, the fixing step includes placing the first capping layer in contact with the second capping layer, the first capping layer and the second capping layer together forming the separation layer; - The first capping layer and the second capping layer may each comprise silicon, and at least one of the first capping layer and the second capping layer may be formed of an oxide; - At least one of the first capping layer and the second capping layer formed of oxide may be formed by a step of forming a silicon layer and a subsequent step of oxidizing the silicon layer; - The method may further include the step of forming at least one etch stop layer on the second substrate prior to forming the seed layer, wherein the etch stop layer is removed in the step of exposing the seed layer; - The at least one etch stop layer may be formed of a layer of the same material as the second sacrificial layer and a layer of the same material as the second channel layer, the layers of the same material as the second sacrificial layer and the layers of the same material as the second channel layer being removed in the step of exposing the seed layer. Attached Figure Description

[0025] Other features and advantages of the invention will become apparent from the following detailed description of the invention, which is given herein by reference to the accompanying drawings, in which: [ Figure 1 ] Figure 1 An example of a manufacturing method according to the present invention is shown; [ Figure 2 ] Figure 2 Examples are shown Figure 1 The order of the methods; [ Figure 3 ] Figure 3 Examples show the ability to pass through Figure 1 and Figure 2 The method obtained the structural variation; [ Figure 4 ] Figure 4 Examples are shown Figure 3 Variations in the separation layer; and [ Figure 5 ] Figure 5 It is a summary Figure 1 and Figure 2 A flowchart of the manufacturing method. Detailed Implementation

[0026] Implementation

[0027] Now through Figures 1 to 5 The following related description will describe one embodiment of the present invention.

[0028] Figure 3(A) illustrates a structure Strc formed by stacking a carrier substrate Car, a first superlattice Stck1, a separation layer Sep, and a second superlattice Stck2 in this order. The first superlattice Stck1 comprises multiple first layers Ch1 and multiple first layers Sac1 stacked alternately, preferably such that each first layer Ch1 is inserted between two first layers Sac1 and in direct contact with these two first layers Sac1. The second superlattice Stck2 comprises multiple second layers Ch2 and multiple second layers Sac2 stacked alternately, preferably such that each second layer Ch2 is inserted between two second layers Sac2 and in direct contact with these two second layers Sac2.

[0029] The first layer Ch1 and the second layer Ch2 are layers formed of at least one semiconductor intended to form a transistor channel region, and may be referred to as the first channel layer Ch1 and the second channel layer Ch2, respectively. These channel layers may be formed of the same material or of different materials.

[0030] The first layer Sac1 and the second layer Sac2 are layers formed of at least one material capable of having a faster etch rate than the first layer Ch1 and the second layer Ch2, and can be designated as the first sacrificial layer Sac1 and the second sacrificial layer Sac2, respectively. These sacrificial layers can be formed of the same material or of different materials. Specifically, layer Sac1 can have Si... 1-x Ge x The composition, and layer Sac2 can have Si 1-y Ge y The composition, where x and y represent the proportions of germanium in layers Sac1 and Sac2, respectively, may be different from or equal to y. Due to the epitaxial growth compatibility of silicon and silicon-germanium alloys, which have fairly similar lattice parameters, the SiGe alloy layers Sac1 and Sac2 can be associated with silicon layers Ch1 and Ch2. Preferably, the proportions x and y are less than 40%, and for example, between 15% and 35%.

[0031] The second layers, Sac1 and Sac2, are intended to serve as sacrificial layers in the process of forming nanosheet transistors. In this process, layers Sac1 and Sac2 are removed by etching (possibly chemical etching) to obtain a structure with suspended stripes formed by layers Ch1 and Ch2. These suspended stripes are then surrounded by a gate dielectric layer and a gate metal to form a nanosheet transistor.

[0032] Figure 1 , Figure 2 and Figure 5An example of a method 500 for fabricating a structure Slc is illustrated, which advantageously relies on the separate fabrication of seed layers Init on two respective substrates: a first superlattice Stck1 and a second superlattice Stck2. The seed layers are then transferred from the second superlattice Stck2 to the first superlattice Stck1. The structure Slc is then completed by fabricating the second superlattice Stck2 by stacking successive layers on the seed layers Init. Figure 5 This is a flowchart schematically illustrating the steps of manufacturing method 500.

[0033] Figure 1 Example of step 510 is shown in (A). Car A first superlattice, Stck1, is formed on a carrier substrate, Car. In this example, the carrier substrate, Car, is a single-crystal silicon wafer.

[0034] On the surface of substrate Car S Car Above, alternating layers of silicon (Si) with a thickness of 5 nm to 15 nm, preferably 7 nm to 10 nm, are epitaxially grown, along with layers of silicon (Si) with a thickness of 5 nm to 10 nm, preferably 6 nm to 9 nm. 1-x Ge x The first silicon-germanium alloy layer Sac1, where x is the percentage of germanium in the alloy, preferably begins and ends with layer Sac1. On the last layer Sac1, in step 520 Car In this process, a capping layer Cap1 is formed, which is made of silicon (Si). This capping layer serves to prevent oxidation of the final layer, Sac1. The thickness of layer Cap1 can be less than the thickness of layers Sac1 and Ch1 that form the superlattice Stck1, and this thickness is preferably between 1 nm and 2 nm. The advantage of limiting the thickness to these values ​​is that no additional silicon channels need to be formed subsequently in the transistors formed using the obtained superlattice stack.

[0035] Figure 1 Example of step 510 is shown in (B). Don Up to step 530 Don In this example, a seed layer Init and associated layers are formed on a donor substrate Don. In this example, the donor substrate Don is a single-crystal silicon wafer.

[0036] In step 520 Don In the middle, on the surface S of the substrate Don Don A seed layer, Init, is deposited on top, wherein the seed layer has a thickness of 5 nm to 10 nm, preferably 6 nm to 9 nm, and has the chemical formula Si. 1-x Ge x The first silicon-germanium alloy layer. On this layer, in step 530 DonA capping layer Cap2 made of silicon is formed. The function of Cap2 is to prevent oxidation of layer Init, and it is preferably configured to be subsequently oxidized to form a bonding interface. The thickness of Cap2 depends on the target thickness of the future oxide layer. In other words, when the target is an oxide layer with a thickness between 10 nm and 35 nm, in this case, Cap2 must have a thickness between approximately 4 nm and 16 nm. Cap2 is optional, and its advantage depends on the ease with which the material forming the last layer of the second superlattice Stck2 is oxidized and the advantage of integrating it into the dielectric separation layer between the two superlattices.

[0037] Optionally, before forming the seed layer Init, the process can be performed in step 510. Don In this process, a Si substrate with a thickness between 5 nm and 10 nm is formed on the donor substrate Don. 1-x Ge x A first silicon-germanium alloy layer, Stp, is formed, followed by a protective silicon layer, Cap2′, with a thickness between 1 nm and 5 nm. These two layers are etch stop layers and are designed to be applied as described below and as... Figure 2 The integrity of the seed layer Init is protected during the manufacturing steps following the splitting of the donor substrate illustrated in (B) and (C).

[0038] Figure 1 Example 540 in oxidation step (C) is shown. Don In this process, the silicon (Si) layer Cap2 is oxidized to form a silicon oxide (SiO2) capping layer Ox2 with a thickness of 10 nm to 35 nm. The Cap2 layer is preferably oxidized over its entire thickness or almost its entire thickness to prevent silicon residue after the sacrificial layer is etched.

[0039] The oxidation temperature and time used are limited to avoid exceeding the allowable thermal budget, thereby avoiding or at least limiting the diffusion of germanium from one layer of the superlattice to another, and in particular avoiding or at least limiting the entire thickness of the channel layer from being contaminated with germanium.

[0040] Figure 1 The example in (C) illustrates step 550. Don In the middle, passing through layer S Don The seed layer Init and, where appropriate, the capping layer Ox2, inject optical seeds (such as hydrogen, helium, or a combination of such seeds) into the donor substrate Don to form a weakening plane Imp in the donor substrate Don.

[0041] After forming the weakened plane Imp, in bonding step 560, the donor substrate Don is flipped, and the oxide layer Ox2 is brought into close contact with and bonded to the silicon layer Cap1, for example by molecular bonding or any other bonding technique, wherein the surfaces of the components to be bonded are placed in direct contact to obtain Figure 2 The structure illustrated in (A) is called component Ass. The resulting structure is called component Ass. The separation layer Sep is formed in this step by bonding the last layers formed on the carrier substrate Car and the donor substrate Don, respectively, and corresponds to the component formed by the layers separating the first superlattice Stck1 and the second superlattice Stck2 (in this embodiment, layers Cap1 and Ox2), as shown. Figure 3 As illustrated, the separation layer Sep preferably completely covers the donor substrate Don. Furthermore, the separation layer Sep is continuously formed on the surface S of the first superlattice Stck1, parallel to the carrier substrate Car. Car In the plane. Even if the separation layer does not strictly cover the entire carrier substrate Car, it is at least continuously formed on the area where a set of semiconductor components (e.g., transistors, possibly a set of CFETs) are to be formed.

[0042] In this manufacturing stage, the seed layer Init is sandwiched between the carrier substrate Car and the donor substrate Don. This seed layer Init must be exposed to make it accessible. This exposure operation 570 is performed in two consecutive steps 570A and 570B. Step 570A involves removing most of the donor substrate, while step 570B involves exposing the seed layer Init by removing the remaining donor substrate. The exposed seed layer Init forms the outer F of the assembly Ass. ext .

[0043] In the splitting and retraction step 570A Figure 2 (B) illustrates how the donor substrate Don is split at the weakened plane Imp obtained by ion implantation, such that a portion of Don... b Removed from the structure illustrated in (A), while part of Don a It remains fixed to the structure. The splitting can be achieved through heat treatment, optionally supplemented by a mechanical force to initiate the splitting, using conventional layer transfer techniques known in the field of microelectronics.

[0044] Preferably, the carrier substrate Car, comprising the first superlattice Stck1 and the seed layer Init, is substantially the same as the donor substrate Don. This advantageously enables them to be easily mass-produced, thereby facilitating their industrialization. Furthermore, using substantially identical carrier and donor substrates advantageously allows for the acquisition of symmetrical bonded structures with similar coefficients of thermal expansion, which advantageously prevents mechanical deformation after the bonding step and subsequent heat treatment.

[0045] Following the assembly and splitting of the donor substrate, heat treatment may be applied to strengthen the bond and repair the bond layer. The heat treatment temperature and time are limited to avoid exceeding the allowable thermal budget, thereby preventing or at least limiting germanium diffusion from one layer of the superlattice to another, and particularly preventing or at least limiting germanium contamination of the entire thickness of the channel layer. Heat treatment typically includes annealing at a temperature of up to 750°C and preferably below 700°C for 2 hours or less.

[0046] An alternative to forming a weakening plane and splitting the donor substrate Don at that plane may include thinning the donor substrate Don by, for example, etching, grinding, and / or chemical mechanical polishing (CMP) after the donor substrates have been bonded. If this thinning continues, for example, to a stop layer Stp, the second substrate Don can be completely removed.

[0047] Figure 2 (C) illustrates the structure illustrated in (B) which undergoes mechanical and / or chemical attack in step 570B to remove a portion of the Don from the donor substrate Don. a The structure after etching the stop layer Stp and the protective layer Cap2′. Therefore, the seed layer Init is exposed in this step and is accessible in the rest of the manufacturing process.

[0048] Next, the second superlattice, Stck2, is formed. First, in a thin film deposition tool, any native oxide is removed from the surface of layer Init using an "in-situ" etching function available in many epitaxial tools, such as HF gas. This operation allows for the cleaning of layer Init and ensures the quality of its surface, which is essential for the quality of the layer deposited on it. Then, in epitaxial step 580, and through alternating epitaxial growth of layers Ch2 and Sac2, the second superlattice, Stck2, is formed directly on the seed layer Init. Cleaning layer Init before deposition is routine and is considered part of the steps for forming layers Ch2 and Sac2 via epitaxy. Alternatively, other known cleaning methods are conceivable, such as complete oxidation of layer Cap2′ and removal of the layer directly in the tool using HF. The main goal is to obtain a clean, unoxidized surface before depositing a thin layer on this surface, regardless of whether the deposition sequence begins with layer Sac2 or layer Ch2.

[0049] Layer Ch2 is preferably made of silicon (Si) and has a thickness of 5 nm to 15 nm, more preferably 7 nm to 10 nm, and layer Sac2 is made of silicon (Si). 1-x Ge xA first silicon-germanium alloy is formed, having a thickness of 5 nm to 10 nm, preferably 6 nm to 9 nm. Preferably, each Ch2 layer is inserted between and in direct contact with two first Sac2 layers, and the seed layer Init is considered one of the Sac2 layers. Therefore, the silicon layer Ch2 can be directly grown on the seed layer Init, where the seed layer Init has the chemical formula Si. 1-x Ge x The first silicon-germanium alloy layer can be formed, or it can be started by forming the first germanium alloy layer Sac2 directly on the seed layer Init and then forming the silicon layer Ch2 on it, and then continuing to form layers Ch2 and Sac2 alternately.

[0050] The characteristics of the seed layer Init depend on step 580: the seed layer Init has chemical properties and crystal structure that allow, for example, the formation of a second superlattice Stck2 by epitaxial continuous growth of layers. In this case, since the second superlattice is formed by alternating layers Ch2 and Sac2, it is suitable to form the layer Init from one of these two types of layers. In this case, Si is chosen as the material. 1-x Ge x The silicon-germanium alloy layer Init can be formed. Alternatively, the layer Init can be formed by another layer capable of forming a sacrificial layer relative to layer Ch2 (i.e., a layer with a faster etch rate than the second layer Ch2). Other alternatives exist, such as forming the layer Init made of silicon, or by a material favorable for forming a silicon (Si) layer or Si... 1-x Ge x Init is a layer made of other materials in the alloy layer.

[0051] Forming the superlattice Stck2 after the transfer step advantageously allows for the avoidance of thermal treatments intended to repair the effects of ion implantation on the superlattice layers. This type of repair thermal treatment can be essential for semiconductor layers used as active layers in transistors. Such thermal treatments can sometimes be performed at considerably high temperatures, which can cause germanium present in adjacent layers to diffuse completely through the channel layer.

[0052] Figure 3 The structure in (A) shows a structure Strc formed by stacking a carrier substrate Car, a first superlattice Stck1, a capping layer Cap1 formed of silicon, a silicon oxide layer Ox2, and a seed layer Init in this order. The capping layer Cap1 and the silicon oxide layer Ox2 form a dielectric separation layer Sep between the first superlattice Stck1 and the second superlattice Stck2. The separation layer is considered a dielectric layer because it is at least partially formed of a material considered to be a dielectric (e.g., silicon nitride, silicon carbonitride, or silicon oxide). This structure is ready for monolithic fabrication of a CFET.

[0053] The accompanying drawings contain indications of "Si" or "SiGe" at the locations of certain layers, particularly those forming the superlattices Stck1 and Stck2, to enhance readability by indicating the composition of these layers in specific examples. However, these indications should not be construed as limiting the nature of the layers so labeled. Other materials, particularly those mentioned herein, may be used to form these layers.

[0054] Figure 3 Structures Strc' and Strc'' are illustrated in (A') and (A''), respectively, having possible variations Sep' and Sep'' of the separation layer Sep of structure Strc. In (A), the separation layer Sep is formed by bonding a capping layer Ox2, formed of oxide, to a capping layer Cap1. These layers are the final layers formed on the donor substrate Don and the carrier substrate Car, respectively.

[0055] The first variation illustrated in (A') includes forming a silicon oxide layer Ox1 as the last layer formed on the carrier substrate Car, and forming a silicon capping layer Cap2 as the last layer formed on the donor substrate Don. Thus, the separation layer Sep' is formed by bonding layer Ox1 and layer Cap2 through molecular bonding.

[0056] The second variation illustrated in (A) includes forming two silicon oxide layers as the final layers formed on substrates Car and Don, respectively. Thus, the two silicon oxide layers are bonded together by molecular bonding to form a separation layer Sep”, and the two silicon oxide layers ultimately form a single silicon oxide layer Ox.

[0057] The separation layer Sep (which is also the layer that connects the two superlattices to each other) does not necessarily have to be formed from crystalline silicon and / or amorphous silicon oxide obtained by silicon oxide. Therefore, although Figure 1 Methods for forming an oxide layer Ox2 via a silicon oxide layer are illustrated in (A) and (B), but the oxide layer Ox2 can also be formed by directly depositing a silicon oxide layer. This observation applies to... Figure 3 The variants of the oxide layer Ox1 of (A') and the layer Ox of (A") are illustrated in (A') and (A"), respectively.

[0058] The separation layer can also consist of layers formed from amorphous silicon or other materials, provided they are compatible with the superlattice processing method envisioned below. Therefore, dielectrics, semiconductors, or metals can typically be used to form the layers constituting the separation layer, with the main limitation being that these materials must be in the form of layers with sufficiently high flatness and sufficiently low roughness to allow for bonding via direct bonding methods such as molecular bonding. When the superlattice is intended to form a CFET, dielectrics and / or semiconductors are preferably used. For example, materials selected from silicon nitride (SiN), silicon carbonitride (SiCN), and their oxides (SiON, SiCNO) can be used. X Materials or combinations thereof, such as silicon dioxide (SiO2), can be deposited or formed by low-temperature oxidation. So-called "high-k" dielectrics, such as HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, alloys thereof, or alloys thereof with silicon, can also be used. More generally, any type of dielectric used in the semiconductor industry can be used as a dielectric layer, protective layer, hard mask, or through-hole coating (intended for use as a liner for TSVs (Through Silicon Vias)).

[0059] Figure 4 An alternative is illustrated in (A), where the separation layer Sep is composed of separation layer Sep. a Sep b and Sep c They form in this order. Molecular bonding occurs in the Sep layer. c With Sep b In the interface plane Int, one layer is formed of silicon, amorphous silicon, or silicon oxide, and the other layer is formed of amorphous silicon or silicon oxide. Layer Sep a It can be formed from silicon nitride, silicon carbonitride, silicon oxide, or other dielectrics. Layer Sep a and Sep b It can replace the Ox2 layer formed on the donor substrate Don, and the Sep layer c It can replace layer Cap1 formed on the carrier substrate Car. Alternatively, layer Sep... a and Sep b It can replace layer Cap1 formed on the carrier substrate Car, and layer Sep c It can replace the Ox2 layer formed on the donor substrate Don.

[0060] Figure 4 The configuration illustrated in (B) differs from the configuration illustrated in (A) in that it further includes a separation layer Sep. d The separation layer Sep d Formed on the interface plane Int and layer Sep cOn the same side, and can be formed of silicon nitride, silicon carbonitride, silicon oxide or other dielectrics.

[0061] Figure 4 The variant separation layer illustrated is a multilayer dielectric (MDL) and, taking into account subsequent manufacturing steps, can be used to improve molecular bonding and adhesion strength.

[0062] Figure 1 and Figure 2 The fabrication method illustrated herein allows for the stacking of two superlattices. Furthermore, this method can be repeated to stack any number of superlattices. Thus, a critical epitaxial thickness can be exceeded: each of the superlattices considered individually can adhere to this thickness for formation by high-quality layers, and stacking them allows for the acquisition of components of superlattices exceeding the critical thickness while maintaining the quality of their constituent layers.

[0063] The formation of a superlattice via epitaxy requires replicating the crystal structure from one layer to the next, and thus the Si and SiGe layers formed sequentially by epitaxy have the same crystal structure. It is generally not possible to epitaxially grow semiconductor layers with acceptable properties for forming transistors on amorphous layers (e.g., dielectric layers, and more particularly oxide layers). Specifically, such layers are unsuitable for the epitaxy of high-quality crystalline semiconductor layers. The separation layer obtained by the method according to the invention enables the placement of a dielectric layer between two superlattices formed from semiconductor layers of sufficient quality, thereby producing transistors for commercial applications.

[0064] Furthermore, the separation layer can be customized according to the intended use of the stacked superlattice (composition, thickness of the single or multiple layers forming it). Thus, by adjusting the thickness of, for example, layer Cap2, the desired electrical insulation between the two superlattices Stck1 and Stck2 can be achieved, which, once oxidized to layer Ox2, forms a high-quality dielectric layer of selected thickness that covers the entire structure (or the entire wafer when the substrate is a wafer).

[0065] The separation layer is continuously formed in a plane parallel to the upper surface of the substrate supporting it, covering essentially the entire surface of the substrate. This geometry contrasts with that found in CFET structures, where the dielectric layer separating the n-type and p-type transistors follows undulations created by the structure formed between the substrate and the transistor, and can be discontinuous.

[0066] Therefore, the separation layer according to the invention can have high quality, a selected thickness, and further, good uniformity in thickness, and is substantially continuous over the segment of interest or over the entire surface of the substrate. This makes it suitable for use as an etch stop layer during various methods of manufacturing transistors, or as an enabler for differentiating transistors formed in a first superlattice from those formed in a second superlattice. Furthermore, if the SOI substrate is used as the substrate Car, the BOX can also be used as an etch stop layer to generate a back-side power supply network (BSPDN). The segment of interest may include the surface of the substrate where the separation layer is expected to be located.

[0067] The carrier substrate Car and the donor substrate Don can include any semiconductor. Besides silicon, the semiconductor can be germanium (GE), silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors, or II-VI compound semiconductors, or SOI substrates (SOI stands for silicon-on-insulator), and more generally, any type of semiconductor substrate including buried or surface dielectric layers. Such dielectric layers can be... Figure 1 and Figure 2 When the structure obtained by the illustrated method is formed on the back side (the same side as the carrier substrate Car), it is used as an etch stop layer, or, if it is located on the surface, as an insulator to prevent latch-up of integrated circuits fabricated based on the structure.

[0068] For example, layers Ch1 and Ch2 can be formed of silicon or III-V compound semiconductors. For example, layers Sac1 and Sac2 can be formed of a silicon-germanium alloy (collectively referred to as SiGe). Layers Ch1 and Ch2 can have the same composition in both superlattices Stck1 and Stck2, and similarly, layers Sac1 and Sac2 can have the same composition Si in both superlattices Stck1 and Stck2. 1- x Ge x This final point allows the sacrificial layers Sac1 and Sac2 to be removed in the same step.

[0069] Alternatively, superlattices Stck1 and Stck2 can have different properties and / or orientations. The orientation of the second superlattice relative to the first superlattice is defined during the bonding step. Layers Sac1 (and Ch1) on one side and Sac2 (and Ch2) on the other side can have different orientations, for example, having crystal axes offset by 45°. It is also possible to use strained silicon, silicon-germanium alloy (SiGe), or germanium for the channel layers of any one or both of the superlattices. When the two superlattices include a silicon-germanium alloy, the proportion of germanium in the alloy can be the same or different in the two superlattices. Of course, the properties and characteristics of the sacrificial layers Sac1 and Sac2 must be adjusted according to the properties and characteristics of layers Ch1 and Ch2. Therefore, the properties and crystal structure of the seed layer Init must be adjusted according to the characteristics of layers Sac2 and Ch2 to ensure sufficient epitaxial growth of these layers.

[0070] Similarly, the number of channel layers and sacrificial layers in the two superlattices can be the same or different.

[0071] The above embodiments exemplify the alternating combination of silicon layers and silicon-germanium alloy layers to form a first superlattice and a second superlattice. However, the invention is not limited to this specific case and can be applied, for example, to (i) superlattices composed of alternating layers of germanium and silicon-germanium alloy; (ii) superlattices composed of alternating layers of a first silicon-germanium alloy having, for example, less than 20% germanium content and layers of a second silicon-germanium alloy having, for example, more than 75% germanium content; (iii) superlattices with layers having different crystal orientations; or (iv) superlattices comprising layers of group III-V semiconductors.

[0072] The above embodiments relate to combinations of superlattices intended for forming transistors, and more specifically nanosheet transistors or CFETs. However, the scope of the invention extends beyond this field and generally includes combinations of superlattices, not just those in the semiconductor field.

[0073] The present invention is not limited to the above-described embodiments, and variations may be made without departing from the scope of the invention as defined by the claims.

Claims

1. A method (500) for fabricating a structure comprising a superlattice stack (Strc, Strc', Strc''), the method (500) comprising the following steps: - A (510) structure is formed on a first substrate (Car) by alternately stacking multiple first channel layers (Ch1) and multiple first sacrificial layers (Sac1). Car First superlattice (Stck1); - By adding material to the second substrate (Don), a (520) is formed. Don The seed layer (Init) of the second superlattice (Stck2); - By implanting light-grained ions into the second substrate (Don), a (550) structure is formed in the second substrate (Don). Don Weakening plane (Imp); - An assembly (Ass) is formed by bonding (560) the seed layer (Init) to the first superlattice (Stck1) via dielectric separation layers (Sep, Sep', Sep''), which separate the first superlattice (Stck1) from the seed layer (Init) and keep them fixed to each other. - After the bonding step (560), the first portion (Don) of the second substrate (Don) is removed (570A) by splitting the second substrate (Don) at the weakened plane (Imp). b ), and remove that portion (Don) of the second substrate (Don). b ); - After step (570A) of splitting the second substrate (Don), the seed layer (Init) is exposed (570B) such that the exposed seed layer forms the outer side (F) of the component (Ass). ext The exposure step includes: removing the first portion (Don) of the second substrate (Don). b After the step of ), the second portion (Don) of the second substrate that remains bonded to the seed layer (Init) is removed. a );as well as - By alternately stacking multiple second channel layers (Ch2) with multiple second sacrificial layers (Sac2), on the outside of the exposed seed layer (Init) (F ext ) on and the outer side (F ext The second superlattice (Stck2) is formed in direct contact with the ground.

2. The method according to claim 1, wherein, The weakening plane (Imp) of the second substrate (Don) is formed by implanting light seed ions into the second substrate (Don) through the seed layer (Init).

3. The method according to claim 1 or 2, wherein, The separation layers (Sep, Sep', Sep'') are continuously formed on the surface (S) parallel to the first substrate (Car) where the first superlattice (Stck1) is formed. Car In the plane of ).

4. The method according to any one of claims 1 to 3, wherein: - The first channel layer (Ch1) and the second channel layer (Ch2) are each formed from semiconductor materials; and - The first sacrificial layer (Sac1) and the second sacrificial layer (Sac2) are each capable of forming materials with a faster etch rate than the first channel layer (Ch1) and the second channel layer (Ch2).

5. The method according to any one of claims 1 to 4, wherein: - The first trench layer (Ch1) and the second trench layer (Ch2) are each formed from silicon; and - The first sacrificial layer (Sac1) and the second sacrificial layer (Sac2) are each formed from a silicon-germanium alloy.

6. The method according to any one of claims 1 to 5, the method comprising the following steps: - Before the fixed step (560), form (520) Car The first capping layer (Cap1, Ox1) covering the first superlattice (Stck1); and - Before the fixing step (560), a second capping layer (Cap2, Ox2) is formed to cover the seed crystal layer (Init). The fixing step (560) includes placing the first capping layer (Cap1, Ox1) in contact with the second capping layer (Cap2, Ox2), wherein the first capping layer (Cap1, Ox1) and the second capping layer (Cap2, Ox2) together form the separation layer (Sep, Sep', Sep'').

7. The method according to claim 6, wherein, The first capping layer (Ox2) and the second capping layer (Cap2) each comprise silicon, and at least one of the first capping layer (Ox1) and the second capping layer (Ox2) is formed of oxide.

8. The method according to claim 7, wherein, At least one of the first capping layer and the second capping layer formed of oxide is formed by (530) Don The steps of the silicon layer (Cap2) and subsequent oxidation (540) Don This silicon layer is formed through a series of steps.

9. The method according to any one of claims 1 to 8, the method further comprising forming (510) on the second substrate (Don) prior to forming the seed layer (Init). Don The step of at least one etch stop layer (Stp, Cap2′) is performed, which is removed in the step (570B) of exposing the seed layer (Init).

10. The method according to claim 9, wherein, The at least one etch stop layer is formed of a layer (Stp) of the same material as the second sacrificial layer (Sac2) and a layer (Cap2') of the same material as the second channel layer (Ch2), which are removed in the step (570B) of exposing the seed layer (Init).

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