Device package having cavities with sloped sidewalls

Abstract

A semiconductor device package (100, 200a, 200b) may include a conductive member (101, 201) having a cavity (102, 202) formed therein, the cavity (102, 202) having at least one sidewall (104, 204, 218) having an angled portion (104a, 204a, 218) angled outward relative to a central portion of the cavity (102, 202). The semiconductor device package (100, 200a, 200b) may include a semiconductor device (203) positioned within the cavity (102, 202) and surrounded by an encapsulant (506, 508, 510, 512). At least one sidewall (104) may have a chamfered edge (104a, 104b, 204a, 204b) or a beveled edge (218).

Description

Cross-references to related applications

[0001] This application claims the benefit and priority of U.S. Provisional Application No. 63 / 649,068, filed May 17, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] This description relates to semiconductor device packaging. Background Technology

[0003] Semiconductor device packaging typically involves encasing one or more semiconductor devices in a protective housing that provides electrical connectivity, heat dissipation, mechanical support, and / or electrical isolation. Many different types of semiconductor device packages exist, offering varying degrees of packaging parameters. These packaging parameters may include, but are not limited to, performance parameters (e.g., speed or power handling performance), cost parameters, and / or size parameters. Summary of the Invention

[0004] According to one general aspect, a semiconductor device package includes: a conductive member having a cavity formed therein, the cavity having at least one sidewall having an angled portion angled outward relative to a central portion of the cavity; and a semiconductor device positioned within the cavity.

[0005] According to another general aspect, a package for an embedded semiconductor device includes: a substrate having a cavity formed therein, the cavity having at least one angled sidewall. The package for the embedded semiconductor device further includes at least one semiconductor device disposed within the cavity; and an encapsulation surrounding the at least one semiconductor device within the cavity.

[0006] According to another general aspect, a method of forming a semiconductor device package includes: forming a cavity within a substrate, the cavity having at least one angled sidewall. The method further includes: disposing at least one semiconductor device within the cavity; and encapsulating the at least one semiconductor device within the cavity with an encapsulating material.

[0007] Details of one or more specific embodiments are set forth in the accompanying drawings and the following description. Other features will be apparent from the specification and drawings, as well as from the claims. Attached Figure Description

[0008] Figure 1 An example is shown of a semiconductor device package including a substrate having a cavity with angled sidewalls.

[0009] Figure 2A It corresponds to Figure 1 The example is a cross-sectional side view illustrating the chamfered edge.

[0010] Figure 2B This is an alternative example implementation, illustrating a similar approach. Figure 1 A cross-sectional side view of an example, with beveled edges.

[0011] Figure 3 yes Figure 2A An alternative cross-sectional side view of the example.

[0012] Figure 4 yes Figure 1 A cross-sectional side view of an example, which includes multiple semiconductor devices.

[0013] Figure 5 yes Figure 4 The example is a cross-sectional side view, illustrating... Figure 4 Example encapsulation of an example.

[0014] Figure 6A Examples Figure 2A The first example package of the implementation scheme.

[0015] Figure 6B Examples Figure 2A The second example encapsulation of the implementation scheme.

[0016] Figure 7 Examples are shown for manufacturing Figures 2 to 2. Figure 6B The first example operation of the implementation scheme.

[0017] Figure 8 Examples are shown for manufacturing Figures 2 to 2. Figure 6B The second example operation of the implementation scheme.

[0018] Figure 9 Examples are shown for manufacturing Figures 2 to 2. Figure 6B The third example operation of the implementation plan.

[0019] Figure 10 Examples are shown for manufacturing Figures 2 to 2. Figure 6B The fourth example operation of the implementation plan.

[0020] Figure 11 Examples are shown for manufacturing Figures 2 to 2. Figure 6B The fifth example operation of the implementation plan.

[0021] Figure 12 Examples are shown for manufacturing Figures 2 to 2. Figure 6B The sixth example operation of the implementation plan.

[0022] Figure 13 Examples are shown for manufacturing Figures 2 to 2. Figure 6B The seventh example operation of the implementation plan.

[0023] Figure 14 This is an example used in manufacturing Figures 1 to 6B A flowchart illustrating example operations of a semiconductor device package, corresponding to... Figures 7 to 13 Example operation. Detailed Implementation

[0024] The described techniques and embodiments provide improved semiconductor device packaging, including facilitating assembly, increasing safety margins, improving electrical isolation, and enhancing encapsulation. For example, one or more semiconductor devices may be disposed within a cavity formed in a substrate, wherein one or more sidewalls of the cavity are tilted or angled relative to the semiconductor device.

[0025] This method of forming the cavity sidewalls provides an opening near the top of the cavity that is wider than the opening at the bottom or base plate. This facilitates the insertion and placement of semiconductor devices within the cavity. For example, a semiconductor device can be inserted into and centered within the cavity without contacting the sidewalls during insertion. Therefore, the assembly of the resulting semiconductor device package is improved compared to existing assembly techniques.

[0026] Once the semiconductor device is placed within the cavity, it can be encapsulated using a suitable encapsulant (e.g., epoxy, polymer, resin, or molding material). In such cases, sloping cavity sidewalls provide wider openings to receive the encapsulant compared to cavities with straight sidewalls. Therefore, during the lamination process, the flow of the encapsulant into the cavity and around the semiconductor device can be improved, ensuring a more complete and consistent encapsulation.

[0027] Furthermore, after the semiconductor device package is assembled, the angled sidewalls provide an increased distance between the top of the semiconductor device and the top of the cavity sidewall. This increased distance provides a high safety margin and isolation capability between the semiconductor device and the substrate.

[0028] In various embodiments, the sloping sidewalls can be chamfered or beveled. The sloping sidewalls can be angled at 45 degrees or at any suitable or desired angle. Cavities including sloping sidewalls can be formed using mechanical techniques (e.g., mechanical stamping or mechanical milling) and / or chemical techniques (e.g., etching). For example, a cavity can be formed using a mechanical die, and then a chemical etching technique can be used to reduce sharp edges / corners on the cavity sidewalls. In other example embodiments, a tumbling polishing technique can be used to remove sharp edges / corners.

[0029] Figure 1 An example of a semiconductor device package 100 is shown, which includes a substrate 101 having a cavity 102, which may also be referred to as a recess, hole, or opening. As shown, a semiconductor device 103 may be positioned within the cavity 102, representing, for example, any suitable semiconductor die or chip. The semiconductor device package 100 may include components not shown for clarity and simplicity. Figure 1 Various other features are shown, such as the encapsulation of the semiconductor device 103 and various types of electrical connections. Some examples of such features are provided below, but no limitation is made to the possible features of the semiconductor device package 100.

[0030] exist Figure 1 In the example, cavity 104 is illustrated as having angled sidewalls 104. As mentioned above and described in more detail below, one or more of the angled sidewalls 104 may be angled outward relative to the intermediate portion (e.g., center) of cavity 102. For example, as shown, all of these sidewalls (e.g., all four sidewalls) may be angled. In other example implementations, fewer sidewalls than all of the sidewalls may be angled; for example, two opposing sidewalls may be angled, and / or different sidewalls (or sidewall pairs) may be angled at different angles.

[0031] The angled sidewall 104 can be partially or fully tilted at any desired or available angle. For example, as illustrated in exploded view 100a, the angled sidewall 104 can be configured with chamfered edges, wherein the upper portion 104a of the angled sidewall 104 is angled relative to the base plate of the semiconductor device 103 and cavity 102, while the lower portion 104b of the angled sidewall 104 forms a smaller angle, for example, perpendicular to the base plate of cavity 102. This will be discussed in more detail below. Figure 2A More detailed examples of implementations with chamfered edges are provided, while Figure 2B An example is provided of angled sidewalls 104 with beveled edges, wherein each angled sidewall in the angled sidewalls 104 is tilted at a constant angle away from the semiconductor device 103 relative to the cavity floor.

[0032] As mentioned above, the angled sidewall 104 facilitates the placement and centering of the semiconductor device 103 within the cavity 102. For example, compared to the base plate of the cavity 102, the angled sidewall 104 provides a larger area and perimeter of the cavity 102 at its top surface. Therefore, when the semiconductor device 103 is positioned relative to the center of the cavity 102 and placed within the cavity 102, the placement tool for placing the semiconductor device 103 within the cavity 102 has a larger error margin.

[0033] Once placed, the increased area at the top of cavity 102 also facilitates the encapsulation of semiconductor device 103, as any encapsulating material with a larger area enters cavity 102 and surrounds semiconductor device 103 (e.g., flows above and around it). After encapsulation, the increased distance between semiconductor device 103 and angled sidewalls 104 at the top of cavity 102 reduces the chance of short-circuit events and generally improves the reliability of semiconductor device package 100. The following section, for example, relates to... Figure 2A, Figure 2B and Figure 3 Additional features and advantages are provided for the angled sidewall 104.

[0034] Figure 1 The rounded corner 106 of cavity 102 is also illustrated. The rounded corner 106 reduces the chance that the corner of semiconductor device 103 will come into contact with substrate 101 during insertion of semiconductor device 103 into cavity 102, which may cause breakage or other damage to semiconductor device 103.

[0035] Figure 2A It corresponds to Figure 1 The example is a cross-sectional side view illustrating a chamfered edge. Figure 2A In the example, semiconductor device package 200a includes a substrate 201 having a cavity 202 with angled sidewalls 204. As shown, semiconductor device 203 may be located within cavity 202.

[0036] As mentioned above Figure 1 As mentioned, the angled sidewalls 204 may be constructed with chamfered edges, wherein the lower portion 204b of each sidewall 204 is perpendicular to the bottom plate of the cavity 202, and the upper portion 204a of each sidewall 204 is angled outward relative to the centerline of the cavity 202 and relative to the semiconductor device 203.

[0037] In other words, the lower portion 204b provides the vertical wall portion of the cavity 102, and the upper portion 204a provides the angled wall portion of the cavity 102, resulting in the sidewall 104 having chamfered edges. Therefore, each such chamfered edge provides a non-uniform (e.g., gradient) distance d2 between the semiconductor device 203 and the substrate 201 at or near the top of the semiconductor device 203, which is greater than the distance d1 between the semiconductor device 203 and the substrate 201 at or near the bottom of the semiconductor device 203.

[0038] exist Figure 2A In the example, substrate 201 may represent any conductive member that provides a suitable mounting surface or mounting member in which a cavity 202 may be formed and a semiconductor device 203 may be positioned. For example, substrate 201 may represent a conductive member such as a lead frame, such as a metal lead frame (e.g., a copper lead frame).

[0039] exist Figure 2A In this configuration, the additional conductive portion 220 is separated from the substrate 201 by an isolation layer 219. For example, the isolation layer 219 may be a ceramic isolation layer or any suitable insulating, non-conductive material. Although not explicitly illustrated in the following examples, it should be understood that such isolation layers and secondary conductive portions may be included in any embodiment of the illustrated and described embodiments.

[0040] More generally, substrate 201 can be implemented as a single material or multiple materials. For example, substrate 201 may include multiple layers in a direct-bonded metal (DBM) or direct-bonded copper (DBC) structure, wherein the dielectric material is situated between two metal materials (e.g., copper or aluminum). Substrate 201 may be part of a larger printed circuit board (PCB) and panel assembly.

[0041] exist Figure 2A In the example, die attachment material 206 attaches the semiconductor device 203 to the substrate 201 within the cavity 202. For example, die attachment material 206 may include Ag sintered material or solder.

[0042] A first or bottom metallization layer 208 is formed on the semiconductor chip or die 210 of the semiconductor device 203 using any suitable metal (e.g., an alloy of titanium, nickel, and silver) and between the semiconductor die 210 and the substrate 201. A second or top metallization layer 212 is formed on the semiconductor die 210 using any suitable metal (e.g., Al) and on the opposite side of the semiconductor die 210. As shown, the first / bottom metallization layer 208 is formed to be in full electrical contact with the substrate 201, while the second / top metallization layer 212 is patterned to connect with the first contact 214 and the second contact 216. The first contact 214 and the second contact 216 may be formed, for example, using plated Cu.

[0043] More generally, the metallization process may include one or more metal layers and / or one or more insulating layers, which may be used as a stacking layer that may result in one or more of the source contact 214 and drain contact 216 being a multilayer structure. In some specific embodiments, the metallization layer may be added after the semiconductor device 203 has been embedded in the substrate 201.

[0044] exist Figure 2A In the example, semiconductor device 203 represents a transistor, wherein substrate 201 provides a drain contact, first contact 214 provides a source contact, and second contact 216 provides a gate contact. The transistor can be any suitable transistor made of any suitable material, such as a silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) transistor. Of course, these are merely examples, and various types of semiconductor devices, such as diodes, or combinations thereof, may be included within cavity 202.

[0045] For example, semiconductor device 203 can represent various types of power transistors, such as insulated-gate bipolar transistors (IGBTs), power metal-oxide-semiconductor field-effect transistors (MOSFETs), etc. Electrical interconnects within the high-power semiconductor device package may include, for example, bonding wires, conductive spacers, metal and insulating building blocks, and conductive clamps.

[0046] The substrate 201 may be implemented as or combined with a leadframe for providing external electrical connections to a high-power semiconductor device package. For example, some of the high-power components described herein operate at voltages ranging from about 200 V to about 800 V. Such high-power chip assemblies, encapsulated as embedded semiconductor device modules, can be used in a variety of applications, including electric vehicles (EVs), hybrid electric vehicles (HEVs), and industrial applications.

[0047] exist Figure 2A In one example, the top surface of semiconductor device 203 (e.g., the top surfaces of the first contact 214 and the second contact 216) is coplanar with the top surface of substrate 201. In other words, the height of semiconductor device 203 is approximately the same as the depth of cavity 202. However, in other examples, the height of semiconductor device 203 may differ from the depth of cavity 202, for example, it may be greater than or less than the depth of cavity 202.

[0048] exist Figure 1 and Figure 2A In the example, the distances d1 and d2 around the semiconductor devices 103 / 203 can be uniform, but such uniformity is not required. For example, the cavity 202 may not be a square or other equilateral shape, thus creating different distances d1 and d2 on different sides of the semiconductor devices 103 / 203. In other examples, two or more devices may exist within the cavity 102 / 202 such that the sides of two devices are adjacent to each other, rather than adjacent to the sidewalls of the corresponding cavities.

[0049] Figure 2B This is an alternative example implementation, illustrating a similar approach. Figure 1 The example is a cross-sectional side view with a beveled edge. That is, as shown... Figure 2B As shown in the semiconductor device package 200b, the angled sidewall 218 is perfectly straight between the bottom plate of the cavity 202 and the top of the substrate 201. Therefore, a distance d3 is defined at the bottom plate of the cavity 202 between the semiconductor device 203 and the sidewall 218, and a distance d4 is defined near the top of the substrate 201 between the semiconductor device 203 and the sidewall 218, where d4 is greater than d3. In other words, distances d3 and d4 (e.g., the difference between distances d4 and d3) define the tilt angle of the sidewall 218.

[0050] Will understand, Figure 2Aand Figure 2B These are non-limiting examples, and various specific implementations may include any angled sidewalls for which the distance between the semiconductor device 203 and the sidewall 218 at the bottom of cavity 202 is smaller than the distance between the semiconductor device 203 and the sidewall 218 near the top of substrate 201. For example, Figure 2B beveled edge or Figure 2A The angle of the chamfered edge can be increased or decreased to provide correspondingly more or less spacing near the top of cavity 202 for placing and encapsulating semiconductor device 203.

[0051] generally, Figure 1 , Figure 2A and Figure 2B Embedded device architectures, as well as the various embedded device architectures described and illustrated below, can provide improved performance compared to surface mount dies, for example, faster speeds due to shorter interconnects. Embedded devices can also produce more compact semiconductor packages and, by extension, miniaturized printed circuit boards (PCBs).

[0052] In some implementations, embedded die packaging technology can be used to package one or more of the described semiconductor devices, wherein the one or more semiconductor devices can be embedded in the PCB rather than mounted on the surface of the PCB. When a system-on-a-chip (SOC) or multiple chips are embedded in the PCB, the resulting system can be referred to as a system-on-board (SiB). In some implementations, to further enhance performance, one or more semiconductor devices can be embedded in substrate 201, and then packaged using embedded die packaging.

[0053] Figure 3 yes Figure 2A An alternative cross-sectional side view of the example. Figure 3 A semiconductor device package 300 having a cavity 302 and chamfered sidewalls 304 is illustrated, and further illustrations of the semiconductor device within the cavity 302 are omitted.

[0054] Figure 3 An example is shown where the height of the vertical sidewall portion 304b is relative to the angled sidewall portion 304a of the chamfered edge 304 and relative to... Figure 2A The examples vary. That is, in various embodiments, the vertical sidewall portion 304b can be a larger or smaller portion of the total height of the chamfered edge 304. Furthermore, the angled sidewall portion 304a can be positioned at any suitable angle, such as 45 degrees.

[0055] Furthermore, as shown in exploded view 300a, the sharp corners of the chamfered edge 304 can be rounded, for example, to reduce changes in electric field density. For example, as described in more detail below, forming the cavity 302 by mechanical means (e.g., by mechanical stamping) may form the sharp corners of the chamfered edge 304, and subsequent processing (e.g., chemical etching, micro-etching, and / or barrel polishing processes) can be used to provide rounding of the sharp corners.

[0056] Figure 4 yes Figure 1 A cross-sectional side view of an example, which includes multiple semiconductor devices. Figure 4 In this embodiment, substrate 401 has a cavity 402, which has angled sidewalls 404 formed therein. Figure 4 In the example, the first semiconductor device 406 and the second semiconductor device 408 are disposed within the cavity 402. The semiconductor devices 406 and 408 can be attached to the substrate 401 using any suitable technique, including, for example, Ag sintering, solder bonding, or diffusion bonding.

[0057] Figure 4 Implementation schemes facilitate, for example, parallel device connections to accommodate higher currents and higher power densities (i.e., higher currents in a smaller footprint than conventional devices). Although Figure 4 Two semiconductor devices 406 and 408 are illustrated, but cavity 402 may include three or more devices.

[0058] Figure 5 yes Figure 4 The example is a cross-sectional side view, illustrating... Figure 4 The example encapsulation of the example. That is, Figure 5 An example is shown after the embedding process. Figure 4 Examples.

[0059] exist Figure 5 In the example, encapsulations 506, 508, 510, and 512 embed semiconductor devices 406 and 408 within cavity 402. Metal layers 504 and 514 provide electrical connections to semiconductor devices 406 and 408. For example, source contacts 516 and gate contacts 518 of semiconductor device 406 are provided through via 502, while metal layer 504 provides drain connections to both semiconductor devices 406 and 408 through via 520. More specifically, as described below... Figures 8 to 14 As described and illustrated in the process flow, through-holes 502 and 520 can be formed through the encapsulations 506, 508, 510, and 512 to establish any desired electrical connection.

[0060] Figure 6A The first example package of the implementation shown in Figure 2 is illustrated. Figure 6AIn the embodiment shown in Figure 2, diced embedded devices 602, 604, and 606 are formed, wherein the encapsulation and electrical connection are similar to those described above. Figure 5 The packaging and electrical connections described and illustrated.

[0061] Figure 6B A second example encapsulation of the embodiment shown in Figure 2 is illustrated. Figure 6B In this configuration, embedded devices 610, 612, and 614 are included in a single bonding panel 608, rather than being separated. As shown, the drain potentials of the different embedded devices 610, 612, and 614 can be bridged by establishing an additional copper plating 618 extending through the via 620.

[0062] Figures 7 to 13 Examples are shown for manufacturing Figures 2 to 2. Figure 6B Exemplary operation of the implementation scheme. Figure 14 This is an example used in manufacturing Figures 1 to 6B A flowchart illustrating example operations of a semiconductor device package, corresponding to... Figures 7 to 13 Example operation.

[0063] exist Figure 7 In the example, a cavity 702 having angled sidewalls 704 can be formed within a substrate 701, for example, using a stamping tool 700. Figure 14 (1402 in the figure). As shown, the stamping tool 700 may have such a shape that, when stamped into the substrate 701, results in the formation of a cavity 702 of a desired size and has angled sidewalls 704 of a desired shape. In other words, the stamping tool 700 may have a shape that is inverted relative to the desired shape of the angled sidewalls 704 (e.g., concave in the case where the angled sidewalls are convex).

[0064] In this way, any desired shape or structure of the angled sidewall 704 can be obtained, including, Figure 7 As shown and above regarding Figure 1 and Figure 2A The formation of the chamfered edges illustrated and described, or as... Figure 2B The beveled edge is shown. More generally, any available or desired angle and / or length of each angled sidewall 704 can be obtained by selecting an appropriate corresponding stamping tool 700.

[0065] although Figure 7 The use of the stamping tool 700 is illustrated, but other techniques can be used to provide the cavity 702 with angled sidewalls 704. For example, a chemical etching process can be used. Furthermore, combinations of these methods can be used. For example, as described above... Figure 3As described, cavity 702 may initially be formed with angled sidewalls 704 having sharp edges / corners. Then, chemical or mechanical processes can be used to reduce or eliminate the sharp edges / corners, for example, to provide rounded corners. Thus, the electric field density at the corners can be reduced.

[0066] When including ceramic insulating layers (such as Figure 2B When forming the isolation layer 219, the cavity 702 can be formed in a manner that takes into account the brittle nature of the isolation layer. For example, mechanical polishing and / or chemical etching can be used.

[0067] Figure 8 The placement of semiconductor device 806 within cavity 702 is illustrated. Figure 14 (1404 in the above description). As described above, the angled sidewall 704 facilitates the placement of the semiconductor device 806 within the cavity 702, for example, by providing a relatively wide opening that allows the semiconductor device 806 to be centered within the cavity 702. The bottom of the cavity 702 can be finished with any suitable surface treatment for die attachment, and attachment can be performed using any suitable technique, such as sintering, soldering, or diffusion bonding.

[0068] although Figure 7 and Figure 8 An example with a single cavity 702 and semiconductor device 806 is illustrated; however, it should be understood that, as described above, cavity 702 can be of any suitable size, and two or more devices can be positioned within cavity 702. Furthermore, it can be formed in one step. Figure 7 and Figure 8 Multiple instances of the example. That is, it can be used. Figure 7 technology (and) Figure 14 In section 1402), multiple cavities are formed in a larger portion of the substrate material (e.g., copper), and can be used... Figure 8 technology (and) Figure 14 (1404) Positions one or more semiconductor devices within a corresponding cavity. Then, dicing can be performed to obtain... Figure 8 The result.

[0069] Figures 9 to 13 The examples illustrate additional operations that can be performed prior to dicing, such that two substrates 701a / 701b and two semiconductor devices 806a / 806b are illustrated. That is, as shown, substrate 701a includes a cavity 702a having angled sidewalls 704a, and substrate 701b includes a cavity 702b having angled sidewalls 704b.

[0070] exist Figure 9 In this process, stacked components were prepared. Figure 14(1406 in the figure). Specifically, substrates 701a and 701b are encapsulated within a core layer 902. Core layer 902 may comprise any suitable material or composite material, such as that used for semiconductor packaging. For example, core layer 902 may be formed of FR-4 (flame retardant 4), which is a composite material of woven glass fiber impregnated with epoxy resin or other reinforcing materials. As shown, core layer 902 may be prepared with notches in which substrates 701a and 701b are placed.

[0071] Furthermore, in Figure 9 In this configuration, prepreg layer 904 is positioned across the top of core layer 902, substrates 701a and 701b, and semiconductor devices 806a and 806b. Similarly, prepreg layer 906 is positioned across the bottom of core layer 902, substrates 701a and 701b, and semiconductor devices 806a and 806b. Prepreg layers 904 and 906 typically refer to reinforcing materials such as fiberglass or other fabrics impregnated with a partially cured resin (such as epoxy resin). Copper layer 908 is positioned on prepreg layer 904, and copper layer 910 is positioned on prepreg layer 906.

[0072] exist Figure 10 In this process, lamination and embedding are performed. Figure 14 (1408 in the example). For example, vacuum embedding can be performed, wherein heat and pressure are applied during the lamination process to cause the resin in the prepreg layers 904, 906 to flow and cure, thereby forming a solid structure as encapsulation 1002. As mentioned above, and as... Figure 9 and Figure 10 As shown, the angled sidewalls 804a and 804b allow the prepreg layer 904 to flow completely, intactly, and reliably into the cavities 702a and 702b and around the semiconductor devices 806a and 806b.

[0073] exist Figure 11 In this process, components for electrical interconnection are formed. Figure 14 Through holes 1102 and 1104 (1410 in the example). For example, laser ablation processes or other techniques (e.g., drilling and / or etching) can be used.

[0074] exist Figure 12 In this process, copper plating of 1202 and 1204 is provided for through-holes to complete the electrical interconnects. Figure 14 (1412 in the middle). Then, in Figure 13 In this configuration, the top copper layer 908 and the bottom copper layer 910 can be configured to isolate previously formed electrical interconnects. For example, as shown, a source connection 1302a and a gate connection 1304a can be established for semiconductor device 806a, and a source connection 1302b and a gate connection 1304b can be established for semiconductor device 806b.

[0075] In some specific implementations, soldering can be or can include a process of joining two surfaces (e.g., metal surfaces) together using a molten filler metal that may be referred to as solder (e.g., metal alloys, tin (Sn), lead (Pb), silver (Ag), copper (Cu)).

[0076] In some embodiments, sintering can be, or can include, a process of fusing particles together into a solid substance using, for example, a combination of pressure and / or heat without melting the material. In some embodiments, sintering can include agglomerating a material (e.g., a powdered material) into a solid or porous substance by heating the material and typically also compressing it without liquefying it. In some embodiments, materials that can be used for sintering can include metals such as silver (Ag), copper (Cu), and / or metal alloys. In some embodiments, sintered joints can have desired electrical and / or thermal conductivity, durability, and a relatively high melting temperature.

[0077] In some specific implementations, one or more components of the parts described herein may be coupled using materials such as solder, sintered (e.g., silver, copper) and / or other metal-to-metal bonding materials.

[0078] In some specific implementations, component coupling can be performed using processes such as soldering, sintering (e.g., silver sintering, copper sintering) and / or other metal-to-metal bonding processes.

[0079] In some embodiments, a DBM substrate can be formed by bonding one or more metal layers (e.g., a first metal layer, a second metal layer) to an insulating layer. In some embodiments, one or more metal layers can be bonded to an insulating layer using, for example, a high-temperature process.

[0080] In some embodiments, the DBM substrate may include an insulating layer disposed between the first metal layer and the second metal layer. The insulating layer may be, for example, a ceramic layer. In some embodiments, the insulating layer may be, or may contain, a ceramic material such as alumina (Al₂O₃) or aluminum nitride (AlN).

[0081] In some embodiments, the first metal layer and / or the second metal layer may be, or can be used as, a heat sink. In some embodiments, the first metal layer and / or the second metal layer may be coupled to a heat sink. In some embodiments, at least a portion of one or more of the first metal layer or the second metal layer may be exposed by a molding material.

[0082] In some embodiments, the first metal layer and / or the second metal layer may be or may include a patterned metal layer, which includes one or more conductive traces. In some embodiments, the first metal layer and / or the second metal layer may be or may include a patterned layer configured to form one or more circuits, one or more conductive blind vias and / or through-holes, etc.

[0083] In some embodiments, the DBM substrate may be or may include a direct-bonded copper (DBC) substrate. In some embodiments, such as in a DBC substrate embodiment, the first metal layer and / or the second metal layer is a copper layer.

[0084] In some embodiments, one or more semiconductor dies (e.g., one or more semiconductor components) may be or may include power semiconductor dies. In some embodiments, one or more semiconductor dies may be one or more of the following (e.g., may be part of one or more of the following) or may include one or more of the following: metal-oxide-semiconductor field-effect transistor (MOSFET) devices, insulated-gate bipolar transistors (IGBTs), integrated circuits (ICs), inverters, power conversion circuits, bridge circuits, fast recovery diodes (FRDs), and / or diodes, etc. In some embodiments, one or more semiconductor dies may be components for electric vehicles (EVs) (e.g., may be part of such components) or may include such components.

[0085] The specific embodiments described herein may include more than one semiconductor die. In some embodiments, different semiconductor substrates (e.g., silicon carbide (SiC substrate, silicon (Si) substrate, gallium nitride (GaN) substrate) may be used to fabricate different semiconductor dies (when more than one semiconductor die is included in some of these embodiments). In other words, different semiconductor dies may be fabricated, for example, on different semiconductor wafers or materials. This may be referred to as a hybrid die configuration. For example, a first semiconductor die may be formed using a SiC substrate, and a second semiconductor die (separate from the first semiconductor die) may be formed using a silicon substrate. As another example, an IGBT may be fabricated using a SiC substrate, while a controller may be fabricated using a silicon substrate.

[0086] In a specific embodiment of the example, the first semiconductor die may be connected to the second die, for example, via an electrical connection (e.g., a wire bond, an electrical clamp) extending directly from the first die into the second die, or via a trace formed in a first conductive layer (e.g., a metal layer) of the electronic power substrate. The first semiconductor die among a plurality of semiconductor dies may also be connected to lead frame posts via electrical connections (such as wire bonds or clamps).

[0087] In some exemplary embodiments, the package (e.g., a power module) may be a hybrid device package comprising one or more semiconductor dies integrated onto a uniform electronic power substrate (e.g., a ceramic substrate, a DBM or DBC substrate, an AMB substrate, an elastomer substrate, an organic substrate, a phenolic substrate, or a PCB / FR-4 substrate). In some embodiments, multiple semiconductor devices may be fabricated, for example, on the same substrate (such as a SiC substrate) suitable for high-power applications.

[0088] Although referred to by way of example as a lead frame in at least some parts of this specific embodiment, the lead frame may include any type of conductive portion of the package (e.g., conductive portion, conductive terminal) that provides an external connection point from the package. Therefore, the lead frame may be referred to as a conductive portion of the package.

[0089] In some implementations, one or more portions of the leadframe may be coupled to pads (e.g., bonding pads) on at least a portion of the DBM substrate.

[0090] In some specific implementations, the molding material (e.g., molding material or compound, encapsulating material) may be or may include a non-conductive layer / material.

[0091] One or more wire bonds that may be included in at least some of the embodiments described herein may be replaced with conductive components. For example, in some embodiments, one or more wire bonds may be replaced with conductive clips. Conductive clips may be coupled to another component (e.g., attachment pads, lead frames, semiconductor dies, etc.) using, for example, solder (e.g., soldering process), sintering coupling (e.g., sintering process), welding, etc. In some embodiments, one or more wire bonds and / or clips may be used as input and / or output power terminals, signal terminals, power terminals, etc.

[0092] In some implementations, one or more semiconductor dies may be embedded within the layer (rather than surface mounted). For example, one or more semiconductor dies may be disposed in a recess (or cavity) of the layer (e.g., substrate, printed circuit board, conductive layer, insulating layer).

[0093] In some implementations, a module (e.g., a package including a semiconductor device) may be included within another module. A module may be referred to as a package. For example, one or more modules may be one or more sub-modules included within another module. In other words, a first module may be included as a sub-module within a second module.

[0094] In a first embodiment (referred to as Embodiment 1), a semiconductor device package includes: a conductive member having a cavity formed therein, the cavity having at least one sidewall having an angled portion angled outward relative to a central portion of the cavity; and a semiconductor device positioned within the cavity.

[0095] Example 2 includes the semiconductor device package according to Example 1, and further includes: a molding material formed around the semiconductor device and within the cavity.

[0096] Example 3 includes a semiconductor device package according to Example 1, wherein at least one sidewall has a chamfered edge, wherein the chamfered edge includes a vertical portion perpendicular to the base plate of the cavity, and the angled portion is engaged with the vertical portion.

[0097] Example 4 includes a semiconductor device package according to Example 3, wherein the corner formed between the vertical portion and the angled portion is rounded.

[0098] Example 5 includes a semiconductor device package according to Example 1, wherein at least one sidewall has a beveled edge.

[0099] Example 6 includes a semiconductor device package according to Example 1, wherein the conductive component is a metal lead frame.

[0100] Example 7 includes a semiconductor device package according to Example 1, wherein the cavity is rectangular.

[0101] Example 8 includes a semiconductor device package according to Example 7, wherein at least one corner of the cavity is rounded.

[0102] Example 9 includes the semiconductor device package according to Example 1, the semiconductor device package further comprising: An isolation layer is disposed on the side of the conductive member opposite to the cavity; and The second conductive component is disposed on the isolation layer.

[0103] In the tenth embodiment (referred to as Embodiment 10), a package for an embedded semiconductor device includes: A substrate having a cavity formed therein, the cavity having at least one angled sidewall; At least one semiconductor device, said at least one semiconductor device being disposed within the cavity; and An encapsulation material that surrounds the at least one semiconductor device within the cavity.

[0104] Example 11 includes the package according to Example 10, wherein each of the angled sidewalls has a chamfered edge, wherein the chamfered edge includes a vertical portion perpendicular to the bottom plate of the cavity, and the angled portion is engaged with the vertical portion.

[0105] Example 12 includes the package according to Example 11, wherein the corner formed between the vertical portion and the angled portion is rounded.

[0106] Example 13 includes the package according to Example 10, wherein the angled sidewalls are angled outward relative to the center of the cavity.

[0107] Example 14 includes the package according to Example 10, wherein each of the angled sidewalls has a beveled edge.

[0108] Example 15 includes the package according to Example 10, wherein the substrate includes a metal lead frame.

[0109] In the sixteenth embodiment (referred to as Embodiment 16), a method for forming a semiconductor device package includes: A cavity is formed within a substrate, the cavity having at least one angled sidewall; At least one semiconductor device is disposed within the cavity; and The at least one semiconductor device is encapsulated within the cavity using an encapsulating material.

[0110] Example 17 includes the method according to Example 16, wherein forming the cavity includes forming the cavity using a mechanical mold.

[0111] Example 18 includes the method according to Example 16, wherein forming the cavity includes forming the at least one angled sidewall having a chamfered edge.

[0112] Example 19 includes the method according to Example 16, wherein forming the cavity includes forming the at least one angled sidewall angled outward relative to the center of the cavity.

[0113] Example 20 includes the method according to Example 16, wherein encapsulating the at least one semiconductor device comprises: At least one layer of prepreg material is provided across the top of the substrate, the cavity, and the at least one semiconductor device; and A lamination process is performed to allow the at least one layer of prepreg material to flow into the cavity and cure, thereby providing the encapsulation.

[0114] It should be understood that in the foregoing description, when an element such as a layer, region, substrate, or component is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, no intermediate element or layer is present. Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the detailed description, elements shown as being directly on, directly connected to, or directly coupled to may be referred to as such. The claims of this application, if any, may be amended to state the exemplary relationships described in the specification or shown in the drawings.

[0115] As used in this specification and claims, the singular form may include the plural form unless the context clearly indicates otherwise. In addition to the orientations depicted in the drawings, spatially relative terms (e.g., above, on, above, below, under, beneath, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may respectively include vertically above and vertically below. In some embodiments, adjacent terms may include laterally adjacent or horizontally adjacent.

[0116] Some specific implementations can be achieved using various semiconductor processing and / or packaging techniques. Some specific implementations can be achieved using various types of semiconductor processing techniques associated with semiconductor substrates, including but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0117] While certain features of the described embodiments have been exemplified as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail are possible. Any parts of the apparatus and / or method described herein can be combined in any way, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

[0118] While certain features of the specific embodiments described herein have been exemplified, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the embodiments.

Claims

1. A semiconductor device package (100, 200a, 200b), said semiconductor device package comprising: A conductive member (101, 201) having a cavity (102, 202) formed therein, the cavity (102, 202) having at least one sidewall (104, 204, 218), the at least one sidewall having an angled portion (104a, 204a, 218) that is angled outward relative to the middle portion of the cavity (102, 202); and Semiconductor device (203) is positioned within the cavity (101, 201).

2. The semiconductor device package according to claim 1, further comprising: Molding materials (506, 508, 510, 512) are formed around the semiconductor device (203) and within the cavity (102, 202).

3. The semiconductor device package of claim 1, wherein the at least one sidewall has a chamfered edge (104a, 104b, 204a, 204b), wherein the chamfered edge (104a, 104b, 204a, 204b) includes a vertical portion (104b, 204b) perpendicular to the base plate of the cavity (102, 202), and the angled portion (104a, 204a) is engaged with the vertical portion (104b, 204b).

4. The semiconductor device package of claim 3, wherein the corner (300a) formed between the vertical portion and the angled portion is circular.

5. The semiconductor device package of claim 1, wherein the at least one sidewall has a chamfered edge (218).

6. The semiconductor device package of claim 1, wherein the conductive component is a metal lead frame.

7. The semiconductor device package of claim 1, wherein the cavity (102, 202) is rectangular.

8. The semiconductor device package of claim 7, wherein at least one corner (106) of the cavity is circular.

9. The semiconductor device package according to claim 1, further comprising: An isolation layer (219) is disposed on the side of the conductive member (201) opposite to the cavity (202); and The second conductive member (220) is disposed on the isolation layer (219).

10. A package (100, 200a, 200b) for an embedded semiconductor device (203), said package (100, 200a, 200b) comprising: A substrate (101, 201) having a cavity (102, 202) formed therein, the cavity (102, 202) having at least one angled sidewall (104, 204, 218). At least one semiconductor device (203) is disposed within the cavity (102, 202); and Encapsulations (506, 508, 510, 512) surround the at least one semiconductor device (203) within the cavity (102, 202).

11. The package of claim 10, wherein the at least one sidewall has chamfered edges (104a, 104b, 204a, 204b), wherein the chamfered edges (104a, 104b, 204a, 204b) include a vertical portion (104b, 204b) of a base plate perpendicular to the cavity (102, 202), and the angled portion (104a, 204a) is engaged with the vertical portion (104b, 204b).

12. The package according to claim 11, wherein the corner (300a) formed between the vertical portion and the angled portion is circular.

13. The package of claim 10, wherein the angled sidewalls (104a, 204a, 218) are angled outward relative to the center of the cavity (102, 202).

14. The package according to claim 10, wherein each of the angled sidewalls (218) has a beveled edge.

15. The package of claim 10, wherein the substrate (101, 201) comprises a metal lead frame.

16. A method of forming a semiconductor device package, the method comprising: A cavity (102, 202) is formed within a substrate (101, 201), the cavity (102, 202) having at least one angled sidewall (104, 204, 218). At least one semiconductor device (203) is disposed (1404) within the cavity (102, 202); as well as The at least one semiconductor device (203) is encapsulated (1408) within the cavity (102, 202) using encapsulants (506, 508, 510, 512).

17. The method of claim 16, wherein forming the cavity comprises forming the cavity using a mechanical mold (700).

18. The method of claim 16, wherein forming the cavity comprises forming the at least one angled sidewall having chamfered edges (104a, 104b, 204a, 204b).

19. The method of claim 16, wherein forming the cavity includes forming the at least one angled sidewall (104a, 204a, 218) angled outward relative to the center of the cavity.

20. The method of claim 16, wherein encapsulating the at least one semiconductor device comprises: At least one layer of prepreg material (904, 906) is provided across the top of the substrate (101, 201, 701a), the cavity (102, 202, 702a), and the at least one semiconductor device (203, 806a); and A lamination process is performed to allow the at least one layer of prepreg material (904, 906) to flow into the cavity (102, 202, 702a) and cure, thereby providing the encapsulation.

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