A method for reducing native defects in silicon single crystals after growth for integrated circuits

Abstract

This application relates to a method for reducing native defects in silicon single crystals after growth for integrated circuits. It discloses a method that utilizes the dual coupling effect of high-frequency eddy current temperature control and DC electric field on the carrier regularization in the crystal to fully dissolve the native defects in the crystal and make them diffuse in a directional and uniform manner, so that the nucleation sites of the native defects are evenly distributed at high temperatures. During the cooling process, a rapid cooling method is used to control the nucleation size of the native defects and restrict their aggregation and diffusion under the action of DC electric field, thereby achieving the purpose of reducing the size of the native defects in the silicon single crystal and making them evenly distributed, thus meeting the requirements of advanced integrated circuit manufacturing processes.

Description

Technical Field

[0001] This invention belongs to the field of crystal growth technology for integrated circuits, and relates to a method for reducing the native defects of a silicon single crystal after growth for integrated circuits. Specifically, it relates to a method for handling the native defects during the crystal growth process after the growth of a large-size single-crystal silicon crystal for integrated circuits. Background Technology

[0002] In the crystal growth process of single-crystal silicon for integrated circuits, due to the temperature difference between the outer and inner layers of the crystal (the inner temperature is higher than the outer temperature), interstitial atoms are more likely to form inside the crystal, while vacancies are more likely to form on the outer layer. Simultaneously, influenced by factors such as melt surface tension, the crystal growth interface is not perfectly horizontal. Therefore, impurity deposits tend to accumulate in a near-ring-shaped region, forming primary defects in the crystal. These primary defects degrade the integrity of the gate oxide layer, affecting the yield and performance of integrated circuits. Therefore, controlling primary defects, especially the size and number of crystal native particles (COPs), is one of the key technical indicators in the growth of large-size single-crystal silicon crystals for integrated circuits.

[0003] COP control is usually carried out during the crystal growth stage. However, due to the crystal growth technology and the properties of the crystal itself, some native defects will inevitably be generated. Large-sized COPs will affect the performance of the finished integrated circuit. Therefore, reducing the size of the COP and promoting the uniform distribution of COP nuclei to eliminate its impact on subsequent products can "eliminate" the native defects of the crystal from another perspective.

[0004] High-temperature annealing of silicon wafers can "heal" existing COPs. High-temperature rapid annealing causes the surface oxide film of COP vacancies to break, allowing silicon atoms to migrate and fill the vacancies, thereby eliminating or reducing near-surface COPs. However, the annealing process is very demanding on the heating-cooling rate and holding time. During cooling, supersaturated vacancies will re-aggregate into secondary vacancies, and dopants will also accumulate during this period, making it impossible to reduce the COP size of the product to meet the requirements of integrated circuit linewidth. Therefore, a method is needed to reduce the size of native defects and homogenize native defects within the crystal, reducing the degree of defect aggregation, so as to eliminate large-size defects to some extent.

[0005] CN117418301A discloses a crystal pulling method for reducing point defects in crystal rods and a single-crystal crystal rod. This method suppresses or reduces the generation and aggregation of point defects (such as vacancies and interstitial atoms) by precisely controlling process parameters such as the thermal field and crystal / crate rotation rate during crystal pulling, thereby preventing defect formation at the source. Application 202510374958.5 discloses a crystal pulling method for reducing micro-defects in large-size crystal rods. This method addresses the challenges of large sizes through more complex thermal field design, cooling path control, or doping processes, ensuring low-defect growth across the entire large-diameter cross-section. Both methods aim to create ideal conditions during crystal growth, striving to minimize or prevent the growth of defects, and are not suitable for crystal rods with pre-existing defects.

[0006] The silicon wafer and annealing method authorized by announcement number CN105297140B are prepared by annealing the silicon wafer under a constant temperature of not less than 1200°C and not more than 1300°C for at least 2 hours in a thermal field and electric field. The method processes the silicon wafer at a temperature of not less than 1200°C and not more than 1300°C. At this temperature, the diffusion rate of atoms is slow. Smaller, unstable primary defects will dissolve, but larger, stable primary defects dissolve very slowly or even cannot dissolve. Moreover, a long holding time is required to see limited effects, resulting in high overall costs.

[0007] Therefore, there is an urgent need for a method to reduce the size of native defects in silicon single crystals and promote their uniform distribution after growth. Summary of the Invention

[0008] The purpose of this invention is to provide a method for reducing the size of native defects in silicon single crystals after growth and promoting their uniform distribution, so that silicon wafers can meet the requirements of advanced manufacturing processes.

[0009] To achieve the above objectives, the basic solution of the present invention provides a method for reducing native defects in a silicon single crystal after growth for integrated circuits, comprising the following steps:

[0010] S1: Crystal rod processing: After the crystal rod is grown, it is cut and rounded.

[0011] S2: High-frequency coil heating: The cut and rounded crystal rod is heated by a high-frequency coil. During the heating process, the frequency is adjusted according to the temperature change to heat the crystal rod to a temperature range of 1280℃-1320℃ and hold it thereafter.

[0012] S3: Apply an electric field: At the heat preservation temperature, apply an electric field to the crystal rod, monitor the DC current value I in the crystal rod, and control the initial current value to be I0. When the rate of change of current I is less than a1, it indicates that the crystal rod has been homogenized.

[0013] S4: Rapid cooling and removal of electric field: After the heat preservation is completed, the crystal rod is rapidly cooled. When the rate of change of current I is less than a2, the electric field is removed. Continue to rapidly cool the crystal rod until it reaches room temperature.

[0014] The principle and beneficial effects of this basic scheme are as follows:

[0015] This invention discloses a method for reducing native defects in silicon single crystals after growth for integrated circuits. It utilizes the dual coupling effect of high-frequency eddy current temperature control and a DC electric field on the carrier regularization in the crystal to fully dissolve native defects and promote their directional and uniform diffusion, resulting in a uniform distribution of native defect nucleation sites at high temperatures. During the cooling process, rapid cooling is employed to control the nucleation size of native defects and restrict their aggregation and diffusion under the influence of the DC electric field. This achieves the goal of reducing the size of native defects in the silicon single crystal and promoting uniform distribution, meeting the requirements of advanced integrated circuit manufacturing processes.

[0016] Compared to existing technologies such as CN117418301A, which uses crystal pulling methods to reduce midpoint defects in crystal rods and methods for single-crystal crystal rods, this solution eliminates native defects in already grown crystals. It's a "rescue" process; even if the crystal pulling process isn't optimal, post-processing can improve the quality of the crystal rod, "repairing" it to acceptable standards, thereby increasing overall yield and offering significant economic benefits. For crystal rods that are "acceptable" according to traditional standards, this treatment creates a high-density, uniformly distributed bulk microdefect (BMD) distribution within them, improving the electrical performance and reliability of the final chip and raising the quality threshold. Furthermore, this solution monitors changes in the current I within the crystal rod to determine the completion of defect homogenization. During defect migration and recombination, the current in the crystal rod changes. When the defect distribution reaches a dynamically stable or uniform state, the current change tends to level off, and the overall conductivity of the crystal rod tends to stabilize. This makes the process endpoint clear and controllable, ensuring batch-to-batch consistency.

[0017] Compared to the silicon wafer and annealing method in existing technology CN105297140B, this invention addresses defects at their source during the ingot stage, after crystal growth and before slicing. It utilizes a high-frequency coil combined with an electric field to create eddy currents, fully dissolving native defects in the crystal and causing them to diffuse uniformly and directionally. This ensures that the nucleation sites for native defects are evenly distributed at high temperatures. Rapid cooling controls the nucleation size of native defects, and the DC electric field restricts their aggregation and diffusion, thereby reducing the size of native defects in silicon monomers and promoting uniform distribution. Furthermore, real-time electrical feedback is used as the control core to monitor the homogenization of native defects in real time. This results in near-perfect ingot material before slicing, providing a higher quality starting point and consistency for subsequent silicon wafer products. It simplifies or even eliminates the complex internal gettering process for silicon wafers, and processes an entire ingot at a time, resulting in higher processing efficiency.

[0018] Optionally, the coil is wired around the crystal rod.

[0019] Optionally, the operating frequency f of the coil satisfies the following relationship:

[0020] (1)

[0021] In the formula, is a function of resistivity and temperature, K is an empirical constant, D is the distance from the OiSF ring to the surface of the crystal rod, and μ is the magnetic permeability of the crystal rod;

[0022] (2)

[0023] In the formula, ρ is the resistivity at room temperature, T0 is 298.15 K at room temperature, B is the silicon material constant, and e is the natural constant.

[0024] This invention has discovered through research that, during the heating process, the operating frequency of the coil needs to be adjusted accordingly based on temperature changes, and the heating depth must match the distance from the OiSF ring of the crystal rod to the surface of the crystal rod.

[0025] Optionally, the initial current value is 4A ≤ I0 ≤ 10A.

[0026] Controlling the initial current to 4A≤I0≤10A can prevent excessive current from causing local energy concentration in the crystal rod, prevent the generation of new lattice defects, and ensure the stability of the defect control process.

[0027] Optionally, a1 ≤ 5%.

[0028] When the original defects are fully dissolved and homogenized, the defect distribution reaches a quasi-steady state. At this point, the change in current over time tends to level off. Setting this threshold as the process endpoint criterion means that the change in the defect structure has become very slow, and it can be considered that the target state of "homogenization" or "stabilization" has been achieved. 5% is an empirical threshold that balances process time and quality requirements.

[0029] Optionally, a2 ≤ 3%.

[0030] During rapid cooling, the nucleation size of primary defects is controlled, and their aggregation and diffusion are limited under the influence of a DC electric field to prevent the formation of harmful secondary defect clusters. As the temperature decreases, the defect reaction slows down dramatically, and the change in current also becomes increasingly slower. When a set threshold is reached, it indicates that the dynamic process of defects has been "essentially frozen." At this point, even if the electric field is removed, primary defects can no longer migrate and aggregate on a large scale to form new defects. Continuing to apply an electric field is ineffective and a waste of energy. The 3% threshold is more stringent than the 5% threshold in the heat preservation stage because defect freezing during the cooling stage is crucial to the final quality and requires higher stability confirmation.

[0031] Optionally, the crystal rod is always in a non-oxidizing atmosphere during the heating, holding, and cooling processes in S2-S4.

[0032] Maintaining a non-oxidizing atmosphere throughout the heating, holding, and cooling process of silicon wafers prevents surface oxidation and ensures process repeatability and uniformity.

[0033] Optionally, the crystal rod is rapidly cooled at a rate of 50-75°C / min.

[0034] 50-75℃ / min is a fast and safe compromise rate. It can effectively control the nucleation size of native defects, lock in the low-defect state of the ingot obtained after high-temperature treatment, and ensure the stability of the process effect. It is also gentle enough to avoid catastrophic thermal stress. This helps to maintain the near-perfect crystal structure of the ingot after treatment, laying the foundation for subsequent cutting of high-quality silicon wafers. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of an embodiment of the present invention, where A represents a current measuring device used to measure the current value in the crystal rod. Detailed Implementation

[0036] The following detailed description illustrates the specific implementation method:

[0037] Comparative Example

[0038] P-type single-crystal silicon rods with a diameter of 12 inches were grown using the Cz method. These rods were then cut and rounded to obtain rods with a length of 40 cm. These rods were then processed into silicon wafers, and the wafers were tested using a BMD analyzer (MO4). The results showed an average BMD size of 78 nm and a density of 5.20 × 10⁻⁶. 7 pcs / cm 3 The mapping plot shows uneven distribution, indicating that the BMD distribution is not uniform; the uniformity of resistivity in the silicon wafer was tested using a four-probe resistivity meter, and its radial resistivity variation (RRV) was found to be 7.81%.

[0039] Example 1

[0040] A 12-inch P-type monocrystalline silicon rod with the same resistivity as the comparative example was selected. The monocrystalline silicon rod was cut and rounded to obtain a 40cm long rod, as shown in the attached figure. Figure 1 As shown, a high-frequency coil is used to heat the crystal rod. The frequency is adjusted according to the temperature change. The crystal rod is heated to 1305℃ and held at that temperature. A unidirectional DC electric field is applied to the single crystal silicon rod, and the DC current value I in the crystal rod is monitored. The initial current value I0 is controlled to be 6A. When the rate of change of current I is less than 5%, it indicates that the original defects of the crystal rod have been homogenized. The crystal rod is held at that temperature for another 2 minutes.

[0041] After the heat preservation period, the crystal rod is rapidly cooled to room temperature at a cooling rate of 70℃ / min. During the cooling process, the change in the current value I in the crystal rod is continuously monitored. When the rate of change of current I is less than 3%, the electric field is removed, thus completing the "elimination" of the original defects in the crystal rod.

[0042] After the crystal ingot was cooled to room temperature, it was processed into a silicon wafer. The wafer was then tested using a BMD analyzer (MO4), revealing an average BMD size of 68 nm, a 12.82% reduction compared to the comparative example, and a BMD density of 3.53 × 10⁻⁶. 8 pcs / cm 3 The value is 6.79 times that of the comparative example. The mapping diagram shows a uniform distribution, proving that the primary defects in the crystal have been effectively reduced, and high-density uniformly distributed bulk microdefects (BMDs) have been formed inside. The resistivity uniformity of the silicon wafer was tested using a four-probe resistivity meter, and its radial resistivity variation (RRV) was found to be 4.68%. Compared with 7.81% of the comparative example, the radial resistivity uniformity has been significantly improved, further proving that the distribution of primary defects has been homogenized.

[0043] Example 2

[0044] A 12-inch P-type single-crystal silicon rod with the same resistivity as in Example 1 was selected. In this example, the holding temperature of the rod was 1280°C. When an electric field was applied to the rod during the holding stage, the initial current value I0 was controlled to be 10A. When the rate of change of the DC current I was less than 5%, the rod was held for another 2 minutes. Then, rapid cooling was performed at a rate of 50°C / min. When the rate of change of the DC current I was less than 3%, the electric field was removed.

[0045] After the crystal ingot was cooled to room temperature, it was processed into a silicon wafer. The wafer was then tested using a BMD analyzer (MO4), revealing an average BMD size of 69 nm, representing an 11.54% reduction in size compared to the comparative example. The BMD density was 3.38 × 10⁻⁶. 8 pcs / cm 3The value is 6.50 times that of the comparative example. The mapping diagram shows a uniform distribution, proving that the primary defects in the crystal have been effectively reduced, and high-density uniformly distributed bulk microdefects (BMDs) have been formed inside. The resistivity uniformity of the silicon wafer was tested using a four-probe resistivity meter, and its radial resistivity variation (RRV) was found to be 4.91%. Compared with 7.81% of the comparative example, the radial resistivity uniformity has been significantly improved, further proving that the distribution of primary defects has been homogenized.

[0046] Example 3

[0047] A 12-inch P-type single-crystal silicon rod with the same resistivity as in Example 1 was selected. In this example, the holding temperature of the rod was 1320℃. When an electric field was applied to the rod during the holding stage, the initial current value I0 was controlled to be 10A. When the rate of change of the DC current I was less than 5%, the rod was held for another 2 minutes. Then, rapid cooling was performed at a rate of 75℃ / min. When the rate of change of the DC current I was less than 3%, the electric field was removed.

[0048] After the crystal ingot was cooled to room temperature, it was processed into a silicon wafer. The wafer was then tested using a BMD analyzer (MO4), revealing an average BMD size of 65 nm, a 16.67% reduction compared to the comparative example, and a BMD density of 4.04 × 10⁻⁶. 8 pcs / cm 3 The value is 7.78 times that of the comparative example. The mapping diagram shows a uniform distribution, proving that the primary defects in the crystal have been effectively reduced, and high-density uniformly distributed bulk microdefects (BMDs) have been formed inside. The resistivity uniformity of the silicon wafer was tested using a four-probe resistivity meter, and its radial resistivity variation (RRV) was found to be 4.74%. Compared with 7.81% of the comparative example, the radial resistivity uniformity has been significantly improved, further proving that the distribution of primary defects has been homogenized.

[0049] Example 4

[0050] A 12-inch P-type single-crystal silicon rod with the same resistivity as in Example 1 was selected. In this example, the holding temperature of the rod was 1300℃. When an electric field was applied to the rod during the holding stage, the initial current value I0 was controlled to be 4A. When the rate of change of the DC current I was less than 5%, the rod was held for another 2 minutes, followed by rapid cooling at a rate of 75℃ / min. When the rate of change of the DC current I was less than 3%, the electric field was removed.

[0051] After the crystal ingot was cooled to room temperature, it was processed into a silicon wafer. The wafer was then tested using a BMD analyzer (MO4), revealing an average BMD size of 68 nm, a 12.82% reduction compared to the comparative example, and a BMD density of 3.53 × 10⁻⁶. 8 pcs / cm 3The value is 6.79 times that of the comparative example. The mapping diagram shows a uniform distribution, proving that the primary defects in the crystal have been effectively reduced, and high-density uniformly distributed bulk microdefects (BMDs) have been formed inside. The resistivity uniformity of the silicon wafer was tested using a four-probe resistivity meter, and its radial resistivity variation (RRV) was found to be 4.93%. Compared with 7.81% of the comparative example, the radial resistivity uniformity has been significantly improved, further proving that the distribution of primary defects has been homogenized.

[0052] The process parameters and results data of Examples 1-4 and the comparative examples are shown in the table below:

[0053]

[0054] Characterization data from Examples 1-4 show that, compared to the comparative examples, the silicon wafers processed from crystal rods treated by the method of this invention exhibit significantly reduced primary crystal defects. Simultaneously, high-density, uniformly distributed bulk microdefects (BMDs) are formed internally, with better radial resistivity uniformity. These results demonstrate that this invention utilizes the dual coupling effect of high-frequency eddy current temperature control and DC electric field on the carrier ordering in the crystal, effectively dissolving primary defects and promoting their directional, uniform diffusion, resulting in a uniform distribution of primary defect nucleation sites at high temperatures. During the cooling process, rapid cooling is employed to control the nucleation size of primary defects and restrict their aggregation and diffusion under the influence of the DC electric field. This achieves the goal of reducing the size of primary defects in silicon monomers and promoting uniform distribution, meeting the requirements of advanced integrated circuit manufacturing processes.

[0055] The above descriptions are merely embodiments of the present invention, and common knowledge regarding specific structures and characteristics is not elaborated upon here. It should be noted that those skilled in the art can make various modifications and improvements without departing from the structure of the present invention, and these should also be considered within the scope of protection of the present invention. These modifications and improvements will not affect the effectiveness of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A method for reducing native defects in a silicon single crystal after growth for integrated circuits, characterized in that: Includes the following steps: S1: Crystal rod processing: After the crystal rod is grown, it is cut and rounded. S2: High-frequency coil heating: The cut and rounded crystal rod is heated by a high-frequency coil. During the heating process, the frequency is adjusted according to the temperature change to heat the crystal rod to a temperature range of 1280℃-1320℃ and hold it thereafter. S3: Apply an electric field: At the heat preservation temperature, apply an electric field to the crystal rod, monitor the DC current value I in the crystal rod, and control the initial current value to be I0. When the rate of change of current I is less than a1, it indicates that the crystal rod has been homogenized. S4: Rapid cooling and removal of electric field: After the heat preservation is completed, the crystal rod is rapidly cooled. When the rate of change of current I is less than a2, the electric field is removed. Continue to rapidly cool the crystal rod until it reaches room temperature.

2. The method for reducing native defects in a silicon single crystal after growth according to claim 1, characterized in that: The coil is wired around the crystal rod.

3. The method for reducing native defects in a silicon single crystal after growth according to claim 1, characterized in that: The operating frequency f of the coil satisfies the following relationship: (1) In the formula, is a function of resistivity and temperature, K is an empirical constant, D is the distance from the OiSF ring to the surface of the crystal rod, and μ is the magnetic permeability of the crystal rod; (2) In the formula, ρ is the resistivity at room temperature, T0 is 298.15 K at room temperature, B is the silicon material constant, and e is the natural constant.

4. The method for reducing native defects in a silicon single crystal after growth according to claim 1, characterized in that: The initial current value is 4A≤I0≤10A.

5. The method for reducing native defects in a silicon single crystal after growth according to claim 1, characterized in that: a1≤5%.

6. The method for reducing native defects in a silicon single crystal after growth according to claim 1, characterized in that: The a2 ≤ 3%.

7. The method for reducing native defects in a silicon single crystal after growth according to claim 1, characterized in that: The crystal rods in S2-S4 are always in a non-oxidizing atmosphere during the heating, holding, and cooling processes.

8. The method for reducing native defects in a silicon single crystal after growth according to claim 1, characterized in that: The crystal rod is rapidly cooled at a rate of 50-75°C / min.

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