An addressable test circuit based on a multi-level switch tree

Abstract

This invention relates to an addressable test circuit based on a multi-level switch tree, comprising: a multi-level switch circuit arranged in a tree structure between a global measurement node and each unit under test (DUT), with the root node being the global measurement node and leaf nodes used to connect to the DUT; and several decoders used to control the switching units at each level of the multi-level switch circuit according to received address signals, so that the switch units between the selected DUT and the global measurement node are turned on, forming a unique selection link. This invention can reduce the scale of leakage current superposition caused by different columns in the same row and different rows in the same column. The global measurement node side only directly faces the off switches of a small number of column group branches, significantly reducing superimposed leakage current and coupling noise.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing, and in particular to an addressable test circuit based on a multi-level switch tree. Background Technology

[0002] As CMOS technology nodes continue to shrink, the impact of random process variations on device performance becomes increasingly significant. Factors such as line edge roughness, random doping variations, and metal gate grain size can lead to significant performance differences in identical transistors, even causing circuit malfunctions and unstable power consumption. Statistical modeling of random variations is required using large amounts of data to ensure sufficient margin in circuit design. To accurately characterize these variations and assess their impact on performance, the traditional method of testing a transistor with four pads is too time- and area-intensive, necessitating a circuit capable of large-scale, rapid transistor testing. Currently, many works have designed test arrays to efficiently characterize transistor performance and reliability. By using address decoding circuits to control switching circuits, thousands of cells under test can be connected together with a limited number of pads, enabling simultaneous measurement and effectively improving testing efficiency.

[0003] Existing addressable test circuits typically employ two-stage transmission gate control for switching, such as row address control in the first stage and column address control in the second stage, selecting a row and then a column within that row. However, when the first-stage row selection is activated, unselected column branches within that row still connect to the row convergence node through the shutdown transmission gate. Due to the superposition of shutdown subthreshold leakage current, junction leakage current, and leakage current caused by node potential differences, considerable interference is generated at high-impedance measurement nodes, especially under conditions of low current measurement, long integration time, or high-impedance sampling, manifesting as significant measurement offset and noise. Therefore, there is an urgent need for a structure that, while maintaining addressability and scalability, reduces the impact of shutdown leakage current from "different columns in the same row" or "different rows in the same column" branches on the measurement nodes. Summary of the Invention

[0004] To address the problem of measurement accuracy degradation caused by superimposed turn-off leakage current in existing two-stage addressable test circuits, this invention aims to provide an addressable test circuit based on a multi-stage switch tree. This invention significantly reduces the number of turn-off branches directly faced by global measurement nodes by dividing the gating stages into multiple levels and introducing intermediate convergence nodes. Structurally, it suppresses the impact of leakage current and coupling interference on high-impedance measurement nodes, thereby improving the accuracy and reliability of testing large-scale device arrays under conditions of weak current and long sampling windows.

[0005] To achieve the above objectives, the technical solution of the present invention includes:

[0006] An addressable test circuit based on a multi-level switch tree, comprising:

[0007] A multi-level switching circuit is set between the global measurement node and each unit under test, forming a tree structure. Its root node is the global measurement node, and the leaf nodes are used to connect to the unit under test.

[0008] Several decoders are used to control the switching units at each level in the multi-level switching circuit according to the received address signal, so that the switching units between the selected unit under test and the global measurement node are turned on, forming a unique selection link.

[0009] A further improvement of the present invention is that, in the multi-stage switching circuit, the switching unit is a transmission gate.

[0010] A further improvement of the present invention is that, in the multi-stage switching circuit, the number of stages of the switching unit is greater than or equal to three.

[0011] A further improvement of the present invention is that, from the root node to the leaf node of the multi-level switching circuit, the input terminal of each switching unit in the first-level switching circuit is connected to the global measurement node; except for the last-level switching circuit, the output terminal of the switching unit of each level of the switching circuit serves as an intermediate convergence node, and the output terminal of the switching unit of the last-level switching circuit serves as a leaf node; except for the first-level switching circuit, the switching units of each level of the switching circuit are divided into several groups, and the input terminal of each group of switching units is connected to the corresponding intermediate convergence node in the previous level of the switching circuit, thereby forming a tree structure; each group of switching units corresponds to an intermediate convergence node.

[0012] A further improvement of the present invention is that each stage of the switching circuit is equipped with a corresponding decoder; the decoder receives the address signal and converts it into an enable signal to control the on / off state of the switching unit.

[0013] A further improvement of the present invention is that the number of stages in the multi-stage switching circuit is three;

[0014] The first-stage switching circuit includes R switching units;

[0015] The second-stage switching circuit includes R×G switching units, which are divided into R groups. The input terminal of each group of switching units is connected to the intermediate convergence node corresponding to the first-stage switching circuit.

[0016] The third-stage switching circuit includes R×G×S switching units, which are divided into R×G groups. The input terminal of each group of switching units is connected to the intermediate convergence node corresponding to the second-stage switching circuit.

[0017] A further improvement of the present invention is that, in the third-stage switching circuit, the number S of each group of switching units is 1 to 4.

[0018] Compared with the prior art, the technical effects of the present invention include:

[0019] 1) This invention can reduce the scale of leakage current superposition caused by different columns in the same row and different rows in the same column. The global measurement node side only directly faces the shut-off switches of a small number of column group branches, which significantly reduces superposition leakage current and coupling noise.

[0020] 2) This invention can perform high-impedance / small-signal measurements more accurately, and has the advantages of smaller offset and better repeatability in long sampling windows or weak current measurements.

[0021] 3) By modifying the number of transmission gates G in the second stage and the number of transmission gates S in the third stage, this invention can flexibly balance interference, area, and delay; Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the architecture of an addressable test circuit based on a multi-level switch tree.

[0023] Figure 2 This is a schematic diagram of the multi-stage switching circuit used in this invention. Detailed Implementation

[0024] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0025] like Figure 1 As shown, embodiments of the present invention provide an addressable test circuit based on a multi-level switch tree, aiming to solve the problems of increased measurement offset, drift, and decreased repeatability caused by the superposition of leakage current and coupling injection of unselected column branches in the same row after a row is selected in the traditional two-level row-column addressing structure. The present invention adopts a multi-level (at least three-level) switch tree gating structure, further classifying column gating and setting intermediate convergence nodes, which significantly reduces the number of shutdown branches directly connected to the global measurement node side, structurally suppressing the impact of leakage current and crosstalk on sensitive measurement nodes, thereby improving test accuracy, consistency, and scalability in scenarios such as long sampling windows and small signal current / voltage measurements.

[0026] The addressable test circuit based on a multi-level switch tree in this embodiment specifically includes:

[0027] A multi-level switching circuit is set between the global measurement node and each unit under test, forming a tree structure. Its root node is the global measurement node, and the leaf nodes are used to connect to the unit under test.

[0028] In this embodiment, each switching unit in the multi-stage switching circuit is implemented using a transmission gate, which has a control terminal. When a corresponding level signal is applied, the input and output terminals of the transmission gate are turned on, and when an inverse level signal is applied, it is turned off.

[0029] From the root node to the leaf node of the multi-stage switching circuit, the input terminals of each switching unit in the first-stage switching circuit are all connected to the global measurement node; except for the last-stage switching circuit, the output terminals of the switching units in each stage of the switching circuit serve as intermediate convergence nodes, and the output terminals of the switching units in the last-stage switching circuit serve as leaf nodes; except for the first-stage switching circuit, the switching units of each stage of the switching circuit are divided into several groups, and the input terminals of each group of switching units are respectively connected to the corresponding intermediate convergence node in the previous stage of the switching circuit, thereby forming a tree structure; each group of switching units corresponds to one intermediate convergence node.

[0030] like Figure 2 In the specific embodiment shown, the multi-stage switching circuit is suitable for an array of R×C units under test (DUT), where C=G×S. The multi-stage switching circuit has three stages: the first stage includes R switching units; the second stage includes R×G switching units, equally divided into R groups, with the input of each group of switching units connected to the corresponding intermediate convergence node (row convergence node) of the first stage switching circuit; the third stage includes R×G×S switching units, equally divided into R×G groups, with the input of each group of switching units connected to the corresponding intermediate convergence node (group convergence node) of the second stage switching circuit.

[0031] Each stage of the switching circuit is equipped with a corresponding decoder; the decoder receives the address signal and converts it into an enable signal to control the on / off state of the switching unit. The decoder, based on the received address signal, controls each stage of the switching unit in the multi-stage switching circuit, ensuring that the switching unit between the selected unit under test and the global measurement node is activated, forming a unique selection link.

[0032] like Figure 1 , 2As shown, in this embodiment, the decoder corresponding to the first-stage switching circuit is a row decoder, the decoder corresponding to the second-stage switching circuit is a column decoder 1, and the decoder corresponding to the third-stage switching circuit is a column decoder 2. When a device under test (DUT) is selected, the first column decoder receives the row address and outputs a hot-swappable row selection signal, controlling the corresponding switch unit in the first-stage switching circuit to conduct, thus coupling the signal of the global measurement node to the corresponding row aggregation node. The first column decoder receives the column group address and controls the corresponding switch unit in each group to conduct. The second column decoder receives the column intra-address and controls the corresponding switch unit in each group to conduct, so as to connect the target DUT to the group aggregation node of the selected column group. Thus, at any given time, only one selection link is established: global measurement node—row aggregation node—group aggregation node—DUT, realizing addressable access and testing of the target DUT.

[0033] In one specific embodiment, the number S of switching units included in each group of the third-level switching circuit is 1; in this case, when a unit under test is selected, only one switching unit is selected in both the second-level and third-level switching circuits, which can minimize the number of unselected columns in the same row.

[0034] The key point of this invention lies in the use of a multi-level switch tree addressing and gating structure. By hierarchically selecting columns and introducing intermediate convergence nodes, the number of directly connected shutdown branches on the global measurement node side is significantly reduced, thereby greatly suppressing the interference of "unselected column branches in the same row" shutdown leakage current and coupling injection on the measurement results. This effectively solves the problems of voltage drift, increased bias of small current measurement, and decreased stability and repeatability under long sampling windows caused by the parallel superposition of shutdown leakage currents in different columns of the same row after selecting a row in traditional two-level row and column addressing structures. Therefore, the point to be protected is to introduce a multi-level (at least three-level) switch tree gating and corresponding intermediate convergence nodes when using addressing methods for large-scale array testing, so as to reduce the number of shutdown branches on the global measurement node side and suppress leakage current interference, thereby improving test accuracy and consistency.

[0035] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. An addressable test circuit based on a multi-level switch tree, characterized in that, include: A multi-level switching circuit is set between the global measurement node and each unit under test, forming a tree structure. Its root node is the global measurement node, and the leaf nodes are used to connect to the unit under test. Several decoders are used to control the switching units at each level in the multi-level switching circuit according to the received address signal, so that the switching units between the selected unit under test and the global measurement node are turned on, forming a unique selection link.

2. The addressable test circuit based on a multi-level switch tree according to claim 1, characterized in that, In the multi-stage switching circuit, the switching unit is a transmission gate.

3. The addressable test circuit based on a multi-level switch tree according to claim 1, characterized in that, In the multi-stage switching circuit, the number of stages of the switching unit is greater than or equal to three.

4. The addressable test circuit based on a multi-level switch tree according to claim 3, characterized in that, From the root node to the leaf node of the multi-level switching circuit, the input terminal of each switching unit in the first-level switching circuit is connected to the global measurement node; except for the last-level switching circuit, the output terminal of the switching unit of each level of the switching circuit serves as an intermediate convergence node, and the output terminal of the switching unit of the last-level switching circuit serves as a leaf node; except for the first-level switching circuit, the switching units of each level of the switching circuit are divided into several groups, and the input terminal of each group of switching units is connected to the corresponding intermediate convergence node in the previous level of the switching circuit, thereby forming a tree structure; each group of switching units corresponds to an intermediate convergence node.

5. An addressable test circuit based on a multi-level switch tree according to claim 4, characterized in that, Each stage of the switching circuit is equipped with a corresponding decoder; the decoder receives the address signal and converts it into an enable signal to control the on / off state of the switching unit.

6. The addressable test circuit based on a multi-level switch tree according to claim 5, characterized in that, The multi-stage switching circuit has three stages; The first-stage switching circuit includes R switching units; The second-stage switching circuit includes R×G switching units, which are divided into R groups. The input terminal of each group of switching units is connected to the intermediate convergence node corresponding to the first-stage switching circuit. The third-stage switching circuit includes R×G×S switching units, which are divided into R×G groups. The input terminal of each group of switching units is connected to the intermediate convergence node corresponding to the second-stage switching circuit.

7. The addressable test circuit based on a multi-level switch tree according to claim 6, characterized in that, In the third-stage switching circuit, the number S of each group of switching units is 1 to 4.

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