An addressable test method, circuit, integrated circuit, device, and system for transistor self-heating effect
By combining addressing decoding with transmission gate switching circuits, independent gating and accurate self-heating effect testing of transistor arrays are achieved, solving the problems of high testing cost and insufficient consistency in existing technologies, and realizing efficient and accurate characterization of self-heating effects.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI JIAOTONG UNIV
- Filing Date
- 2026-04-03
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies for testing transistor self-heating effects suffer from high testing time and cost, waste of probe resources and large chip area overhead. Furthermore, the self-heating effect causes parameter drift and reliability degradation, making it difficult to achieve large-scale and accurate self-heating characterization.
An architecture combining addressing decoding and transmission gate switching circuits is adopted. The target transistor is independently selected through address selection, and the excitation and sampling signals are transmitted to the selected transistor respectively. At the same time, the nodes of unselected transistors are turned off and forced to zero. The gate resistance is measured in conjunction with a four-terminal Kelvin measurement structure.
It achieves stable and accurate characterization of the self-heating effect of large-scale transistor arrays, improves test consistency and accuracy, reduces leakage current and thermal coupling interference of unselected channels, and supports high-throughput self-heating behavior evaluation.
Smart Images
Figure CN122307286A_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of semiconductor wafer testing technology, and specifically relates to an addressable testing method, circuit, integrated circuit, device and system for transistor self-heating effect. Background Technology
[0002] As CMOS technology nodes continue to shrink, the impact of random process variations on device electrical characteristics becomes increasingly prominent. Influenced by factors such as line edge roughness, random doping variations, metal gate particle size, and stress distribution differences, transistors of the same layout size may exhibit significant dispersion in threshold voltage, drive current, and leakage current, leading to circuit malfunctions, unstable power consumption, and decreased yield. To statistically model these random variations and guide circuit margin design, a large amount of device-level test data is needed as support.
[0003] On the other hand, the introduction of low thermal conductivity materials and thermally constrained geometries in advanced processes further exacerbates the self-heating effect of transistors. Temperature rise during device operation leads to parameter drift and reliability degradation, necessitating high-throughput self-heating characterization on different device samples to assess the impact of random fluctuations on self-heating behavior. Traditional methods using multiple PADs to test individual transistors are too costly in terms of testing time, probe resources, and chip area overhead, making them unsuitable for large-scale statistical applications. Summary of the Invention
[0004] One aspect of this disclosure is an addressable test circuit for transistor self-heating effects, comprising:
[0005] The addressing circuit is configured to receive an N-bit address signal and generate a corresponding gating control signal.
[0006] Switching circuits include excitation switching circuits and sensing switching circuits composed of transmission gates;
[0007] The device under test array includes multiple transistors under test arranged in an array. The gate of each transistor under test is connected to four test ports, namely the high-side excitation port FORCE_H, the low-side excitation port FORCE_L, the high-side sampling port SENSE_H, and the low-side sampling port SENSE_L.
[0008] The addressing circuit controls the transmission gates in the excitation switch circuit and the sensing switch circuit to be turned on or off through the gating control signal, so as to transmit the external excitation signal to the selected transistor under test, while turning off the transmission gates corresponding to the unselected transistor under test.
[0009] Each test port, source, and drain of the unselected transistor under test is connected to a pull-down transistor. The pull-down transistor is configured to force the voltage of the connected node to zero potential when the corresponding transmission gate is turned off, so as to eliminate leakage current and thermal coupling interference.
[0010] In one aspect of this disclosure, there is an integrated circuit, an addressable test circuit for the self-heating effect of transistors, wherein the array of devices under test is integrated on the same semiconductor substrate.
[0011] In one aspect of this disclosure, a wafer testing structure includes the integrated circuit and a plurality of test pads disposed on the integrated circuit, the test pads being electrically connected to a selected transistor under test via the switching circuit.
[0012] In one aspect of this disclosure, an electronic device includes the integrated circuit or the wafer test structure described above, and a probe card for providing test signals to the addressable test circuit.
[0013] One aspect of this disclosure is a method for testing the self-heating effect of transistors, which uses an addressable test circuit to test a large-scale array of devices under test, characterized by comprising the following steps:
[0014] The addressing circuit generates a gating control signal based on the input address signal, which selects the target transistor under test and turns off the transmission gate corresponding to the unselected transistor under test.
[0015] An excitation signal is applied to the gate of the selected target transistor under test, and the actual voltage difference across the gate resistor is acquired through a four-terminal Kelvin measurement structure, wherein the four-terminal Kelvin measurement structure includes a high-side excitation port FORCE_H, a low-side excitation port FORCE_L, a high-side sampling port SENSE_H, and a low-side sampling port SENSE_L.
[0016] The drain voltage VD, source voltage VS, and potentials of the four test ports of the unselected transistor under test are forced down to zero by using pull-down transistors to avoid leakage current and self-heating effects of the unselected transistor under test.
[0017] The gate resistance is calculated based on the voltage difference and the excitation current flowing through the gate, and a correspondence is established between the change in gate resistance and the power consumption of the transistor under test to characterize the temperature rise due to the self-heating effect of the transistor.
[0018] In one aspect of this disclosure, a transistor self-heating effect testing system includes:
[0019] The addressable test circuit described above;
[0020] The test instrument is configured to provide a programmable excitation signal to the addressable test circuit and receive a sampling signal;
[0021] The control unit is configured to generate the N-bit address signal to control the gating operation of the addressing circuit and to synchronously control the signal output and acquisition timing of the test instrument.
[0022] This disclosure proposes an addressable test circuit for transistor self-heating effects, used to characterize the self-heating effects of large-scale device under test (DUT) arrays. Traditional array test structures often suffer from inconsistent and inaccurate testing due to complex connection paths, leakage in unselected channels, and thermal coupling interference during multi-device scanning. To address these issues, this disclosure employs an architecture combining addressing decoding and transmission gate switching circuits. Address selection enables independent selection of the target DUT, and the force excitation and sense sampling signals are transmitted to the selected DUT separately. Simultaneously, relevant nodes of unselected DUTs are shut down, isolated, and forced to zero, thereby avoiding the influence of leakage current and additional heat generation on the test results. Combined with a four-terminal force / sense measurement method, the gate resistance extraction accuracy can be effectively improved, thus achieving stable and accurate characterization of transistor self-heating effects. Attached Figure Description
[0023] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example, not limitation, in which:
[0024] Figure 1 A schematic diagram of the architecture of an addressable test circuit according to one embodiment of the present invention.
[0025] Figure 2 A schematic diagram of the through-hole connection for self-heating effect testing of a DUT according to one embodiment of the present invention. Detailed Implementation
[0026] Existing technologies have proposed efficient characterization schemes based on test arrays. These schemes use address decoding circuits to control switching networks, enabling a finite number of pads to connect thousands of DUTs on demand, thereby improving test efficiency and supporting batch data acquisition. However, while existing addressable test circuits can connect a large number of DUTs with a finite number of pads, they still have shortcomings in accurately characterizing self-heating effects. Excitation and sampling signals must pass through switching devices and interconnect paths; on-resistance and line resistance introduce voltage deviations, affecting the actual application conditions and resistance extraction accuracy. As the array size increases, unselected channels may experience leakage current and background power consumption due to parasitic coupling or residual potential, resulting in additional heat and thermal coupling interference, reducing test consistency and repeatability. Furthermore, differences in trace lengths and switching paths among different DUTs can lead to inconsistent test conditions, affecting the reliability of inter-device comparisons.
[0027] Therefore, this disclosure provides an addressable test circuit for transistor self-heating effects. It addresses the problems of voltage drop and errors easily generated during the transmission of excitation and sampling signals through switching networks in existing addressable test structures, as well as leakage current and background heating interference that may occur in unselected channels, leading to insufficient measurement accuracy, consistency, and comparability between devices. Furthermore, this disclosure aims to achieve scalable independent gating testing and suppress the influence of unselected channels, thereby improving the reliability of self-heating characterization.
[0028] According to one or more embodiments, an addressable test circuit for transistor self-heating effect mainly includes an addressing circuit, a switching circuit, and a device-under-test (DUT) array. Further, the test circuit, according to its connection relationship, sequentially includes a decoder, an excitation switching circuit, a DUT array, and a detection switching circuit. Figure 1 As shown, the addressing circuit can be set to any bit width. Let the total bit width be N, then 2N DUTs can be connected for testing. The switching circuit consists of transmission gates. Under the decoding action of the addressing circuit, the force switch circuit transmits the excitation signals VD and FORCE_H, and the sense switch circuit transmits the sense signals SENSE_H and SENSE_L. The address signals control the transmission gates, transmitting the externally applied signal to the DUT at the selected address, while other unselected DUTs remain off.
[0029] Figure 1 The English terminology explanations include:
[0030] Address \[0:N-1] — Address \[0:N-1], used to select the address signal of the device under test;
[0031] Decoder – A decoder (or decoder) converts address signals into control signals that select specific devices;
[0032] Force Switch Circuit — A drive switch circuit (or excitation switch circuit) used to apply test signals to the device under test;
[0033] DUT Array—Device Under Test (DUT) array, DUT = Device Under Test, the array of chips or devices to be tested;
[0034] Sense Switch Circuit — A detection switch circuit (or sensing switch circuit) used to detect / measure the output response of the device under test;
[0035] FORCE_H — High-side drive (or high-level excitation), a high-level or high-port drive signal input;
[0036] FORCE_L — Low-side drive (or low-level excitation), a low-level or low-port drive signal input;
[0037] VD—Drive voltage, drive level / excitation signal;
[0038] VS — Source voltage (or power supply voltage);
[0039] SENSE_H — High-end detection (or high-level sensing), outputting a high-port or high-level detection signal;
[0040] SENSE_L — Low-end detection (or low-level sensing), outputting a low-port or low-level detection signal.
[0041] In the DUT array, each DUT's gate is led out with four vias for signal measurement: FORCE_H, FORCE_L, SENSE_H, and SENSE_L. Figure 2 As shown. When the DUT is selected for self-heating effect testing, the main test is the change of the DUT gate resistance R with the current IDS. FORCE_H and FORCE_L are used as force ports to apply voltage and measure the current IR. SENSE_H and SENSE_L are used as sense ports to measure the actual voltages SENSE1 and SENSE2 across the terminals. The final gate resistance is...
[0042] (1)
[0043] Figure 2 The English terms used include: Gate, Source, and Drain. Figure 2 This demonstrates a Kelvin four-wire test pin configuration for precision semiconductor parameter testing. The FORCE (drive / excite) pins are used to inject current or apply voltage to the device, while the SENSE (sensitivity / detection) pins are used to accurately measure the actual voltage at the device terminals, eliminating the influence of lead resistance and contact resistance. The high-side (H) and low-side (L) pins correspond to high-potential and low-potential test points, respectively.
[0044] To test the change of the gate resistance R of the transistor under test (DUT) with current IDS, first, set the voltages VD and VS to 0V, and establish a voltage difference between FORCE_H and FORCE_L. In this example, 1V and 0V are applied respectively. By changing the ambient temperature, the curve of R changing with T is measured. Next, the ambient temperature T0 is fixed, and the voltage VD is changed, i.e., the current IDS of the DUT is changed. The gate resistance R is then measured to obtain the relationship between R and power dissipation P (Vd × IDS), thus finally obtaining the relationship between ∆T (T - T0) and P, completing the test of the transistor's self-heating effect.
[0045] The voltages VD, VS, FORCE_H, FORCE_L, SENSE_H, and SENSE_L of the unselected DUT are controlled by the address to turn off the transmission gate directly connected to it, set the pull-down transistor to open, and set all these signals to 0V. This ensures that no current flows through the unselected DUT and no additional heat is generated to interfere with the self-heating effect test of the selected DUT.
[0046] The core of this disclosed test circuit lies in employing addressing decoding and switching circuits to achieve independent selection of different DUTs in the array, and combining a force / sense measurement structure to complete gate resistance and self-heating effect testing. Therefore, this disclosure achieves independent selection of a large-scale DUT array by using an addressable test architecture combining addressing decoding and transmission gate switching circuits, and transmits the force excitation signal and sense sampling signal to the selected DUT under controlled conditions, while shutting down and forcing the relevant nodes of the unselected DUTs to zero. This structure can complete multi-device scan testing without adding external test ports, avoids thermal coupling interference introduced by leakage current and additional heat generation from unselected DUTs, and improves the gate resistance extraction accuracy with a four-terminal force / sense measurement method, thereby achieving stable and accurate characterization of transistor self-heating effects. Therefore, when using the addressing method for large-scale DUT testing, this disclosure uses a decoded and controlled transmission gate switch network to select and transmit signals such as VD, FORCE_H, SENSE_H, and SENSE_L, and adopts a shutdown and pull-down zeroing strategy for unselected channels to achieve precise measurement of the four terminals of the selected DUT and self-heating effect testing, and ensures the accuracy, consistency and scalability of the testing process.
[0047] The beneficial effects of this disclosure include:
[0048] 1) A configurable bit-width addressing decoding structure is adopted, which, together with the transmission gate switch, enables independent gating tests of 2N DUTs, and completes large-scale array scanning without adding external test interfaces.
[0049] 2) Four ports, FORCE_H / L and SENSE_H / L, are led out from the gate of the DUT to form a Kelvin measurement structure, which can effectively eliminate the voltage drop error caused by the trace resistance and contact resistance, and make the gate resistance extraction more accurate.
[0050] 3) For unselected DUTs, turn off the corresponding transmission gates and turn on the pull-down transistors to force VD, VS, and force / sense nodes to 0V, thereby avoiding leakage current and additional heat generation and reducing the interference of thermal coupling on self-heating tests.
[0051] 4) Supports obtaining the RT curve first and then obtaining the RP curve under a fixed T0, thereby establishing the correspondence between ΔT and power consumption P, realizing the complete characterization of transistor self-heating effect and the performance comparison of different DUTs.
[0052] It should be understood that in the embodiments of the present invention, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following associated objects have an "or" relationship.
[0053] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. An addressable test circuit for transistor self-heating effect, characterized in that, include: The addressing circuit is configured to receive an N-bit address signal and generate a corresponding gating control signal. Switching circuits include excitation switching circuits and sensing switching circuits composed of transmission gates; The device under test array includes multiple transistors under test arranged in an array. The gate of each transistor under test is connected to four test ports, namely the high-side excitation port FORCE_H, the low-side excitation port FORCE_L, the high-side sampling port SENSE_H, and the low-side sampling port SENSE_L. The addressing circuit controls the transmission gates in the excitation switch circuit and the sensing switch circuit to be turned on or off through the gating control signal, so as to transmit the external excitation signal to the selected transistor under test, while turning off the transmission gates corresponding to the unselected transistor under test. Each test port, source, and drain of the unselected transistor under test is connected to a pull-down transistor. The pull-down transistor is configured to force the voltage of the connected node to zero potential when the corresponding transmission gate is turned off, so as to eliminate leakage current and thermal coupling interference.
2. The addressable test circuit according to claim 1, characterized in that, The excitation switch circuit is configured to transmit the drain voltage VD and the high-side excitation signal FORCE_H, and the sensing switch circuit is configured to transmit the high-side sampling signal SENSE_H and the low-side sampling signal SENSE_L.
3. The addressable test circuit according to claim 1, characterized in that, The transmission gate is composed of a PMOS transistor and an NMOS transistor connected in parallel. The gating control signal output by the addressing circuit includes a first control signal and a second control signal that are inversely related, which control the gates of the NMOS transistor and the PMOS transistor, respectively.
4. The addressable test circuit according to claim 1, characterized in that, The pull-down transistor is an NMOS transistor or a ground resistor, and its control terminal is connected to the inverted gating signal output by the addressing circuit.
5. An integrated circuit, characterized in that, The device under test (DUT) array is integrated on the same semiconductor substrate and includes an addressable test circuit for transistor self-heating effect as described in any one of claims 1 to 4.
6. A wafer testing structure, characterized in that, The device includes the integrated circuit as described in claim 5, and a plurality of test pads disposed on the integrated circuit, the test pads being electrically connected to a selected transistor under test via the switching circuit.
7. An electronic device, characterized in that, Includes the integrated circuit as described in claim 5, or the wafer test structure as described in claim 6, and a probe card for providing test signals to the addressable test circuit.
8. A method for testing the self-heating effect of transistors, employing an addressable test circuit to test a large-scale array of devices under test, characterized in that... Includes the following steps: The addressing circuit generates a gating control signal based on the input address signal, which selects the target transistor under test and turns off the transmission gate corresponding to the unselected transistor under test. An excitation signal is applied to the gate of the selected target transistor under test, and the actual voltage difference across the gate resistor is acquired through a four-terminal Kelvin measurement structure, wherein the four-terminal Kelvin measurement structure includes a high-side excitation port FORCE_H, a low-side excitation port FORCE_L, a high-side sampling port SENSE_H, and a low-side sampling port SENSE_L. The drain voltage VD, source voltage VS, and potentials of the four test ports of the unselected transistor under test are forced down to zero by using pull-down transistors to avoid leakage current and self-heating effects of the unselected transistor under test. The gate resistance is calculated based on the voltage difference and the excitation current flowing through the gate, and a correspondence is established between the change in gate resistance and the power consumption of the transistor under test to characterize the temperature rise due to the self-heating effect of the transistor.
9. The test method according to claim 8, characterized in that, The step of establishing the correspondence between the gate resistance change and power consumption includes: Under zero drain-source voltage conditions, the temperature coefficient of resistance is obtained by measuring the curve of gate resistance versus temperature under varying ambient temperature. At a fixed ambient temperature, the drain voltage was varied to change the drain-source current, and the gate resistance value was measured under different power consumption conditions. The temperature rise ΔT is calculated based on the temperature coefficient of resistance and the change in gate resistance, and the relationship between temperature rise ΔT and power consumption P is established.
10. A transistor self-heating effect testing system, characterized in that, include: The addressable test circuit as described in any one of claims 1 to 4; The test instrument is configured to provide a programmable excitation signal to the addressable test circuit and receive a sampling signal; The control unit is configured to generate the N-bit address signal to control the gating operation of the addressing circuit and to synchronously control the signal output and acquisition timing of the test instrument.