Technology for stacked photonic integrated circuit dies

Abstract

Techniques for stacking photonic integrated circuit (PIC) dies are disclosed. In illustrative embodiments, two or more PIC dies are stacked on top of each other, with electronic integrated circuit (EIC) dies stacked on top. The PIC dies can be optically coupled in any suitable manner, such as mirrors in an optical bridge, direct-write waveguides in an optical bridge, or photonic wire bonding. Stacking PIC dies can increase yield, reduce footprint, lower cost, and allow the integration of different PIC technologies into a single device.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 202280096341.6, filed on June 24, 2022, entitled "Technology for Stacked Photonic Integrated Circuit Dies". Background Technology

[0002] Photonic integrated circuits (PICs) can be used in several applications such as communications. As PIC size increases, yield may decrease, and the required package size may also increase, thereby increasing costs and potentially limiting PIC performance. Attached Figure Description

[0003] Figure 1 This is an isometric view of one embodiment of a device having stacked PIC dies.

[0004] Figure 2 yes Figure 1 A cross-sectional view of one embodiment of the device.

[0005] Figure 3 yes Figure 1 A cross-sectional view of one embodiment of the device.

[0006] Figure 4 yes Figure 1 A cross-sectional view of one embodiment of the device.

[0007] Figure 5 yes Figure 1 A cross-sectional view of one embodiment of the device.

[0008] Figure 6 yes Figure 1 A cross-sectional view of one embodiment of the device.

[0009] Figure 7 This is a simplified flowchart of at least one embodiment of a method for manufacturing a PIC die having stacks.

[0010] Figure 8 This is a top view of a wafer and die that may be included in a microelectronic assembly according to any embodiment disclosed herein.

[0011] Figure 9 This is a cross-sectional side view of an integrated circuit device that may be included in a microelectronic assembly according to any embodiment disclosed herein.

[0012] Figures 10A to 10D This is a perspective view of an exemplary planar, full-ring gate, and stacked full-ring gate transistor.

[0013] Figure 11This is a cross-sectional side view of an integrated circuit device assembly that may include microelectronic components according to any embodiment disclosed herein.

[0014] Figure 12 This is a block diagram of an example electrical device that may include a microelectronic assembly according to any embodiment disclosed herein. Detailed Implementation

[0015] In the various embodiments disclosed herein, a device includes a plurality of photonic integrated circuit (PIC) dies and electronic integrated circuit (EIC) dies stacked on top of each other. Waveguides in the PIC dies are coupled to each other using optical bridges (such as mirrors or lenses in glass, direct-write waveguides, or photonic wire bonding). Using stacked PIC dies can increase throughput and reduce the device footprint.

[0016] As used herein, the phrase "communicatively coupled" refers to the ability of one component to send or receive signals from another component. The signals can be of any type, such as input signals, output signals, or power signals. A component can send or receive signals to or from another component it is communicatively coupled to via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of communicatively coupled components include: integrated circuit dies located in the same package that communicate via embedded bridges in the package substrate; and integrated circuit assemblies attached to a printed circuit board that send or receive signals to or from other integrated circuit assemblies or electronic devices attached to the printed circuit board.

[0017] In the following description, specific details are set forth, but embodiments of the techniques described herein may be practiced without these specific details. Well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this description. Phrases such as “embodiment,” “various embodiments,” “some embodiments,” etc., may include features, structures, or characteristics, but not every embodiment necessarily includes a particular feature, structure, or characteristic.

[0018] Some embodiments may have some, all, or none of the features described for other embodiments. Terms such as “first,” “second,” “third,” etc., describe common objects and indicate different instances of similar objects referenced. Such adjectives do not imply that the objects so described must be in a given sequence, in order of rank, or in any other way, in time or space. “Connection” may indicate direct physical or electrical contact between elements, and “coupling” may indicate cooperative operation or interaction between elements, but they may or may not be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” etc., used with respect to embodiments of this disclosure are synonymous. Terms modified by the word “substantially” include arrangements, orientations, spacing, or positions that differ slightly in meaning from unmodified terms. For example, the central axis of a magnetic plug substantially coaxially aligned with a through-hole may be misaligned by a few degrees with the central axis of the through-hole. In another example, features of a substrate assembly described as having substantially the listed dimensions, such as through-width, may vary within a few percent of the listed dimensions.

[0019] It should be understood that in the examples further shown and described below, the figures may not be drawn to scale and may not include all possible layers and / or circuit components. Additionally, it will be understood that while some figures illustrate transistor designs with orthogonal (e.g., vertical) boundaries for source / drain regions, electrodes, etc., the embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within orthogonality + / - 5 or 10 degrees) due to the manufacturing methods used to produce such devices or for other reasons.

[0020] Referring now to the accompanying drawings, which are not necessarily drawn to scale, similar or identical numerals may be used to designate the same or similar parts in different drawings. The use of similar or identical numerals in different drawings does not imply that all drawings including similar or identical numerals constitute a single or identical embodiment. Identical numerals with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example and not limitation.

[0021] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding thereof. However, it will be apparent that novel embodiments can be practiced without these specific details. In other instances, well-known structures and apparatuses are shown in block diagram form for ease of description. The intention is to cover all modifications, equivalents, and alternatives within the scope of the claims.

[0022] As used herein, the phrase “located” in the context of a first layer or component being located on a second layer or component means that the first layer or component is directly and physically attached to the second layer or component (with no layer or component between the first layer or component and the second layer or component) or is physically attached to the second layer or component using one or more intermediate layers or components.

[0023] As used herein, the term "adjacent" means layers or components that are physically in contact with each other. That is, there are no layers or components between the adjacent layers or components. For example, layer X adjacent to layer Y means that layer X is physically in contact with layer Y.

[0024] Now for reference Figures 1 to 3 In one embodiment, device 100 includes two photonic integrated circuit (PIC) dies 104 and 106 and an electrical integrated circuit (EIC) die 102 stacked on top of each other. Figure 2 A cross-sectional side view of the device 100 is shown, and Figure 3 A top view of one of the PIC dies 106 is shown. An optical bridge 108 couples the waveguide in the upper PIC die 104 to the lower PIC die 106. The EIC die 102 and PIC dies 104 and 106 are supported on a circuit board 110.

[0025] Device 100 may be embodied or otherwise include a system-on-a-chip (SoC), processor, memory, graphics processor, accelerator, application-specific integrated circuit, field-programmable gate array, network router, network switch, network interface controller, server computer, mobile computing device, etc.

[0026] In the illustrative embodiments, stacking two or more PIC dies 104, 106 offers several advantages. The yield of each of the smaller PIC dies 104, 106 will generally be higher than that of the larger PIC die. Stacking PIC dies 104, 106 can reduce the footprint required for the PIC dies 104, 106, or alternatively, increase the actual estate of the PIC dies 104, 106 within the same footprint. Furthermore, in some embodiments, the PIC dies 104, 106 can be manufactured using different technology nodes, can use different substrates, or may otherwise be incompatible with manufacturing on a single PIC die.

[0027] like Figure 2As shown, in one embodiment, PIC die 104 has a substrate 202 and a photonic layer 204. Similarly, PIC die 106 has a substrate 206 and a photonic layer 208. In illustrative embodiments, some or all of the photonic components (i.e., waveguides, splitters, filters, lasers, etc.) are located in photonic layers 204, 208. Electrical vias 210, 212 can provide electrical connections between PIC dies 104, 106 and / or EIC die 102. Vias 210, 212 can provide input / output connections, power delivery, etc. In some embodiments, vias 210, 212 can provide electrical connections between circuit board 110 and PIC dies 104, 106 and / or EIC die 102.

[0028] In one embodiment, waveguide 222 in PIC die 104 is coupled to vertical coupler 214, which vertically guides the light in waveguide 222. The light forms a beam 218 outside PIC die 104, which is reflected from mirror 220 toward PIC die 106. Vertical coupler 216 in PIC die 106 couples beam 218 into waveguide 224 in PIC die 106. Waveguides 222, 224 and other components of PIC dies 104 and 106 can operate at any suitable wavelength (e.g., 400-1800 nm). In an illustrative embodiment, the operating wavelength has a center wavelength between 1260-1360 nm for O-band signals or between 1530-1565 nm for C-band signals. In other embodiments, the operating wavelength can be, for example, an S-band signal or an L-band signal.

[0029] To focus light from vertical coupler 214 to vertical coupler 216 (or vice versa), any suitable technique can be used, such as forming lenses or mirrors in photonic layers 204, 208 or substrates 202, 206, using curved mirror 220 or lenses in optical bridge 108, etc.

[0030] EIC die 102 can be embodied as any suitable electrical integrated circuit. EIC die 102 can be embodied as, form part of, or include the following: processor, system-on-a-chip (SoC), memory, graphics processor, accelerator, application-specific integrated circuit, field-programmable gate array, etc. In the illustrative embodiment, EIC die 102 is electrically coupled to PIC dies 104, 106 via vias 210, 212. Alternatively or additionally, EIC die 102 can be electrically coupled to PIC dies 104, 106 or other components such as board 110 in any other suitable manner (such as wire bonding, bumping, embedded multi-die interconnect bridge (EMIB), etc.).

[0031] PIC dies 104 and 106 can be made of any suitable material. In the illustrative embodiment, the substrates 202 and 206 of PIC dies 104 and 106 are made of silicon. In other embodiments, the substrates 202 and 206 of PIC dies 104 and 106 can be made of any suitable material, such as glass, silicon oxide, polymers, etc. Similarly, photonic layers 204 and 208 can be made of or comprise any suitable material, such as silicon, silicon oxide, silicon nitride, polymers, glass, etc.

[0032] In the illustrative embodiment, waveguides 222, 224 are silicon waveguides in silicon oxide layers 204, 208. Each waveguide 222, 224 can have any suitable size, such as a width and / or height of 0.1-10 micrometers. In the illustrative embodiment, each waveguide 222, 224 is square. In other embodiments, waveguides 222, 224 can have different shapes, such as rectangular shapes. PIC die 104 can include any suitable number of waveguides 222 coupled to waveguides 224 of PIC die 106, such as 1-128 waveguides 222 or more. Of course, PIC dies 104, 106 can include additional waveguides internally.

[0033] PIC dies 104 and 106 may include one or more lasers or other light sources, detectors, amplitude and / or phase modulators, filters, splitters, amplifiers, interferometers, microring resonators, gratings, extrusion or other quantum light sources, etc. In some embodiments, light from an external source (such as a laser) may be provided to PIC dies 104 and 106. PIC dies 104 and 106 may perform any suitable function, such as converting optical signals to electrical signals or vice versa, matrix multiplication, quantum logic gates, optical computing gates, etc.

[0034] exist Figure 3 The image shows a top view of one embodiment of the PIC die 106. In the illustrative embodiment, the PIC die 106 includes an array of Mach-Zehnder interferometers 304. A vertical coupler 216 couples light into and out of waveguide 302. The vertical coupler 216 can be connected to another PIC die, such as PIC die 104. The waveguide 302 of the PIC die 106 is provided as input to the array of Mach-Zehnder interferometers 304. Each Mach-Zehnder interferometer includes two splitters 306 and a phase shifter 308. In the illustrative embodiment, the phase shifter 308 is controlled by electrical signals from the EIC 102 through vias 210, 212. It should be understood that... Figure 3 The embodiment shown is only one possible embodiment of the PIC die 106, and other PIC dies 106 may include those with... Figure 3The components shown are compared to additional or fewer components. In some embodiments, PIC dies 104, 106 may include, as needed, vertical couplers 214, 216 along any edge of the PIC dies 104, 106.

[0035] In the illustrative embodiment, hybrid bonding is used to bond EIC die 102 and PIC die 104 together. In other embodiments, other techniques may be used, such as microbumps. PIC dies 104 and 106 may be bonded together in a similar manner.

[0036] Any suitable technique can be used to place PIC dies 104, 106, and / or EIC dies 102, such as by using a pick-and-place machine. PIC dies 104, 106, and / or EIC dies 102 may include one or more references, which can be used by the pick-and-place machine to place another PIC die 104, 106, and / or EIC die 102. References can be represented, for example, as points, lines, or other structures indicating the location of specific portions of PIC dies 104, 106, and / or EIC dies 102. The pick-and-place machine can align PIC dies 104, 106, and / or EIC dies 102 with high precision, such as misalignment of less than 3-0.3 micrometers at 3 sigma.

[0037] The optical bridge 108 can be made of any suitable material, such as glass, silicon, silicon oxide, polymer, etc. The reflector 220 can be made of any suitable material, such as aluminum, silver, interference film, etc. The device 100 can include any suitable number of optical bridges 108. For example, in one embodiment, one optical bridge 108 can provide all connections between PIC dies 104, 106. In other embodiments, several optical bridges 108 can be used to provide connections between PIC dies 104, 106. The optical bridges 108 can be located at any suitable location, such as along any edge of the PIC dies 104, 106. In some embodiments, a channel can be defined within the PIC dies 104, 106, and a portion of one or more optical bridges 108 can be placed within the channel, potentially aligned with one or more waveguides.

[0038] The illustrative circuit board 110 may be made of ceramic, glass, and / or organic-based materials containing glass fibers and resin (such as FR-4). The circuit board 110 may have any suitable length or width, such as 10-500 mm. The circuit board 110 may have any suitable thickness, such as 0.2-5 mm. The circuit board 110 may support additional components besides PIC dies 104, 106, and EIC die 102, such as additional EIC dies or PIC dies, processor units, memory devices, accelerator devices, etc.

[0039] It should be understood that Figure 1 The configuration shown, in which an EIC die 102 is stacked on top of two PIC dies 104, 106, is merely one possible embodiment. In some embodiments, more or fewer EIC dies and / or PIC dies may be included. For example, in some embodiments, PIC die 104 may have two EIC dies 102 on top of it. In another example, two PIC dies may be below EIC dies 102. In some embodiments, one or more EIC dies 102 may be between two PIC dies 104, 106. Generally, any suitable arrangement of stacked EIC dies and / or PIC dies can be used. For example, device 100 may include, for example, 2-10 PIC dies and / or EIC dies stacked on top of each other. In some embodiments, an optical bridge 108 may connect more than two PIC dies. For example, an optical bridge 108 may optically couple a first PIC die to a second PIC die, an second PIC die to a third PIC die, and a first PIC die to a third PIC die. Alternatively, an optical bridge 108 may be used to optically couple the first PIC die to the second PIC die, and the second optical bridge 108 may be used to optically couple the second PIC die to the third PIC die.

[0040] Now for reference Figure 4 In one embodiment, device 100 includes PIC dies 104, 106, wherein waveguides 222, 224 extend to the edges of PIC dies 104, 106. In such an embodiment, optical bridge 108 may include a mirror 220 that reflects light emitted from the edge from waveguide 222 to waveguide 224 (or vice versa). Similar to the above regarding... Figure 1 and Figure 2 In the described embodiments, any suitable technique can be used to focus light from waveguide 222 to waveguide 224, such as forming lenses or mirrors in photonic layers 204, 208 or substrates 202, 206, using a curved mirror 220 or lens in optical bridge 108, etc.

[0041] Now for reference Figure 5 In one embodiment, device 100 includes an optical bridge 108 having a direct-write waveguide 502 that connects light from vertical coupler 214 to vertical coupler 216. Any suitable direct-write method can be used, such as writing the waveguide in glass, crystal, or polymer using a femtosecond laser.

[0042] Now for reference Figure 6In one embodiment, the device 100 includes an optical bridge 108 having a photonic wire bond 602 connecting waveguide 222 to waveguide 224. In an illustrative embodiment, light from waveguide 222 is evanescently coupled to the photonic wire bond 602, and then light in the photonic wire bond is evanescently coupled to waveguide 224.

[0043] It should be understood that the above-described methods for optically coupling PIC dies 104 and 106 together are merely some of the possible methods, and other methods or combinations may be used. For example, in one embodiment, a write-through waveguide may be used to create waveguides that are eerily coupled to waveguides 222 and / or 224. In another example, photonic wire bonding 602 may be coupled to edge-emitting waveguides 222, 224 and / or vertical couplers 214, 216. Generally, any suitable coupling technique or combination of techniques may be used to optically couple PIC dies 104 and 106.

[0044] Now for reference Figure 7 In one embodiment, a flowchart of a method 700 for creating device 100 is shown. Method 700 can be performed by a technician and / or by one or more automated machines. In some embodiments, one or more machines can be programmed to perform some or all of the steps of method 700. Such machines may include, for example, memory, processor, data storage, etc. The memory and / or data storage may store instructions that, when executed by the machine, cause the machine to perform some or all of the steps of method 700. Method 700 can use any suitable set of techniques used in semiconductor processes, such as chemical vapor deposition, atomic layer deposition, physical layer deposition, molecular beam epitaxy, layer transfer, photolithography, ion implantation, dry etching, wet etching, thermal processing, flip chip, layer transfer, magnetron sputtering deposition, pulsed laser deposition, pick-and-place, etc. It should be understood that method 700 is merely one embodiment of a method for creating device 100, and other methods can be used to create device 100. In some embodiments, the steps of method 700 may be performed in a different order than that shown in the flowchart.

[0045] Method 700 begins at block 702, in which PIC dies, such as PIC dies 104 and 106, are fabricated. In block 704, PIC dies can be fabricated on different substrates. In block 706, different nodes can be used to fabricate PIC dies. In block 708, different lasers can be used to fabricate PIC dies.

[0046] In block 710, the PIC die is tested. In block 712, the faulty PIC die is discarded. In some embodiments, the PIC die may be relatively small, so that if a fault exists, only the relatively small component can be discarded.

[0047] In box 714, PIC dies are stacked on top of each other. Any suitable technique can be used to stack PIC dies, such as copper bumps or hybrid bonding.

[0048] In box 716, a PIC die optically coupled to a stack using optical bridge 108 is used. In box 718, a PIC die optically coupled to a stack using vertically coupled waveguides and mirror 220 can be used, such as... Figure 2 As shown. In box 720, a PIC die optically coupled to a stack of edge-emitting waveguides 222, 224 and mirror 220 can be used, such as... Figure 4 As shown. In box 722, a PIC die can be optically coupled to the stack using the direct-write waveguide 502 in the glass optical bridge 108, such as... Figure 6 As shown. In box 724, a PIC die with a 602 optically coupled stack can be used via photonic wire bonding, such as... Figure 6 As shown.

[0049] In block 726, one or more EIC dies 102 can be stacked on the PIC die. Additional packaging steps, such as wire bonding connections from the circuit board 110 to the EIC die 102, can then be performed.

[0050] Figure 8 This is a top view of a wafer 800 and die 802 (e.g., any suitable die 102, 104, 106) that may be included in any device 100 disclosed herein. The wafer 800 may be composed of semiconductor material and may include one or more dies 802 having an integrated circuit structure formed on the surface of the wafer 800. Each die 802 may be a repeating unit of an integrated circuit product including any suitable integrated circuit. After the semiconductor product is manufactured, the wafer 800 may undergo a singulation process, in which the dies 802 are separated from each other to provide a discrete “chip” of the integrated circuit product. The die 802 may be any of dies 102, 104, 106 as described herein. The die 802 may include one or more transistors (e.g., discussed below). Figure 9The transistors 940 (some of which are transistors), supporting circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the die 800 or die 802 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), conductive bridged RAM (CBRAM), etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple devices of these devices may be combined on a single die 802. For example, a memory array formed by multiple memory devices may be formed in conjunction with a processor unit (e.g., Figure 12 The processor unit 1202 or other logically identical die 802 is configured to store information in a memory device or execute instructions stored in a memory array. The various devices in the device 100 disclosed herein can be manufactured using die-to-wafer assembly technology, wherein some of the dies 102, 104, 106 are attached to a wafer 800 including other dies among dies 102, 104, 106, and subsequently the wafer 800 is monolithized.

[0051] Figure 9 This is a cross-sectional side view of an integrated circuit device 900 that may be included in any of the devices 100 disclosed herein (e.g., in any of dies 102, 104, 106). One or more of the integrated circuit devices 900 may be included in one or more dies 802 ( Figure 8 The integrated circuit device 900 can be formed on the die substrate 902 (e.g., ...). Figure 8 On the 800 chip, and may be included in the die (e.g., Figure 8 The die substrate 902 can be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). The die substrate 902 can include, for example, a crystalline substrate formed using bulk silicon or silicon-on-insulator (SOI) substructures. In some embodiments, the die substrate 902 can be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV can also be used to form the die substrate 902. Although several examples of materials that can form the die substrate 902 are described herein, any material that can be used as the basis for the integrated circuit device 900 can be used. The die substrate 902 can be a single die (e.g., Figure 8 The 802 die or chip (e.g., Figure 8It is part of the 800 chip.

[0052] Integrated circuit device 900 may include one or more device layers 904 disposed on a die substrate 902. Device layer 904 may include features of one or more transistors 940 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 902. Transistor 940 may include, for example, one or more source and / or drain (S / D) regions 920, a gate 922 for controlling current flow between S / D regions 920, and one or more S / D contacts 924 for routing electrical signals to / from S / D regions 920. Transistor 940 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. Transistor 940 is not limited to... Figure 9 The types and configurations described herein may include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or combinations thereof. Non-planar transistors may include FinFET transistors (such as dual-gate or tri-gate transistors) and all-around or full-ring gate transistors (such as nanoribbon transistors, nanosheet transistors, or nanowire transistors).

[0053] Figures 10A to 10D This is a simplified perspective view of exemplary planar, FinFET, full-gate, and stacked full-gate transistors. Figures 10A to 10D The transistor shown is formed on a substrate 1016 having a surface 1008. An isolation region 1014 separates the source and drain regions of the transistor from other transistors and the body region 1018 of the substrate 1016.

[0054] Figure 10A This is a perspective view of an exemplary planar transistor 1000, which includes a gate 1002 that controls current flow between a source region 1004 and a drain region 1006. The transistor 1000 is planar because the source region 1004 and the drain region 1006 are planar with respect to a substrate surface 1008.

[0055] Figure 10B This is a perspective view of an example FinFET transistor 1020, which includes a gate 1022 that controls current flow between a source region 1024 and a drain region 1026. The transistor 1020 is non-planar because the source region 1024 and the drain region 1026 include “fins” extending upward from a substrate surface 1028. Since the gate 1022 surrounds three sides of the semiconductor fins extending from the source region 1024 to the drain region 1026, the transistor 1020 can be considered a tri-gate transistor. Figure 10BA single S / D fin extending through the gate 1022 is shown, but multiple S / D fins may extend through the gate of a FinFET transistor.

[0056] Figure 10C This is a perspective view of a gate-all-around (GAA) transistor 1040, which includes a gate 1042 that controls current flow between a source region 1044 and a drain region 1046. The transistor 1040 is non-planar because the source region 1044 and the drain region 1046 rise from a substrate surface 1028.

[0057] Figure 10D This is a perspective view of a GAA transistor 1060, which includes a gate 1062 that controls current flow between a plurality of raised source regions 1064 and a plurality of raised drain regions 1066. Transistor 1060 is a stacked GAA transistor because the gate controls current flow between the plurality of raised S / D regions stacked on top of each other. Transistors 1040 and 1060 are considered full-to-the-loop gate transistors because the gate surrounds all sides of the semiconductor portion extending from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., widths 1048 and 1068 of transistors 1040 and 1060, respectively), transistors 1040 and 1060 may alternatively be referred to as nanowire transistors, nanosheet transistors, or nanoribbon transistors.

[0058] return Figure 9 The transistor 940 may include a gate 922 formed of at least two layers (a gate dielectric and a gate electrode). The gate dielectric may include a single layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0059] High-k dielectric materials can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using high-k materials, the gate dielectric can be annealed to improve its quality.

[0060] The gate electrode may be formed on the gate dielectric and may include at least one p-type or n-type work function metal, depending on whether the transistor 940 is a p-type metal-oxide-semiconductor (PMOS) or n-type metal-oxide-semiconductor (NMOS) transistor. In some embodiments, the gate electrode may consist of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0061] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0062] In some embodiments, when viewed as a cross-section of the transistor 940 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 902 and two sidewall portions substantially perpendicular to the top surface of the die substrate 902. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 902 and does not include the sidewall portions substantially perpendicular to the top surface of the die substrate 902. In other embodiments, the gate electrode may consist of a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0063] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and typically include deposition and etching steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0064] The S / D region 920 can be formed within a die substrate 902 adjacent to the gate 922 of the individual transistor 940. For example, the S / D region 920 can be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic can be implanted into the die substrate 902 to form the S / D region 920. An annealing process, activating the dopant and allowing it to diffuse further into the die substrate 902, can follow the ion implantation process. In the latter process, the die substrate 902 can be etched first to form a trench at the location of the S / D region 920. An epitaxial deposition process can then be performed to fill the trench using the material used to fabricate the S / D region 920. In some embodiments, a silicon alloy such as silicon germanium or silicon carbide can be used to fabricate the S / D region 920. In some embodiments, the epitaxially deposited silicon alloy can be in-situ doped with dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials, such as germanium or group III-V materials or alloys, may be used to form the S / D region 920. In other embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D region 920.

[0065] Electrical signals such as power and / or input / output (I / O) signals can be transmitted through one or more interconnect layers disposed on device layer 904 (in Figure 9 The interconnect layers 906-910 are shown as routing to and / or from devices in device layer 904 (e.g., transistor 940). For example, conductive features of device layer 904 (e.g., gate 922 and S / D contact 924) may be electrically coupled to interconnect structures 928 of interconnect layers 906-910. One or more interconnect layers 906-910 may form a metallized stack (also referred to as an "ILD stack") 919 of integrated circuit device 900.

[0066] Interconnect structures 928 can be arranged within interconnect layers 906-910 to route electrical signals according to various designs; in particular, this arrangement is not limited to... Figure 9 The specific configuration of the interconnect structure 928 depicted in the diagram. Although in Figure 9 The present disclosure depicts a specific number of interconnect layers 906-910, but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than those depicted.

[0067] In some embodiments, the interconnect structure 928 may include lines 928a and / or vias 928b filled with a conductive material such as a metal. Lines 928a may be arranged to route electrical signals in a direction substantially parallel to a plane of the die substrate 902 on which the device layer 904 is formed. For example, lines 928a may route electrical signals in a direction in and / or across a page. Vias 928b may be arranged to route electrical signals in a direction substantially perpendicular to a plane of the die substrate 902 on which the device layer 904 is formed. In some embodiments, vias 928b may electrically couple lines 928a of different interconnect layers 906-910 together.

[0068] like Figure 9 As shown, interconnect layers 906-910 may include dielectric material 926 disposed between interconnect structures 928. In some embodiments, the dielectric material 926 disposed between interconnect structures 928 in different interconnect layers of interconnect layers 906-910 may have different compositions; in other embodiments, the composition of the dielectric material 926 between different interconnect layers 906-910 may be the same. Device layer 904 may also include dielectric material 926 disposed between transistor 940 and the bottom layer of metallization stack. The dielectric material 926 included in device layer 904 may have a different composition than the dielectric material 926 included in interconnect layers 906-910; in other embodiments, the composition of the dielectric material 926 in device layer 904 may be the same as the dielectric material 926 included in any of interconnect layers 906-910.

[0069] A first interconnect layer 906 (referred to as metal 1 or "M1") may be formed directly on device layer 904. In some embodiments, as shown, the first interconnect layer 906 may include a line 928a and / or a via 928b. The line 928a of the first interconnect layer 906 may be coupled to a contact of device layer 904 (e.g., S / D contact 924). The via 928b of the first interconnect layer 906 may be coupled to a line 928a of a second interconnect layer 908.

[0070] The second interconnect layer 908 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 906. In some embodiments, the second interconnect layer 908 may include a via 928b to couple a line 928a of the second interconnect layer 908 to a line 928a of the third interconnect layer 910. Although for clarity, the lines 928a and vias 928b are structurally depicted in lines within the respective interconnect layers, in some embodiments, the lines 928a and vias 928b may be structurally and / or materially continuous (e.g., simultaneously filled during a dual damascene process).

[0071] Based on similar techniques and configurations described in conjunction with the second interconnect layer 908 or the first interconnect layer 906, a third interconnect layer 910 (referred to as metal 3 or "M3") (and additional interconnect layers as needed) can be continuously formed on the second interconnect layer 908. In some embodiments, the interconnect layers in the metallization stack 919 that are "higher" (i.e., farther from device layer 904) in the integrated circuit device 900 can be thicker than the interconnect layers in the metallization stack 919, wherein lines 928a and vias 928b in the higher interconnect layers are thicker than lines 928a and vias 928b in the lower interconnect layers.

[0072] The integrated circuit device 900 may include a solder resist material 934 (e.g., polyimide or a similar material) and one or more conductive contacts 936 formed on interconnect layers 906-910. Figure 9 In this diagram, conductive contact 936 is shown in the form of a bonding pad. Conductive contact 936 may be electrically coupled to interconnect structure 928 and configured to route electrical signals from transistor(s) 940 to an external device. For example, solder bonds may be formed on one or more conductive contacts 936 to mechanically and / or electrically couple an integrated circuit die including integrated circuit device 900 to another component (e.g., a printed circuit board). Integrated circuit device 900 may include additional or alternative structures for routing electrical signals from interconnect layers 906-910; for example, conductive contact 936 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0073] In some embodiments where the integrated circuit device 900 is a double-sided die, the integrated circuit device 900 may include another metallization stack (not shown) on the opposite side of device layer(s) 904. This metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 906-910 to provide a conductive path (e.g., including wires and vias) between device layer(s) 904 and additional conductive contacts (not shown) on the side of the integrated circuit device 900 opposite to conductive contacts 936.

[0074] In other embodiments where the integrated circuit device 900 is a double-sided die, the integrated circuit device 900 may include one or more through-silicon vias (TSVs) through the die substrate 902; these TSVs may contact one or more device layers 904 and may provide a conductive path between one or more device layers 904 and additional conductive contacts (not shown) on the side of the integrated circuit device 900 opposite to the conductive contact 936. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the side of the integrated circuit device 900 opposite to the conductive contact 936 to the transistor 940 and any other components integrated into the die 900, and the metallized stack 919 may be used to route I / O signals from the conductive contact 936 to the transistor 940 and any other components integrated into the die 900.

[0075] Multiple integrated circuit devices 900 can be stacked with one or more TSVs in various stacked devices, thereby providing connectivity between one device and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide connectivity between the respective HBM and the base integrated circuit die. Conductive contacts can provide additional connectivity between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

[0076] Figure 11 This is a cross-sectional side view of an integrated circuit device assembly 1100 that may be included in any device 100 disclosed herein. In some embodiments, the integrated circuit device assembly 1100 may be device 100. The integrated circuit device assembly 1100 includes a plurality of components disposed on a circuit board 1102 (which may be a motherboard, system board, motherboard, etc.). The integrated circuit device assembly 1100 includes components disposed on a first surface 1140 and an opposing second surface 1142 of the circuit board 1102; typically, the components may be disposed on one or both of surfaces 1140 and 1142. Any integrated circuit component discussed below with reference to the integrated circuit device assembly 1100 may take the form of any suitable embodiment of the device 100 disclosed herein.

[0077] In some embodiments, circuit board 1102 may be a printed circuit board (PCB) comprising a plurality of metal (or interconnect) layers separated from each other by dielectric material layers and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1102 (optionally in conjunction with other metal layers). In other embodiments, circuit board 1102 may be a non-PCB substrate. In some embodiments, circuit board 1102 may be, for example, circuit board 110. Figure 11 The illustrated integrated circuit device assembly 1100 includes a package-on-interposer (PIP) structure 1136 coupled to a first side 1140 of a circuit board 1102 via a coupling assembly 1116. The coupling assembly 1116 electrically and mechanically couples the PIP structure 1136 to the circuit board 1102 and may include solder balls (such as...). Figure 11 The pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a pad grid array (LGA), male and female portions of the socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures shown), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a pad grid array (LGA), male and female portions of the socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0078] The on-intermediate layer package structure 1136 may include an integrated circuit component 1120 coupled to the intermediate layer 1104 via a coupling component 1118. The coupling component 1118 may take any suitable form for the application, such as the form discussed above with reference to coupling component 1116. Although in Figure 11 A single integrated circuit component 1120 is shown, but multiple integrated circuit components can be coupled to the interposer 1104; in fact, additional interposers can be coupled to the interposer 1104. The interposer 1104 can provide an interposer substrate for bridging the circuit board 1102 and the integrated circuit component 1120.

[0079] Integrated circuit assembly 1120 may be a packaged or unpackaged integrated circuit product, comprising one or more integrated circuit dies (e.g., Figure 8 802 core, Figure 9The packaged integrated circuit assembly 1120 includes an integrated circuit device 900 and / or one or more other suitable components. The packaged integrated circuit assembly includes one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit die and the package substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit assembly 1120, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1104. The integrated circuit assembly 1120 may include one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, the integrated circuit assembly 1120 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0080] In embodiments where integrated circuit assembly 1120 includes multiple integrated circuit dies, these dies may be of the same type (homogeneous multi-die integrated circuit assembly) or two or more different types (heterogeneous multi-die integrated circuit assembly). A multi-die integrated circuit assembly may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0081] In addition to including one or more processor units, the integrated circuit assembly 1120 may also include additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may reside on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die including the processor unit. These individual integrated circuit dies may be referred to as “chiplets.” In embodiments where the integrated circuit assembly includes multiple integrated circuit dies, interconnections between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as the Intel® Embedded Multi-Die Interconnect Bridge (EMIB)), or combinations thereof.

[0082] Typically, interposer 1104 can extend connections to wider spacing or reroute connections to different connections. For example, interposer 1104 can couple integrated circuit component 1120 to a set of ball grid array (BGA) conductive contacts of coupling component 1116 to couple to circuit board 1102. Figure 11In the illustrated embodiment, integrated circuit component 1120 and circuit board 1102 are attached to opposite sides of interposer 1104; in other embodiments, integrated circuit component 1120 and circuit board 1102 may be attached to the same side of interposer 1104. In some embodiments, three or more components may be interconnected via interposer 1104.

[0083] In some embodiments, the interposer 1104 may be formed as a PCB, comprising a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1104 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the interposer 1104 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1104 may include metal interconnects 1108 and vias 1110, including but not limited to through-hole vias 1110-1 (extending from a first side 1150 of the interposer 1104 to a second side 1154 of the interposer 1104), blind vias 1110-2 (extending from a first side 1150 or a second side 1154 of the interposer 1104 to an inner metal layer), and buried vias 1110-3 (connecting to an inner metal layer).

[0084] In some embodiments, the interposer 1104 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer can connect the connections on the first side of the silicon interposer to the opposite second side of the silicon interposer. In some embodiments, the interposer 1104 including the silicon interposer may further include one or more wiring layers to route the connections on the first side of the interposer 1104 to the opposite second side of the interposer 1104.

[0085] Intermediate layer 1104 may also include embedded devices 1114, including passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on intermediate layer 1104. The on-intermediate package structure 1136 may take the form of any on-intermediate package structure known in the art. In this embodiment, the intermediate layer is a non-printed circuit board.

[0086] The integrated circuit device assembly 1100 may include an integrated circuit component 1124 coupled to a first surface 1140 of a circuit board 1102 via a coupling component 1122. The coupling component 1122 may take the form of any of the embodiments discussed above with reference to coupling component 1116, and the integrated circuit component 1124 may take the form of any of the embodiments discussed above with reference to integrated circuit component 1120.

[0087] Figure 11 The illustrated integrated circuit device assembly 1100 includes a package-on-package structure 1134 coupled to a second side 1142 of a circuit board 1102 via a coupling component 1128. The package-on-package structure 1134 may include integrated circuit components 1126 and 1132 coupled together via a coupling component 1130, such that integrated circuit component 1126 is disposed between the circuit board 1102 and integrated circuit component 1132. Coupling components 1128 and 1130 may take the form of any of the embodiments of coupling component 1116 discussed above, and integrated circuit components 1126 and 1132 may take the form of any of the embodiments of integrated circuit component 1120 discussed above. The package-on-package structure 1134 can be configured according to any package-on-package structure known in the art.

[0088] Figure 12 This may be a block diagram of an example electrical device 1200 that may include one or more of the devices 100 disclosed herein. For example, any suitable component of the electrical device 1200 may include one or more of the integrated circuit device assembly 1100, integrated circuit assembly 1120, integrated circuit device 900, or integrated circuit die 802 disclosed herein, and may be arranged in any of the devices 100 disclosed herein. Multiple components in Figure 12 The components are shown as included in electrical device 1200, but any one or more of these components may be omitted or copied for the application, as applicable. In some embodiments, some or all of the components included in electrical device 1200 may be attached to one or more motherboards or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-a-chip (SoC) die.

[0089] Additionally, in various embodiments, electrical device 1200 may not include... Figure 12The electrical device 1200 may include one or more components as shown, but may include interface circuitry systems for coupling to one or more components. For example, the electrical device 1200 may not include the display device 1206, but may include display device interface circuitry systems (e.g., connector and driver circuitry systems) to which the display device 1206 may be coupled. In another set of examples, the electrical device 1200 may not include the audio input device 1224 or the audio output device 1208, but may include audio input or output device interface circuitry systems (e.g., connector and support circuitry systems) to which the audio input device 1224 or the audio output device 1208 may be coupled.

[0090] Electrical device 1200 may include one or more processor units 1202 (e.g., one or more processor cells). As used herein, the terms "processor unit," "processing unit," or "processor" may refer to any means or part of a means of processing electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processor unit 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Thus, a processor unit may be referred to as an XPU (or xPU).

[0091] Electrical device 1200 may include memory 1204, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or hard disk drive. In some embodiments, memory 1204 may include memory located on the same integrated circuit die as processor unit 1202. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last-level cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0092] In some embodiments, the electrical device 1200 may include one or more processor units 1202 that are heterogeneous or asymmetric to other processor units 1202 in the electrical device 1200. Various differences may exist between the processing units 1202 in the system based on a range of quality metrics including architecture, microarchitecture, thermal, power consumption characteristics, etc. These differences can effectively manifest themselves as asymmetry and heterogeneity between the processor units 1202 in the electrical device 1200.

[0093] In some embodiments, electrical device 1200 may include communication component 1212 (e.g., one or more communication components). For example, communication component 1212 may manage wireless communication for transmitting data to and from electrical device 1200. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data via a non-solid-state medium using modulated electromagnetic radiation. The term "wireless" does not imply that the associated apparatus does not contain any wires, although in some embodiments they may not contain any wires.

[0094] Communication component 1212 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) projects, and any revisions, updates, and / or modifications (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as “3GPP2”), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks (an acronym for Global Microwave Access Interoperability), and are certification marks for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. Communication component 1212 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication component 1212 may operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication component 1212 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO), and their derivatives, as well as any other radio protocol designated as 3G, 4G, 5G, and above. In other embodiments, communication component 1212 may operate according to other radio protocols. Electrical device 1200 may include antenna 1222 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0095] In some embodiments, communication component 1212 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet standard). As described above, communication component 1212 may include multiple communication components. For example, a first communication component 1212 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication component 1212 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication component 1212 may be dedicated to wireless communications, and the second communication component 1212 may be dedicated to wired communications.

[0096] Electrical device 1200 may include battery / power circuit system 1214. Battery / power circuit system 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of electrical device 1200 to an energy source (e.g., AC line power) separate from electrical device 1200.

[0097] Electrical device 1200 may include display device 1206 (or a corresponding interface circuit system, as discussed above). Display device 1206 may include one or more embedded or wired or wirelessly connected external visual indicators, such as head-up displays, computer monitors, projectors, touch screen displays, liquid crystal displays (LCDs), light-emitting diode displays, or flat panel displays.

[0098] Electrical device 1200 may include audio output device 1208 (or a corresponding interface circuit system, as discussed above). Audio output device 1208 may include any embedded or wired or wirelessly connected external device that generates audible indicators, such as a speaker, headphones, or earbuds.

[0099] Electrical device 1200 may include an audio input device 1224 (or a corresponding interface circuitry system, as discussed above). The audio input device 1224 may include any embedded or wired or wirelessly connected device that generates signals representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output). Electrical device 1200 may include a Global Navigation Satellite System (GNSS) device 1218 (or a corresponding interface circuitry system, as discussed above), such as a Global Positioning System (GPS) device. GNSS device 1218 may communicate with satellite-based systems and may determine the geographical location of electrical device 1200 based on information received from one or more GNSS satellites, as is known in the art.

[0100] Electrical device 1200 may include other output devices 1210 (or corresponding interface circuitry systems, as discussed above). Examples of other output devices 1210 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0101] Electrical device 1200 may include other input devices 1220 (or corresponding interface circuitry systems, as discussed above). Examples of other input devices 1220 may include accelerometers, gyroscopes, compasses, image capture devices (e.g., single-field-of-view or stereo cameras), trackballs, touchpads, keyboards, cursor control devices such as mice, styluses, touchscreens, proximity sensors, microphones, barcode readers, quick-response (QR) code readers, electrocardiogram (ECG) sensors, PPG (photoplethysmography) sensors, skin conductance sensors, any other sensors, or radio frequency identification (RFID) readers.

[0102] Electrical device 1200 can have any desired form factor, such as handheld or mobile electrical devices (e.g., cellular phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, 2-in-1 convertible computers, portable all-in-one computers, netbook computers, ultrabook computers, personal digital assistants (PDAs), ultra-mobile personal computers, portable game consoles, etc.), desktop electrical devices, servers, rack-level computing solutions (e.g., blade, tray, or sled computing systems), workstations or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, fixed game consoles, smart TVs, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., computing systems as part of a vehicle, smart home appliance, consumer electronics product or equipment, or manufacturing equipment). In some embodiments, electrical device 1200 can be any other electronic device that processes data. In some embodiments, electrical device 1200 can include multiple discrete physical components. Given the range of devices that electrical device 1200 can represent in various embodiments, in some embodiments, electrical device 1200 may be referred to as a computing device or computing system. Example

[0103] Illustrative examples of the techniques disclosed herein are provided below. Embodiments of the techniques may include any one or more of the examples described below, and any combination thereof.

[0104] Example 1 includes an apparatus comprising: a first photonic integrated circuit (PIC) die, wherein a first plurality of waveguides are defined in the first PIC die; and a second PIC die stacked on the first PIC die, wherein a second plurality of waveguides are defined in the second PIC die, wherein each waveguide of the first plurality of waveguides is optically coupled to each waveguide of the second plurality of waveguides.

[0105] Example 2 includes the subject of Example 1 and also includes an optical bridge, wherein the optical bridge optically couples the first plurality of waveguides to the second plurality of waveguides.

[0106] Example 3 includes the subject matter of any one of Examples 1 and 2, and wherein the optical bridge includes one or more mirrors, wherein the one or more mirrors direct beams from the first plurality of waveguides to the second plurality of waveguides.

[0107] Example 4 includes the subject matter of any one of Examples 1-3, and wherein the optical bridge includes a plurality of direct-write waveguides, wherein the plurality of direct-write waveguides guide light from the first plurality of waveguides to the second plurality of waveguides.

[0108] Example 5 includes the subject matter of any one of Examples 1-4, and wherein the first PIC die includes a first plurality of vertical couplers, wherein each of the first plurality of vertical couplers is used to couple light from each of the first plurality of waveguides from the surface of the first PIC die to each of the plurality of direct-write waveguides, wherein the second PIC die includes a second plurality of vertical couplers, wherein each of the second plurality of vertical couplers is used to couple light from each of the second plurality of waveguides from the surface of the second PIC die to each of the plurality of direct-write waveguides.

[0109] Example 6 includes the subject matter of any one of Examples 1-5, and wherein the optical bridge includes a plurality of photonic wire bonds, wherein the plurality of photonic wire bonds guide light from the first plurality of waveguides to the second plurality of waveguides.

[0110] Example 7 includes the subject matter of any one of Examples 1-6, and wherein each of the plurality of photonic wire bonds is evanescently coupled to each of the first plurality of waveguides and is evanescently coupled to each of the second plurality of waveguides.

[0111] Example 8 includes the subject of any one of Examples 1-7, and wherein the device includes at least four PIC dies stacked on top of each other, wherein the at least four PIC dies include the first PIC die and the second PIC die.

[0112] Example 9 includes the subject matter of any one of Examples 1-8, and also includes an electronic integrated circuit (EIC) die stacked on top of the second PIC die.

[0113] Example 10 includes the subject matter of any one of Examples 1-9, and further includes one or more vias extending from the EIC die to the second PIC die, and one or more vias extending from the second PIC die to the first PIC die.

[0114] Example 11 includes the subject of any one of Examples 1-10, and wherein the second PIC die is hybrid-bonded to the first PIC die.

[0115] Example 12 includes the subject matter of any one of Examples 1-11, and wherein the substrate of the first PIC die is of a different type than the substrate of the second PIC die.

[0116] Example 13 includes an apparatus comprising: a first photonic integrated circuit (PIC) die, wherein a first plurality of waveguides are defined in the first PIC die; a second PIC die stacked on the first PIC die, wherein a second plurality of waveguides are defined in the second PIC die; and a unit for optically coupling the first plurality of waveguides and the second plurality of waveguides.

[0117] Example 14 includes the subject of Example 13, and wherein the unit for optically coupling the first plurality of waveguides and the second plurality of waveguides includes an optical bridge.

[0118] Example 15 includes the subject matter of any one of Examples 13 and 14, and wherein the optical bridge includes one or more mirrors, wherein the one or more mirrors direct beams from the first plurality of waveguides to the second plurality of waveguides.

[0119] Example 16 includes the subject matter of any one of Examples 13-15, and wherein the optical bridge includes a plurality of direct-write waveguides, wherein the plurality of direct-write waveguides guide light from the first plurality of waveguides to the second plurality of waveguides.

[0120] Example 17 includes the subject matter of any one of Examples 13-16, and wherein the first PIC die includes a first plurality of vertical couplers, wherein each of the first plurality of vertical couplers is used to couple light from each of the first plurality of waveguides from the surface of the first PIC die to each of the plurality of direct-write waveguides, wherein the second PIC die includes a second plurality of vertical couplers, wherein each of the second plurality of vertical couplers is used to couple light from each of the second plurality of waveguides from the surface of the second PIC die to each of the plurality of direct-write waveguides.

[0121] Example 18 includes the subject matter of any one of Examples 13-17, and wherein the optical bridge includes a plurality of photonic wire bonds, wherein the plurality of photonic wire bonds guide light from the first plurality of waveguides to the second plurality of waveguides.

[0122] Example 19 includes the subject matter of any one of Examples 13-18, and wherein each of the plurality of photonic wire bonds is evanescently coupled to each of the first plurality of waveguides and is evanescently coupled to each of the second plurality of waveguides.

[0123] Example 20 includes the subject matter of any one of Examples 13-19, and wherein the device includes at least four PIC dies stacked on top of each other, wherein the at least four PIC dies include the first PIC die and the second PIC die.

[0124] Example 21 includes the subject matter of any one of Examples 13-20, and also includes an electronic integrated circuit (EIC) die stacked on top of the second PIC die.

[0125] Example 22 includes the subject matter of any one of Examples 13-21, and further includes one or more vias extending from the EIC die to the second PIC die, and one or more vias extending from the second PIC die to the first PIC die.

[0126] Example 23 includes the subject matter of any one of Examples 13-22, and wherein the second PIC die is mixed-bonded to the first PIC die.

[0127] Example 24 includes the subject matter of any one of Examples 13-23, and wherein the substrate of the first PIC die is of a different type than the substrate of the second PIC die.

[0128] Example 25 includes a method comprising: fabricating a plurality of photonic integrated circuit (PIC) dies, wherein each PIC die in the plurality of PIC dies includes a plurality of waveguides; testing each PIC die in the plurality of PIC dies to determine a plurality of non-faulty PIC dies; stacking two or more of the plurality of non-faulty PIC dies; and optically coupling the plurality of waveguides of the two or more of the plurality of non-faulty PIC dies to each other.

[0129] Example 26 includes the subject matter of Example 25, and wherein two or more of the plurality of non-faulty PIC dies comprise a first PIC die and a second PIC die, wherein optically coupling the plurality of waveguides of the two or more of the plurality of non-faulty PIC dies to each other comprises: optically coupling the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die using an optical bridge.

[0130] Example 27 includes the subject matter of any one of Examples 25 and 26, and wherein the optical bridge includes one or more mirrors, wherein the one or more mirrors direct a beam of light from the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die.

[0131] Example 28 includes the subject matter of any one of Examples 25-27, and wherein the optical bridge includes a plurality of direct-write waveguides, wherein the plurality of direct-write waveguides guide light from the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die.

[0132] Example 29 includes the subject matter of any one of Examples 25-28, and wherein the first PIC die includes a first plurality of vertical couplers, wherein each of the first plurality of vertical couplers is configured to couple light from a plurality of waveguides of the first PIC die from a surface of the first PIC die to a plurality of direct-write waveguides, wherein the second PIC die includes a second plurality of vertical couplers, wherein each of the second plurality of vertical couplers is configured to couple light from a plurality of waveguides of the second PIC die from a surface of the second PIC die to a plurality of direct-write waveguides.

[0133] Example 30 includes the subject matter of any one of Examples 25-29, and wherein the optical bridge includes a plurality of photonic wire bonds, wherein the plurality of photonic wire bonds guide light from the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die.

[0134] Example 31 includes the subject matter of any one of Examples 25-30, and wherein each of the plurality of photonic wire bonds is evanescently coupled to each of the plurality of waveguides of the first PIC die, and is evanescently coupled to each of the plurality of waveguides of the second PIC die.

[0135] Example 32 includes the subject matter of any one of Examples 25-31, and wherein two or more of the plurality of non-faulty PIC dies comprise at least four PIC dies.

[0136] Example 33 includes the subject matter of any one of Examples 25-32, and also includes an electronic integrated circuit (EIC) die stacked on top of the plurality of non-faulty PIC dies.

[0137] Example 34 includes the subject matter of any one of Examples 25-33, and also includes one or more vias extending from the EIC die to the plurality of non-faulty PIC dies.

[0138] Example 35 includes the subject matter of any one of Examples 25-34, and wherein the plurality of non-faulty PIC dies are mixed-bonded together.

[0139] Example 36 includes the subject matter of any one of Examples 25-35, and wherein the plurality of non-faulty PIC dies comprise two or more different types of substrates.

Claims

1. A photonic device, comprising: Circuit board; A photonic integrated circuit (PIC) die located on the circuit board; An electronic integrated circuit (EIC) die, wherein a portion of the PIC die is located between the circuit board and the EIC die; and The conductive interconnect extending between the PIC die and the EIC die, The PIC die includes: A separator is used to separate a first waveguide into a second and a third waveguide. Multiple phase shifters; Modulator; Detector, and Raster.

2. The photonic device according to claim 1, wherein, The PIC die includes a silicon waveguide.

3. The photonic device according to claim 1, wherein, The PIC die includes a silicon waveguide in a silicon oxide layer.

4. The photonic device according to claim 1, wherein, The height of at least one waveguide of the PIC die is between 0.1 micrometers and 10 micrometers.

5. The photonic device according to claim 1, wherein, The PIC die occupies a larger area than the EIC die.

6. The photonic device according to claim 1, wherein, The PIC die operates at wavelengths between 400 nm and 1800 nm.

7. The photonic device according to claim 1, wherein, The PIC die operates at wavelengths in the C-band.

8. The photonic device according to claim 1, wherein, The PIC die includes layers comprising silicon and nitrogen.

9. A photonic device, comprising: Circuit board; A photonic integrated circuit (PIC) die located on the circuit board; as well as An electronic integrated circuit (EIC) die, wherein a portion of the PIC die is located between the circuit board and the EIC die. in: The PIC die includes a first waveguide and a second waveguide. The first waveguide and the second waveguide approach each other in a first plane, the first waveguide follows a first curved path that bends toward the second waveguide, and the second waveguide follows a second curved path that bends toward the first waveguide, until the first waveguide and the second waveguide travel side by side from the first end to the second end of a straight path. After the second end of the straight path, the first waveguide and the second waveguide separate from each other, the first waveguide follows a third curved path away from the curve of the second waveguide, and the second waveguide follows a fourth curved path away from the curve of the first waveguide. The first curved path and the second curved path are symmetrical with respect to the second plane, which is perpendicular to the first plane and parallel to the straight path. The first curved path and the third curved path are symmetrical with respect to a third plane, which is perpendicular to the first plane and also perpendicular to the straight path. The second and fourth curved paths are asymmetrical with respect to the third plane.

10. The photonic device according to claim 9, wherein, The third plane intersects the straight path at the middle of the straight path.

11. The photonic device according to claim 10, wherein, When measuring between the third plane and a fourth plane that is parallel to the third plane and at a non-zero distance from the third plane in a first direction away from the straight path: The length of the fourth curved path is longer than the length of the third curved path.

12. The photonic device according to claim 11, wherein, When measuring between the third plane and a fifth plane that is parallel to the third plane and at a non-zero distance from the third plane in a second direction opposite to the first direction and away from the straight path: The length of the first curved path is the same as the length of the second curved path.

13. The photonic device according to claim 10, wherein, When measuring between the third plane and a fourth plane that is parallel to the third plane and at a non-zero distance from the third plane: The length of the first curved path is the same as the length of the second curved path.

14. The photonic device according to claim 9, wherein, The PIC die also includes a phase shifter.

15. The photonic device according to claim 14, wherein, The phase shifter is located along one of the first waveguides or the second waveguides after the first waveguides and the second waveguides have moved away from each other and separated.

16. The photonic device according to claim 14, wherein, The phase shifter is located along the second waveguide after the first waveguide and the second waveguide have moved away from each other and separated.

17. The photonic device according to claim 9, wherein, The PIC die also includes a modulator.

18. The photonic device according to claim 9, wherein, The PIC die also includes a detector.

19. The photonic device according to claim 9, further comprising: Conductive interconnects are electrically coupled to the PIC die and the EIC die.

20. A photonic device, comprising: Circuit board; A photonic integrated circuit (PIC) die located on the circuit board; An electronic integrated circuit (EIC) die, wherein a portion of the PIC die is located between the circuit board and the EIC die; and The conductive interconnect extending between the PIC die and the EIC die, in: The planar surface of the PIC die includes a first waveguide and a second waveguide. In the first portion of the plane, the first waveguide and the second waveguide bend inward toward each other. In the second portion of the plane, the first waveguide and the second waveguide are parallel to each other. In the third portion of the plane, the first waveguide and the second waveguide bend outwards away from each other. The second portion of the plane is between the first portion of the plane and the third portion of the plane.

21. The photonic device according to claim 20, wherein: In the first portion of the plane, the first waveguide has a first curved portion that bends toward the second waveguide, and the second waveguide has a second curved portion that bends toward the first waveguide.

22. The photonic device according to claim 21, wherein: In the second portion of the plane, the first waveguide has a first straight portion, and the second waveguide has a second straight portion parallel to the first straight portion.

23. The photonic device according to claim 22, wherein: In the third portion of the plane, the first waveguide has a third curved portion away from the curvature of the second waveguide, and the second waveguide has a fourth curved portion away from the curvature of the first waveguide.

24. The photonic device according to claim 23, wherein: The first straight portion lies between the first curved portion and the third curved portion, and The second straight portion lies between the second curved portion and the fourth curved portion.

25. The photonic device according to claim 23, wherein, The fourth curved portion is longer than the third curved portion.

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