vertical die-to-die (d2d) interconnects on glass cores

Abstract

A vertical die-to-die (D2D) interconnect chiplet on a glass core is disclosed. The chiplet consists of two distinct integrated circuit dies, often considered "hot" dies and referred to herein as the top die. The glass core includes a cavity. An active I / O die is located within the cavity to provide D2D communication, its top surface being flush with the top surface of the glass core. Two microbumps of different sizes are used; the first microbump has a smaller pitch (e.g., "fine pitch") and is used to attach the top die to the top surface. The second microbump is larger than the first microbump (e.g., "coarse pitch") and is used to attach the top die to the upper surface of the glass core. Organic components and solder ball backsides can be fabricated on the lower surface of the glass core.

Description

Background Technology

[0001] Semiconductor systems and packaged components that interconnect multiple chiplets require chiplet-to-chiplet communication channels. Typically, chiplet-to-chiplet communication channels implemented as die-to-die (D2D) interconnects result in bandwidth, latency, and power consumption losses. Therefore, improved architectures and methods for D2D interconnects are desired. Attached Figure Description

[0002] Figure 1 This is a simplified cross-sectional view of a vertical D2D interconnect chip on a glass core according to various embodiments.

[0003] Figure 2 This is a simplified cross-sectional diagram of the input / output (I / O) die according to various embodiments.

[0004] Figures 3-6 The various stages of fabricating vertical D2D interconnect chiplets on a glass core according to various embodiments are described.

[0005] Figure 7 The illustration shows an example method for a vertical D2D interconnect chip on a glass core, according to various embodiments.

[0006] Figure 8 The illustration shows additional embodiments supported by the provided methods and architecture.

[0007] Figure 9 It is a top view of a wafer and die that may be included in a microelectronic assembly, according to any of the embodiments disclosed herein.

[0008] Figure 10 This is a simplified cross-sectional side view illustrating an implementation of an on-die integrated circuit that may be included in any of the embodiments disclosed herein.

[0009] Figure 11 It may be a cross-sectional side view of a microelectronic component that may include any of the embodiments disclosed herein.

[0010] Figure 12 It may be a block diagram of an example electrical device that may include any of the embodiments disclosed herein. Detailed Implementation

[0011] Semiconductor systems and packaged components that interconnect multiple chiplets rely on chiplet-to-chiplet communication channels, which are implemented as die-to-die (D2D) interconnects. Technical challenges remain for chiplet-to-chiplet communication across various applications; specifically, D2D communication channels can lead to bandwidth, latency, and power consumption losses.

[0012] Some solutions, known as lateral D2D solutions, place the dies in the same plane, making their communication channels laterally oriented in a cross-sectional view. However, since latency and power consumption are proportionally affected by the length of the communication channel between the die and chiplet, improvements to lateral D2D solutions are desired.

[0013] Some solutions utilize contemporary microbump solder connections or hybrid bonding to achieve vertical interconnects for chiplet-to-chiplet communication; these solutions can be implemented with face-to-face (F2F) and / or face-to-backside (F2B) orientations between two dies / chiplets. However, these solutions are typically implemented using through-silicon vias (TSVs) in silicon interposers or silicon bridges. The anticipated higher switching performance requirements of applications such as artificial intelligence (AI), coupled with scaling needs, will necessitate packaging components implemented on glass-core substrates, thus highlighting the necessity of D2D interconnect solutions that reduce communication channel lengths and are suitable for glass-core substrates.

[0014] The embodiments described herein provide technical solutions to these technical challenges in the form of vertical D2D interconnect chiplets on a glass core. The embodiments arrange dies on a glass core semiconductor substrate in an interleaved, stacked manner to realize vertical D2D interconnect chiplets (dies). Vertical D2D communication channels are shorter than lateral D2D communication channels, thereby improving latency and power consumption. These concepts will be explained in more detail below.

[0015] The following description of exemplary embodiments is in conjunction with the accompanying drawings, in which similar reference numerals denote similar elements. Unless otherwise stated, the drawings are not necessarily to scale but may rely on the spatial orientation and relative positioning of features. As will be appreciated, certain terms such as “ceiling” and “base”, and “upper,” “top,” “lower,” “above,” “below,” “bottom,” and “top” refer to the orientation based on observation of the drawings referenced. Furthermore, terms such as “front,” “rear,” “rear,” “side,” “vertical,” and “horizontal” may describe the orientation and / or position of parts of a component within a consistent but arbitrary frame of reference, which becomes clear by referring to the text describing the component in question and the associated drawings. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0016] As used herein, the term “adjacent” refers to layers or components that are in direct physical contact with each other without any layers or components in between. For example, layer X adjacent to layer Y is a layer that is in direct physical contact with layer Y. Conversely, as used herein, the phrase “on top of” (or, in the context of a first layer or component located on a second layer or component, “below,” “above,” or “next to”) includes (i) a configuration in which the first layer or component is directly and physically attached to the second layer (i.e., adjacent), and (ii) a component and configuration in which the first layer or component is attached (e.g., coupled) to the second layer or component via one or more intermediate layers or components.

[0017] The following detailed description is not intended to limit the application and use of the disclosed technology. It will be apparent that novel embodiments can be implemented without every detail described herein. For brevity, well-known structures and devices are shown in block diagram form to facilitate the description of these structures and devices.

[0018] Figure 1 This is a simplified cross-sectional view of a vertical D2D interconnect chiplet on a glass core. Embodiment 100 depicts three dies (or chipsets) arranged on a glass core having cavities formed therein. First die 102 and third die 104 are vertically D2D interconnected via a second die 106. In various embodiments, first die 102 and third die 104 are integrated circuit dies, and second die 106 is an input / output channel die.

[0019] An interleaved and / or partially stacked arrangement of the first die 102 and the second die 106 is depicted in region 108-1, and a corresponding interleaved / partially stacked arrangement of the third die 104 and the second die 106 is depicted in region 108-2. This interleaved arrangement is an architectural feature that can be visually observed to indicate the practice of the embodiments described herein. The first die 102 and the third die 104 may be referred to as “top dies” because they are attached to the upper surface of the glass core 124. For the same reason, the second die 106 may also be referred to as a “bottom die” (or chiplet).

[0020] Regions 108-1 and 108-2 depict overlapping (or “staggered” or “stacked”) areas between the top dies (first die 102 and third die 104, respectively) and the bottom die 106, and vertical D2D interconnects can be identified in these regions. Although only two top dies and one bottom die are depicted in this exemplary embodiment, those skilled in the art will appreciate that in other embodiments, as can be revealed by the top view, there may be more than two top dies communicating via the bottom die; furthermore, other embodiments may have a second bottom die in a second cavity and support additional top dies in the same manner as described for this example.

[0021] Vertical D2D interconnects are structures implemented in zones 108-1 and 108-2, which include a set of conductive contacts as microbumps 114. In various embodiments, the microbumps 114 have a solder bump pitch (BP) (commonly referred to as "fine pitch") ranging from 25 micrometers to 55 micrometers plus or minus 10%. In some scenarios, the fine pitch BP can be 10 micrometers + / - 10%. For the sake of image simplicity, one microbump 114 is indicated in zone 108-1, and another microbump 114 is indicated in zone 108-2. As will be understood, in a top view, this would be represented by one row of microbumps 114 in zone 108-1 and one row of microbumps 114 in zone 108-2. The length 134 of the overlap or overhang can vary, representing up to about 5-10% of the planar surface area of ​​the top die (where about means plus or minus 10%), and in other embodiments, more than one row of micro-protrusions 114 can be supported in zones 108-1 and 108-2.

[0022] In overlap regions 108-1 and 108-2, the vertical D2D interconnect structure includes corresponding microbump pads, serving as conductive pads, on the top die and the bottom die, for attachment to microbump 114. In various embodiments, the bottom surface of the top die includes at least one microbump pad 112, and the upper surface of the bottom die 106 includes at least one microbump pad 116 for receiving microbump 114. When microbump 114 is attached to microbump pad 112, it provides an electrical path to the electronic circuitry within the top die (third die 104) via internal vias and traces (typically indicated by via 110); similarly, when microbumps are present in region 108-1, they provide an electrical path to the electronic circuitry within the top die (third die 102) via internal vias and traces.

[0023] When microbump 114 is attached to a microbump pad (microbump pad 116) on the upper surface of the bottom die, microbump 114 provides an electrical path to the electronic circuitry within the bottom die 106 via internal vias and traces (typically represented by via 118). (Similarly, when microbump 114 is attached to region 108-1, it provides an electrical path to the electronic circuitry within the bottom die 106 via internal vias and traces.) Finally, microbump 114 attaches the top die to the bottom die, thereby completing one or more electrical pathways between two or more top dies through the bottom die.

[0024] In addition to being attached to the bottom die via a vertical D2D interconnect structure, the two top dies (first die 102 and third die 104) are also attached to the glass core 124, as indicated, using a second set of microbumps 122. The first die 102 extends on the upper surface of the glass layer and includes the arrangement of microbumps 122; the third die 104 extends on the upper surface of the glass layer and includes another arrangement of microbumps 122. As shown, the first die 102 and the third die 104 are positioned adjacent to each other but not abutting, and their lower surfaces are coplanar and face the glass layer or the upper surface of the glass core 124. The second set of microbumps 122 can be arranged with a “coarse pitch,” which refers to a pitch >90 micrometers plus or minus 10%. The second set of microbumps 122 attaches the respective top dies to the upper surface of the glass core 124 and is electrically coupled to the conductive material in the respective glass vias (TGV 132).

[0025] Note that the second die 106 / bottom die is located inside a cavity within the glass core 124, enclosed on the sides and bottom by a cavity formed within the glass core 124. This advantageously provides insulation to the bottom die, in addition to maintaining a profile or Z-height less than that of a solution placing the die on top of a cavityless glass core. The bottom die is positioned such that its upper surface is substantially plane with the upper surface of the glass core 124, as shown. Although the image is drawn in two dimensions, it can be understood that the cavity can be defined in three dimensions such that when the bottom die is placed within the cavity, only its upper surface is exposed at the upper surface of the glass core 124.

[0026] Example 100 depicts an organic building block layer 126 on the lower surface of a glass core 124, and solder balls 128 on the lower surface of the organic building block layer 126. In various embodiments, a bottom die (die 106) provides one or more electrical paths through the glass core 124, through vias and traces in the organic building block layer 126, to one or more solder balls 128 on the bottom surface of the organic building block layer 126. For this purpose, the bottom die 106 may have conductive pads on its lower surface to electrically couple to conductive material in the glass vias (e.g., TGV 132) in the glass core 124.

[0027] In the encapsulation assembly, a molding / underfill (MUF 130) material may surround the top dies 102 and 104 on the upper surface of the glass core 124. A dielectric layer 123 may cover the upper surface of the glass core 124, sandwiched between the top die and the upper surface of the glass core. Alternatively, as shown, some embodiments may attach a dummy silicon block 120 to an exposed portion of the upper surface of the bottom die 106, i.e., where it is not covered by the overhangs of regions 108-1 and 108-2.

[0028] Top dies 102 and 104 may be unpackaged integrated circuit dies and may be alternatively referred to as chips, chiplets, chiplet complexes, or chiplet complexes. While the terms die, chip, and chiplet are used interchangeably, the term chiplet is sometimes used to refer to an integrated circuit die that implements a subset of the functions of a larger integrated circuit component. Chipslets can vary depending on their type / function (e.g., computing, memory, I / O, power management, i.e., controlling the delivery of power and / or providing power to components).

[0029] In various applications, the first die 102 and / or the third die 104 are "hot" dies, such as central processing units (CPUs), graphics processing units (GPUs), etc. The described and illustrated architecture advantageously keeps the upper surface of the hot die uncovered and exposed at the upper surface of the embodiment. The glass core surrounding / enclosing the bottom die 106 provides insulation against the heat generated by the hot die. The dummy block 120 can also be used for heat mitigation purposes.

[0030] The embodiments facilitate cooling of the CPU or hot-top die because they are exposed; this advantageously enables further thermal mitigation techniques and methods (e.g., heat sinks). Embodiments of the vertical D2D interconnect chiplets are described in more detail in the following discussion.

[0031] Go to Figure 2 Further description of the bottom die or I / O die. A simplified cross-sectional view of embodiment 200 of the input / output (I / O) die according to various embodiments. The I / O die is more complex than a simple passive bridge. An active circuit layer 202 covers a silicon substrate 204. The silicon substrate 204 has a plurality of through-silicon vias (TSVs 206). Embodiment 200 of the I / O die has at least one electrical path from microbump pads 116-1 on its upper surface through the active circuit layer 202 to microbump pads 116-2 on its upper surface (return to reference). Figure 1Microbump pad 116-1 corresponds to region 108-1, and microbump pad 116-2 corresponds to region 108-2. Additionally, at least one electrical path extends from the active circuit layer 202 through TSV 206 to the lower surface, where the TSV is attached to copper pad 208 in the insulating material 210. The total Z-height 205 of the I / O die (minus the microbump pads) is indicated. The cavity in the glass core 124 has a Z-depth sufficient to accommodate the Z-height 205.

[0032] The microbump pad 116 may include metal and may include copper. In various embodiments, the TSV 206 has a conductive material therein, such as copper.

[0033] The insulating material 210 can be any dielectric material, such as suitable nitrides or oxides, such as silicon dioxide (SiO2), carbon-doped silicon dioxide (C-doped SiO2, also known as CDO or organosilicon glass, which is a material comprising silicon, oxygen, and carbon), fluorine-doped silicon dioxide (F-doped SiO2, also known as fluorosilicate glass, which is a material comprising fluorine, silicon, and oxygen), and hydrogen-doped silicon dioxide (H-doped SiO2, which is a material comprising silicon, oxygen, and hydrogen). In some embodiments, the dielectric layer comprises a photo-imageable dielectric (PID). In some embodiments, the dielectric layer comprises an Ajinomoto build-up film (commonly referred to as ABF), which is a material comprising an organic resin matrix comprising different types of fillers (e.g., silicon dioxide fillers of different sizes or hollow fillers of different sizes) to control the coefficient of thermal expansion (CTE) and / or electrical properties (e.g., dielectric constant (Dk) and / or dissipation factor (insertion loss) (Df)). In other embodiments, the dielectric material can be any type of epoxy molding compound.

[0034] Figure 3 , Figure 4 , Figure 5 and Figure 6 The fabrication stages of vertical D2D interconnect chiplets on a glass core are described, and Figure 7 The figures illustrate example methods for vertical D2D interconnect chiplets on a glass core according to various embodiments.

[0035] At 702, the glass layer to be the glass core 124 is patterned using TGV 304, and a cavity 306 is formed therein. The glass core 124 / 302 / 402 / 502-1 / 502-2 may comprise a glass layer (as used herein, the glass may be an alkali-free alkaline earth borosilicate glass, such as a glass comprising aluminum, oxygen, boron, silicon, and alkaline earth metals (e.g., beryllium, magnesium, calcium, strontium, barium, radium), such as a glass comprising SiO2, Al2O3, B2O3, and MgO) or a photosensitive glass (photoprocessable or photostructureable glass). In some embodiments, the photosensitive glass may be a lithium silicate-based glass (e.g., a glass comprising lithium, silicon, and oxygen) comprising metal particles, such as gold, silver, or other suitable metal particles. The glass core 124 / 302 / 402 / 502-1 / 502-2 may have a CTE in the range of 2-20 ppm / K. In some embodiments, it is advantageous for glass layer 402 to have a CTE that matches the CTE of the intended die 102 / 104 in the assembled product. In various embodiments, die 102 / 104 is an integrated circuit die (e.g., matching the CTE of silicon) or has a CTE that matches the substrate or PCB.

[0036] In some embodiments, the glass core 124 / 302 / 402 / 502-1 / 502-2 may include a plurality of glass sheets bonded together using an adhesive layer; and may further exhibit a CTE gradient along the Z-axis. In various embodiments, for example, in glass substrates with a Z-height (in the figures) ranging from about ≤1 mm to 5 mm, or in embodiment 300, the glass layer 302 or glass core may have a thickness (Z-height) ranging from about 50 + / - 5 micrometers to about 1.5 mm (+ / - 10%). TGV 304 is a volume in which glass is removed and conductive material is placed, sufficient to enable electrical communication from the upper surface to the lower surface. As illustrated in embodiment 300 of glass layer 302, TGV 304 is substantially perpendicular to the upper surface of glass layer 302. In each embodiment of panel manufacturing, the X length and the corresponding Y length (defined in a top view or plan view) can be within the range of a first length (e.g., X) in the range of 10 mm to 500 mm and a second length (e.g., Y) in the range of 10 mm to 500 mm, with the first length perpendicular to the second length.

[0037] Example 300 depicts a glass core 124 / 204 / 402 having a glass through-hole (TGV 304) formed therein and a cavity 306 formed in the upper surface of the glass core or glass layer 302. The figures reflect a cross-sectional view, where the portion for the cavity is depicted as the width from left to right on the page; however, in a top view, the portion for the cavity is shown as an area. The TGV 304 and cavity 306 are created in the glass core or glass layer 302 by removing a certain amount of glass material. The TGV 304 and cavity 306 can be created by wet etching followed by laser drilling or ablation. The TGV sidewalls and cavity walls are substantially straight (i.e., at 90 degrees, plus or minus 20 degrees, perpendicular to the upper surface of the glass core or glass layer 302; however, in other embodiments, the cavity walls may be 90 degrees plus or minus 10 degrees) and may have an internal taper reflecting the drilling or ablation process for the conductive cavity.

[0038] At 704, as indicated in Example 330, a die attach film (DAF) 332 is applied to the lower surface of the I / O chiplet (e.g., bottom die example 200), and the I / O chiplet is then inserted into cavity 306 such that the DAF 332 attaches the I / O chiplet to the bottom plate of the cavity, as shown.

[0039] At 706, laser removal technology 352 applied from the lower surface of the glass core or glass layer 302 in the TGV is used to remove the DAF in the TGV to expose the Cu pads 208 on the lower surface of the bottom die embodiment 200 at the corresponding TGV, as illustrated in embodiments 350 and 370.

[0040] At 708, Example 370 illustrates the application of copper metallization to fill the TGV vias and form copper pads on the upper and lower surfaces of glass layer 302. At 710, Example 400 illustrates the application of a solder resist or polyimide film lamination across the top of Example 370, thereby producing Example 400. As used herein, when a TGV is “filled” with copper, this means that there is sufficient copper material in the vias of the TGV to provide an electrical path within the TGV from one surface of the glass layer to the opposite surface of the glass layer.

[0041] As illustrated in Embodiment 430, the upper surface of Embodiment 400 is removably attached to the temporary carrier 432. In some manufacturing processes, the temporary carrier 432 supports two face-to-face embodiments (402-1 and 402-2), as shown.

[0042] At 712, organic building blocks 504 are formed on the lower surfaces of glass cores 402-1 and 402-2, respectively. As is known in the art, organic building blocks 504 include one or more dielectric layers with patterned redistribution layer (RDL) conductive traces. The dielectric layers can be suitable dielectrics as described above. The conductive materials used for conductive contacts, RDL traces, and vias can include metals (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof) or other suitable conductive materials.

[0043] After the organic building layer is manufactured, the glass core substrates of Examples 532-1 and 532-2 can be removed from the temporary carrier (as illustrated in Example 530), flipped over again, and have a glass carrier 622 having the organic building layer 504 removably attached to the lower surface of the embodiment (e.g., Example 532-1, as shown in Example 600).

[0044] At position 716, microbumps 122 and 114 described above can be added, and the top die (die 102 and die 104) can be attached to Embodiment 532-1 via microbumps 122 and 114. Optionally, silicon block 120 can be attached to the I / O die. In various embodiments, microbumps 122 and 114 can be subjected to heating (reflow) to complete the attachment of the top die to Embodiment 532-1.

[0045] At 718, molding / underfill (MUF 130) can be applied around the top die on the upper surface of the glass core substrate of Example 532-1, and deposition of conductive contacts (such as solder balls 128 arranged in a ball grid array (BGA)) can be performed to produce Example 630, which is similar to Example 100.

[0046] At or after 718, Embodiment 630 may undergo further assembly in a system package, such as attachment to a printed circuit board (PCB) or motherboard, having a sealant covering Embodiment 630, having a power source electrically coupled to Embodiment 630, etc. Further, overmolding and thermal solutions (not shown) may be added.

[0047] Figure 8Some additional variations can be achieved with respect to the illustrated embodiments. Since the glass core 124 can be fabricated as a single sheet, a sheet with a gradient from the upper surface to the lower surface, or can be fabricated as multiple fused sheets, indicated in a non-limiting example as three layers (e.g., glass layers 302 / 402 / 502-1), where the sheet is a glass layer as described above, those skilled in the art will appreciate that the methods and apparatus described herein support other variations. Embodiment 800 illustrates a glass core 802-1 comprising only one sheet / glass layer, and a cavity 306 extending through the glass core 802-1 (i.e., the cavity is a via). Cu pads 208 on the lower surface of the bottom die embodiment 200 can be directly attached to corresponding conductive pads within the organic building block layer 504. In Embodiment 830, one less sheet or glass layer is present in the glass core 802-2, and the cavity 306 extends through the first glass layer. As described above, an I / O chiplet or die is attached in the cavity to the upper surface of the bottom glass layer using a DAF.

[0048] Therefore, vertical D2D interconnect chiplets on glass cores have been described. The above embodiments can provide functionality conventionally associated with a system-on-a-chip (SoC) in multi-die packages or multi-die assemblies. The above is not an exhaustive list of multi-die assemblies or systems implementing a suspended cache architecture. Those skilled in the art will appreciate that additional multi-die assembly embodiments, not illustrated, are supported based on the accompanying drawings and descriptions included herein. The following drawings and descriptions provide additional context for the aforementioned chips, wafers, and assemblies.

[0049] Figure 9 This is a top view of a wafer 900 and a die 902 that may be included in any of the embodiments disclosed herein. The wafer 900 may be made of a semiconductor material and may include one or more dies 902 formed on the surface of the wafer 900. After the fabrication of the integrated circuit components on the wafer 900 is complete, the wafer 900 may undergo a separation process, in which the dies 902 are separated from each other to provide discrete “chips” or integrated circuit components for packaging. Each die 902 including the integrated circuit components may include one or more transistors (e.g., discussed below). Figure 10The transistors 1040 include some transistors, supporting circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 900 or die 902 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive-bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Additionally, multiple devices may be combined on a single die 902. For example, a memory array formed by multiple memory devices may be formed as a processor unit (e.g., ...) on the same die 902. Figure 12 The processor unit 1202 or other logic configured to store information in a memory device or execute instructions stored in a memory array. In some embodiments, die 902 may be attached to a wafer 900 that includes other dies, and wafer 900 may then be separated, a manufacturing process known as die-to-wafer assembly technology.

[0050] Figure 10 This is a cross-sectional side view of an integrated circuit 1000 that may be included in any of the embodiments disclosed herein. One or more of the integrated circuits 1000 may be included in one or more dies 902 ( Figure 9 The integrated circuit 1000 can be located in a die substrate 1002 (e.g., Figure 9 The wafer 900 is formed on the die (e.g., Figure 9 In the 902 core.

[0051] The die substrate 1002 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type material system or a p-type material system (or a combination of both). The die substrate 1002 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1002 may be formed using alternative materials, which may or may not be combined with silicon. These alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 1002. Although several examples of materials from which the die substrate 1002 can be formed are described herein, any material that can be used as the basis for the integrated circuit 1000 may be used. The die substrate 1002 may be a discrete die (e.g., Figure 9 The 902 die or chip (e.g., Figure 9 The chip 900 is part of it.

[0052] The integrated circuit 1000 may include one or more device layers 1004 disposed on a die substrate 1002. Device layer 1004 may include features of one or more transistors 1040 (e.g., metal oxide semiconductor field-effect transistors, MOSFETs) formed on the die substrate 1002. Transistor 1040 may include, for example, one or more source and / or drain (S / D) regions 1020, a gate 1022 for controlling current flow between S / D regions 1020, and one or more S / D contacts 1024 for routing electrical signals to and / or from the S / D regions 1020.

[0053] The gate 1022 may be formed of at least two layers (a gate dielectric and a gate electrode). The gate dielectric may comprise a stack of one or more layers. One or more layers may comprise silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may comprise elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve the quality of the gate dielectric when a high-k material is used.

[0054] The gate electrode may be formed on the gate dielectric and, depending on whether the transistor 1040 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NOMS) transistor, may include at least one p-type work function metal or an n-type work function metal. In some implementations, the gate electrode may include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as barrier layers.

[0055] For PMOS transistors, metals that can be used as the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that can be used as the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0056] In some embodiments, when viewed as a cross-section of transistor 1040 along the source-channel-drain direction, the gate electrode may include a U-shaped structure and two sidewall portions, the U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1002, and the two sidewall portions substantially perpendicular to the top surface of die substrate 1002. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 1002 and does not include a sidewall portion substantially perpendicular to the top surface of die substrate 1002. In other embodiments, the gate electrode may include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0057] In some embodiments, pairs of sidewall spacers may be formed on opposite sides of the gate stack to be positioned on both sides of the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and include deposition and etching processes. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0058] The S / D region 1020 may be formed within the die substrate 1002, adjacent to the gate 1022 of each transistor 1040. For example, the S / D region 1020 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into the die substrate 1002 to form the S / D region 1020. An annealing process to activate the dopant and further diffuse it into the die substrate 1002 may follow the ion implantation process. In the latter process, the die substrate 1002 may be etched first to form a recess at the location of the S / D region 1020. An epitaxial deposition process may then be performed to fill the recess using the material used to fabricate the S / D region 1020. In some implementations, the S / D region 1020 may be fabricated using a silicon alloy (such as silicon germanium or silicon carbide). In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopant such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1020 may be formed using one or more alternative semiconductor materials such as germanium or group III-V materials or alloys. In further embodiments, the S / D region 1020 may be formed using one or more layers of metal and / or layers of metal alloys.

[0059] Electrical signals such as power signals and / or input / output (I / O) signals can be transmitted through one or more interconnect layers disposed on device layer 1004. Figure 10 The interconnect layers (illustrated as interconnect layers 1006-1010) are routed to devices (e.g., transistor 1040) in device layer 1004, and / or routed from devices (e.g., transistor 1040) in device layer 1004. For example, conductive features of device layer 1004 (e.g., gate 1022 and S / D contact 1024) may be electrically coupled to interconnect structures 1028 of interconnect layers 1006-1010. One or more interconnect layers 1006-1010 may form a metallization stack (also referred to as an “ILD” stack) 1019 of integrated circuit 1000.

[0060] Interconnect structure 1028 can be arranged within interconnect layers 1006-1010 to route electrical signals according to a wide range of designs; specifically, the arrangement is not limited to... Figure 10 The specific configuration of the interconnect structure 1028 depicted. Although in Figure 10 The disclosure depicts a specific number of interconnect layers 1006-1010, but embodiments of the present disclosure include integrated circuits having more or fewer interconnect layers than depicted.

[0061] In some embodiments, the interconnect structure 1028 may include lines 1028a and / or vias 1028b filled with a conductive material such as a metal. Lines 1028a may be arranged to route electrical signals in a direction substantially parallel to a plane of the die substrate 1002 on which the device layer 1004 is formed. For example, lines 1028a may route electrical signals in the direction of entering and leaving a page, and / or in the direction of crossing a page. Vias 1028b may be arranged to route electrical signals in a direction substantially perpendicular to a plane of the die substrate 1002 on which the device layer 1004 is formed. In some embodiments, vias 1028b may electrically couple lines 1028a of different interconnect layers 1006-1010 together.

[0062] Interconnect layers 1006-1010 may include dielectric material 1026 disposed between interconnect structures 1028, such as... Figure 10 As shown in the figure. In some embodiments, the dielectric material 1026 disposed between interconnect structures 1028 in different interconnect layers 1006-1010 may have different compositions; in other embodiments, the composition of the dielectric material 1026 between different interconnect layers 1006-1010 may be the same. Device layer 1004 may also include dielectric material 1026 disposed between transistor 1040 and the bottom layer of metallization stack. The dielectric material 1026 included in device layer 1004 may have a different composition than the dielectric material 1026 included in interconnect layers 1006-1010; in other embodiments, the composition of the dielectric material 1026 in device layer 1004 may be the same as the dielectric material 1026 included in any of the interconnect layers 1006-1010.

[0063] A first interconnect layer 1006 (referred to as metal 1 or "M1") may be formed directly on device layer 1004. In some embodiments, the first interconnect layer 1006 may include a line 1028a and / or a via 1028b, as shown. The line 1028a of the first interconnect layer 1006 may be coupled to a contact portion (e.g., S / D contact 1024) of device layer 1004. The via 1028b of the first interconnect layer 1006 may be coupled to the line 1028a of the second interconnect layer 1008.

[0064] The second interconnect layer 1008 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1006. In some embodiments, the second interconnect layer 1008 may include vias 1028b to couple lines of the interconnect structure 1028 of the second interconnect layer 1008 to lines 1028a of the third interconnect layer 1010. Although for clarity, lines 1028a and vias 1028b are structurally depicted as lines within separate interconnect layers, in some embodiments, lines 1028a and vias 1028b may be structurally and / or materially adjacent (e.g., simultaneously filled during a dual damascene process).

[0065] The third interconnect layer 1010 (referred to as metal 3 or "M3") (and, if necessary, additional interconnect layers) may be sequentially formed on the second interconnect layer 1008 according to similar techniques and configurations described in conjunction with the second interconnect layer 1008 or the first interconnect layer 1006. In some embodiments, the "higher" (i.e., further away from device layer 1004) interconnect layers in the metallization stack 1019 of the integrated circuit 1000 may be thicker than the lower interconnect layers in the metallization stack 1019, wherein the lines 1028a and vias 1028b in the higher interconnect layers are thicker than the lines 1028a and vias 1028b in the lower interconnect layers.

[0066] The integrated circuit 1000 may include a solder resist 1034 (e.g., polyimide or a similar material) formed on interconnect layers 1006-1010 and one or more conductive contacts 1036. Figure 10 In the illustration, conductive contact 1036 is shown in the form of a bonding pad. Conductive contact 1036 may be electrically coupled to interconnect structure 1028 and configured to route electrical signals from transistor(s) 1040 to an external device. For example, solder bonds may be formed on one or more conductive contacts 1036 to mechanically and / or electrically couple an integrated circuit die including integrated circuit 1000 to another component (e.g., a printed circuit board). Integrated circuit 1000 may include additional or alternative structures for routing electrical signals from interconnect layers 1006-1010; for example, conductive contact 1036 may include other similar features (e.g., pillars) for routing electrical signals to external components.

[0067] In some embodiments where the integrated circuit 1000 is a dual-sided die, the integrated circuit 1000 may include another metallization stack (not shown) on the opposite side of device layer(s) 1004. This metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 1006-1010 to provide a conductive path (e.g., including conductive lines and vias) between device layer(s) 1004 and additional conductive contacts (not shown) on the opposite side of the integrated circuit 1000, away from conductive contact 1036.

[0068] In other embodiments where the integrated circuit 1000 is a dual-sided die, the integrated circuit 1000 may include one or more through-silicon vias (TSVs) through the die substrate 1002; these TSVs may contact one or more device layers 1004 and may provide a conductive path between the one or more device layers and additional conductive contacts (not shown) on the opposite side of the integrated circuit 1000, away from the conductive contact 1036. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the opposite side of the integrated circuit 1000, away from the conductive contact 1036, to the transistor 1040 and any other components integrated into the integrated circuit 1000 die, and the metallization stack 1019 may be used to route I / O signals from the conductive contact 1036 to the transistor 1040 and any other components integrated into the integrated circuit 1000 die.

[0069] Multiple integrated circuits 1000 may be connected to one or more TSV stacks of devices in a stack, providing connections between one device in the stack and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM die may provide connections between the respective HBM and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine-pitch solder bumps (microbumps).

[0070] Figure 11 This is a cross-sectional side view of a microelectronic assembly 1100, which may include any of the embodiments disclosed herein. The microelectronic assembly 1100 includes a plurality of integrated circuit components disposed on a circuit board 1102 (which may be a motherboard, system board, host board, etc.). The microelectronic assembly 1100 may include components disposed on a first surface 1140 and an opposing second surface 1142 of the circuit board 1102; generally, components may be disposed on one or both of surfaces 1140 and 1142.

[0071] In some embodiments, circuit board 1102 may be a printed circuit board (PCB) comprising multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1102 (optionally, in conjunction with other metal layers). In other embodiments, circuit board 1102 may be a non-PCB substrate. Figure 11 The microelectronic component 1100 illustrated in the figure includes a package-on-interposer (PAI) structure 1136, which is coupled to a first side 1440 of a circuit board 1102 via a coupling member 1116. The coupling member 1116 can electrically and mechanically couple the PAI structure 1136 to the circuit board 1102 and may include solder balls (such as...). Figure 11 The following are included: pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of the socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0072] The on-intermediate package structure 1136 may include an integrated circuit component 1120, which is coupled to the intermediate layer 1104 via a coupling member 1118. The coupling member 1118 may take any suitable form for the application, such as the form discussed above with reference to coupling member 1116. Although Figure 11 A single integrated circuit component 1120 is shown, but multiple integrated circuit components can be coupled to the interposer 1104; in fact, additional interposers can be coupled to the interposer 1104. The interposer 1104 can provide an intermediate substrate for bridging the circuit board 1102 and the integrated circuit component 1120.

[0073] Integrated circuit component 1120 may include one or more integrated circuit dies (e.g., Figure 9 902 core, Figure 10 Packaged or unpackaged integrated circuit components (1000) and / or one or more other suitable components.

[0074] The unpackaged integrated circuit component 1120 includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1104. In embodiments where the integrated circuit component 1120 includes multiple integrated circuit dies, these dies may be of the same type (homogeneous multi-die integrated circuit component) or of two or more different types (heterogeneous multi-die integrated circuit component). In addition to including one or more processor units, the integrated circuit component 1120 may also include additional components such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may reside on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die including the processor unit. These separate integrated circuit dies may be referred to as “chiplets.” In embodiments where the integrated circuit component includes multiple integrated circuit dies, interconnections between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate, or a combination of the foregoing. Packaged multi-chip integrated circuit components can be referred to as multi-chip packages (MCPs) or multi-chip modules (MCMs).

[0075] Intermediate layer 1104 can extend connections to wider spacing or rewire connections into different connections. For example, intermediate layer 1104 can couple integrated circuit component 1120 to the collection of ball grid array (BGA) conductive contacts of coupling component 1116 to couple to circuit board 1102. Figure 11 In the embodiment illustrated, integrated circuit component 1120 and circuit board 1102 are attached to opposite sides of interposer 1104; in other embodiments, integrated circuit component 1120 and circuit board 1102 may be attached to the same side of interposer 1104. In some embodiments, three or more components may be interconnected by means of interposer 1104.

[0076] In some embodiments, the interposer 1104 may be formed as a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 1104 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the interposer 1104 may be formed of an alternative rigid or flexible material, including the same materials described above for use in semiconductor substrates (such as silicon, germanium, and other Group III-V and Group IV materials). Intermediate layer 1104 may include metal interconnects 1108 and vias 1110, including but not limited to a through hole via 1110-1 (extending from the first side 1150 of the intermediate layer 1104 to the second side 1154 of the intermediate layer 1104), a blind via 1110-2 (extending from the first side 1150 or the second side 1154 of the intermediate layer 1104 to an intermediate metal layer), and a buried via 1110-3 (connecting to an inner metal layer).

[0077] In some embodiments, the interposer 1104 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer can connect portions on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, the interposer 1104 including the silicon interposer may further include one or more routing layers for routing the connections on the first side of the interposer 1104 to an opposite second side of the interposer 1104.

[0078] Intermediate layer 1104 may further include embedded devices 1114, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices, may also be formed on intermediate layer 1104. The on-intermediate package structure 1136 may take the form of any structure known in the art for on-intermediate package structures.

[0079] Integrated circuit assembly 1100 may include integrated circuit component 1124, which is coupled to a first surface 1140 of circuit board 1102 via coupling component 1122. Coupling component 1122 may take the form of any embodiment discussed above with reference to coupling component 1116, and integrated circuit component 1124 may take the form of any embodiment discussed above with reference to integrated circuit component 1120.

[0080] Figure 11 The integrated circuit assembly 1100 illustrated in the figure includes a package-on-package structure 1134 coupled to a second side 1142 of a circuit board 1102 via a coupling member 1128. The package-on-package structure 1134 may include integrated circuit components 1126 and 1132 coupled together via a coupling member 1130, such that integrated circuit component 1126 is disposed between the circuit board 1102 and integrated circuit component 1132. Coupling members 1128 and 1130 may take the form of any embodiment of the coupling member 1116 discussed above, and integrated circuit components 1126 and 1132 may take the form of any embodiment of the integrated circuit component 1120 discussed above. The package-on-package structure 1134 may be configured according to any package-on-package structure known in the art.

[0081] Figure 12 This may be a block diagram of an example electrical device 1200 that may include one or more embodiments disclosed herein. For example, any suitable component of the electrical device 1200 may include one or more of the following: microelectronic component 1100, integrated circuit component 1120, integrated circuit 1000, integrated circuit die 902, or a structure disclosed herein. Several components in Figure 12 The components are illustrated as being included in electrical device 1200, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in electrical device 1200 may be attached to one or more motherboards, motherboards, printed circuit boards, or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-a-chip (SoC) die. In various embodiments, electrical device 3000 is enclosed by a housing or integrated with a housing.

[0082] Additionally, in various embodiments, electrical equipment 1200 may not include... Figure 12The electrical device 1200 may include one or more of the components shown in the diagram, but may include interface circuitry for coupling to one or more components. For example, the electrical device 1200 may not include display device 1206, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 1206 may be coupled. In another set of examples, the electrical device 1200 may not include audio input device 1224 or audio output device 1208, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which audio input device 1224 or audio output device 1208 may be coupled.

[0083] Electrical device 1200 may include one or more processor units 1202 (e.g., one or more processor cells). As used herein, the terms “processor cell,” “processing unit,” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processor unit 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, the processor unit can be called an XPU (or xPU).

[0084] Electrical device 1200 may include memory 1204, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or hard drives. In some embodiments, memory 1204 may include memory located on the same integrated circuit die as processor unit 1202. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0085] In some embodiments, electrical device 1200 may include one or more processor units 1202 that are heterogeneous or asymmetric to another processor unit 1202 in electrical device 1200. Various differences may exist between processor units 1202 in the system in terms of a range of metrics including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, etc. These differences can be effectively manifested in themselves as asymmetry and heterogeneity between processor units 1202 in electrical device 1200.

[0086] In some embodiments, electrical device 1200 may include communication component 1212 (e.g., one or more communication components). For example, communication component 1212 may manage wireless communication for transmitting data to and from electrical device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that may use modulated electromagnetic radiation to enable data transmission through a non-solid-state medium. The term "wireless" does not imply that the associated device does not contain any wires, but in some embodiments, the associated device may not contain any wires.

[0087] Communication component 1212 can implement any of several wireless standards or protocols, including but not limited to: Institute for Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision); Long-Term Evolution (LTE) projects and any modifications, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Boardband (UMB) projects (also known as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compliant with IEEE 802.16 are generally referred to as WiMAX networks, an acronym for Global Microwave Access Interoperability, and are certification marks used for products that have passed compliance and interoperability testing to the IEEE 802.16 standard. Communication component 1212 can operate under Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication component 1212 can also operate under Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTERAN (E-UTRAN).Communication component 1212 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and higher generations. In other embodiments, communication component 1212 may operate according to other wireless protocols. Electrical device 1200 may include antenna 1222 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0088] In some embodiments, communication component 1212 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet standard). As described above, communication component 1212 may include multiple communication components. For example, a first communication component 1212 may be dedicated to shorter-range wireless communications (such as Wi-Fi or Bluetooth), and a second communication component 1212 may be dedicated to longer-range wireless communications (such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others). In some embodiments, the first communication component 1212 may be dedicated to wireless communications, and the second communication component 1212 may be dedicated to wired communications.

[0089] Electrical device 1200 may include battery / power circuit system 1214. Battery / power circuit system 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of electrical device 1200 to a power source (e.g., AC line power) separate from electrical device 1200.

[0090] Electrical device 1200 may include display device 1206 (or a corresponding interface circuit system, as discussed above). Display device 1206 may include one or more embedded, or wired or wirelessly connected external visual indicators, such as head-up displays, computer monitors, projectors, touch screen displays, liquid crystal displays (LCDs), light-emitting diode displays, or flat panel displays.

[0091] Electrical device 1200 may include audio output device 1208 (or a corresponding interface circuit system, as discussed above). Audio output device 1208 may include any embedded, wired or wirelessly connected external device that generates auditory indicators, such as a speaker, headphones, or earbuds.

[0092] Electrical device 1200 may include audio input device 1224 (or a corresponding interface circuitry system, as discussed above). Audio input device 1224 may include any embedded, wired or wirelessly connected device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a musical instrument digital interface (MIDI) output). Electrical device 1200 may include Global Navigation Satellite System (GNSS) device 1218 (or a corresponding interface circuitry system, as discussed above), such as a Global Positioning System (GPS) device. GNSS device 1218 may communicate with satellite-based systems and may determine the geographical location of electrical device 1200 based on information received from one or more GNSS satellites, as is known in the art.

[0093] Electrical device 1200 may include another output device 1210 (or a corresponding interface circuit system, as discussed above). Examples of other output devices 1210 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0094] Electrical device 1200 may include another input device 1220 (or a corresponding interface circuit system, as discussed above). Examples of other input devices 1220 may include accelerometers, gyroscopes, compasses, image capture devices (e.g., single-field-of-view or stereo cameras), trackballs, trackpads, touchpads, keyboards, cursor control devices (such as mice), styluses, touchscreens, proximity sensors, microphones, barcode readers, Quick Response (QR) code readers, electrocardiogram (ECG) sensors, photoplethysmogram (PPG) sensors, electrodermal response sensors, any other sensors, or radio frequency identification (RFID) readers.

[0095] Electrical device 1200 may have any desired form factor, such as handheld or mobile electrical devices (e.g., cellular phones, smartphones, mobile internet devices, music players, tablets, laptops, 2-in-1 convertible computers, portable all-in-one computers, netbooks, ultrabooks, personal digital assistants (PDAs), ultra-mobile personal computers, portable game consoles, etc.), desktop electrical devices, servers, rack-mount computing solutions (blade, tray, or skid-mount computing systems), workstations or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, stationary game consoles, smart TVs, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., computing systems as part of vehicles, smart home appliances, consumer electronics products or equipment, or manufacturing equipment). In some embodiments, electrical device 1200 may be any other electronic device that processes data. In some embodiments, electrical device 1200 may include multiple discrete physical components. Given the range of devices that the electrical device 1200 may present in various embodiments, in some embodiments the electrical device 1200 may be referred to as a computing device or computing system.

[0096] While at least one embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the disclosed embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing the disclosed embodiments. Various changes may be made to the function and arrangement of the elements without departing from the scope of this disclosure as set forth in the appended claims and their legal equivalents.

[0097] As used herein, the term “electronic component” can refer to active electronic circuitry (e.g., processing unit, memory, storage device, FET) or passive electronic circuitry (e.g., resistor, inductor, capacitor).

[0098] As used herein, the term "integrated circuit component" can refer to an electronic component disposed on semiconductor material to perform a function. An integrated circuit (IC) component may include one or more of any computing system components described or referenced herein, or any other computing system components, such as processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controllers, memory or network interface controllers, and may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0099] Non-limiting examples of unpackaged integrated circuit components include a single monolithic integrated circuit die; the die may include solder bumps on contacts attached to the die. When present on the die, solder bumps or other conductive contacts allow the die to be directly attached to a printed circuit board (PCB) or other substrate.

[0100] Non-limiting examples of packaged integrated circuit components include one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit die and the package substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. Typically, the housing includes an integrated heat spreader (IHS); the packaged integrated circuit component typically has bumps, leads, or pins attached to the package substrate (either directly or by wires with bumps, leads, or pins attached to the package substrate) for attaching the packaged integrated circuit component to a printed circuit board (or motherboard or substrate) or another component.

[0101] As used herein, phrases such as “embodiment,” “various embodiments,” “some embodiments,” etc., indicate that some embodiments may have some, all, or no features of those described for other embodiments. “First,” “second,” “third,” etc., describe a common object and indicate different instances of the same object mentioned; unless specifically stated otherwise, they do not imply a given sequence in time or space, order, or any other manner. According to patent application terminology, “connected” indicates that elements are in direct physical or electrical contact with each other, and “coupled” indicates that elements cooperate or interact with each other; coupled elements may or may not be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” etc., are used synonymously to indicate non-exclusive inclusion.

[0102] As used in this application and in the claims, a list of items joined by the terms "at least one of..." or "one or more of..." may refer to any combination of the listed items. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C. Similarly, the phrase "one or more of A, B, and C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0103] As used in this application and claims, the phrase “...individuals” or “...each” followed by a list of items described or stated to have features, characteristics, etc., means that all items in the list have the described or stated features, characteristics, etc. For example, the phrase “individuals of A, B or C include sidewalls” or “A, B or C each include sidewalls” means that A includes sidewalls, B includes sidewalls, and C includes sidewalls.

[0104] The operational theories, scientific principles, or other theoretical descriptions of the apparatuses or methods described herein are provided for the purpose of better understanding and are not intended to limit the scope. The apparatuses and methods in the appended claims are not limited to those that operate in a manner described by such operational theories.

[0105] The following examples relate to additional embodiments of the techniques disclosed herein.

[0106] Example

[0107] Example 1 is an apparatus comprising: a first die including an upper surface having a first set of first conductive pads in a first region and a second set of first conductive pads in a second region; a second die in the first region; a third die in the second region; a plurality of first conductive contacts for attaching the second die in the first region at the first conductive pads and for attaching the third die in the second region at the second set of conductive pads; a glass layer having a plurality of glass vias and a cavity formed in a top surface; wherein the first die is in the cavity; wherein the second die extends on the top surface and is attached to the top surface using a first set of second conductive contacts; and wherein the third die extends on the top surface and is attached to the top surface using a second set of second conductive contacts; wherein the plurality of first conductive contacts have a smaller spacing than the second conductive contacts.

[0108] Example 2 includes the subject of Example 1, wherein the first die is an input / output die that includes an active circuit layer on a silicon substrate.

[0109] Example 3 includes the subject of Example 1 or Example 2, wherein the second die is an integrated circuit die and the third die is another integrated circuit die.

[0110] Example 4 includes the subject of Example 1 or Example 2, wherein the second die or the third die is a central processing unit or a graphics processing unit.

[0111] Example 5 includes the subject matter of any one of Examples 1 or 2-4, wherein a plurality of first conductive contacts include solder bumps defined by a first pitch ranging from 25 micrometers to 55 micrometers + / - 10%.

[0112] Example 6 includes the subject of Example 5, wherein the second conductive contact also includes solder and is defined by a second pitch of >90 micrometers + / - 10%.

[0113] Example 7 includes the subject matter of any one of Examples 1 or 2-6, and further includes an organically constructed layer on the bottom surface of the glass layer, the organically constructed layer including a dielectric material having one or more conductive traces therein.

[0114] Example 8 includes the subject matter of Example 7, and further includes: a plurality of solder balls on the lower surface of the organic building layer; and at least one electrical path from the first die to the solder balls.

[0115] Example 9 includes the subject of Example 8, and further includes a printed circuit board attached to a plurality of solder balls.

[0116] Example 10 includes the subject of Example 8, and further includes a molding and underfill material surrounding a second and a third die on the upper surface of the glass layer.

[0117] Example 11 includes the subject matter of any one of Examples 1 or 2-10, wherein the thickness of the glass layer is in the range of 20 micrometers + / - 5 micrometers to 1.5 millimeters + / - 5 micrometers.

[0118] Example 12 includes the subject of Example 2, wherein: the silicon in the input / output die includes through-silicon vias (TSVs); and at least some of the TSVs are used to electrically couple an active circuit layer to the bottom surface of a glass layer.

[0119] Example 13 is a multi-die assembly comprising: a glass layer having a plurality of glass vias extending from a top surface to a bottom surface, and a cavity formed in the top surface; a first die in the cavity, the first die including an upper surface having a plurality of first conductive pads arranged in a first group in a first region and in a second group in a second region; a second die on the top surface of the glass layer and in the first region; a third die on the top surface of the glass layer and in the second region; a plurality of first conductive contacts, wherein some of the first conductive pads are electrically coupled to the second die via the first conductive contacts in the first region, and the remaining first conductive pads are electrically coupled to the third die in the second region via another first conductive contact; wherein the second die is attached to the top surface using a first group of second conductive contacts; wherein the third die is attached to the top surface using a second group of second conductive contacts; wherein the plurality of first conductive contacts have a smaller spacing than the second conductive contacts; and an organic building layer on the bottom surface.

[0120] Example 14 includes the subject matter of Example 13, and further includes: a plurality of solder balls on the lower surface of the organic building layer; and at least one electrical path from the second die or the third die to the solder balls.

[0121] Example 15 includes the subject of Example 13, wherein the first die is an input / output die that includes an active circuit layer on a silicon substrate.

[0122] Example 16 includes the subject of Example 13, wherein the second die or the third die is a central processing unit or a graphics processing unit.

[0123] Example 17 includes the subject matter of Example 13, wherein a plurality of first conductive contacts include solder bumps defined by a first pitch in the range of 25 micrometers to 55 micrometers + / - 10%, and second conductive contacts also include solder and are defined by a second pitch of >90 micrometers + / - 10%.

[0124] Example 18 is a method comprising: fabricating a glass substrate including a plurality of through-glass vias (TGVs) and a cavity in an upper surface; attaching an active input / output (I / O) die to a base plate of the cavity, wherein the top surface of the I / O die is exposed at the upper surface; filling the TGVs with copper; attaching a first integrated circuit die to the upper surface and a first region on the top surface of the I / O die; and attaching a second integrated circuit die to the upper surface and a second region on the top surface of the I / O die.

[0125] Example 19 includes the subject matter of Example 18, and further includes: attaching an active input / output die to a base plate of a cavity using a die attachment film (DAF); and laser-removing the DAF from the TGV before filling the TGV with copper.

[0126] Example 20 includes the subject matter of Example 19, further comprising: attaching a first integrated circuit die and a second integrated circuit die to an upper surface with a first pitch of solder bumps; and attaching the first integrated circuit die and the second integrated circuit die to the top surface of an I / O die with a second pitch of solder bumps smaller than the first pitch.

Claims

1. An apparatus comprising: A first die, the first die including an upper surface having a first set of first conductive pads in a first region and a second set of first conductive pads in a second region; The second die in the first region; The third die in the second region; A plurality of first conductive contacts are used for attaching the second die in the first region at the first conductive pad, and for attaching the third die in the second region at the second set of conductive pads; A glass layer having a plurality of glass through-holes and a cavity formed in the top surface; The first core is located in the cavity; The second die extends on the top surface and is attached to the top surface by a first set of second conductive contacts; and The third die extends on the top surface and is attached to the top surface by means of a second set of second conductive contacts; The plurality of first conductive contacts have a smaller spacing than the second conductive contacts.

2. The apparatus according to claim 1, wherein, The first die is an input / output die that includes an active circuit layer on a silicon substrate.

3. The apparatus according to claim 2, wherein: The silicon substrate in the input / output die includes a through-silicon via (TSV); and At least some of the TSVs are used to electrically couple the active circuit layer to the bottom surface of the glass layer.

4. The apparatus according to claim 1, wherein, The second die is an integrated circuit die, and the third die is another integrated circuit die.

5. The apparatus according to claim 1, wherein, The second die or the third die is a central processing unit or a graphics processing unit.

6. The apparatus according to claim 1, wherein, The plurality of first conductive contacts include solder bumps defined by a first spacing in the range of 25 micrometers to 55 micrometers + / - 10%.

7. The apparatus according to claim 6, wherein, The second conductive contact also includes solder and is defined by a second pitch of >90 micrometers + / - 10%.

8. The apparatus according to any one of claims 1-7, further comprising an organic building layer on the bottom surface of the glass layer, the organic building layer comprising a dielectric material having one or more conductive traces therein.

9. The apparatus according to claim 8, further comprising: Multiple solder balls on the lower surface of the organic building block layer; as well as At least one electrical path from the first die to the solder ball.

10. The apparatus of claim 9, further comprising a printed circuit board attached to the plurality of solder balls.

11. The apparatus of claim 9, further comprising molding and underfill material surrounding the second and third dies on the upper surface of the glass layer.

12. The apparatus according to any one of claims 1-7, wherein, The thickness of the glass layer is in the range of 20 micrometers + / - 5 micrometers to 1.5 millimeters + / - 5 micrometers.

13. A multi-chip assembly, comprising: A glass layer having a plurality of glass through-holes extending from a top surface to a bottom surface, and a cavity formed in the top surface; The first die in the cavity includes an upper surface having a plurality of first conductive pads arranged in a first group in a first region and in a second group in a second region. The second die on the top surface of the glass layer and in the first region; The third die on the top surface of the glass layer and in the second region; A plurality of first conductive contacts, wherein some of the plurality of first conductive pads are electrically coupled to the second die via a first conductive contact in the first region, and the remaining of the plurality of first conductive pads are electrically coupled to the third die in the second region via another first conductive contact; The second die is attached to the top surface using a first set of second conductive contacts; The third die is attached to the top surface using a second set of second conductive contacts; Wherein, the plurality of first conductive contacts have a smaller spacing than the second conductive contacts; and Organic building blocks on the bottom surface.

14. The multi-die assembly of claim 13, further comprising: Multiple solder balls on the lower surface of the organic building block layer; as well as At least one electrical path from the second die or the third die to the solder ball.

15. The multi-chip assembly according to claim 13, wherein, The first die is an input / output die that includes an active circuit layer on a silicon substrate.

16. The multi-chip assembly according to any one of claims 13-15, wherein, The second die or the third die is a central processing unit or a graphics processing unit.

17. The multi-chip assembly according to any one of claims 13-15, wherein, The plurality of first conductive contacts include solder bumps defined by a first pitch in the range of 25 micrometers to 55 micrometers + / - 10%, and the second conductive contacts also include solder and are defined by a second pitch of >90 micrometers + / - 10%.

18. A method comprising: The glass substrate is fabricated to include multiple glass through-holes (TGVs) and a cavity in the upper surface; An active input / output (I / O) die is attached to the bottom plate of the cavity, wherein the top surface of the I / O die is exposed at the upper surface; The TGV is filled with copper. The first integrated circuit die is attached to the upper surface and the first region of the top surface of the I / O die; as well as The second integrated circuit die is attached to the upper surface and the second region of the top surface of the I / O die.

19. The method of claim 18, further comprising: The active input / output die is attached to the base plate of the cavity using a die attachment film (DAF). as well as The DAF is laser-removed from the TGV before it is filled with copper.

20. The method of claim 19, further comprising: The first integrated circuit die and the second integrated circuit die are attached to the upper surface with a first spacing of solder bumps; as well as The first integrated circuit die and the second integrated circuit die are attached to the top surface of the I / O die with a second spacing of solder protrusion smaller than the first spacing.

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