A multi-core packaging structure and its fabrication method

Abstract

This invention provides a multi-chip packaging structure and manufacturing method, relating to the semiconductor field, comprising: N laterally arranged chip combinations, where N is an integer greater than 1, each chip combination including two back-to-back stacked chips; an interconnect mechanism including a stacking portion disposed between the chip combinations and a top RDL and a bottom RDL disposed above and below the stacking portion, wherein the top RDL and the bottom RDL are interconnected through the stacking portion, and the chips in each chip combination are bonded to the top RDL and the bottom RDL; a transition plate disposed below the interconnect mechanism; and a substrate disposed below the transition plate and bonded to the transition plate with solder balls. This application, through improvements to the interconnect mechanism and the transition plate, not only avoids the high threshold design of traditional interconnect schemes that require pre-reserved through-silicon vias inside the chips, but also utilizes the top RDL and bottom RDL of the interconnect mechanism, as well as the external stacking portion, to achieve efficient expansion of lateral interconnects between chips.

Description

Technical Field

[0001] This invention relates to semiconductor packaging, and particularly to a multi-chip packaging structure and manufacturing method. Background Technology

[0002] Chiplet packaging, as a core approach to continuing Moore's Law, integrates functional chips from different process nodes, such as computing, storage, and I / O, into a single package, breaking through the physical limits of single-chip solutions and becoming a fundamental technology supporting cutting-edge fields such as AI and high-performance computing. Its core competitiveness lies in achieving high-density, low-loss, bidirectional interconnections between chips and between chips and the substrate through advanced packaging. However, existing interconnection solutions have significant bottlenecks in performance, cost, and reliability, hindering the large-scale application of the technology.

[0003] Existing interconnect solutions each have limitations, making it difficult to balance density, cost, and functional requirements. Organic RDL interconnects rely on surface redistribution layers, with line widths and spacing typically ≥10μm, resulting in low interconnect density. Furthermore, the high dielectric constant of organic materials (>4.0) leads to significant losses and increased latency in high-speed signal transmission, making it difficult to meet the requirements of 100nm-scale interconnects and high-frequency interfaces. While silicon interposers can achieve vertical interconnects via TSVs, they force TSV integration into the chip, significantly increasing design complexity and tape-out costs. Thin silicon interposers are also prone to package warpage due to insufficient mechanical support. Ordinary silicon bridges can only achieve short-distance lateral interconnects between adjacent chips (spacing ≤50μm), failing to address vertical connections from chip to substrate. They are functionally limited and have poor scalability, and signal integrity deteriorates rapidly with increasing stacked layers. The core drawbacks of these solutions are that they either cannot achieve high-density bidirectional vertical (chip-substrate) and horizontal (chip-to-chip) interconnects without TSV chips, or they suffer from high cost and poor reliability due to TSV dependence or material characteristics.

[0004] Based on the shortcomings of current multi-chip packaging interconnection schemes, this application provides a packaging structure and manufacturing method that reduces the actual complexity and cost of the chips, balances the horizontal and vertical interconnection effects, and reduces the difficulty of the manufacturing process. Summary of the Invention

[0005] This invention provides a multi-core packaging structure and manufacturing method, which aims to solve the problems of high difficulty and technical requirements in existing multi-core packaging.

[0006] To achieve the above objectives, embodiments of the present invention provide a multi-core packaging structure, comprising: There are N horizontally arranged chip combinations, where N is an integer greater than 1, and each chip combination consists of two chips stacked back to back. The interconnection mechanism includes a stacking portion disposed between chip assemblies and a top RDL and a bottom RDL disposed above and below the stacking portion, wherein the top RDL and the bottom RDL are interconnected through the stacking portion, and one chip in each chip assembly is bonded to the top RDL. An adapter board is disposed below the interconnect mechanism, and the bottom RDL and another chip in each chip assembly are respectively bonded to the adapter board; The substrate is located below the adapter plate and is bonded to the solder balls of the adapter plate.

[0007] Preferably, the number of stacked portions is N-1, the top RDL is located above each core assembly, and the bottom RDL is located between each core assembly.

[0008] Preferably, the stacked portion includes a silicon substrate, on which through-silicon vias are arranged, the through-silicon vias being electrically connected to a top RDL and N-1 bottom RDLs respectively; the wires in the top RDL and bottom RDLs are tightly stacked.

[0009] Preferably, the substrate is further provided with a Ring, which surrounds the core assembly, interconnect mechanism and adapter plate.

[0010] On the other hand, this application also provides a method for fabricating a multi-core packaging structure, used to fabricate the aforementioned multi-core packaging structure, comprising: S100. Fabricate the interconnection mechanism; S200. Bond one chip in the chip assembly to the top RDL of the interconnect mechanism. The S300 bonds another chip in the chip assembly to the adapter board and bonds the bottom RDL to the adapter board; S400. Bond the adapter board to the substrate.

[0011] Preferably, step S100 includes: S110. Select N-1 single-crystal silicon wafers and fabricate through-silicon vias on each single-crystal silicon wafer to form a stacked portion with through-silicon vias; S120. Deposit a PI dielectric layer on a temporary carrier, and after photolithography and development, electroplate a conductive dielectric to form a top RDL. Electrically connect the pads of the top RDL to the top of the through-silicon via, and match the pads of the top RDL with the I / O terminals of the chip. S130. A PI dielectric layer is deposited on the other side of each stack, and after photolithography and development, a conductive dielectric is electroplated to form a bottom RDL. The pads of the bottom RDL are electrically connected to the bottom end of the through silicon via, and the pads of the bottom RDL are matched with the I / O terminals of the chip.

[0012] Preferably, in step S200, the chip is flip-chip mounted onto the pads of the top RDL using a flip-chip process.

[0013] Preferably, in step S300, microbumps are used to connect the bottom RDL of the interconnect mechanism to the upper RDL of the adapter plate; The chip is flip-mounted onto the pads of the upper RDL on the adapter board.

[0014] Preferably, in step S400, the RDL of the lower layer of the adapter board is connected to the RDL of the upper layer of the substrate by solder balls, and solder balls are placed on the RDL of the lower layer of the substrate.

[0015] Preferably, the manufacturing method further includes step S500, which involves attaching a ring to the substrate.

[0016] The above-described solution of the present invention has the following beneficial effects: This application achieves a high-density, low-loss, through-silicon via-free (TSV) compatible multi-chip packaging solution through improvements to the interconnect mechanism and adapter board, balancing performance, cost, and reliability. It not only avoids the high-barrier design of traditional interconnect solutions that require TSVs to be pre-reserved within the chip, but also utilizes the top and bottom RDLs of the interconnect mechanism, as well as the external stacking section, to achieve efficient expansion of lateral interconnects between chips.

[0017] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0018] Figure 1 This is a cross-sectional schematic diagram of the present invention; Figure 2 This is a schematic diagram of the signal interconnection of the present invention.

[0019] [Explanation of Labels in the Attached Image] 10-Core assembly, 20 - Interconnection mechanism, 21 - Stacking section, 22 - Top RDL, 23 - Bottom RDL 30-Adapter board 40-Substrate, 51-Microbump, 52-Solder ball 60-Ring. Detailed Implementation

[0020] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0021] like Figure 1 and 2As shown, an embodiment of the present invention provides a multi-chip packaging structure, including a chip assembly 10, which has N chips, where N is an integer greater than 1. In each chip assembly 10, two chips are stacked back to back. It should be noted that the back sides of the two stacked chips are close to each other, and the active surfaces face upward and downward respectively. The two stacked chips cannot be vertically interconnected due to the back-to-back stacking.

[0022] The packaging structure also includes an interconnect mechanism 20, which has three parts: a stacking section 21, a top RDL 22, and a bottom RDL 23. There is one top RDL 22 and at least one bottom RDL 23. The top RDL 22 and the bottom RDL 23 are electrically connected through the stacking section 21. In each chip assembly 10, the chip closest to the top RDL 22 is bonded to the top RDL 22.

[0023] Below the interconnect mechanism 20, there is also an adapter board 30. The bottom RDL 23 is bonded to the adapter board 30, and the adapter board 30 is also bonded to another chip in each chip assembly 10.

[0024] A substrate 40 is also provided below the adapter plate 30, and the substrate 40 is bonded to the solder balls 52 of the adapter plate 30.

[0025] In this application, the two chips in the chip assembly 10 are horizontally interconnected via the top RDL 22 or the adapter board 30. When vertical interconnection is required, the top RDL 22 and the adapter board 30 are interconnected via the stacking section 21, thereby achieving vertical interconnection of chips in different chip assemblies 10. The two chips in the chip assembly 10 do not need to integrate through-silicon vias (TSVs), reducing chip design complexity and cost, and making it more suitable for mass production of existing through-silicon via-less chip assemblies 10.

[0026] Furthermore, the number of stacked sections 21 is N-1, with the top RDL 22 located above each chip assembly 10 and the bottom RDL 23 located between each chip assembly 10. Specifically, the stacked section 21 includes a silicon substrate on which through-silicon vias (TSVs) are arranged. These TSVs are electrically connected to the top RDL 22 and the bottom RDL 23, respectively. The conductors in the top RDL 22 and the bottom RDL 23 are tightly connected, with a linewidth / spacing of 3μm / 3μm. Using a silicon substrate as the main body of the stacked section 21 provides strong mechanical support, and under temperature cycling tests at -55°C to 125°C for 1000 cycles, the interconnect resistance change rate is <5%, meeting JEDEC standards.

[0027] The linewidth / spacing of the top RDL22 and bottom RDL23 can reach 3μm / 3μm, and the interconnect density is 3 times higher than that of the traditional adapter board 30. Moreover, the silicon substrate has lower electrical loss, reducing the insertion loss of 10Gbps signals by 40% and increasing the eye diagram opening by 25%.

[0028] Preferably, a Ring 60 is also provided on the substrate 40, and the Ring 60 is arranged around the core assembly 10, the interconnect mechanism 20 and the adapter plate 30.

[0029] In this application, the Ring 60 can be configured in different ways depending on the needs of different scenarios. For example, a shielding ring can be configured to prevent electromagnetic interference and protect sensitive internal areas from external noise; a ring pad can be configured to provide additional insulation space and prevent electrical short circuits between different layers.

[0030] This application also provides a method for fabricating a multi-core packaging structure, including the following steps: S100. Fabricate interconnection mechanism 20.

[0031] include: N-1 single-crystal silicon wafers are selected as silicon substrates, and through-silicon vias are fabricated on the single-crystal silicon wafers respectively.

[0032] N-1 single-crystal silicon wafers with a thickness of 200μm are selected, and a silicon via array with a diameter of 5μm and a depth of 200μm is prepared by deep silicon etching. A 1μm thick insulating layer is deposited in the silicon via array, preferably silicon dioxide. A 50nm thick titanium layer and a 500nm thick copper layer are sequentially deposited on the insulating layer to form a seed layer. After the seed layer is prepared, copper pillars are electroplated in the silicon via array to fill the silicon vias, forming a stacked part 21 with conductive vias.

[0033] A temporary carrier board is selected, a PI dielectric layer is deposited on the temporary carrier board, and copper is electroplated after photolithography and development to form the top RDL22. The temporary carrier board is then removed, and the top RDL22 is electrically connected to the through-silicon vias (TSVs) of each stacked section 21 through the pads of the top RDL22. The conductors of the top RDL22 are tightly stacked with a linewidth / spacing of 3μm / 3μm. The pads of the top RDL22 are matched with the I / O terminals of the chip for easy subsequent connection.

[0034] The stacked section 21 is flipped, and a PI dielectric layer is deposited on each stacked section 21. After photolithography and development, copper is electroplated to form a bottom RDL 23. The pads of each bottom RDL 23 are electrically connected to the bottom end of the corresponding through-silicon via. The pads of the bottom RDL 23 are matched with the I / O terminals of the chip.

[0035] S200. Bond one of the chips in the chip assembly 10 to the top RDL22 of the interconnect mechanism 20.

[0036] The chip at the top of the chip assembly 10 is flip-chipped onto the pad of the top RDL22 using a flip-chip process.

[0037] S300. Attach another chip from the chip assembly 10 to the adapter board 30, and attach the bottom RDL23 to the adapter board 30.

[0038] Specifically, an adapter board 30 with an upper RDL linewidth / spacing of 5μm / 5μm is selected, another chip is flip-chip mounted on the upper RDL of the adapter board 30, and the bottom RDL23 of the interconnect mechanism 20 is connected to the upper RDL of the adapter board 30 using 4μm×4μm microbumps 51.

[0039] S400. Bond the adapter plate 30 to the substrate 40.

[0040] The lower RDL of the adapter board 30 is connected to the upper RDL of the substrate 40 through solder balls 52, and solder balls are placed on the lower RDL of the substrate 40.

[0041] S500. After bonding the adapter plate 30 to the substrate 40, a ring 60 is mounted on the substrate 40.

[0042] The advantages of this process are: it does not require modification of existing TSV-free chips, is suitable for mass production systems of existing chips, and has a simple manufacturing process that does not require complex design of chip assemblies. Furthermore, the interconnect mechanism 20 achieves a linewidth / spacing of 3μm / 3μm, significantly improving the interconnect density. Under the action of the interconnect mechanism 20, high-density lateral and / or vertical interconnections can be effectively achieved between chip assemblies 10.

[0043] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multi-core packaging structure, characterized in that, include: N horizontally arranged chip combinations (10), where N is an integer greater than 1, each chip combination (10) includes two chips stacked back to back; The interconnection mechanism (20) includes a stack (21) arranged between the chip assemblies (10) and a top RDL (22) and a bottom RDL (23) disposed above and below the stack (21), wherein the top RDL (22) and the bottom RDL (23) are interconnected through the stack (21), and one chip in each chip assembly (10) is bonded to the top RDL (22); An adapter board (30) is disposed below the interconnect mechanism (20), and the bottom RDL (23) and another chip in each chip assembly (10) are respectively bonded to the adapter board (30); The substrate (40) is disposed below the adapter plate (30) and bonded to the solder balls (52) of the adapter plate (30).

2. The multi-core packaging structure according to claim 1, characterized in that: The number of stacked sections (21) is N-1, the top RDL (22) is located above each core assembly (10), and the bottom RDL (23) is located between each core assembly (10).

3. The multi-core packaging structure according to claim 1, characterized in that: The stack (21) includes a silicon substrate on which through-silicon vias are arranged, the through-silicon vias being electrically connected to a top RDL (22) and N-1 bottom RDLs (23); the wires in the top RDL (22) and bottom RDLs (23) are tightly stacked.

4. The multi-core packaging structure according to claim 1, characterized in that: The substrate (40) is also provided with a Ring (60), which surrounds the core assembly (10), the interconnect mechanism (20), and the adapter plate (30).

5. A method for fabricating a multi-core encapsulation structure, used to fabricate the multi-core encapsulation structure according to any one of claims 1-4, characterized in that, include: S100. Fabricate the interconnection mechanism (20); S200. Bond one chip in the chip assembly (10) to the top RDL (22) of the interconnect mechanism (20). S300 bonds another chip in the chip assembly (10) to the adapter plate (30) and bonds the bottom RDL (23) to the adapter plate (30); S400. Bond the adapter plate (30) to the substrate (40).

6. The manufacturing method according to claim 5, characterized in that, Step S100 includes: S110. Select N-1 single-crystal silicon wafers and fabricate through-silicon vias on each single-crystal silicon wafer to form a stacked portion with through-silicon vias (21). S120. Deposit a PI dielectric layer on a temporary substrate, and after photolithography and development, electroplate a conductive dielectric to form a top RDL (22). Electrically connect the pads of the top RDL (22) to the top of the through-silicon via. The pads of the top RDL (22) are matched with the I / O terminals of the chip. S130. A PI dielectric layer is deposited on the other side of each stack (21), and a conductive dielectric is electroplated after photolithography and development to form a bottom RDL (23). The pads of the bottom RDL (23) are electrically connected to the bottom end of the through silicon via, and the pads of the bottom RDL (23) are matched with the I / O terminals of the chip.

7. The manufacturing method according to claim 5, characterized in that, In step S200, the chip is flip-chip mounted onto the pads of the top RDL (22) using a flip-chip process.

8. The manufacturing method according to claim 5, characterized in that, In step S300, the bottom RDL (23) of the interconnect mechanism (20) is connected to the upper RDL of the adapter plate (30) using micro bumps (51); The chip is flip-mounted onto the pads of the upper RDL of the adapter board (30).

9. The manufacturing method according to claim 5, characterized in that, In step S400, the RDL of the lower layer of the adapter board (30) is connected to the RDL of the upper layer of the substrate (40) by solder balls (52), and solder balls are placed on the RDL of the lower layer of the substrate (40).

10. The manufacturing method according to claim 5, characterized in that, The manufacturing method also includes step S500, which involves attaching a Ring (60) onto the substrate (40).

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