Simple LDO circuit with temperature coefficient compensation
By adding a temperature compensation circuit to a simple LDO circuit, the output voltage is corrected using a reference voltage with a positive temperature coefficient, thus solving the problem of large output voltage variations with temperature and achieving higher voltage output accuracy and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2026-03-27
- Publication Date
- 2026-06-30
AI Technical Summary
The output voltage of existing simple LDO circuits varies greatly with temperature, leading to voltage drift problems.
A temperature compensation circuit is added to the existing simple LDO circuit structure to correct the output voltage of the LDO circuit by generating a reference voltage with a positive temperature coefficient. A bias circuit is used to provide bias current, and a startup circuit is formed by combining transistors and resistors to ensure that the circuit starts up normally.
It effectively reduces the impact of temperature changes on the output voltage, improves the accuracy and stability of the voltage output, and reduces the temperature coefficient.
Smart Images
Figure CN122308549A_ABST
Abstract
Description
Technical Field
[0002] This invention relates to circuit structure, and in particular to a simple LDO circuit with temperature coefficient compensation function. Background Technology
[0003] An LDO (low dropout regulator) is an IP circuit structure used to provide a stable voltage source with a certain load-carrying capacity. Due to the rapid development of portable electronic products and the widespread adoption of wearable electronic information products, on-chip LDOs are widely used. A simple LDO is an LDO circuit without external capacitors. It typically powers low-power IP modules such as POR, OSC, and Pump, which requires the LDO's output voltage (Vout) to have minimal deviation from changes in temperature, supply voltage, and load power.
[0004] A simple LDO circuit structure is as follows Figure 1 As shown, the circuit consists of two resistors, R1 and R2, and 11 MOSFETs, NM0 to NM4 and PM0 to PM5. The circuit structure can be divided into three parts: startup circuit, bias circuit, and LDO circuit. The startup circuit consists of resistor R1 and MOSFETs PM4 and PM5. Its function is to assist in the startup of the circuit. When the overall circuit VDD25 is powered on, the VM signal voltage is low, MOSFET PM5 is turned on, and the drain voltage follows the power supply voltage VDD25. Therefore, the gate voltages of NM0, NM1, and NM5 also follow the power supply voltage VDD25, eliminating the startup problem during the power-on process of the bias circuit. When the power supply VDD25 is fully powered on, PM4 mirrors the bias circuit current flowing through resistor R1, causing the VM signal voltage to rise. MOSFET PM5 is turned off, and the VD1 signal is determined by the normal operating state of the circuit. The bias circuit consists of resistor R2 and MOSFETs NM0, MN1, PM0, and PM1. NM0, PM0, and PM1 can maintain a consistent width-to-length ratio (W / L), with NM1 having a size of K*W / L. NM1 is a self-well transistor to eliminate the body effect. PM0 and PM1 are of similar size and are mirror images of each other, thus... And based on the gate voltages NM0 and NM1, the following can be listed: ① According to the saturation current formula: ② have to: ③ Simplifying, we get the following formula ④: ④ According to formula ④, since K, W, and L are fixed constants, the resistance R2 and the gate oxide capacitance Cox do not change much with temperature and can be ignored. Therefore, the current is mainly determined by the temperature coefficient of electron mobility. As we know from semiconductor physics, the electron mobility decreases with increasing temperature, so the current exhibits a positive temperature coefficient. The LDO circuit consists of five MOSFETs: PM2, PM3, NM2, NM3, and NM4. PM2 mirrors the current generated by the bias circuit, supplying it to the LDO module. PM3 is a self-well source follower MOSFET. NM2 and NM3 form current mirrors, with the NM3 current mirror primarily providing a stable quiescent current for the PM3 source follower. NM4 is a power transistor; its saturation current can be calculated using the following formula: ⑤ in As in formula ⑥: ⑥ Substituting ⑥ into ⑤, we get: ⑦ in, Hole mobility The value is relatively small. Although there are parameters related to temperature changes in this item, the overall change has a small impact on V12. Therefore, the output voltage of V12 can be considered to be mainly determined by temperature. add Impact, approximately considered Because the threshold voltage has a negative temperature coefficient, the voltage output of V12 varies greatly with temperature. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a simple LDO circuit with temperature coefficient compensation function, so as to solve the problem of the output voltage of the existing LDO circuit drifting with temperature changes.
[0006] To address the above problems, this invention provides a simple LDO circuit with temperature coefficient compensation function, comprising: The circuit includes a startup circuit, a bias circuit, a temperature compensation circuit, and an LDO circuit. The starting circuit is used to assist the entire circuit in starting up, and enables the circuit to start normally when it is powered on. The bias circuit is located in the secondary stage of the startup circuit and acts as a mirror current source to provide bias current to the subsequent LDO circuit. The temperature compensation circuit provides a reference voltage with a positive temperature coefficient to the subsequent LDO circuit. The LDO circuit described above outputs a stable output voltage that is independent of temperature fluctuations, with the reference voltage correction provided by the temperature compensation circuit. The startup circuit, bias circuit, temperature compensation circuit, and LDO circuit are all connected to power supply VDD25.
[0007] The startup circuit includes transistors PM4, PM5, and PM6, and resistor R1; the source of transistor PM4 is connected to power supply VDD25, the drain of transistor PM4 is grounded through resistor R1, and the gate of transistor PM4 forms node VG1. The gates of transistors PM5 and PM6 are both connected to the drain of transistor PM4, and the sources of transistors PM5 and PM6 are both connected to power supply VDD25. The drain of transistor PM5 forms output node VD1, and the drain of transistor PM6 forms output node VD2.
[0008] The aforementioned bias circuit is a bias circuit that provides bias current to the LDO circuit. It includes transistors PM0, PM1, NM0, NM1 and resistor R2. Among them, transistors PM0 and NM0 form the first branch with a first current ID1, and transistors PM1, NM1 and resistor R2 form the second branch with a second current ID2 mirroring the first current ID1. The aforementioned Bias circuit is used to generate a current with a positive temperature coefficient.
[0009] In the aforementioned Bias circuit, the sources of transistors PM0 and PM1 are both connected to power supply VDD25, and their gates are both connected to node VG1. The drain of transistor PM1, the drain of transistor NM0, the gate of transistor NM0, and the gate of transistor NM1 are all connected to node VD1, and the source of NM0 is grounded. The drain of transistor PM1 is connected to the drain of transistor NM1, and the source of transistor NM1 is grounded through resistor R2.
[0010] The temperature compensation circuit includes transistor PM7 and resistor R3; Among them, the source of transistor PM7 is connected to power supply VDD25, the gate of transistor PM7 is connected to node VG1, and the drain of transistor PM7 is grounded through resistor R3. The drain of transistor PM7 forms a node, and the output has a reference voltage VR with a positive temperature coefficient.
[0011] Furthermore, the LDO circuit includes transistors PM2, PM3, NM2, NM3, and NM4; Among them, the source of transistor PM2 and the drain of NM4 are connected to power supply VDD25, the gate of transistor PM2 is connected to node VG1, the gate of transistor NM4 is connected to the drain of transistor PM2 to form node VG2, the drain of transistor NM2 is connected to the drain of transistor PM2, and the source of transistor NM2 is grounded. The source of transistor PM3 is connected to the source of transistor NM4 to form the output port of the LDO circuit, which outputs voltage V12. The drain of transistor PM3 is connected to the drain of transistor NM3, and the source of transistor NM3 is grounded. The gate of transistor PM3 is connected to a reference voltage VR with a positive temperature coefficient; The gate of transistor NM2, the gate of transistor NM3, and the drain of transistor NM3 are connected together and connected to node VD2; The output voltage V12 is mainly determined by the reference voltage VR and the threshold voltage Vth of transistor PM3.
[0012] Furthermore, the transistor PM3 forms a source follower, the gate of which is controlled by a reference voltage VR with a positive temperature coefficient.
[0013] Furthermore, the temperature coefficient of the output voltage V12 is obtained by compensating the threshold voltage Vth of the negative temperature coefficient transistor PM3 with the reference voltage VR signal with a positive temperature coefficient, thereby reducing the influence of temperature on the output voltage V12.
[0014] The transistors PM0 to PM7 are PMOS transistors, and the transistors NM0 to NM4 are NMOS transistors.
[0015] The simplified LDO circuit with temperature coefficient compensation described in this invention optimizes the existing simplified LDO circuit structure by adding a positive temperature coefficient compensation circuit to generate a reference voltage with a positive temperature coefficient, which is provided to the source follower at the output terminal of the LDO circuit. At this time, the LDO output voltage... The addition of the two voltages with positive and negative temperature coefficients compensates for the effect of temperature changes on the output of V12, thereby reducing the temperature coefficient. Attached Figure Description
[0016] Figure 1 This is a circuit diagram of an existing LDO circuit.
[0017] Figure 2 This invention is an LDO circuit with added positive temperature coefficient compensation circuit.
[0018] Figure 3 This is a comparison of the output voltage curves of the LDO circuit before temperature compensation and after temperature compensation according to the present invention.
[0019] Figure 4 The test simulation verifies the corner, comparing the voltage output curve of the existing simple LDO corner with the voltage output curve of the improved circuit of this invention. Detailed Implementation
[0020] The following detailed description, in conjunction with the accompanying drawings, provides specific embodiments of the present invention and clearly and completely describes the technical solutions of the present invention. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0021] It should be understood that the present invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout. It should be understood that when an element or layer is referred to as “on,” “adjacent to,” “connected to,” or “coupled to” other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.
[0022] The purpose of this invention is to propose a novel and simple LDO circuit structure to solve the problem that the output voltage of the current simple LDO circuit varies greatly with temperature.
[0023] This invention improves upon the existing simple LDO circuit structure by adding a temperature compensation circuit to stabilize the output voltage of the LDO circuit. Figure 2The circuit structure diagram of the present invention is shown in the figure. Transistors PM0 to PM7 are PMOS transistors, and transistors NM0 to NM4 are NMOS transistors.
[0024] This circuit structure can be divided into four parts: startup circuit, bias circuit, temperature compensation circuit, and LDO circuit.
[0025] The startup circuit consists of resistor R1 and MOSFETs PM4, PM5, and PM6, and its function is to assist in starting the circuit. The source of transistor PM4 is connected to the power supply VDD25, the drain of transistor PM4 is grounded through resistor R1, and the gate of transistor PM4 forms node VG1. The gates of transistors PM5 and PM6 are both connected to the drain of transistor PM4, and the sources of transistors PM5 and PM6 are both connected to power supply VDD25. The drain of transistor PM5 forms output node VD1, and the drain of transistor PM6 forms output node VD2.
[0026] The aforementioned bias circuit LDO circuit provides bias current, wherein transistor PM0 and NM0 form a first branch with a first current ID1, and transistor PM1, NM1 and resistor R2 form a second branch with a second current ID2 mirroring the first current ID1; the sources of transistors PM0 and PM1 are both connected to power supply VDD25, and their gates are both connected to node VG1.
[0027] The drain of transistor PM1, the drain of transistor NM0, the gate of transistor NM0, and the gate of transistor NM1 are all connected to node VD1, and the source of NM0 is grounded. The drain of transistor PM1 is connected to the drain of transistor NM1, and the source of transistor NM1 is grounded through resistor R2.
[0028] The aforementioned Bias circuit generates a current with a positive temperature coefficient.
[0029] The temperature compensation circuit includes transistor PM7 and resistor R3. The source of transistor PM7 is connected to power supply VDD25, the gate of transistor PM7 is connected to node VG1, and the drain of transistor PM7 is grounded through resistor R3. The drain of transistor PM7 forms a node, and the output has a reference voltage VR with a positive temperature coefficient.
[0030] The LDO circuit includes transistors PM2, PM3, NM2, NM3 and NM4.
[0031] Among them, the source of transistor PM2 and the drain of NM4 are connected to power supply VDD25, the gate of transistor PM2 is connected to node VG1, the gate of transistor NM4 is connected to the drain of transistor PM2 to form node VG2, the drain of transistor NM2 is connected to the drain of transistor PM2, and the source of transistor NM2 is grounded. Transistor PM3 is a self-well source follower transistor. The source of transistor PM3 is connected to the source of transistor NM4 to form the output port of the LDO circuit, which outputs voltage V12. The drain of transistor PM3 is connected to the drain of transistor NM3, and the source of transistor NM3 is grounded. The gate of transistor PM3 is connected to a reference voltage VR with a positive temperature coefficient; The gate of transistor NM2, the gate of transistor NM3, and the drain of transistor NM3 are connected together and connected to node VD2; The mirror current of transistor NM3 mainly provides a stable quiescent current for source follower transistor PM3, while NM4 is a POWER transistor.
[0032] The output voltage V12 is mainly determined by the reference voltage VR and the threshold voltage Vth of transistor PM3.
[0033] Figure 2 The circuit shown works as follows: when the overall circuit power supply VDD25 is powered on, the node VM signal voltage is low, PM5 and PM6 transistors are turned on, and the drain voltages of PM5 and PM6 follow the power supply voltage VDD25. Therefore, the gate voltages of NM0, NM1, NM2, and NM3 also follow the power supply voltage VDD25, eliminating the startup problem during the power-on process of the bias circuit and LDO circuit. When the VDD25 power supply is fully powered on, the current of the bias circuit mirrored by PM4 flows through resistor R1, raising the node VM signal voltage. MOSFETs PM5 and PM6 are turned off, and the VD1 and VD2 signals are determined by the normal operating state of the circuit.
[0034] The bias circuit consists of resistor R2 and MOSFETs NM0, MN1, PM0, and PM1. The dimensions of NM0, PM0, and PM1 can be consistent, with a width-to-length ratio of W / L. The dimension of NM1 is set to K*W / L, where K is a set coefficient. NM1 is a self-well transistor to eliminate the body effect. PM0 and PM1 are of similar size and are mirror images of each other, therefore the current = , and based on the gate voltages of NM0 and NM1, the following can be derived: ① According to the saturation current formula: ② have to: ③ Simplifying, we get: ④ According to formula ④, since K, W, and L are fixed constants, and the resistance R2 and gate oxide capacitance Cox change little with temperature, they can be ignored. Therefore, the current is mainly determined by the electron mobility. The temperature coefficient determines the electron mobility; as we know from semiconductor physics, electron mobility decreases with increasing temperature, therefore the current... It exhibits a positive temperature coefficient.
[0035] According to formula ④, the current generated by the Bias module has a positive temperature coefficient. When this current passes through R3 (which has a small temperature coefficient of resistance), a reference voltage VR with a positive temperature coefficient can be obtained.
[0036] The output voltage V12 can be obtained as follows:
[0037] in, The value is relatively small. Although this term has parameters related to temperature changes, the overall change has a small impact on the output voltage V12 because the threshold voltage has a negative temperature coefficient, while the constructed VR voltage has a positive temperature coefficient. Therefore, the output voltage V12 can be considered to be mainly determined by the VR voltage plus... Impact, approximately considered The addition of the two voltages with positive and negative temperature coefficients compensates for the effect of temperature changes on the output voltage V12, thereby reducing the temperature coefficient and improving the range of V12's voltage output with temperature variation.
[0038] This invention adds two PMOS transistors, PM6 and PM7, and one resistor, R3, to improve the accuracy of the voltage output. The method proposed in this invention has been designed and simulated. Simulation results show that this circuit can reduce the impact of temperature on voltage output accuracy and also improves the performance of the circuit to some extent, such as… Figure 3 , Figure 4 As shown.
[0039] The compensation method provided by this invention was used to design and simulate a simplified LDO circuit, such as... Figure 3 As shown, curve A is the voltage output versus temperature curve before temperature compensation (existing structure). It can be seen that the output voltage is 1.2V at 25℃, and the voltage output range is 1.32V to 1.03V from -40℃ to 125℃, with a voltage deviation range of -15% to +10% and a temperature coefficient of -1.79mV / ℃. Curve B is the voltage output versus temperature curve after temperature compensation (this invention). It can be seen that the output voltage is 1.2V at 25℃, and the voltage output range is 1.227V to 1.187V from -40℃ to 125℃, with a voltage deviation range of 1.08% to +2.25% and a temperature coefficient of -0.24mV / ℃. It is evident that this compensation method significantly improves performance.
[0040] Perform corner simulation verification on the circuit, such as Figure 4 As shown, the voltage output range of the existing simple LDO structure under corner is 1.399V to 0.974V, with a voltage deviation range of -18.83% to +16.58%; the improved circuit structure of this invention has a voltage output range of 1.250V to 1.183V, with a voltage deviation range of -1.412% to +4.167%; this invention can also significantly improve the impact of corner changes.
[0041] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A simple LDO circuit with temperature coefficient compensation function, characterized in that: The circuit includes a startup circuit, a bias circuit, a temperature compensation circuit, and an LDO circuit. The starting circuit is used to assist the entire circuit in starting up, and enables the circuit to start normally when it is powered on. The bias circuit is located in the secondary stage of the startup circuit and acts as a mirror current source to provide bias current to the subsequent LDO circuit. The temperature compensation circuit provides a reference voltage with a positive temperature coefficient to the subsequent LDO circuit. The LDO circuit described above outputs a stable output voltage that is independent of temperature fluctuations, with the reference voltage correction provided by the temperature compensation circuit. The startup circuit, bias circuit, temperature compensation circuit, and LDO circuit are all connected to power supply VDD25.
2. The simplified LDO circuit with temperature coefficient compensation function as described in claim 1, characterized in that: The startup circuit includes transistors PM4, PM5, and PM6, and resistor R1; the source of transistor PM4 is connected to power supply VDD25, the drain of transistor PM4 is grounded through resistor R1, and the gate of transistor PM4 forms node VG1. The gates of transistors PM5 and PM6 are both connected to the drain of transistor PM4, and the sources of transistors PM5 and PM6 are both connected to power supply VDD25. The drain of transistor PM5 forms output node VD1, and the drain of transistor PM6 forms output node VD2.
3. The simplified LDO circuit with temperature coefficient compensation function as described in claim 2, characterized in that: The aforementioned bias circuit is a bias circuit that provides bias current to the LDO circuit. It includes transistors PM0, PM1, NM0, NM1 and resistor R2. Among them, transistors PM0 and NM0 form the first branch with a first current ID1, and transistors PM1, NM1 and resistor R2 form the second branch with a second current ID2 mirroring the first current ID1. The transistor NM1 is a self-well transistor, which eliminates the influence of the bulk effect; The transistors NM0, PM0, and PM1 have the same dimensions and a width-to-length ratio of W / L. Transistors PM0 and PM1 are mirror images of each other. The dimension of transistor NM1 is set to K*W / L, where K is a coefficient. The aforementioned Bias circuit is used to generate a current with a positive temperature coefficient.
4. The simplified LDO circuit with temperature coefficient compensation function as described in claim 3, characterized in that: In the aforementioned Bias circuit, the sources of transistors PM0 and PM1 are both connected to power supply VDD25, and their gates are both connected to node VG1. The drain of transistor PM1, the drain of transistor NM0, the gate of transistor NM0, and the gate of transistor NM1 are all connected to node VD1, and the source of NM0 is grounded. The drain of transistor PM1 is connected to the drain of transistor NM1, and the source of transistor NM1 is grounded through resistor R2.
5. The simplified LDO circuit with temperature coefficient compensation function as described in claim 2, characterized in that: The temperature compensation circuit includes transistor PM7 and resistor R3; Among them, the source of transistor PM7 is connected to power supply VDD25, the gate of transistor PM7 is connected to node VG1, and the drain of transistor PM7 is grounded through resistor R3. The drain of transistor PM7 forms a node, and the output has a reference voltage VR with a positive temperature coefficient.
6. The simplified LDO circuit with temperature coefficient compensation function as described in claim 1, characterized in that: The LDO circuit includes transistors PM2, PM3, NM2, NM3, and NM4; Among them, the source of transistor PM2 and the drain of NM4 are connected to power supply VDD25, the gate of transistor PM2 is connected to node VG1, the gate of transistor NM4 is connected to the drain of transistor PM2 to form node VG2, the drain of transistor NM2 is connected to the drain of transistor PM2, and the source of transistor NM2 is grounded. The source of transistor PM3 is connected to the source of transistor NM4 to form the output port of the LDO circuit, which outputs voltage V12. The drain of transistor PM3 is connected to the drain of transistor NM3, and the source of transistor NM3 is grounded. The gate of transistor PM3 is connected to a reference voltage VR with a positive temperature coefficient; The gate of transistor NM2, the gate of transistor NM3, and the drain of transistor NM3 are connected together and connected to node VD2; The output voltage V12 is mainly determined by the reference voltage VR and the threshold voltage Vth of transistor PM3.
7. The simplified LDO circuit with temperature coefficient compensation function as described in claim 6, characterized in that: The transistor PM3 forms a source follower, whose gate is controlled by a reference voltage VR with a positive temperature coefficient.
8. The simplified LDO circuit with temperature coefficient compensation function as described in claim 1, characterized in that: The temperature coefficient of the output voltage V12 is obtained by compensating the threshold voltage Vth of the negative temperature coefficient transistor PM3 with the reference voltage VR signal with a positive temperature coefficient, thereby reducing the influence of temperature on the output voltage V12.
9. The simplified LDO circuit with temperature coefficient compensation function according to any one of claims 1 to 8, characterized in that: The transistors PM0 to PM7 are PMOS transistors, and the transistors NM0 to NM4 are NMOS transistors.