A server clock topology switching system and method

Abstract

The application provides a server clock topology switching system and method, comprising a switching backboard and N mainboards. The switching backboard is provided with a first controller, and the mainboard is provided with a clock generator, a clock selector, a second controller and a CPU. When the first controller receives a switching-to-N-way working mode instruction and confirms that each mainboard is in place, the first controller sends a local gating signal to the second controller of the i-th mainboard, so that the CPU of the i-th mainboard uses the clock signal provided by the clock generator of the mainboard; and sends a common gating signal to the second controller of the remaining mainboards, so that the CPUs of the remaining mainboards all use the clock signal provided by the clock generator of the i-th mainboard. When the first controller receives a switching-to-single-way working mode instruction, the first controller sends a local gating signal to the second controller of each mainboard in place, so that the CPUs of the mainboards all use the clock signal provided by the clock generator of the mainboard where the CPU is located, to realize flexible configuration.

Description

Technical Field

[0001] This application relates to the field of server technology, and more specifically, to a server clock topology switching system and method. Background Technology

[0002] With the improvement of CPU (Central Processing Unit) performance, single-socket server systems can now cover most application scenarios (such as cloud computing and routine data center workloads). Driven by industry demands (such as cost optimization and simplified design), single-socket server architectures are gradually becoming more common, and the reliance on multi-socket servers is gradually decreasing. Nevertheless, traditional multi-socket servers (such as dual-socket servers) still dominate the market at present, but in order to adapt to ever-changing application scenarios, traditional multi-socket servers are required to have greater flexibility, and can be flexibly reconfigured into multiple independent single-socket servers when needed.

[0003] However, in traditional high-density server designs such as 2U 2-node or 2U 4-node servers, each node can only operate as an independent system, limiting flexible configuration. For example, a 2U 2-node server consisting of two single-socket nodes cannot be reconfigured into a dual-socket server system; similarly, a dual-socket server system cannot be reconfigured into two independent single-socket server systems. Existing server designs cannot meet the requirements for flexible configuration, necessitating the development of multiple motherboards for different models, increasing development investment, costs, and time-to-market. Summary of the Invention

[0004] The purpose of this application is to provide a server clock topology switching system and method to support the dynamic switching of server systems between single-path and multi-path operating modes, enabling flexible configuration, thereby reducing hardware costs and shortening product time-to-market.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: On one hand, this application provides a server clock topology switching system, including a backplane and N motherboards, each motherboard being connected to the backplane; the backplane is provided with a first controller, and each motherboard is provided with a clock generator, a clock selector, a second controller, and a CPU; The first controller is connected to the second controller of each motherboard, and the CPUs of all motherboards are interconnected through the adapter backplane. In each motherboard, the output of the second controller is connected to the control terminal of the clock selector, the output of the clock selector is connected to the CPU, the first output of the clock generator is connected to the local input of the clock selector, and the second output of the clock generator is connected to the corresponding common input of the clock selectors in the other motherboards through the adapter backplane. When the first controller receives the instruction to switch to N-channel working mode and confirms that all motherboards are in place, the first controller sends a local strobe signal to the second controller of the i-th motherboard, so that the CPU of the i-th motherboard uses the clock signal provided by the clock generator of this motherboard; and sends a common strobe signal to the second controllers of the other motherboards, so that the CPUs of the other motherboards all use the clock signal provided by the clock generator of the i-th motherboard; where 1≤i≤N, N≥2; When the first controller receives a command to switch to single-channel operating mode, it sends a local strobe signal to the second controller of each in-situ motherboard, so that the CPU of each motherboard uses the clock signal provided by the clock generator of its respective motherboard.

[0006] Furthermore, the N motherboards include a first motherboard and a second motherboard, and the adapter backplane is also provided with a CPU interconnect link, a first internal clock link and a second internal clock link. The CPU of the first motherboard is connected to the CPU of the second motherboard through the CPU interconnect link in the adapter backplane; the second output terminal of the clock generator in the first motherboard is connected to the common input terminal of the clock selector in the second motherboard through the first internal clock link in the adapter backplane; the second output terminal of the clock generator in the second motherboard is connected to the common input terminal of the clock selector in the first motherboard through the second internal clock link in the adapter backplane.

[0007] Furthermore, the default operating mode for each motherboard is single-socket operation. When the first controller receives an instruction to switch from single-channel to dual-channel operation mode and confirms that both motherboards are in place, the first controller sends a local strobe signal to the second controller of the first motherboard and a common strobe signal to the second controller of the second motherboard. The second controller of the first motherboard outputs a first level to the clock selector of its own motherboard according to the local strobe signal, so that the clock selector outputs the clock signal at the local input terminal to the CPU of its own motherboard. The second controller of the second motherboard outputs a second level to the clock selector of its own motherboard according to the common strobe signal, so that the clock selector outputs the clock signal at the common input terminal to the CPU of its own motherboard. When the first controller receives a command to switch from dual-channel operating mode to single-channel operating mode, the first controller sends a local strobe signal to the second controller of all in-situ motherboards so that each motherboard can resume using its own local clock.

[0008] Furthermore, the adapter backplane is also provided with a first motherboard presence detection link and a second motherboard presence detection link. The first motherboard is also provided with a first upper bias circuit and a first lower bias circuit, and the second motherboard is also provided with a second upper bias circuit and a second lower bias circuit. The motherboard presence detection terminal of the second controller in the first motherboard is connected to one end of the first upper bias circuit, and the other end of the first upper bias circuit is connected to the power supply; the motherboard presence detection terminal of the second controller in the first motherboard is also connected to one end of the second lower bias circuit in the second motherboard through the second motherboard presence detection link in the adapter backplane, and the other end of the second lower bias circuit is grounded. The motherboard presence detection terminal of the second controller in the second motherboard is connected to one end of the second upper bias circuit, and the other end of the second upper bias circuit is connected to the power supply; the motherboard presence detection terminal of the second controller in the second motherboard is also connected to one end of the first lower bias circuit in the first motherboard through the first motherboard presence detection link in the adapter backplane, and the other end of the first lower bias circuit is grounded. The second controller of the first motherboard is used to determine whether the second motherboard is in place under the action of the first upper bias circuit and the second lower bias circuit; The second controller of the second motherboard is used to determine whether the first motherboard is in place under the action of the second upper bias circuit and the first lower bias circuit.

[0009] Furthermore, the adapter backplane is also provided with a third upper bias circuit; The first motherboard presence detection terminal of the first controller is connected to the first motherboard presence detection link, and the second motherboard presence detection terminal of the first controller is connected to the second motherboard presence detection link; one end of the third upper bias circuit is connected to the first motherboard presence detection terminal and the second motherboard presence detection terminal of the first controller respectively, and the other end of the third upper bias circuit is connected to the power supply. The first controller is used to determine whether the first motherboard is in place under the action of the third upper bias circuit and the first lower bias circuit; The first controller is also used to determine whether the second motherboard is in place under the action of the third upper bias circuit and the second lower bias circuit.

[0010] Furthermore, the first motherboard is also provided with a first ID setting circuit, the second motherboard is also provided with a second ID setting circuit, and the adapter backplane is also provided with a third ID setting circuit and a fourth ID setting circuit. The ID terminal of the second controller in the first motherboard is connected to one end of the first ID setting circuit, and the other end of the first ID setting circuit is connected to the power supply. The ID terminal of the second controller in the first motherboard is also connected to one end of the third ID setting circuit in the adapter backplane, and the other end of the third ID setting circuit is grounded. The ID terminal of the second controller in the second motherboard is connected to one end of the second ID setting circuit, and the other end of the second ID setting circuit is connected to the power supply. The ID terminal of the second controller in the second motherboard is also connected to one end of the fourth ID setting circuit in the adapter backplane, and the other end of the fourth ID setting circuit is grounded. The second controller of the first motherboard is used to identify the ID value of the first motherboard when it is in place, under the action of the first ID setting circuit and the third ID setting circuit. The second controller of the second motherboard is used to identify the ID value of the second motherboard when it is in place, under the action of the second ID setting circuit and the fourth ID setting circuit. The ID value of the first motherboard when it was in place was different from the ID value of the second motherboard when it was in place.

[0011] Furthermore, the adapter backplane is also provided with a first motherboard ID0 link, a first motherboard ID1 link, a second motherboard ID0 link, and a second motherboard ID1 link; the first ID setting circuit includes a first pull-up resistor and a second pull-up resistor, the second ID setting circuit includes a third pull-up resistor and a fourth pull-up resistor, the third ID setting circuit includes a first pull-down resistor and a second pull-down resistor, and the fourth ID setting circuit includes a third pull-down resistor. In the first motherboard, the ID1 and ID0 terminals of the second controller are respectively connected to one end of the first pull-up resistor and the second pull-up resistor, and the other ends of the first pull-up resistor and the second pull-up resistor are both connected to the power supply; the ID1 terminal of the second controller in the first motherboard is also connected to one end of the first pull-down resistor through the first motherboard ID1 link in the adapter backplane, and the ID0 terminal of the second controller in the first motherboard is also connected to one end of the second pull-down resistor through the first motherboard ID0 link in the adapter backplane, and the other ends of the first pull-down resistor and the second pull-down resistor are both grounded; In the second motherboard, the ID1 and ID0 terminals of the second controller are respectively connected to one end of the third pull-up resistor and the fourth pull-up resistor, and the other ends of the third pull-up resistor and the fourth pull-up resistor are both connected to the power supply; the ID1 terminal of the second controller in the second motherboard is also connected to one end of the third pull-down resistor through the second motherboard ID1 link in the adapter backplane, and the other end of the third pull-down resistor is grounded; the ID0 terminal of the second controller in the second motherboard is also connected to one end of the second motherboard ID0 link in the adapter backplane, and the other end of the second motherboard ID0 link is floating. When the first motherboard is in place, the second controller in the first motherboard recognizes that the ID value of the first motherboard is 00; When the second motherboard is in place, the second controller in the second motherboard recognizes that the ID value of the second motherboard is 01.

[0012] Furthermore, each motherboard also includes a clock buffer and PCIe devices; In each motherboard, the input of the clock buffer is connected to the output of the clock selector, and the first and second outputs of the clock buffer are connected to the CPU and the PCIe device, respectively. The PCIe device is connected to the CPU via a bus.

[0013] Furthermore, the server clock topology switching system also includes board-to-board connectors; the adapter backplane is detachably connected to N motherboards via the board-to-board connectors.

[0014] On the other hand, this application also provides a server clock topology switching method, applied to the server clock topology switching system as described in any of the foregoing embodiments, the method comprising: When the first controller receives the instruction to switch to N-channel working mode and confirms that all motherboards are in place, the first controller sends a local strobe signal to the second controller of the i-th motherboard, so that the CPU of the i-th motherboard uses the clock signal provided by the clock generator of this motherboard; and sends a common strobe signal to the second controllers of the other motherboards, so that the CPUs of the other motherboards all use the clock signal provided by the clock generator of the i-th motherboard. When the first controller receives a command to switch to single-channel operating mode, it sends a local strobe signal to the second controller of each in-situ motherboard, so that the CPU of each motherboard uses the clock signal provided by the clock generator of its respective motherboard.

[0015] Compared with the prior art, this application has the following advantages: The server clock topology switching system provided in this application includes an adapter backplane and N motherboards, each motherboard connected to the adapter backplane. The adapter backplane has a first controller, and each motherboard has a clock generator, a clock selector, a second controller, and a CPU. The first controller is connected to the second controller of each motherboard, and the CPUs of all motherboards are interconnected through the adapter backplane. In each motherboard, the output of the second controller is connected to the control terminal of the clock selector, the output of the clock selector is connected to the CPU, the first output of the clock generator is connected to the local input of the clock selector, and the second output of the clock generator is connected to the corresponding common input of the clock selectors in the remaining motherboards through the adapter backplane. When the first controller receives a command to switch to N-way operating mode and confirms that all motherboards are in place, the first controller sends a local strobe signal to the second controller of the i-th motherboard, causing the CPU of the i-th motherboard to use the clock signal provided by its clock generator; and sends a common strobe signal to the second controllers of the remaining motherboards, causing the CPUs of the remaining motherboards to use the clock signal provided by the clock generator of the i-th motherboard. When the first controller receives a command to switch to single-channel operating mode, it sends a local strobe signal to the second controller of each in-situ motherboard, so that the CPU of each motherboard uses the clock signal provided by the clock generator of its respective motherboard.

[0016] This application achieves automated configuration of single-socket and multi-socket servers by dynamically switching the system reference clock topology and flexibly controlling the clock distribution path. It breaks through the limitations of traditional server architecture and realizes the self-adaptation of single / multi-socket server architecture, thus providing a cost-effective and scalable hardware design solution for application scenarios such as data centers and edge computing. Attached Figure Description

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0018] Figure 1 This is one of the schematic diagrams of a server clock topology switching system provided in an embodiment of this application; Figure 2 This is a second schematic diagram of the architecture of a server clock topology switching system provided in an embodiment of this application; Figure 3 A schematic diagram of the system architecture in dual-path working mode provided for an embodiment of this application; Figure 4 A schematic diagram of the system architecture in single-path working mode provided for an embodiment of this application; Figure 5 A flowchart illustrating the switching from a single-channel working mode to a dual-channel working mode, provided for an embodiment of this application; Figure 6 A flowchart illustrating the switching from a dual-channel working mode to a single-channel working mode, provided for an embodiment of this application; Figure 7 This is a flowchart illustrating a server clock topology switching method provided in an embodiment of this application.

[0019] Icons: 100 - Adapter backplane; 110 - First controller; 120 - Third upper bias circuit; 130 - Third ID setting circuit; 140 - Fourth ID setting circuit; 210 - Clock generator; 220 - Clock selector; 230 - Second controller; 240 - Clock buffer; 250 - PCIe device; 300 - First motherboard; 310 - First upper bias circuit; 320 - First lower bias circuit; 330 - First ID setting circuit; 400 - Second motherboard; 410 - Second upper bias circuit; 420 - Second lower bias circuit; 430 - Second ID setting circuit; 500 - Board-to-board connector; Rp1 - First pull-up resistor; Rp2 - Second pull-up resistor; Rp3 - Third pull-up resistor; Rp4 - Fourth pull-up resistor; Rp5 - Fifth pull-up resistor; Rp6 - Sixth pull-up resistor; Rp7 - Seventh pull-up resistor; Rp8 - Eighth pull-up resistor; Rd1 - First pull-down resistor; Rd2 - Second pull-down resistor; Rd3 - Third pull-down resistor; Rd4 - Fourth pull-down resistor; Rd5 - Fifth pull-down resistor. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0022] As described in the background section, existing server designs cannot dynamically switch between single-socket and multi-socket configurations. For example, existing 2U 2-node and 2U 4-node servers either use a single-socket or dual-socket architecture and cannot be dynamically configured as two single-socket servers, one dual-socket server, or one quad-socket server. This makes it difficult to meet users' needs for flexible configuration, resulting in the need to develop multiple motherboards for different models, increasing development investment, costs, and time to market.

[0023] Therefore, a new server system design is needed that allows users to flexibly configure the motherboard, enabling each node to be used as an independent server or dynamically configured as a multi-processor server. A key issue that needs to be addressed to achieve dynamic switching between single-processor and dual-processor modes is system clock allocation.

[0024] In view of this, please refer to Figure 1 This application provides a server clock topology switching system, which includes a backplane 100 and N motherboards, each motherboard being connected to the backplane 100. Wherein, N ≥ 2.

[0025] The adapter backplane 100 is equipped with a first controller 110, and each mainboard is equipped with a clock generator 210, a clock selector 220, a second controller 230, and a CPU. Optionally, the first controller 110 can be a BMC (Baseboard Management Controller), and the second controller 230 can be a CPLD (Complex Programmable Logic Device).

[0026] The first controller 110 is connected to the second controller 230 of each motherboard, and the CPUs of all motherboards are interconnected through the adapter backplane 100.

[0027] In each motherboard, the output of the second controller 230 is connected to the control terminal of the clock selector 220, the output of the clock selector 220 is connected to the CPU, the first output of the clock generator 210 is connected to the local input of the clock selector 220, and the second output of the clock generator 210 is connected to the corresponding common input of the clock selectors 220 in the other motherboards via the adapter backplane 100. Understandably, the clock selector 220 includes N inputs (each receiving a local clock signal from this motherboard and N-1 common clock signals from other motherboards), one output, and one control terminal. The clock selector 220 is used to select a clock signal from the N inputs according to the control signal (MUX_CTRL) output by the second controller 230, and transmit it to the CPU of this motherboard through the output.

[0028] When the first controller 110 receives an instruction to switch to N-channel operating mode and confirms that all motherboards are in place, the first controller 110 sends a local strobe signal to the second controller 230 of the i-th motherboard, causing the CPU of the i-th motherboard to use the clock signal provided by the clock generator 210 of that motherboard (i.e., the local clock); and sends a common strobe signal to the second controllers 230 of the remaining motherboards, causing the CPUs of the remaining motherboards to use the clock signal provided by the clock generator 210 of the i-th motherboard (i.e., the common clock). Where 1 ≤ i ≤ N.

[0029] When the first controller 110 receives a command to switch to single-channel working mode, the first controller 110 sends a local strobe signal to the second controller 230 of each in-situ motherboard, so that the CPU of each motherboard uses the clock signal (i.e., local clock) provided by the clock generator 210 in its respective motherboard.

[0030] Understandably, this application achieves automated configuration of single-path and multi-path servers by dynamically switching the system reference clock topology and flexibly controlling the clock distribution path. This breaks through the limitations of traditional server architecture and enables adaptive single / multi-path server architecture, thus providing a cost-effective and scalable hardware design solution for application scenarios such as data centers and edge computing.

[0031] Specifically, when a user issues a mode switching command to the first controller 110, the first controller 110 first checks whether all relevant motherboards are in place to ensure the feasibility of the switching operation. When it is necessary to switch to an N-way working mode (such as a dual-way or quad-way working mode), the first controller 110 selects one of the motherboards (i.e., the i-th motherboard) as the clock source motherboard and sends a local strobe signal to the second controller 230 of that motherboard, so that the second controller 230 controls the clock selector 220 to connect to the local clock signal provided by the clock generator 210 of that motherboard for use by the CPU of that motherboard; at the same time, the first controller 110 sends a common strobe signal to the second controllers 230 of all other motherboards, so that the clock selectors 220 of these motherboards all connect to the common clock signal provided by the clock generator 210 of the i-th motherboard, thereby realizing clock synchronization of all motherboard CPUs and forming a unified multi-way server system. Conversely, when it is necessary to switch back to single-channel working mode, the first controller 110 sends a local strobe signal to the second controller 230 of each in-situ motherboard, so that the clock selector 220 of each motherboard uses the local clock signal provided by the clock generator 210 of its own motherboard, and each motherboard is restored to multiple independent and non-interfering single-channel servers.

[0032] Therefore, the server clock topology switching system provided in this application supports automatic setting and dynamic switching of operating modes, flexibly supporting single-CPU operating mode (single-socket server) and multi-CPU interconnected operating mode (multi-socket server). The entire switching process does not require hardware replacement or rewiring, enabling dynamic reconfiguration of the server system between single-socket and multi-socket modes. Compared to existing technologies that require developing separate motherboards for different single-socket, dual-socket, and quad-socket models, this application effectively reduces the number of motherboard models, lowers hardware development costs, and shortens product launch time. Simultaneously, users can flexibly allocate computing resources according to business load, thereby better adapting to the differentiated needs of various application scenarios such as data centers and edge computing.

[0033] In one alternative implementation, the server clock topology switching system further includes board-to-board connectors 500. The adapter backplane 100 is detachably connected to N motherboards via the board-to-board connectors 500.

[0034] Understandably, the adapter backplane 100 is detachably connected to N motherboards via board-to-board connectors 500. This design creates an independent modular structure between the motherboards and the adapter backplane 100. On the one hand, each motherboard can be installed or removed independently, facilitating system production assembly and field maintenance. On the other hand, the board-to-board connectors 500 provide a high-speed, low-latency signal transmission channel, ensuring reliable transmission of clock signals, control signals, bus signals, CPU interconnect signals, etc., between the adapter backplane 100 and each motherboard, providing a hardware connection foundation for dynamic switching between single-channel and multi-channel operating modes.

[0035] In another alternative implementation, please refer to Figure 2 Each motherboard also includes a clock buffer 240 and a PCIe (Peripheral Component Interconnect Express) device. In each motherboard, the input of the clock buffer 240 is connected to the output of the clock selector 220, and the first and second outputs of the clock buffer 240 are connected to the CPU and the PCIe device 250, respectively. The PCIe device 250 is connected to the CPU via a bus (such as a PCIe bus).

[0036] Understandably, since both the CPU and PCIe device 250 require a stable clock signal to function properly, and the PCIe bus protocol has high requirements for clock synchronization between the transmitting and receiving parties, this application first sends the clock signal output by the clock selector 220 into the clock buffer 240, and then the clock buffer 240 expands one clock input into multiple clock outputs, which are supplied to the CPU and PCIe device 250 respectively. This ensures that the CPU and PCIe device 250 on the same motherboard can obtain the same clock signal, effectively ensuring the reliability and signal integrity of PCIe bus communication.

[0037] To better understand the technical solution of this application, the following explanation uses two motherboards as an example: the clock distribution of the overall system supports both each motherboard forming a single-socket system independently and the two motherboards forming a dual-socket system together.

[0038] like Figure 2 As shown in this embodiment, the N motherboards include a first motherboard 300 and a second motherboard 400, and each motherboard is connected to the adapter backplane 100 via a board-to-board connector 500. The first motherboard 300 and the second motherboard 400 are of the same model, meaning they have the same hardware design, differing only in their installation positions within the adapter backplane 100.

[0039] The adapter backplane 100 also includes a bus link, a CPU interconnect link, a first internal clock link (i.e., Int_Ref_CLK1), and a second internal clock link (i.e., Int_Ref_CLK2).

[0040] The first controller 110 is connected to the second controller 230 of the first motherboard 300 and the second controller 230 of the second motherboard 400 via a bus link (such as an I2C bus). The CPUs of the first motherboard 300 and the second motherboard 400 are both connected to the adapter backplane 100, and the CPUs of the two motherboards are interconnected through the CPU interconnection link in the adapter backplane 100 (that is, the CPU of the first motherboard 300 is connected to the CPU of the second motherboard 400 through the CPU interconnection link in the adapter backplane 100).

[0041] The first output terminal of the clock generator 210 in the first motherboard 300 is connected to the local input terminal of the clock selector 220 of the motherboard 300 to provide a local clock signal to the clock selector 220 of the first motherboard 300. The second output terminal of the clock generator 210 in the first motherboard 300 is connected to the adapter backplane 100, and is connected to the common input terminal of the clock selector 220 in the second motherboard 400 through the first internal clock link in the adapter backplane 100 to provide a common clock signal to the clock selector 220 of the second motherboard 400.

[0042] The first output of the clock generator 210 in the second motherboard 400 is connected to the local input of the clock selector 220 of the motherboard 400 to provide a local clock signal to the clock selector 220 of the second motherboard 400. The second output of the clock generator 210 in the second motherboard 400 is connected to the adapter backplane 100, and is connected to the common input of the clock selector 220 in the first motherboard 300 through the second internal clock link in the adapter backplane 100 to provide a common clock signal to the clock selector 220 of the first motherboard 300.

[0043] The default operating mode of each motherboard is single-processor mode. That is, when each motherboard system is first powered on, regardless of whether the motherboard is in place (i.e., whether it is connected to the adapter backplane 100), the second controller 230 in the motherboard will output a first level (such as a low level) to the control terminal of the clock selector 220, so that the clock selector 220 selects the local clock signal and outputs it to the CPU, thereby operating independently in single-processor server mode.

[0044] When the first controller 110 receives a user-sent instruction to switch from single-channel to dual-channel operating mode, and confirms that both motherboards are in place, the first controller 110 sends a local strobe signal to the second controller 230 of the first motherboard 300 and a common strobe signal to the second controller 230 of the second motherboard 400. The second controller 230 of the first motherboard 300 outputs a first level (e.g., low level) to the clock selector 220 of its own motherboard according to the local strobe signal, causing the clock selector 220 to output the clock signal from its local input (i.e., the clock signal output by the clock generator 210 of the first motherboard 300) to the CPU of its own motherboard. The second controller 230 of the second motherboard 400 outputs a second level (e.g., high level) to the clock selector 220 of its own motherboard according to the common strobe signal, causing the clock selector 220 to output the clock signal from its common input (i.e., the clock signal output by the clock generator 210 of the first motherboard 300) to the CPU of its own motherboard. Ultimately, this forms the following... Figure 3 The dual-socket server system shown has two motherboards whose CPUs are interconnected via a backplane 100 and operate synchronously using a clock signal provided by the same clock generator 210. In this configuration, two motherboards are placed side-by-side in a chassis and connected via the backplane 100 to form a dual-socket server with two nodes.

[0045] When the first controller 110 receives a user-sent instruction to switch from dual-channel operating mode to single-channel operating mode, two scenarios occur: For currently active motherboards, the first controller 110 sends a local strobe signal to the second controller 230 of each active motherboard, enabling the CPU of each motherboard to resume using its own local clock; for currently inactive motherboards, although the first controller 110 cannot send a signal, since the motherboard is in single-channel operating mode by default upon power-up (i.e., the second controller 230 outputs the first level by default to control the clock selector 220 to select the local clock), the motherboard will automatically operate independently in single-channel operating mode after power-up. Ultimately, this results in the following: Figure 4 The single-processor server system shown in the diagram uses a local clock signal provided by the clock generator 210 of each of the two motherboards' CPUs. In this case, two motherboards are placed in a single chassis, forming a single-processor server with two nodes.

[0046] Therefore, since each motherboard in this application has an independent clock generator 210 and the default working mode is single-channel, the prerequisite for switching the system from single-channel to dual-channel working mode is that both motherboards are in place (i.e., both are connected to the adapter backplane 100), while the switch from dual-channel to single-channel working mode is not limited by the motherboard's in-place status.

[0047] To check the presence status of each motherboard, please refer again. Figure 2 In one optional implementation, the adapter backplane 100 further includes a first motherboard presence detection link (i.e., MB1_PRESENT_N) and a second motherboard presence detection link (i.e., MB2_PRESENT_N). The first motherboard 300 further includes a first upper bias circuit 310 and a first lower bias circuit 320, and the second motherboard 400 further includes a second upper bias circuit 410 and a second lower bias circuit 420.

[0048] The motherboard presence detection terminal of the second controller 230 in the first motherboard 300 is connected to one end of the first upper bias circuit 310, and the other end of the first upper bias circuit 310 is connected to the power supply VCC. The motherboard presence detection terminal of the second controller 230 in the first motherboard 300 is also connected to the adapter backplane 100, and is connected to one end of the second lower bias circuit 420 in the second motherboard 400 through the second motherboard presence detection link in the adapter backplane 100. The other end of the second lower bias circuit 420 is grounded.

[0049] The motherboard presence detection terminal of the second controller 230 in the second motherboard 400 is connected to one end of the second upper bias circuit 410, and the other end of the second upper bias circuit 410 is connected to the power supply VCC. The motherboard presence detection terminal of the second controller 230 in the second motherboard 400 is also connected to the adapter backplane 100, and is connected to one end of the first lower bias circuit 320 in the first motherboard 300 through the first motherboard presence detection link in the adapter backplane 100. The other end of the first lower bias circuit 320 is grounded.

[0050] The second controller 230 of the first motherboard 300 is used to determine whether the second motherboard 400 is in place under the action of the first upper bias circuit 310 and the second lower bias circuit 420.

[0051] The second controller 230 of the second motherboard 400 is used to determine whether the first motherboard 300 is in place under the action of the second upper bias circuit 410 and the first lower bias circuit 320.

[0052] Optionally, the first upper bias circuit 310 includes a fifth pull-up resistor Rp5, the first lower bias circuit 320 includes a fourth pull-down resistor Rd4, the second upper bias circuit 410 includes a sixth pull-up resistor Rp6, and the second lower bias circuit 420 includes a fifth pull-down resistor Rd5. The resistance value of the pull-up resistor is greater than the resistance value of the pull-down resistor.

[0053] Taking the first motherboard 300 detecting whether the second motherboard 400 is in place as an example, the specific working principle is as follows: When both motherboards are in place, the motherboard presence detection terminal of the second controller 230 in the first motherboard 300 is pulled down to a low level by the fifth pull-down resistor Rd5 (i.e., the second down-bias circuit 420) on the second motherboard 400. At this time, the second controller 230 in the first motherboard 300 determines that both the first motherboard 300 and the second motherboard 400 are in place. Similarly, the motherboard presence detection terminal of the second controller 230 in the second motherboard 400 is pulled down to a low level by the fourth pull-down resistor Rd4 (i.e., the first down-bias circuit 320) on the first motherboard 300. At this time, the second controller 230 in the second motherboard 400 determines that both the first motherboard 300 and the second motherboard 400 are in place.

[0054] When only one motherboard is present, for example, the first motherboard 300 is present while the second motherboard 400 is not. In this case, the motherboard presence detection terminal of the second controller 230 in the first motherboard 300 is pulled high by the fifth pull-up resistor Rp5 (i.e., the first upper bias circuit 310) on the first motherboard 300. At this time, the second controller 230 in the first motherboard 300 determines that the second motherboard 400 is not present, and vice versa.

[0055] Furthermore, the adapter backplane 100 also includes a third upper bias circuit 120. The first motherboard presence detection terminal of the first controller 110 is connected to the first motherboard presence detection link, and the second motherboard presence detection terminal of the first controller 110 is connected to the second motherboard presence detection link. One end of the third upper bias circuit 120 is connected to both the first and second motherboard presence detection terminals of the first controller 110, and the other end of the third upper bias circuit 120 is connected to the power supply VCC.

[0056] The first controller 110 is used to determine whether the first motherboard 300 is in place under the action of the third upper bias circuit 120 and the first lower bias circuit 320.

[0057] The first controller 110 is also used to determine whether the second motherboard 400 is in place under the action of the third upper bias circuit 120 and the second lower bias circuit 420.

[0058] Optionally, the third upper bias circuit 120 includes a seventh pull-up resistor Rp7 and an eighth pull-up resistor Rp8. One end of the seventh pull-up resistor Rp7 is connected to the first motherboard presence detection terminal of the first controller 110, one end of the eighth pull-up resistor Rp8 is connected to the second motherboard presence detection terminal of the first controller 110, and the other ends of both the seventh pull-up resistor Rp7 and the eighth pull-up resistor Rp8 are connected to the power supply VCC.

[0059] The working principle of the first controller 110 in detecting whether each motherboard is in place is as follows: When both motherboards are in place, the first motherboard presence detection terminal of the first controller 110 is pulled low by the fourth pull-down resistor Rd4 on the first motherboard 300, thus determining that the first motherboard 300 is in place; the second motherboard presence detection terminal of the first controller 110 is pulled low by the fifth pull-down resistor Rd5 on the second motherboard 400, thus determining that the second motherboard 400 is in place.

[0060] When the first motherboard 300 is in place and the second motherboard 400 is not in place, the first motherboard presence detection terminal of the first controller 110 is pulled low by the fourth pull-down resistor Rd4 on the first motherboard 300, thus determining that the first motherboard 300 is in place; the second motherboard presence detection terminal of the first controller 110 is pulled high by the eighth pull-up resistor Rp8 on the adapter backplane 100, thus determining that the second motherboard 400 is not in place.

[0061] When the first motherboard 300 is not in place and the second motherboard 400 is in place, the first motherboard presence detection terminal of the first controller 110 is pulled high by the seventh pull-up resistor Rp7 on the adapter backplane 100, thus determining that the first motherboard 300 is not in place; the second motherboard presence detection terminal of the first controller 110 is pulled low by the fifth pull-down resistor Rd5 on the second motherboard 400, thus determining that the second motherboard 400 is in place.

[0062] When neither motherboard is in place, the first motherboard presence detection terminal of the first controller 110 is pulled high by the seventh pull-up resistor Rp7 on the adapter backplane 100, thus determining that the first motherboard 300 is not in place; the second motherboard presence detection terminal of the first controller 110 is pulled high by the eighth pull-up resistor Rp8 on the adapter backplane 100, thus determining that the second motherboard 400 is not in place.

[0063] After the two motherboards are in place, each motherboard needs to be configured with a unique ID identifier in order to confirm its position in the system. In view of this, in an optional implementation, the first motherboard 300 is further provided with a first ID setting circuit 330, the second motherboard 400 is further provided with a second ID setting circuit 430, and the adapter backplane 100 is further provided with a third ID setting circuit 130 and a fourth ID setting circuit 140.

[0064] The ID terminal of the second controller 230 in the first motherboard 300 is connected to one end of the first ID setting circuit 330, and the other end of the first ID setting circuit 330 is connected to the power supply VCC. The ID terminal of the second controller 230 in the first motherboard 300 is also connected to one end of the third ID setting circuit 130 in the adapter backplane 100, and the other end of the third ID setting circuit 130 is grounded.

[0065] The ID terminal of the second controller 230 in the second motherboard 400 is connected to one end of the second ID setting circuit 430, and the other end of the second ID setting circuit 430 is connected to the power supply VCC. The ID terminal of the second controller 230 in the second motherboard 400 is also connected to one end of the fourth ID setting circuit 140 in the adapter backplane 100, and the other end of the fourth ID setting circuit 140 is grounded.

[0066] The second controller 230 of the first motherboard 300 is used to identify the ID value of the first motherboard 300 when it is in place, under the action of the first ID setting circuit 330 and the third ID setting circuit 130.

[0067] The second controller 230 of the second motherboard 400 is used to identify the ID value of the second motherboard 400 when it is in place, under the action of the second ID setting circuit 430 and the fourth ID setting circuit 140.

[0068] The ID value of the first motherboard 300 when it is in place is different from the ID value of the second motherboard 400 when it is in place.

[0069] In an optional embodiment, the adapter backplane 100 further includes a first motherboard ID0 link (i.e., MB1_ID0), a first motherboard ID1 link (i.e., MB1_ID1), a second motherboard ID0 link (i.e., MB2_ID0), and a second motherboard ID1 link (i.e., MB2_ID1). The first ID setting circuit 330 includes a first pull-up resistor Rp1 and a second pull-up resistor Rp2, the second ID setting circuit 430 includes a third pull-up resistor Rp3 and a fourth pull-up resistor Rp4, the third ID setting circuit 130 includes a first pull-down resistor Rd1 and a second pull-down resistor Rd2, and the fourth ID setting circuit 140 includes a third pull-down resistor Rd3.

[0070] In the first motherboard 300, the ID1 and ID0 terminals of the second controller 230 are respectively connected to one end of the first pull-up resistor Rp1 and the second pull-up resistor Rp2. The other ends of the first pull-up resistor Rp1 and the second pull-up resistor Rp2 are both connected to the power supply VCC. The ID1 terminal of the second controller 230 in the first motherboard 300 is also connected to one end of the first pull-down resistor Rd1 through the first motherboard ID1 link in the adapter backplane 100. The ID0 terminal of the second controller 230 in the first motherboard 300 is also connected to one end of the second pull-down resistor Rd2 through the first motherboard ID0 link in the adapter backplane 100. The other ends of the first pull-down resistor Rd1 and the second pull-down resistor Rd2 are both grounded.

[0071] In the second motherboard 400, the ID1 and ID0 terminals of the second controller 230 are connected to one end of the third pull-up resistor Rp3 and the fourth pull-up resistor Rp4, respectively. The other ends of both the third and fourth pull-up resistors Rp3 and Rp4 are connected to the power supply VCC. The ID1 terminal of the second controller 230 in the second motherboard 400 is also connected to one end of the third pull-down resistor Rd3 via the second motherboard ID1 link in the adapter backplane 100. The other end of the third pull-down resistor Rd3 is grounded. The ID0 terminal of the second controller 230 in the second motherboard 400 is also connected to one end of the second motherboard ID0 link in the adapter backplane 100. The other end of the second motherboard ID0 link is floating (neither connected to a pull-up nor a pull-down resistor).

[0072] When the first motherboard 300 is in place, the ID1 and ID0 terminals of the second controller 230 in the first motherboard 300 are pulled low to a low level (i.e., ID1=0, ID0=0) by the first pull-down resistor Rd1 and the second pull-down resistor Rd2 on the adapter backplane 100, respectively. At this time, the second controller 230 in the first motherboard 300 recognizes that the ID value of the first motherboard 300 is 00.

[0073] When the second motherboard 400 is in place, the ID1 terminal of the second controller 230 in the second motherboard 400 is pulled low by the third pull-down resistor Rd3 on the adapter backplane 100, and the ID0 terminal of the second controller 230 in the second motherboard 400 is pulled high by the fourth pull-up resistor Rp4 on the second motherboard 400 (i.e., ID1=0, ID0=1). At this time, the second controller 230 in the second motherboard 400 recognizes that the ID value of the second motherboard 400 is 01.

[0074] As can be seen, this application assigns a unique ID value to motherboards in different slots by setting pull-up resistors on the motherboard and pull-down resistors on the adapter backplane 100, thereby realizing automatic hardware identification of motherboard slots and laying the foundation for flexible control of subsequent clock allocation paths.

[0075] Based on the above design, the following section uses two motherboards as an example to explain the entire working process of the server clock topology switching system.

[0076] First, after the system is powered on, each motherboard operates independently in single-processor mode by default.

[0077] like Figure 5 As shown, when the first controller 110 receives a remote instruction from the user to switch from single-channel to dual-channel operating mode, the first controller 110 notifies the second controller 230 on each motherboard via the I2C bus, and the second controller 230 controls its respective motherboard system to power down. After the system completes the power-down and power-on, the second controller 230 of each motherboard first checks the ID value of its motherboard. If the second controller 230 detects that its own motherboard ID value is 00 (i.e., the first motherboard 300), it outputs a first level (such as a low level) to control the clock selector 220 to select the local clock provided by the motherboard clock generator 210 and output it to the CPU; if the second controller 230 detects that its own motherboard ID value is not 00 (i.e., the second motherboard 400), it further checks whether its own motherboard presence detection terminal is low. If the motherboard presence detection terminal is low, it indicates that both the first motherboard 300 and the second motherboard 400 are present. The second controller 230 then outputs a second level (e.g., high level) to control the clock selector 220 to select the common clock provided by the clock generator 210 of the first motherboard 300 and output it to the CPU. If the motherboard presence detection terminal is high, it indicates that the first motherboard 300 is not present. The second controller 230 then outputs a first level (e.g., low level) to control the clock selector 220 to select the local clock and output it to the CPU. After the clock path configuration is complete, the second controller 230 releases the CPU from its reset state, the CPU begins initialization, and the motherboard system starts and runs normally.

[0078] like Figure 6As shown, when the first controller 110 receives a remote instruction from the user to switch from dual-channel to single-channel operation mode, the first controller 110 notifies the second controller 230 on each motherboard via the I2C bus. The second controller 230 then controls its respective motherboard system to power down. After the system powers on again, the second controller 230 outputs a first level (e.g., low level) to control the clock selector 220 to select the local clock provided by the motherboard clock generator 210 and output it to the CPU. After the clock path configuration is complete, the second controller 230 releases the CPU from its reset state, the CPU begins initialization, and the motherboard system starts up and runs normally.

[0079] In summary, the server clock topology switching system provided in this application achieves flexible switching between single-processor and multi-processor operating modes through the coordinated operation of a first controller on the adapter backplane and a second controller on each motherboard, combined with motherboard presence detection and motherboard ID recognition mechanisms. In multi-processor mode, the system automatically identifies and designates a specific motherboard (e.g., the one with the smallest ID value) as the clock source, and the remaining motherboards synchronously follow this clock source, ensuring that the clock signals of each CPU in the multi-processor system are in phase and frequency. In single-processor mode, each motherboard operates independently using its local clock and is unaffected by the presence status of other motherboards. This application effectively improves the flexibility and reliability of the server system clock topology, supports dynamic switching between single-processor and multi-processor operating modes, covers more application scenarios, reduces hardware development costs, and shortens time-to-market.

[0080] Based on the above system concept, please refer to Figure 7 In an optional implementation, this application also provides a server clock topology switching method, which is applied to a server clock topology switching system as described in any of the foregoing embodiments. The method includes the following steps: Step S10: When the first controller receives the instruction to switch to N-channel working mode and confirms that all motherboards are in place, the first controller sends a local strobe signal to the second controller of the i-th motherboard, so that the CPU of the i-th motherboard uses the clock signal provided by the clock generator of this motherboard; and sends a common strobe signal to the second controllers of the other motherboards, so that the CPUs of the other motherboards all use the clock signal provided by the clock generator of the i-th motherboard.

[0081] In step S20, when the first controller receives the instruction to switch to single-channel working mode, the first controller sends a local strobe signal to the second controller of each in-situ motherboard, so that the CPU of each motherboard uses the clock signal provided by the clock generator of its respective motherboard.

[0082] For specific limitations on server clock topology switching methods, please refer to the limitations on server clock topology switching systems mentioned above, which will not be repeated here.

[0083] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0084] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A server clock topology switching system, characterized in that, It includes an adapter backplane and N motherboards, each motherboard being connected to the adapter backplane; the adapter backplane is equipped with a first controller, and each motherboard is equipped with a clock generator, a clock selector, a second controller, and a CPU; The first controller is connected to the second controller of each motherboard, and the CPUs of all motherboards are interconnected through the adapter backplane. In each motherboard, the output of the second controller is connected to the control terminal of the clock selector, the output of the clock selector is connected to the CPU, the first output of the clock generator is connected to the local input terminal of the clock selector, and the second output of the clock generator is connected to the corresponding common input terminal of the clock selector in the other motherboards through the adapter backplane. When the first controller receives the instruction to switch to N-channel working mode and confirms that all motherboards are in place, the first controller sends a local strobe signal to the second controller of the i-th motherboard, so that the CPU of the i-th motherboard uses the clock signal provided by the clock generator of this motherboard. It also sends a common strobe signal to the second controller of the other motherboards, so that the CPUs of the other motherboards all use the clock signal provided by the clock generator of the i-th motherboard; where 1≤i≤N, N≥2; When the first controller receives a command to switch to single-channel operating mode, the first controller sends a local strobe signal to the second controller of each in-situ motherboard, so that the CPU of each motherboard uses the clock signal provided by the clock generator of its respective motherboard. The N motherboards include a first motherboard and a second motherboard. The adapter backplane is also provided with a CPU interconnect link, a first internal clock link, a second internal clock link, a first motherboard presence detection link, and a second motherboard presence detection link. The first motherboard is also provided with a first upper bias circuit and a first lower bias circuit, and the second motherboard is also provided with a second upper bias circuit and a second lower bias circuit. The CPU of the first motherboard is connected to the CPU of the second motherboard through the CPU interconnect link in the adapter backplane; the second output terminal of the clock generator in the first motherboard is connected to the common input terminal of the clock selector in the second motherboard through the first internal clock link in the adapter backplane; the second output terminal of the clock generator in the second motherboard is connected to the common input terminal of the clock selector in the first motherboard through the second internal clock link in the adapter backplane. The motherboard presence detection terminal of the second controller in the first motherboard is connected to one end of the first upper bias circuit, and the other end of the first upper bias circuit is connected to the power supply; the motherboard presence detection terminal of the second controller in the first motherboard is also connected to one end of the second lower bias circuit in the second motherboard through the second motherboard presence detection link in the adapter backplane, and the other end of the second lower bias circuit is grounded. The motherboard presence detection terminal of the second controller in the second motherboard is connected to one end of the second upper bias circuit, and the other end of the second upper bias circuit is connected to the power supply; the motherboard presence detection terminal of the second controller in the second motherboard is also connected to one end of the first lower bias circuit in the first motherboard through the first motherboard presence detection link in the adapter backplane, and the other end of the first lower bias circuit is grounded. The second controller of the first motherboard is used to determine whether the second motherboard is in place under the action of the first upper bias circuit and the second lower bias circuit; The second controller of the second motherboard is used to determine whether the first motherboard is in place under the action of the second upper bias circuit and the first lower bias circuit.

2. The server clock topology switching system according to claim 1, characterized in that, The default operating mode for each motherboard is single-socket operation. When the first controller receives an instruction to switch from single-channel to dual-channel operation mode and confirms that both motherboards are in place, the first controller sends a local strobe signal to the second controller of the first motherboard and a common strobe signal to the second controller of the second motherboard. The second controller of the first motherboard outputs a first level to the clock selector of its own motherboard according to the local strobe signal, so that the clock selector outputs the clock signal at the local input terminal to the CPU of its own motherboard. The second controller of the second motherboard outputs a second level to the clock selector of its own motherboard according to the common strobe signal, so that the clock selector outputs the clock signal at the common input terminal to the CPU of its own motherboard. When the first controller receives a command to switch from dual-channel operating mode to single-channel operating mode, the first controller sends a local strobe signal to the second controller of all in-situ motherboards so that each motherboard can resume using its own local clock.

3. The server clock topology switching system according to claim 1, characterized in that, The adapter backplate is also provided with a third upper bias circuit; The first motherboard presence detection terminal of the first controller is connected to the first motherboard presence detection link, and the second motherboard presence detection terminal of the first controller is connected to the second motherboard presence detection link; one end of the third upper bias circuit is connected to the first motherboard presence detection terminal and the second motherboard presence detection terminal of the first controller respectively, and the other end of the third upper bias circuit is connected to the power supply. The first controller is used to determine whether the first motherboard is in place under the action of the third upper bias circuit and the first lower bias circuit; The first controller is also used to determine whether the second motherboard is in place under the action of the third upper bias circuit and the second lower bias circuit.

4. The server clock topology switching system according to claim 1, characterized in that, The first motherboard is also provided with a first ID setting circuit, the second motherboard is also provided with a second ID setting circuit, and the adapter backplane is also provided with a third ID setting circuit and a fourth ID setting circuit. The ID terminal of the second controller in the first motherboard is connected to one end of the first ID setting circuit, and the other end of the first ID setting circuit is connected to the power supply. The ID terminal of the second controller in the first motherboard is also connected to one end of the third ID setting circuit in the adapter backplane, and the other end of the third ID setting circuit is grounded. The ID terminal of the second controller in the second motherboard is connected to one end of the second ID setting circuit, and the other end of the second ID setting circuit is connected to the power supply. The ID terminal of the second controller in the second motherboard is also connected to one end of the fourth ID setting circuit in the adapter backplane, and the other end of the fourth ID setting circuit is grounded. The second controller of the first motherboard is used to identify the ID value of the first motherboard when it is in place, under the action of the first ID setting circuit and the third ID setting circuit. The second controller of the second motherboard is used to identify the ID value of the second motherboard when it is in place, under the action of the second ID setting circuit and the fourth ID setting circuit. The ID value of the first motherboard when it was in place was different from the ID value of the second motherboard when it was in place.

5. The server clock topology switching system according to claim 4, characterized in that, The adapter backplane is also provided with a first motherboard ID0 link, a first motherboard ID1 link, a second motherboard ID0 link, and a second motherboard ID1 link; the first ID setting circuit includes a first pull-up resistor and a second pull-up resistor, the second ID setting circuit includes a third pull-up resistor and a fourth pull-up resistor, the third ID setting circuit includes a first pull-down resistor and a second pull-down resistor, and the fourth ID setting circuit includes a third pull-down resistor. In the first motherboard, the ID1 and ID0 terminals of the second controller are respectively connected to one end of the first pull-up resistor and the second pull-up resistor, and the other ends of the first pull-up resistor and the second pull-up resistor are both connected to the power supply; the ID1 terminal of the second controller in the first motherboard is also connected to one end of the first pull-down resistor through the first motherboard ID1 link in the adapter backplane, and the ID0 terminal of the second controller in the first motherboard is also connected to one end of the second pull-down resistor through the first motherboard ID0 link in the adapter backplane, and the other ends of the first pull-down resistor and the second pull-down resistor are both grounded; In the second motherboard, the ID1 and ID0 terminals of the second controller are respectively connected to one end of the third pull-up resistor and the fourth pull-up resistor, and the other ends of the third pull-up resistor and the fourth pull-up resistor are both connected to the power supply; the ID1 terminal of the second controller in the second motherboard is also connected to one end of the third pull-down resistor through the second motherboard ID1 link in the adapter backplane, and the other end of the third pull-down resistor is grounded; the ID0 terminal of the second controller in the second motherboard is also connected to one end of the second motherboard ID0 link in the adapter backplane, and the other end of the second motherboard ID0 link is floating. When the first motherboard is in place, the second controller in the first motherboard recognizes that the ID value of the first motherboard is 00; When the second motherboard is in place, the second controller in the second motherboard recognizes that the ID value of the second motherboard is 01.

6. The server clock topology switching system according to claim 1, characterized in that, Each motherboard also includes a clock buffer and PCIe devices; In each motherboard, the input of the clock buffer is connected to the output of the clock selector, and the first and second outputs of the clock buffer are connected to the CPU and the PCIe device, respectively. The PCIe device is connected to the CPU via a bus.

7. The server clock topology switching system according to claim 1, characterized in that, The server clock topology switching system also includes board-to-board connectors; the adapter backplane is detachably connected to N motherboards via the board-to-board connectors.

8. A server clock topology switching method, characterized in that, Applied to the server clock topology switching system as described in any one of claims 1-7, the method comprises: When the first controller receives the instruction to switch to N-channel working mode and confirms that all motherboards are in place, the first controller sends a local strobe signal to the second controller of the i-th motherboard, so that the CPU of the i-th motherboard uses the clock signal provided by the clock generator of this motherboard; and sends a common strobe signal to the second controllers of the other motherboards, so that the CPUs of the other motherboards all use the clock signal provided by the clock generator of the i-th motherboard. When the first controller receives a command to switch to single-channel operating mode, it sends a local strobe signal to the second controller of each in-situ motherboard, so that the CPU of each motherboard uses the clock signal provided by the clock generator of its respective motherboard.

Images