Method and control means for reducing read command latency with early crc check

Abstract

This application provides a method and control component for reducing read command latency through early CRC checksum verification, relating to the field of storage devices. The data path for the control component to read data from an NVM chip includes: a first CRC checksum unit and a decoding circuit; the first CRC checksum unit is coupled to the host and the decoding circuit, respectively; in response to receiving a data frame read from the NVM chip by the control component, the first CRC checksum unit verifies a first data unit in the data frame using a first CRC checksum in the data frame; in response to successful verification, determining that the first data unit is error-free, the first data unit is not sent to the decoding circuit for LDPC decoding, but is directly sent to the host. By performing CRC checksum verification on the data unit read from the NVM chip before decoding, and directly sending the data unit to the host upon successful verification, the control component can reduce the latency of processing read commands.

Description

Technical Field

[0001] This application relates to the field of storage devices, and in particular to a method and control component for reducing read command latency through early CRC check. Background Technology

[0002] Figure 1A A block diagram of a solid-state storage device (SSD) is shown. The SSD 102 is coupled to a host computer to provide storage capabilities. The host computer and the SSD 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Solid-state storage device 102 (hereinafter referred to as storage device) includes interface 103, control unit 104, one or more NVM chips 105 and DRAM (Dynamic Random Access Memory) 110.

[0003] The aforementioned NVM chip 105 includes NAND flash memory, phase-change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc., which are common storage media.

[0004] The aforementioned interface 103 can be adapted to exchange data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The aforementioned control unit 104 is used to control data transmission between interface 103, NVM chip 105, and DRAM 110, and is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. Control unit 104 can be implemented in various ways, including software, hardware, firmware, or combinations thereof. For example, control unit 104 can be in the form of an FPGA (Field-programmable gate array), ASIC (Application Specific Integrated Circuit), or a combination thereof. Control unit 104 may also include a processor or controller, in which software is executed to manipulate the hardware of control unit 104 to process I / O (Input / Output) commands. Control unit 104 can also be coupled to DRAM 110 and can access data in DRAM 110. FTL tables and / or cached I / O command data can be stored in DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] The host accesses storage device 102 using I / O commands that conform to the storage protocol. The control unit 104 generates one or more media interface commands based on the I / O commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) that conform to the interface protocol of the NVM chip based on the media interface commands. The control unit also tracks the completion of all media interface commands generated from an I / O command and indicates the processing results of the I / O commands to the host.

[0008] Figure 1B A schematic diagram of the control component is shown. (See attached image.) Figure 1BThe control unit 104 includes a host interface 1041, a host command processing unit 1042, a storage command processing unit 1043, a media interface controller 1044, and a storage media management unit 1045. The host interface 1041 receives I / O commands from the host. The host command processing unit 1042 generates storage commands based on the I / O commands and provides them to the storage command processing unit 1043. Each storage command can access a storage space of the same size, such as 4KB. The data accessed by a storage command, recorded in the NVM chip, is called a data unit. A physical page records one or more data units. For example, if the physical page size is 17664 bytes and the data unit size is 4KB, then one physical page can store four data units.

[0009] The storage media management unit 1045 maintains the translation from logical address to physical address for each storage command. For example, the storage media management unit 1045 includes an FTL table (explained below). For a read command, the storage media management unit 1045 outputs the physical address corresponding to the logical address (LBA) accessed by the storage command. For a write command, the storage media management unit 1045 allocates an available physical address and records the mapping relationship between the accessed logical address (LBA) and the allocated physical address. The storage media management unit 1045 also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling. The FTL (Flash Translation Layer) table maintains the mapping information from logical address (LBA) to physical address. Logical addresses constitute the storage space of the solid-state storage device as perceived by upper-layer software such as the operating system. Physical addresses are the addresses used to access the physical storage units of the solid-state storage device. In related technologies, address mapping can also be implemented using intermediate address formats. For example, a logical address can be mapped to an intermediate address, and then the intermediate address can be further mapped to a physical address. The table structure that stores the mapping information from logical addresses to physical addresses is called the FTL table. The FTL table is important metadata in storage devices. The data items in the FTL table record the address mapping relationships in the storage device, with each data unit as a unit.

[0010] The storage command processing unit 1043, based on the physical address provided by the storage media management unit 1045, operates the media interface controller 1044 to send a storage media access command to the NVM chip 105.

[0011] For clarity, commands sent from the host to storage device 102 are called I / O commands (including, for example, NVMe read commands and NVMe write commands); commands sent from host command processing unit 1042 to storage command processing unit 1043 are called storage commands; commands sent from storage command processing unit 1043 to media interface controller 1044 are called media interface commands; and commands sent from media interface controller 1044 to NVM chip 105 are called storage media access commands. Storage media access commands conform to the NVM chip's interface protocol.

[0012] Data stored in NVM chips is susceptible to corruption to some extent. To overcome this, error-correcting codes (ECC, used to detect and correct errors in data transmission) are typically used to protect the data stored on the NVM chip when accessing it. Commonly used error-correcting codes include BCH (Bose–Chaudhuri–Hocquenghem codes), LDPC (Low-density Parity-check) codes, and RS (Reed-Solomon) codes, with LDPC codes being the most widely used error-correcting code in modern solid-state storage devices. Figure 2A As shown, to utilize LDPC codes, the control unit includes an LDPC encoder and an LDPC decoder. When the control unit writes data to the NVM chip, the LDPC encoder encodes the data to be written, generating a checksum (called an LDPC checksum) corresponding to the data to be written (hereinafter referred to as a data unit, which is data of a specified size, such as 512 bytes, 1KB, 2KB, 4KB, etc.). The data unit and the LDPC checksum are then written together into the NVM chip. When the control unit reads data from the NVM chip, the read data (including the data unit and the LDPC checksum) is provided to the LDPC decoder for decoding. During the decoding process, the LDPC checksum is used to correct erroneous bits in the data unit, resulting in the decoded data.

[0013] LDPC encoding exhibits an error floor characteristic. An error floor refers to a low-error-rate region where the frame error rate (FER) tends to a non-zero constant, and increasing the strength of the error correction code (ECC) cannot further reduce the error rate. In error floor regions, the LDPC decoder may be unable to effectively identify and correct certain error patterns. To ensure the reliability of data stored in solid-state storage devices, additional verification is provided in the control unit using error check codes different from LDPC encoding. For example, a data verification mode combining LDPC encoding and CRC encoding is commonly used in the control unit. Alternatively, CRC encoding can be replaced by other error check codes such as BCH codes or Reed-Solomon codes, using a data verification mode combining LDPC encoding with, for example, BCH codes or RS codes. Figure 2B As shown, compared to Figure 2A The control components shown Figure 2B The control unit shown has been augmented with a CRC encoding unit and a CRC check unit. When the control unit writes data to the NVM chip, it first uses the CRC encoding unit to perform CRC encoding on the data unit, generating a CRC checksum. The LDPC encoder then performs LDPC encoding on the data unit and the CRC checksum as a whole, generating an LDPC checksum, and writes the data unit, CRC checksum, and LDPC checksum together into the NVM chip. In this structure, the LDPC checksum corresponds to the combination of the data unit and the CRC checksum, protecting both the data unit and the CRC checksum, while the CRC checksum corresponds only to the data unit.

[0014] When the control unit reads data from the NVM chip, the read data includes data units, CRC checksums, and LDPC checksums (hereinafter, the combination of data units, CRC checksums, and LDPC checksums is referred to as a data frame). The LDPC decoder performs LDPC decoding on the read data frame, obtaining the decoded data units and CRC checksums. If the LDPC decoder indicates successful decoding, the CRC checksum unit then checks the decoded data units and CRC checksums to identify any errors. If the CRC checksum unit succeeds, it means the data units are correct. If the CRC checksum unit fails, it means the decoded data units still contain errors, and these errors cannot be corrected by the LDPC decoder. Therefore, other methods such as RAID or read-redo are needed to attempt to obtain the correct data.

[0015] Among various error check codes, LDPC codes exhibit superior performance and are therefore widely used. However, LDPC codes are also complex, introducing a latency of approximately several hundred nanoseconds to 1 microsecond for both writing and reading data from the NVM chip. When processing write I / O commands from the host, write caching techniques can partially conceal this latency. However, the latency for reading data from the NVM chip cannot be concealed when processing read I / O commands from the host. Therefore, the latency for processing write I / O commands in solid-state storage devices is generally higher than that for processing read I / O commands. Consequently, it is necessary to reduce the latency of processing read I / O commands. Summary of the Invention

[0016] To solve the above-mentioned technical problems, or at least partially solve them, embodiments of this application provide a method and control component for reducing read command latency through advance CRC check.

[0017] In a first aspect, embodiments of this application provide a control component, wherein the data path through which the control component reads data from the NVM chip includes: a first CRC check unit and a decoding circuit;

[0018] The first CRC check unit is coupled to the host of the decoding circuit and the control component respectively. In response to receiving a data frame read from the NVM chip by the control component, the first CRC check unit uses the first CRC check code in the data frame to check the first data unit in the data frame. In response to successful check, it is determined that the first data unit has no error, and the first data unit is not sent to the decoding circuit for LDPC decoding, but is directly sent to the host.

[0019] Optionally, the decoding circuit includes an LDPC decoder and a second CRC check unit;

[0020] In response to a verification failure, the first CRC verification unit sends the data frame to the LDPC decoder;

[0021] The LDPC decoder is coupled to the first CRC check unit and the second CRC check unit respectively. In response to receiving the data frame, the LDPC decoder uses the first LDPC check code in the data frame to perform LDPC decoding on the first data unit and the first CRC check code as a whole to obtain the decoded first data unit and the decoded first CRC check code, and sends the decoded first data unit and the decoded first CRC check code to the second CRC check unit.

[0022] The second CRC check unit is coupled to the host computer that is coupled to the LDPC decoder and the control unit; in response to receiving the decoded first data unit and the decoded first CRC check code, the second CRC check unit uses the decoded first CRC check code to check the decoded first data unit, and in response to successful check, sends the decoded first data unit to the host computer.

[0023] Optionally, the data frame read by the control unit from the NVM chip includes N second data units, N second LDPC check codes, and one second CRC check code; the N second data units correspond one-to-one with the N second LDPC check codes; N is an integer greater than or equal to 2; the sum of the sizes of the N second data units is equal to the size of the first data unit, and the second CRC check code is obtained by performing CRC encoding on the N second data units as a whole.

[0024] Optionally, in response to receiving the data frame, the first CRC check unit verifies the N second data units as a whole using the second CRC check code in the data frame; in response to the successful verification of the N second data units as a whole, the first CRC check unit sends the N second data units as a whole to the host.

[0025] Optionally, in response to the overall verification failure of the N second data units, the data frame is sent to the LDPC decoder;

[0026] In response to receiving the data frame, the LDPC decoder performs LDPC decoding on each second data unit, using the second LDPC check code corresponding to the second data unit as a whole, and the second data unit and the second CRC check code in the data frame as a whole, to obtain a set of decoded data. The N sets of decoded data corresponding to the N second data units are sent to the second CRC check unit. Each set of decoded data includes the decoded second data unit and the decoded second CRC check code.

[0027] In response to receiving the N sets of decoded data, the second CRC check unit uses the decoded second CRC check code in each set of decoded data to check the decoded second data unit. In response to all N decoded second data units being successfully checked, the N decoded second data units are sent to the host as a whole.

[0028] Optionally, the N second data units include 4 second data units, and the N second LDPC check codes include 4 second LDPC check codes;

[0029] In response to receiving the data frame, the first CRC check unit verifies the four second data units as a whole using the second CRC check code; in response to successful verification, it sends the four second data units as a whole to the host.

[0030] Optionally, in response to the overall verification failure of the four second data units, the first CRC verification unit sends the data frame to the LDPC decoder;

[0031] In response to receiving the data frame, the LDPC decoder performs LDPC decoding on each second data unit, using the second LDPC check code corresponding to the second data unit as a whole, and the second data unit and the second CRC check code in the data frame as a whole, to obtain a set of decoded data. The four sets of decoded data corresponding to the four second data units are sent to the second CRC check unit. Each set of decoded data includes the decoded second data unit and the decoded second CRC check code.

[0032] In response to receiving the four sets of decoded data, the second CRC check unit uses the decoded second CRC check code in each set of decoded data to check the decoded second data unit. In response to all four decoded second data units being successfully checked, the unit sends the whole of the four decoded second data units to the host.

[0033] Optionally, the data path through which the control unit writes data to the NVM chip includes a CRC encoding unit and an LDPC encoder;

[0034] In response to receiving a data unit sent by the host, the CRC encoding unit performs CRC encoding on the received data unit, generates a CRC check code, and sends the data unit and the CRC check code to the LDPC encoder.

[0035] In response to receiving the data unit and the CRC checksum, the LDPC encoder encodes the data unit and the CRC checksum as a whole using LDPC encoding to generate an LDPC checksum, and writes the data frame formed by the data unit, the CRC checksum, and the LDPC checksum into the NVM chip.

[0036] Optionally, the data path for the control unit to write data to the NVM chip further includes a randomizer, which uses a randomization seed to randomize the received data; or, it uses a randomization seed to randomize the randomization seed and the received data as a whole.

[0037] The data path for controlling the reading of data from the NVM chip also includes a derandomization unit, which uses a randomization seed to derandomize the received data.

[0038] Optionally, the randomizer is coupled to the CRC encoding unit, and the derandomization unit is coupled to the first CRC check unit and the second CRC check unit, respectively.

[0039] In response to receiving a data unit sent by the host, the randomizer randomizes the received data unit using a randomization seed to obtain a new data unit, and sends the new data unit and the randomization seed to the CRC encoding unit; or, it randomizes the randomization seed and the received data unit as a whole using a randomization seed to obtain a new data unit, and sends the new data unit and the randomization seed to the CRC encoding unit.

[0040] In response to receiving a data unit and a randomization seed, the CRC encoding unit encodes the received data unit and randomization seed as a whole according to a specified encoding method, generates a CRC check code, and sends the received data unit, randomization seed, and the CRC check code to the LDPC encoder.

[0041] The LDPC encoder, in response to receiving a data unit, a randomization seed, and a CRC checksum, performs LDPC encoding on the received data unit, randomization seed, and CRC checksum as a whole to obtain an LDPC checksum, and writes the data frame formed by the received data unit, randomization seed, CRC checksum, and LDPC checksum into the NVM chip, or writes the data frame formed by the received data unit, randomization seed, CRC checksum, and LDPC checksum into the NVM chip.

[0042] The first CRC check unit receives a data frame read from the NVM chip by the control unit. If the data frame includes a randomization seed, it uses the CRC checksum in the data frame to check the randomization seed and the data unit in the data frame as a whole. Alternatively, if the data frame does not include a randomization seed, it determines the randomization seed corresponding to the data unit in the data frame and checks the data unit and the randomization seed corresponding to the data unit as a whole. In response to a successful check, the randomization seed and the data unit in the data frame are sent to the derandomization unit.

[0043] In response to receiving a randomization seed and a data unit, the derandomization unit uses the received randomization seed to derandomize the received data unit, obtains a derandomized data unit, and sends the derandomized data unit to the host.

[0044] Optionally, in response to a verification failure, the first CRC verification unit sends the data frame, or the data frame and its corresponding randomization seed, to the LDPC decoder.

[0045] In response to receiving the randomization seed and the data frame, the LDPC decoder uses the LDPC checksum in the data frame to perform LDPC decoding on the randomization seed, the data unit in the data frame, and the CRC checksum in the data frame as a whole, to obtain the decoded data unit, the decoded CRC checksum, and the decoded randomization seed, and sends the decoded data unit, the decoded CRC checksum, and the decoded randomization seed to the second CRC check unit.

[0046] In response to receiving the decoded data unit, the decoded CRC check code, and the decoded randomization seed, the second CRC check unit uses the decoded CRC check code to check the decoded data unit and the decoded randomization seed as a whole. In response to successful verification, the second CRC check unit sends the decoded data unit and the decoded randomization seed to the derandomization unit.

[0047] In response to receiving the decoded data unit and the decoded randomization seed, the derandomization unit derandomizes the decoded data unit using the decoded randomization seed to obtain a derandomized data unit, and then sends the derandomized data unit to the host.

[0048] Optionally, the randomizer is coupled to the LDPC encoder, and the derandomization unit is coupled to the first CRC check unit;

[0049] In response to receiving data units, CRC check codes, and LDPC check codes sent by the LDPC encoder, the randomizer uses a randomization seed to randomize the data frame formed by the received data units, CRC check codes, and LDPC check codes, and writes the randomized data frame into the NVM chip.

[0050] The derandomization unit receives the data frame read from the NVM chip by the control component, derandomizes the data frame using a randomization seed, and sends the derandomized data frame to the first CRC verification unit.

[0051] Optionally, the randomizer uses the same randomization seed to randomize different received data units; the derandomization unit uses the same randomization seed to derandomize different received data units.

[0052] Optionally, the randomizer uses different randomization seeds to randomize different received data units.

[0053] Optionally, the randomizer determines the randomization seed corresponding to the data unit to be written to the NVM chip as indicated by the write command received by the control unit, based on the physical address of the data unit to be written to the NVM chip on the NVM chip.

[0054] If the data frame written to the NVM chip does not include a randomization seed, the first CRC check unit determines the randomization seed corresponding to the data unit read from the specified physical address indicated by the read command on the NVM chip, based on the specified physical address indicated by the read command received by the control unit; or, if the data frame written to the NVM chip does not include a randomization seed, the derandomization unit determines the randomization seed corresponding to the data unit read from the specified physical address indicated by the read command, based on the specified physical address indicated by the read command received by the control unit.

[0055] Optionally, the control component includes a decoder pool, which includes multiple LDPC decoders;

[0056] In response to a failure to verify a data unit in a received data frame, the first CRC check unit sends the data frame to any idle LDPC decoder in the decoder pool.

[0057] Optionally, the control unit couples to M NVM chips, and the control unit includes M first CRC check units, each of which corresponds one-to-one with one of the M NVM chips, where M is an integer greater than or equal to 2.

[0058] Each of the first CRC check units receives a data frame read from its corresponding NVM chip and checks the data units in the data frame.

[0059] Optionally, the control component monitors the working effect of the first CRC verification unit and determines whether to shut down the first CRC verification unit based on the working effect of the first CRC verification unit.

[0060] Without disabling the first CRC check unit, the control unit sends the data frame read from the NVM chip to the first CRC check unit;

[0061] With the first CRC check unit disabled, the control unit sends the data frames read from the NVM chip to the LDPC encoder.

[0062] Optionally, in response to the successful verification of the data unit, the first CRC check unit adds a specified tag to the data unit and sends the data unit carrying the specified tag to the host.

[0063] The control unit determines whether to disable the first CRC check unit based on the number of data units carrying the specified marker.

[0064] Optionally, in response to detecting that the proportion of the data unit carrying the specified tag in all data units sent to the host is less than or equal to a preset first threshold, the control component determines to disable the first CRC check unit.

[0065] Optionally, the control unit records the time when the first CRC check unit sends a data unit carrying the specified tag to the host, and determines to shut down the first CRC check unit in response to the fact that no data unit carrying the specified tag is detected being sent to the host by the first CRC check unit within a specified time interval.

[0066] Optionally, the control unit determines to disable the first CRC check unit in response to detecting that the NVM chip is in the middle or late stage of its life cycle.

[0067] Secondly, embodiments of this application provide a data processing method, including:

[0068] In response to reading a data frame from the NVM chip, the first data unit in the data frame is verified using the first CRC checksum in the data frame.

[0069] In response to the successful verification of the first data unit, and determining that there are no errors in the first data unit, the first data unit is not subjected to LDPC decoding, but is directly sent to the host.

[0070] Optionally, the method further includes:

[0071] In response to the failure of the first data unit verification, the first data unit and the first CRC check code are used as a whole to perform LDPC decoding on the first data unit and the first CRC check code in the data frame to obtain the decoded first data unit and the decoded first CRC check code.

[0072] The decoded first data unit is verified using the decoded first CRC checksum. If the decoded first data unit is successfully verified, it is determined that the decoded first data unit has no errors and the decoded first data unit is sent to the host.

[0073] Optionally, the data frame includes N second data units, N second LDPC check codes, and one second CRC check code; the N second data units correspond one-to-one with the N second LDPC check codes; N is an integer greater than or equal to 2; the sum of the sizes of the N second data units is equal to the size of the first data unit; the second CRC check code is obtained by performing CRC encoding on the N second data units as a whole.

[0074] Optionally, the method includes:

[0075] In response to receiving the data frame, the N second data units are verified as a whole using the second CRC checksum in the data frame;

[0076] In response to the successful verification of the overall structure formed by the N second data units, the N second data units are sent as a whole to the host.

[0077] Optionally, the method includes:

[0078] In response to the overall verification failure of the N second data units, for each second data unit, the second LDPC check code corresponding to the second data unit is used to perform LDPC decoding on the second data unit and the second CRC check code in the data frame as a whole to obtain a set of decoded data. The N sets of decoded data corresponding to the N second data units are sent to the second CRC check unit. Each set of decoded data includes the decoded second data unit and the decoded second CRC check code.

[0079] The decoded second data unit is verified using the second CRC check code in each group of decoded data. In response to the successful verification of all N decoded second data units, the N decoded second data units are sent to the host as a whole.

[0080] Optionally, the method further includes:

[0081] In response to receiving a data unit sent by the host, the received data unit is CRC encoded to generate a CRC checksum.

[0082] The data unit and the CRC check code are treated as a whole and LDPC encoded to generate an LDPC check code. The data frame formed by the data unit, the CRC check code and the LDPC check code is then written into the NVM chip.

[0083] Optionally, the method further includes:

[0084] In response to receiving a data unit sent by the host, the received data unit is randomized using a randomization seed to obtain a new data unit; or, the randomization seed and the received data unit are randomized as a whole using a randomization seed to obtain a new data unit.

[0085] In response to receiving a data unit and a randomization seed, the received data unit and randomization seed are encoded as a whole according to the specified encoding method to generate a CRC check code;

[0086] The data unit, the randomization seed, and the CRC check code are treated as a whole and LDPC encoded to obtain the LDPC check code. The data frame formed by the data unit, the randomization seed, the CRC check code, and the LDPC check code is written into the NVM chip, or the data frame formed by the data unit, the randomization seed, the CRC check code, and the LDPC check code is written into the NVM chip.

[0087] In response to reading a data frame from the NVM chip, if the data frame includes a randomization seed, the randomization seed and the data unit in the data frame are verified as a whole using the CRC checksum in the data frame; or, if the data frame does not include a randomization seed, the randomization seed corresponding to the data unit in the data frame is determined, and the data unit in the data frame and the randomization seed corresponding to the data unit are verified as a whole.

[0088] In response to successful verification, the data unit is derandomized using the randomization seed to obtain a derandomized data unit, which is then sent to the host.

[0089] Optionally, the method includes:

[0090] In response to a verification failure, the randomization seed, the data unit in the data frame, and the CRC checksum in the data frame are used as a whole to perform LDPC decoding to obtain the decoded data unit, the decoded CRC checksum, and the decoded randomization seed.

[0091] Using the decoded CRC checksum, the decoded data unit and the decoded randomization seed are verified as a whole. In response to successful verification, the decoded data unit and the decoded randomization seed are sent to the derandomization unit.

[0092] The decoded data unit is derandomized using the decoded randomization seed to obtain a derandomized data unit, which is then sent to the host.

[0093] Optionally, the method includes:

[0094] In response to receiving a data unit sent by the host, the received data unit is CRC encoded to generate a CRC checksum.

[0095] The data unit and the CRC check code are treated as a whole and LDPC encoded to generate an LDPC check code.

[0096] The data frame formed by the data unit, the CRC check code, and the LDPC check code is randomized using a randomization seed, and the randomized data frame is written into the NVM chip.

[0097] In response to receiving a data frame read from the NVM chip, the data frame is derandomized using a randomization seed, and the data units of the derandomized data frame are processed using the CRC checksum in the derandomized data frame.

[0098] Optionally, the method includes: randomizing different received data units using the same randomization seed; and derandomizing the different received data units using the same randomization seed.

[0099] Optionally, the method includes: randomizing different received data units using different randomization seeds.

[0100] Optionally, the method includes: determining a randomization seed corresponding to the data unit to be written to the NVM chip as indicated by the received write command, based on the physical address of the data unit to be written to the NVM chip as indicated by the write command; and, if the data frame written to the NVM chip does not include a randomization seed, determining a randomization seed corresponding to the data unit read from the specified physical address as indicated by the received read command, based on the specified physical address of the NVM chip as indicated by the read command.

[0101] Thirdly, embodiments of this application provide a storage device, which includes a control component for advance CRC verification provided in any embodiment of this application.

[0102] The method and control component for reducing read command latency through advance CRC verification provided in this application embodiment perform CRC verification on the data unit read from the NVM chip before performing LDPC decoding on the data unit; in response to the successful verification of the data unit, it is determined that the data unit does not have any errors and does not perform LDPC decoding, and directly sends the data unit to the host, thereby reducing the latency of processing read IO commands. Attached Figure Description

[0103] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0104] Figure 1A A schematic diagram of the solid-state storage device is shown.

[0105] Figure 1B A schematic diagram of the structure of a prior art control component is shown;

[0106] Figure 2A A schematic diagram of the structure of another control component in the prior art is shown;

[0107] Figure 2B A schematic diagram of the structure of another control component in the prior art is shown;

[0108] Figure 3 A schematic diagram of the structure of a control component provided in an embodiment of this application is shown;

[0109] Figure 4 This illustration shows a schematic diagram of the control unit writing a data frame to the NVM chip according to an embodiment of this application;

[0110] Figure 5A A schematic diagram of the structure of a control component provided in another embodiment of this application is shown;

[0111] Figure 5B A schematic diagram of the structure of a control component provided in another embodiment of this application is shown;

[0112] Figure 6 A schematic diagram of the structure of a control component provided in yet another embodiment of this application is shown. Detailed Implementation

[0113] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0114] Figure 3 A schematic diagram of the structure of the control component according to an embodiment of this application is shown. Figure 3 As shown, the control components include a CRC encoding unit, an LDPC encoder, a CRC check unit 1, an LDPC decoder, and a CRC check unit 2.

[0115] The CRC encoding unit is coupled to the LDPC encoder. The LDPC encoder is coupled to both the CRC encoding unit and the NVM chip. CRC check unit 1 is coupled to the NVM chip, the LDPC decoder, and the host. The LDPC decoder is coupled to both CRC check unit 1 and CRC check unit 2. CRC check unit 2 is coupled to both the LDPC decoder and the host.

[0116] like Figure 3 As shown, the CRC encoding unit and the LDPC encoder constitute the path for the control unit to write data to the NVM chip, and this path is connected to... Figure 2B The path for the control unit to write data to the NVM chip is the same as shown. The process by which the control unit in this embodiment writes data to the NVM chip is the same as in prior art, including:

[0117] In response to receiving a write command from the host, the control unit provides the data (denoted as data unit 0) that the write command indicates to be written to the NVM chip to the CRC encoding unit.

[0118] In response to receiving data unit 0, the CRC encoding unit performs CRC encoding on data unit 0 to generate CRC check code 0, and provides data unit 0 and CRC check code 0 to the LDPC encoder.

[0119] In response to receiving data unit 0 and CRC checksum 0, the LDPC encoder performs LDPC encoding on data unit 0 and CRC checksum 0 as a whole, generating LDPC checksum 0. The LDPC encoder then writes data frame 0 (the combination of data unit 0, CRC checksum 0, and LDPC checksum 0 is called data frame 0) into the NVM chip. The LDPC checksum corresponds to the combination of data unit 0 and CRC checksum 0. The LDPC checksum can be used to correct errors in data unit 0 and CRC checksum 0, protecting them. CRC checksum 0 only corresponds to data unit 0.

[0120] like Figure 3 As shown, CRC check unit 1, LDPC decoder, and CRC check unit 2 constitute the path for the control unit to read data from the NVM chip. Compared to Figure 2B The control components shown Figure 3 The control unit shown adds a CRC check unit (CRC check unit 1) to the data reading path, and the processes for reading data from the NVM chip differ between the two. The process for the control unit in this embodiment to read data from the NVM chip includes:

[0121] In response to receiving a read command from the host, the control unit reads data from the NVM chip (denoted as raw data frame 1) and provides the read raw data frame 1 to the CRC check unit 1. Raw data frame 1 includes data unit 1, CRC check code 1, and LDPC check code 1.

[0122] In response to receiving data frame 1, CRC check unit 1 performs a check using data unit 1 and CRC checksum 1 from the original data frame. If CRC check unit 1 succeeds, it indicates that data unit 1 and CRC checksum 1 in the original data frame are error-free. If CRC check unit 1 fails, it indicates that data unit 1 and / or CRC checksum 1 in the original data frame contain errors. CRC check unit 1 cannot identify the source of the erroneous data; for example, erroneous data may exist in data unit 1, or erroneous data may exist in CRC checksum 1, or both data unit 1 and CRC checksum 1 may contain errors.

[0123] In response to a successful CRC check, CRC check unit 1 will send data unit 1 obtained from the original data frame 1 directly to the host as a response to the read IO command, instead of providing the original data frame 1 to the LDPC decoder.

[0124] In response to a failed CRC check, CRC check unit 1 provides the original data frame 1 to the LDPC decoder.

[0125] In response to receiving the original data frame 1, the LDPC decoder uses the LDPC check code to decode the data unit 1 and CRC check code 1 in the original data frame 1, and obtains the decoded data unit (denoted as data unit 2) and the decoded CRC check code (denoted as CRC check code 2). For example, if neither data unit 1 nor CRC checksum 1 contains erroneous data, then data unit 2 decoded by the LDPC decoder is the same as data unit 1, and CRC checksum 2 is the same as CRC checksum 1. If data unit 1 contains erroneous data, but CRC checksum 1 does not contain erroneous data, then data unit 2 is different from data unit 1, and the data in data unit 2 is the corrected data after correcting the erroneous data in data unit 1, and CRC checksum 2 is the same as CRC checksum 1. If data unit 1 does not contain erroneous data, but CRC checksum 1 contains erroneous data, then data unit 2 is the same as data unit 1, but CRC checksum 2 is different from CRC checksum 1, and the data in CRC checksum 2 is the corrected data after correcting the erroneous data in CRC checksum 1. If both data unit 1 and CRC checksum 1 contain erroneous data, then data unit 2 is different from data unit 1, and the data in data unit 2 is the corrected data after correcting the erroneous data in data unit 1, and CRC checksum 2 is different from CRC checksum 1, and the data in CRC checksum 2 is the corrected data after correcting the erroneous data in CRC checksum 1.

[0126] The LDPC decoder provides the decoded data unit 2 and CRC check code 2 to the CRC check unit 2.

[0127] CRC check unit 2 responds to the received data unit 2 and CRC checksum 2 by using CRC checksum 2 to verify data unit 2. If CRC check unit 2 succeeds, it indicates that the LDPC decoder has successfully decoded the data, and data unit 2 is provided to the host as a response to the read command. If CRC check unit 2 fails, it means that the LDPC decoder has failed to decode the data, and there is an error in the data unit 2 decoded by the LDPC decoder. Other methods need to be tried to correct the error in data unit 2. As an optional example, RAID technology or read-redo technology can be used to correct the error in data unit 2.

[0128] It should be understood that the data stored in the NVM chip may be corrupted. The probability of data corruption is relatively small in the early stage of the NVM chip's life cycle, and relatively large in the middle and late stages of the life cycle. Therefore, there is a certain probability that the CRC check unit 1 fails to pass the check when verifying the original data frame. Especially in the middle and late stages of the NVM chip's life cycle, the probability of verification failure will increase further (even approaching 1, that is, 100% verification failure). This is also the reason why the prior art did not recognize the embodiments of the present application. Among them, the distinction between the early, middle, and late stages of the NVM chip's life cycle is the prior art. For example, it can be distinguished by the working time of the NVM chip, the amount of data written to the NVM chip, or the number of erasures performed on the physical blocks of the NVM chip.

[0129] However, during the design and use of the control component, it is found that there is also a certain probability that the CRC check unit 1 passes the check successfully. This possibility is of great significance for reducing the latency of the storage device in processing read I / O commands. For example, assume that the probability of the CRC check unit 1 passing the check successfully is P, and the probability of failure is (1 - P). The time required for the CRC check unit 1 to perform the CRC check is T1, and the sum of the time required for the LDPC decoder to perform LDPC decoding and the time required for the CRC check unit 2 to perform the CRC check is T2. When the CRC check unit 1 passes the check successfully, the read data latency introduced by the CRC check unit 1 is T1. When the CRC check unit 1 fails to pass the check, the read data latency introduced by the CRC check unit 1, the LDPC decoder, and the CRC check unit 2 is (T1 + T2).

[0130] For N read commands, Figure 2B the total latency of the control component shown in processing these N read commands is N * T2. Figure 3 The total latency of the control component shown in processing these N read commands is N * P * T1 + N * (1 - P) * (T1 + T2). Due to the principle of LDPC decoding, T2 is much larger than T1. Therefore, N * P * T1 + N * (1 - P) * (T1 + T2) ≈ N * P * T1 + N * (1 - P) * T2 = N * T2 + N * P * (T1 - T2). Since T1 - T2 < 0, N * P * (T1 - T2) < 0. Furthermore, N * T + N * P * (T1 - T2) < N * T2, that is, Figure 3 the total latency of the control component shown in processing N read commands is less than the total latency of the control component shown in Figure 2 in processing N read commands.

[0131] For N read commands, Figure 2B the average latency of the control component shown in processing these N read commands is T2, Figure 3The average latency for the control component shown to process the N read commands is P*T1 + (1 - P)*T2. Since the principle of LDPC decoding makes T2 much larger than T1, then P*T1 + (1 - P)*T2 ≈ (1 - P)*T2. Since P is greater than 0, thus (1 - P)*T2 < T2. That is Figure 3 The average latency for the control component shown to process N read commands is less than the average latency for the control component shown in Figure 2 to process N read commands.

[0132] Therefore, relative to Figure 2B the control component shown Figure 3 the control component shown can reduce the latency of processing read I / O commands.

[0133] There may be several to dozens of error bits in the original data frame of the NVM chip. These error bits are randomly distributed throughout the original data frame. And the size of the data unit accounts for 50% - 95% of the size of the entire original data frame. As a simple estimate, when there is 1 error bit in the original data frame and the size of the data unit accounts for 90% of the size of the entire original data frame, the value of P is approximately 10%. Thus, it can be estimated that in the early stage of the NVM chip's life cycle, the number of error bits in the original data frame is relatively small. The embodiments of the present application can reduce the average processing latency of read I / O commands by about a single-digit percentage value. And in the later stage of the NVM chip's life cycle, the reduction of the processing latency of read I / O commands by the embodiments of the present application becomes insignificant.

[0134] In an optional embodiment, the control component (such as Figure 1B the host command processing unit 1042 shown) can turn off the CRC check unit 1 in the middle and / or later stage of the NVM chip cycle, and directly provide the original data frame read from the NVM chip to the LDPC decoder to eliminate the latency introduced by the CRC check unit 1. And with the further development of the NVM chip technology, the error bit rate in the original data frame is further reduced, enabling the embodiments of the present application to obtain a more significant effect of reducing the processing latency of read I / O commands.

[0135] In an optional embodiment, in response to a successful verification, CRC check unit 1 adds a specified flag to the successfully verified data unit and directly provides the data unit carrying the specified flag to the host. The control unit determines whether to disable CRC check unit 1 based on the specified flag. Optionally, the control unit determines whether to disable CRC check unit 1 based on the number of data units carrying the specified flag or the proportion of data units carrying the specified flag among all data units provided to the host. For example, in the middle to late stages of the NVM chip's lifecycle, due to the increase in the number of error bits in the original data frame, CRC check unit 1 may fail verification with a high probability, the number of data units carrying the specified flag decreases (the proportion of data units carrying the specified flag among all data units provided to the host decreases), or even no longer contains data units carrying the specified flag, thus causing CRC check unit 1 to have a negative impact on the control unit (such as increased power consumption and increased read data latency). At this time, the control unit can disable CRC check 1, and all original data frames read from the NVM chip are directly provided to the LDPC decoder for processing, without being processed by CRC check unit 1. Optionally, the control unit can record the time when the CRC verification unit 1 sends a data unit carrying a specified tag to the host. If the CRC verification unit 1 does not send a data unit carrying the specified tag to the host within the specified time interval, the CRC verification unit 1 can be turned off.

[0136] In some alternative embodiments, besides responding to read I / O commands, the storage device may read data from the NVM chip for other purposes, such as performing GC (garbage collection) operations, loading firmware stored in the NVM chip, etc. The control components based on embodiments of this application can also reduce the latency of the storage device reading data from the NVM chip for other purposes.

[0137] In an optional embodiment, the format of the data frames stored in the NVM chip is changed, such that each data frame includes 4 data units, 4 LDPC check codes, and 1 CRC check code.

[0138] Figure 4 A schematic diagram illustrating the control unit writing a data frame to an NVM chip according to an embodiment of the present invention is shown. Figure 4As shown, the data frame includes four data units (data unit 3, data unit 4, data unit 5, and data unit 6), four LDPC checksums (LDPC encoding 3, LDPC encoding 4, LDPC encoding 5, and LDPC encoding 6), and one CRC checksum (CRC checksum 0). The four data units correspond one-to-one with the four LDPC checksums; for example, LDPC encoding 3 corresponds to data unit 3, LDPC encoding 4 corresponds to data unit 4, LDPC encoding 5 corresponds to data unit 5, and LDPC encoding 6 corresponds to data unit 6. The size of each data unit in the data frame is relatively small, for example, 512 bytes. Optionally, Figure 4 The sum of the sizes of the four data units in the data frame shown is equal to Figure 3 The size of one data unit (e.g., data unit 0) in the data frame shown. Figure 3 As shown, each data frame stored in the NVM chip includes one data unit, one CRC checksum, and one LDPC checksum.

[0139] For example, based on Figure 3 The control unit shown has a CRC encoding unit that, in response to receiving data unit 0 (e.g., 4KB), performs CRC encoding on data unit 0 to generate CRC checksum 0, and provides data unit 0 and CRC checksum 0 to the LDPC encoder. The LDPC encoder divides data unit 0 into data unit 3, data unit 4, data unit 5, and data unit 6 (each data unit is, for example, 512 bytes in size). Alternatively, the CRC encoding unit divides data unit 0 into data unit 3, data unit 4, data unit 5, and data unit 6, and provides data unit 3 with CRC checksum 0, data unit 4 with CRC checksum 0, data unit 5 with CRC checksum 0, and data unit 6 with CRC checksum 0 to the LDPC encoder, respectively. In response to receiving data unit 3 and CRC checksum 0, the LDPC encoder performs LDPC encoding on data unit 3 and CRC checksum 0 to obtain LDPC encoding 3. In response to receiving data unit 4 and CRC checksum 0, the LDPC encoder performs LDPC encoding on data unit 4 and CRC checksum 0 to obtain LDPC encoding 4. In response to receiving data unit 5 and CRC checksum 0, the LDPC encoder performs LDPC encoding on data unit 5 and CRC checksum 0 to obtain LDPC encoding 5. In response to receiving data unit 6 and CRC checksum 0, the LDPC encoder performs LDPC encoding on data unit 6 and CRC checksum 0 to obtain LDPC encoding 6. The LDPC encoder writes data unit 3, data unit 4, data unit 5, data unit 6, LDPC encoding 3, LDPC encoding 4, LDPC encoding 5, LDPC encoding 6, and CRC checksum 0 as a single data frame into the NVM chip.

[0140] For example, CRC checksum 0 includes 16 bits (0-15). The CRC encoding unit provides data unit 3 and bits 0-3 of CRC checksum 0 to the LDPC encoder. In response to receiving data unit 3 and bits 0-3 of CRC checksum 0, the LDPC encoder performs LDPC encoding on data unit 3 and bits 0-3 of CRC checksum 0 to obtain LDPC code 3. The CRC encoding unit then provides data unit 4 and bits 4-7 of CRC checksum 0 to the LDPC encoder. In response to receiving data unit 4 and bits 4-7 of CRC checksum 0, the LDPC encoder performs LDPC encoding on data unit 4 and bits 4-7 of CRC checksum 0 to obtain... LDPC encoding 4; The CRC encoding unit provides data unit 5 and bits 8-11 of CRC checksum 0 to the LDPC encoder. In response to receiving data unit 5 and bits 8-11 of CRC checksum 0, the LDPC encoder performs LDPC encoding on data unit 5 and bits 8-11 of CRC checksum 0 to obtain LDPC encoding 5; The CRC encoding unit provides data unit 6 and bits 12-15 of CRC checksum 0 to the LDPC encoder. In response to receiving data unit 6 and bits 12-15 of CRC checksum 0, the LDPC encoder performs LDPC encoding on data unit 6 and bits 12-15 of CRC checksum 0 to obtain LDPC encoding 6.

[0141] and Figure 3 Compared to the data frames shown, the control unit processes... Figure 4 When processing data frames as shown, data units within a single data frame are split into multiple smaller data units. This reduces the complexity of the LDPC encoder and decoder due to the smaller unit size, allowing for processing through multiple LDPC encoding operations. Figure 3 The data frame shown encodes one data unit. CRC encoding and CRC check are relatively simple. The CRC encoder that encodes data units 3, 4, 5, and 6 as a whole, and the CRC check unit that performs the check, do not introduce excessive complexity or hardware resource consumption.

[0142] refer to Figure 4 The raw data frame read by the control unit from the NVM chip includes 4 data units, 4 LDPC checksums, and 1 CRC checksum. Based on Figure 3The control unit shown uses the CRC checksum in the original data frame to check the overall structure of the four data units (data unit 3, data unit 4, data unit 5, and data unit 6). In response to a successful check, the CRC check unit 1 provides all four data units from the original data frame to the host, and none of these four data units require LDPC decoding. In response to a failed check, the CRC check unit 1 provides the original data frame to the LDPC decoder for decoding.

[0143] In response to receiving the original data frame sent by CRC check unit 1, the LDPC decoder decodes the data unit 3 and CRC check unit 0 using LDPC check code 3 to obtain the decoded data unit 3 and the decoded CRC check unit 0 (referred to as the first set of decoded data); it decodes the data unit 4 and CRC check unit 0 using LDPC check code 4 to obtain the decoded data unit 4 and the decoded CRC check unit 0 (referred to as the second set of decoded data); it decodes the data unit 5 and CRC check unit 0 using LDPC check code 5 to obtain the decoded data unit 5 and the decoded CRC check unit 0 (referred to as the third set of decoded data); and it decodes the data unit 6 and CRC check unit 0 using LDPC check code 6 to obtain the decoded data unit 6 and the decoded CRC check unit 0 (referred to as the fourth set of decoded data).

[0144] The LDPC decoder sends the first set of decoded data, the second set of decoded data, the third set of decoded data, and the fourth set of decoded data to the CRC check unit 2.

[0145] CRC check unit 2 uses the decoded CRC check code 0 from the first set of decoded data to check the decoded data unit 3, uses the decoded CRC check code 0 from the second set of decoded data to check the decoded data unit 4, uses the decoded CRC check code 0 from the third set of decoded data to check the decoded data unit 5, and uses the decoded CRC check code 0 from the fourth set of decoded data to check the decoded data unit 6.

[0146] If all the decoded data units 3, 4, 5, and 6 are successfully verified, it means that the LDPC decoder has been successfully decoded. The CRC verification unit 2 then sends the entire set of decoded data units 3, 4, 5, and 6 to the host.

[0147] If one or more data units fail to be verified among the decoded data units 3, 4, 5, and 6 (for example, decoded data unit 4 fails to be verified, while decoded data units 3, 5, and 6 all succeed), it means that the LDPC decoder failed to decode data unit 4, and other methods need to be tried to correct the error in data unit 4.

[0148] In some optional embodiments, the state of the data stored in the NVM chip is required to be highly random, so that the charge representing different data states is evenly distributed in the NVM chip, avoiding inconsistencies in storage capacity due to uneven charge distribution. However, the data to be written to the NVM chip by the host write command is user-specified, which cannot meet the requirement of high randomness. To solve this technical problem, embodiments of the present invention provide a control component capable of randomizing the data written to the NVM chip.

[0149] Figure 5A A schematic diagram of the structure of a control component according to another embodiment of the present invention is shown. For example... Figure 5A As shown, in Figure 3 Based on the control unit shown in Figure 5, a randomizer and a derandomization unit are added to the control unit. The randomizer is located on the path where the control unit writes data to the NVM chip and is used to randomize the received data. The derandomization unit is located on the path where the control unit reads data from the NVM chip and is used to derandomize the received data.

[0150] like Figure 5A As shown, the control unit includes: a randomizer, a CRC encoding unit, an LDPC encoder, a CRC check unit 1, an LDPC decoder, a CRC check unit 2, and a derandomization unit. The randomizer is coupled to the CRC encoding unit. The CRC encoding unit is coupled to the LDPC encoder. CRC check unit 1 is coupled to both the LDPC decoder and the derandomization unit. The LDPC decoder is coupled to both CRC check unit 1 and CRC check unit 2. CRC check unit 2 is coupled to both the LDPC decoder and the derandomization unit. The derandomization unit is coupled to both CRC check unit 1 and CRC check unit 2.

[0151] based on Figure 5A The process by which the control unit shown writes data to the NVM chip includes:

[0152] In response to receiving a write command from the host, the control unit provides the data to be written to the NVM chip as instructed by the write command to the randomizer. For example, in response to receiving data unit 7 from the host, the randomizer randomizes data unit 7 and provides the randomized data unit (denoted as data unit 8) to the CRC encoder. Optionally, the randomizer uses a randomization seed (denoted as RS) to randomize the data unit; for example, randomizing data unit 7 using randomization seed 0 yields the randomized data unit 8.

[0153] Different data units can use different randomization seeds, resulting in different randomization results for each unit. Even if different data units have the same data content, their randomization results will differ, thus ensuring the randomness of data storage in the NVM chip and preventing the loss of overall randomness in data writing due to similar data carried by I / O commands. Optionally, the corresponding randomization seed can be determined based on the physical address of the data unit to be written to the NVM chip as indicated by the write command.

[0154] Different data units can also use the same randomization seed to randomize all data written to the NVM.

[0155] As another example, the CRC encoding unit performs CRC encoding on the received data unit and randomization seed as a whole; for instance, in response to receiving data unit 8 and randomization seed 0, the CRC encoding unit encodes the whole formed by data unit 8 and randomization seed 0 to obtain the CRC check code (denoted as CRC check code 3); where CRC check code 3 corresponds to data unit 8 and randomization seed 0. The CRC encoding unit provides data unit 8, randomization seed 0, and CRC check code 3 to the LDPC encoder.

[0156] As another example, the LDPC encoder performs LDPC encoding on the received data unit, randomization seed, and CRC check code as a whole. For example, in response to receiving data unit 8, randomization seed 0, and CRC check code 3, the LDPC encoder performs LDPC encoding on the whole formed by data unit 8, randomization seed 0, and CRC check code 3 to obtain the LDPC check code, and writes data unit 8, CRC check code 3, LDPC check code, and randomization seed 0 into the NVM chip. The LDPC check code corresponds to data unit 8, CRC check code 3, and randomization seed 0.

[0157] As another example, the data frames stored in an NVM chip include data units, CRC checksums, LDPC checksums, and randomization seeds.

[0158] In an optional embodiment, the randomization seed may not be written to the NVM chip, but rather recorded by the control unit.

[0159] based on Figure 5A The control unit shown in the diagram reads data from the NVM chip, and the process includes:

[0160] For example, in response to receiving a read command, the control unit reads a raw data frame from the NVM chip. This raw data frame includes a data unit (denoted as data unit 8), a CRC checksum 3, an LDPC checksum, and a randomization seed 0. The control unit then provides the read raw data frame to the CRC check unit 1.

[0161] For example, in the path of writing data to the NVM chip, the CRC encoding unit encodes the data unit and the randomization seed as a whole, so the resulting CRC checksum corresponds to the data unit and the randomization seed. In the path of reading data from the NVM chip, the CRC check unit 1 checks the data unit and the randomization seed as a whole in the data frame based on the CRC checksum in the data frame read from the NVM chip. For example, in response to receiving an original data frame, the CRC check unit 1 uses the CRC checksum 3 in the original data frame to check the data unit 8 and the randomization seed 0.

[0162] In response to successful verification, CRC verification unit 1 provides the data unit 8 and randomization seed 0 to the derandomization unit. Upon receiving the data unit 8 and randomization seed 0, the derandomization unit performs a derandomization operation on the data unit 8 using the randomization seed 0 to obtain data unit 7. The derandomization unit then provides this data unit 7 to the host.

[0163] Alternatively, in response to a verification failure, CRC check unit 1 provides the original data frame to the LDPC decoder. Upon receiving the original data frame, the LDPC decoder uses the LDPC checksum in the original data frame to decode the entire data unit 8, CRC checksum 3, and randomization seed 0, obtaining the decoded data unit 8, decoded CRC checksum 3, and decoded randomization seed 0. The LDPC decoder then provides the decoded data unit 8, decoded CRC checksum 3, and decoded randomization seed 0 to CRC check unit 2.

[0164] In response to receiving the decoded data unit 8, the decoded CRC check code 3, and the decoded randomization seed 0, the CRC check unit 2 uses the decoded CRC check code 3 to check the decoded data unit 8.

[0165] In response to successful verification, CRC verification unit 2 provides the decoded data unit 8 and the decoded randomization seed 0 to the derandomization unit.

[0166] In response to receiving the decoded data unit 8 and the decoded randomization seed 0, the derandomization unit performs a derandomization operation on the decoded data unit 8 using the decoded randomization seed 0 to obtain data unit 7. The derandomization unit provides data unit 7 to the host as a response to the read command.

[0167] Figure 5B A schematic diagram of the structure of a control component according to another embodiment of the present invention is shown. For example... Figure 5B As shown, the control unit includes: a randomizer, a CRC encoding unit, an LDPC encoder, a CRC check unit 1, an LDPC decoder, a CRC check unit 2, and a derandomization unit. The CRC encoding unit is coupled to the LDPC encoder. The LDPC encoder is coupled to both the CRC encoding unit and the randomizer. The randomizer is coupled to the LDPC encoder. The derandomization unit is coupled to CRC check unit 1. CRC check unit 1 is coupled to both the LDPC decoder and the host computer. The LDPC decoder is coupled to both CRC check unit 1 and CRC check unit 2. CRC check unit 2 is coupled to both the LDPC decoder and the host computer.

[0168] based on Figure 5B The process by which the control unit shown writes data to the NVM chip includes:

[0169] In response to receiving a write command from the host, the control unit provides the data (denoted as data unit 9) that the write command indicates to be written to the NVM chip to the CRC encoding unit.

[0170] In response to receiving data unit 9, the CRC encoding unit performs CRC encoding on data unit 9 to generate CRC check code 4, and provides data unit 9 and CRC check code 4 to the LDPC encoder.

[0171] In response to receiving data unit 9 and CRC checksum 4, the LDPC encoder performs LDPC encoding on data unit 9 and CRC checksum 4 as a whole to generate an LDPC checksum. The LDPC encoder then provides the whole set of data unit 9, CRC checksum 4, and LDPC checksum to the randomizer.

[0172] The randomizer randomizes the data unit 9, CRC check code 4 and LDPC check code as a whole, and writes the randomized data unit 9, CRC check code 4 and LDPC check code and randomization seed into the NVM chip.

[0173] based on Figure 5BThe control unit shown in the diagram reads data from the NVM chip, including the following steps:

[0174] In response to receiving a read command, the control unit reads data frame 3 from the NVM chip and provides data frame 3 to the derandomization unit.

[0175] In response to receiving data frame 3, the derandomization unit uses the randomization seed in data frame 3 to derandomize the entire data unit 9, CRC checksum 4, and LDPC checksum in data frame 3, obtaining the derandomized data unit 9, CRC checksum 4, and LDPC checksum. This derandomized data unit 9, CRC checksum 4, and LDPC checksum are then provided to CRC verification unit 1. The subsequent processing procedures of CRC verification unit 1, LDPC decoder, and CRC verification unit 1 are similar to those described above. Figure 3 The embodiments shown are the same, and will not be repeated here to avoid repetition.

[0176] refer to Figure 5A and Figure 5B The randomizer can be located at different positions on the path where the control unit writes data to the NVM chip, for example... Figure 5A The method shown can be to first randomize the data units received by the control unit, and then perform CRC encoding and LDPC encoding on the randomized data units, or as shown in the example. Figure 5B The diagram shows that the data units received by the control unit are first CRC encoded and LDPC encoded, and then the LDPC-encoded data units are randomized. The derandomization unit can also be located at different positions along the data reading path from the NVM chip by the control unit, for example... Figure 5A As shown, the data units in the data frame read from the NVM chip are first subjected to CRC verification. The derandomization unit derandomizes the data units that have been successfully verified by CRC verification unit 1 and CRC verification unit 2. Alternatively, it can be done as follows: Figure 5B The data frame read from the NVM chip is first randomized, and then the derandomized data frame is subjected to CRC verification.

[0177] The control component provided in this application performs a randomization operation on the data written to the NVM chip through a randomizer, making the data written to the NVM chip highly random, and performs a derandomization operation on the data read from the NVM chip through a derandomization unit, so as to feed back the correct data to the host.

[0178] The processing capabilities of a CRC check unit and an LDPC decoder differ. The time required for a CRC check unit to perform CRC checks is significantly less than the time required for an LDPC decoder to perform LDPC decoding. (Reference) Figure 3During the decoding process of the LDPC encoder, CRC check unit 1 may become idle, resulting in wasted storage device performance.

[0179] refer to Figure 1A The control unit is coupled to multiple NVM chips. An NVM channel is a collection of hardware resources provided by the control unit for connecting to and accessing NVM chips. Optionally, an NVM channel includes dedicated I / O pins, allowing different NVM channels to transmit data in parallel without interfering with each other. This enables the control unit to couple with multiple NVM chips via NVM channels and read data from multiple NVM chips in parallel and independently. To avoid performance waste caused by idle CRC check units during LDPC decoder decoding, embodiments of this application can provide multiple CRC check units 1. Optionally, the number of CRC check units 1 is the same as the number of NVM channels, with different CRC check units 1 corresponding to different NVM channels. Data frames transmitted from different NVM channels can undergo CRC checks in parallel.

[0180] Optionally, embodiments of this application may also provide a decoder pool comprising multiple LDPC decoders. The number of LDPC decoders in the decoder pool may exceed the number of CRC check units 1. During the process of reading data from the NVM chip, if the CRC check unit 1 fails to verify and LDPC decoding is required, an available LDPC decoder is selected from the decoder pool for LDPC decoding.

[0181] The throughput (e.g. bandwidth) of a single CRC check unit 1 performing CRC check is greater than the bandwidth of a single LDPC decoder. By providing a larger number of LDPC decoders, the total bandwidth of each LDPC decoder in the decoder pool is roughly the same as the total bandwidth of multiple CRC check units 1 (the number of CRC check units is the same as the number of NVM channels), so that both CRC check units 1 and LDPC decoders in the control unit are working, thus avoiding idle hardware resources due to performance mismatch.

[0182] Since some data frames do not need to go through the LDPC decoder and CRC check unit 2, the number of CRC check units 2 can be less than the number of LDPC decoders, or less than the number of CRC check units 1.

[0183] Figure 6 A schematic diagram of the structure of a control component provided in an embodiment of the present invention is shown. For example... Figure 6As shown, the control unit includes: a randomizer, a CRC encoding unit, an LDPC encoder, a CRC check unit 11, a CRC check unit 12, a decoder pool, a CRC check unit 2, and a derandomization unit. The decoder pool includes multiple LDPC decoders, such as LDPC decoder 0, LDPC decoder 1, LDPC decoder 2, and LDPC decoder 3.

[0184] CRC check unit 11 is coupled to NVM chip 1 and checks the data units read from NVM chip 1. CRC check unit 12 is coupled to NVM chip 2 and checks the data units read from NVM chip 2. CRC check unit 11 and CRC check unit 12 can operate in parallel and independently of each other.

[0185] For example, the control unit sequentially receives read command 1, read command 2, read command 3, and read command 4 from the host. Read command 1 and read command 3 respectively instruct data to be read from NVM chip 1, while read command 2 and read command 4 respectively instruct data to be read from NVM chip 2.

[0186] In response to receiving read command 1, the control unit reads the raw data frame 10 from the NVM chip 1. If the CRC check unit 11 fails to check the data unit 10 in the raw data frame 10, it provides the raw data frame 10 to an idle LDPC decoder in the decoder pool. For example, if LDPC decoder 0 is idle, the CRC check unit 11 provides the raw data frame 10 to LDPC decoder 0.

[0187] In response to receiving read command 2, the control unit reads the raw data frame 11 from NVM chip 2. If the CRC check unit 12 fails to check the data unit 11 in the raw data frame 11, it provides the raw data frame 11 to an idle LDPC decoder in the decoder pool. For example, if LDPC decoder 0 is processing the decoding of raw data frame 10 and LDPC decoder 1 is idle, the CRC check unit 12 provides the raw data frame 11 to LDPC decoder 1.

[0188] In response to receiving read command 3, the control unit reads the raw data frame 12 from NVM chip 1. If the CRC check unit 11 fails to check the data unit 12 in the raw data frame 12, the raw data frame 12 is provided to an idle LDPC decoder in the decoder pool. For example, if LDPC decoder 0 is processing the decoding of raw data frame 10 and LDPC decoder 1 is processing the decoding of raw data frame 11, the CRC check unit 11 provides the raw data frame 12 to LDPC decoder 2.

[0189] In response to receiving read command 4, the control unit reads the raw data frame 13 from NVM chip 2. If the CRC check unit 12 fails to check the data unit 13 in the raw data frame 13, the raw data frame 13 is provided to an idle LDPC decoder in the decoder pool. For example, if LDPC decoder 0 is processing the decoding of raw data frame 10, LDPC decoder 1 is processing the decoding of raw data frame 11, and LDPC decoder 2 is processing the decoding of raw data frame 12, then the CRC check unit 12 provides the raw data frame 13 to LDPC decoder 3.

[0190] In an optional embodiment, CRC check units 11 and 12 add a specified flag to the successfully checked data units upon successful verification, and directly provide the data units carrying the specified flag to the host. The control unit, based on the specified flag, identifies the working effect of CRC check units 11 and 12, and then determines whether to disable CRC check units 1 and / or 12. For example, NVM chip 1 and NVM chip 2 have different performance; NVM chip 1 has fewer error bits in its data frames, while NVM chip 2 has more error bits. CRC check unit 11 directly provides the host with more data units carrying the specified flag, while CRC check unit 12 directly provides the host with fewer data units carrying the specified flag. Based on the number of data units carrying the specified flag, CRC check unit 12 is disabled, while CRC check unit 11 remains enabled.

[0191] It should be understood that in this application example, the CRC encoding unit, LDPC encoder, CRC check unit, and LDPC decoder are all located as follows: Figure 1B In the media interface controller shown, the NVM chip is a NAND flash memory.

[0192] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A control unit, characterized by The data path through which the control unit reads data from the NVM chip includes: a first CRC check unit and a decoding circuit; The first CRC check unit is coupled to the host of the decoding circuit and the control component respectively. In response to receiving a data frame read from the NVM chip by the control component, the first CRC check unit uses the first CRC check code in the data frame to check the first data unit in the data frame. In response to successful check, it is determined that the first data unit has no error, and the first data unit is not sent to the decoding circuit for LDPC decoding, but is directly sent to the host.

2. The control unit according to claim 1, characterized in that The decoding circuit includes an LDPC decoder and a second CRC check unit. In response to a verification failure, the first CRC verification unit sends the data frame to the LDPC decoder; The LDPC decoder is coupled to the first CRC check unit and the second CRC check unit respectively. In response to receiving the data frame, the LDPC decoder uses the first LDPC check code in the data frame to perform LDPC decoding on the first data unit and the first CRC check code as a whole to obtain the decoded first data unit and the decoded first CRC check code, and sends the decoded first data unit and the decoded first CRC check code to the second CRC check unit. The second CRC check unit is coupled to the host computer that is coupled to the LDPC decoder and the control unit; in response to receiving the decoded first data unit and the decoded first CRC check code, the second CRC check unit uses the decoded first CRC check code to check the decoded first data unit, and in response to successful check, sends the decoded first data unit to the host computer.

3. The control unit according to claim 2, characterized in that The data frame read by the control unit from the NVM chip includes N second data units, N second LDPC check codes, and one second CRC check code; the N second data units correspond one-to-one with the N second LDPC check codes; N is an integer greater than or equal to 2; the sum of the sizes of the N second data units is equal to the size of the first data unit, and the second CRC check code is obtained by performing CRC encoding on the N second data units as a whole.

4. The control unit according to claim 3, wherein In response to receiving the data frame, the first CRC check unit uses the second CRC check code in the data frame to check the N second data units as a whole; in response to the successful verification of the whole formed by the N second data units, the first CRC check unit sends the N second data units as a whole to the host.

5. The control member according to any one of claims 1 to 4, characterized in that The data path through which the control unit writes data to the NVM chip includes a CRC encoding unit and an LDPC encoder. In response to receiving a data unit sent by the host, the CRC encoding unit performs CRC encoding on the received data unit, generates a CRC check code, and sends the data unit and the CRC check code to the LDPC encoder. In response to receiving the data unit and the CRC checksum, the LDPC encoder encodes the data unit and the CRC checksum as a whole using LDPC encoding to generate an LDPC checksum, and writes the data frame formed by the data unit, the CRC checksum, and the LDPC checksum into the NVM chip.

6. The control unit according to claim 5, wherein The data path for the control unit to write data to the NVM chip also includes a randomizer, which uses a randomization seed to randomize the received data; or, uses a randomization seed to randomize the randomization seed and the received data as a whole. The data path for controlling the reading of data from the NVM chip also includes a derandomization unit, which uses a randomization seed to derandomize the received data.

7. The control member according to any one of claims 1 to 6, characterized in that The control component includes a decoder pool, which includes multiple LDPC decoders; In response to a failure to verify a data unit in a received data frame, the first CRC check unit sends the data frame to any idle LDPC decoder in the decoder pool.

8. The control unit according to claim 7, characterized in that The control unit is coupled to M NVM chips. The control unit includes M first CRC check units, and each of the M first CRC check units corresponds one-to-one with one of the M NVM chips. M is an integer greater than or equal to 2. Each of the first CRC check units receives a data frame read from its corresponding NVM chip and checks the data units in the data frame.

9. The control component according to any one of claims 1-8, characterized in that, The control component monitors the working effect of the first CRC verification unit and determines whether to shut down the first CRC verification unit based on the working effect of the first CRC verification unit. Without disabling the first CRC check unit, the control unit sends the data frame read from the NVM chip to the first CRC check unit; With the first CRC check unit disabled, the control unit sends the data frames read from the NVM chip to the LDPC encoder.

10. A data processing method, characterized in that, include: In response to reading a data frame from the NVM chip, the first data unit in the data frame is verified using the first CRC checksum in the data frame. In response to the successful verification of the first data unit, and determining that there are no errors in the first data unit, the first data unit is not subjected to LDPC decoding, but is directly sent to the host.

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