Area optimization method of double-precision multiplier-adder based on pipeline stall technique

Abstract

This invention provides a method for optimizing the area of ​​a double-precision multiply-accumulator based on pipelined pause technology. Considering the application scenarios of double-precision floating-point data, while meeting the performance requirements of most double-precision floating-point computation scenarios, the method improves the multiply-accumulator algorithm by changing the dual data path to a single data path during the double-precision floating-point multiply-accumulator computation process. By combining this with real-world application scenarios, it ensures that performance loss due to pipelined pauses is not incurred in common situations. For special low-probability events, performance is sacrificed by reducing the area of ​​the multiply-accumulator. The bit width is reduced based on the actual statistical situation of the operator, and pipelined pause multiplexing logic blocks are used to improve the area of ​​the adder, shifter, and leading zero statistics module, thereby improving the area of ​​the multiply-accumulator module.

Description

Technical Field

[0001] This invention belongs to the field of chip processing technology, and specifically relates to a method for optimizing the area of ​​a double-precision multiply-accumulator based on pipeline pause technology. Background Technology

[0002] In existing technologies, floating-point numbers are a real number data type in computers, possessing high computational precision and meeting the requirements of high-precision calculations. With the continuous development of modern technology, the importance of floating-point arithmetic capabilities has become increasingly prominent, playing an indispensable key element in various fields such as scientific computing, computer technology, and engineering. In scientific computing, large-scale data simulations are needed for in-depth research. For example, scientists in meteorological forecasting, fluid mechanics, and exploration need to perform high-precision floating-point calculations to obtain accurate simulation results. Similarly, in the booming field of autonomous driving, accurate floating-point calculations are crucial for the correctness and performance of algorithms. For machine learning algorithm optimization, floating-point calculations are highly efficient, accelerating the computation process and improving algorithm performance and efficiency, playing a vital role. Furthermore, with advancements in hardware technology, floating-point computing units can now be integrated into CPUs, becoming an important component of the CPU's core computing power.

[0003] In floating-point computing units, double-precision multiply-accumulators occupy a large design area. A large chip area has a series of negative impacts; as the area increases, so does power consumption and cost. Therefore, the design strategy of this module will significantly affect the overall power consumption, performance, and area of ​​the computing unit. A key challenge is how to minimize area overhead, thereby reducing power consumption and cost, in double-precision floating-point applications while improving or maintaining basic performance.

[0004] Current technologies typically employ a two-path approach, separating the process into near-path and far-path paths, to ensure performance. However, this approach incurs additional area overhead. This application takes a different approach, prioritizing performance for common double-precision applications while mitigating area overhead by reducing performance costs for less frequent scenarios. The core principle here is that less frequent scenarios are inherently low-probability events, and there's no need to incur significant area overhead for these low-probability events, thus avoiding increased power consumption and cost.

[0005] Existing technologies mainly employ the approach of splitting the path into two parts: a far-path and a near-path.

[0006] Near-path is primarily used when the multiplication result and addend operand do not require extensive shifting for alignment. The addend is shifted and aligned according to the exponent difference, and the multiplication is performed in parallel with the multiplier to obtain the multiplication result. Both are then fed into the adder to calculate the mantissa sum, followed by post-normalization to obtain the final result. Although near-path allows for a small shifter width during the alignment stage, this operation results in a significantly larger post-normalization shifter area required.

[0007] Far-path is primarily used for cases where the multiplication result and addend operands require significant shifting for alignment. In this case, it waits for the multiplication result to complete before moving the product or addend to the correct order using a shifter. Then, it moves to the adder to calculate the mantissa sum, rounds it off, and obtains the final result. Although the shifter width is relatively small in far-path, it consumes a significant amount of shifter area during the alignment stage.

[0008] Due to the different alignment methods, each of the two paths requires a different alignment shifter to perform the alignment operation in different pipeline stages; the two alignment shifters cannot be reused. Furthermore, in the post-alignment section, the near-path requires a large post-alignment shifter to ensure the correctness of the result. Because of the different alignment methods used in the near-path and far-path, the adders for the mantissa summation of the two paths are not in the same pipeline stage, and therefore cannot be reused.

[0009] While existing technologies aim to improve performance by changing floating-point multiply-accumulate operations from a single data path to a dual data path, this also brings a significant problem: related devices with the same logic in different data paths cannot be reused, resulting in additional area.

[0010] In summary, the main technical drawback of the existing technology is the area overhead caused by the inability to reuse the same logical module due to the dual data paths. Summary of the Invention

[0011] To address the aforementioned issues, the purpose of this application is to combine the application of double-precision floating-point data in real-world scenarios with a single data path, ensuring the reuse of the same internal logic modules and reducing area overhead. Under the single data path design, to guarantee performance, based on the characteristics of double-precision data occurrence, performance is maintained for common scenarios, while for low-probability scenarios, pipeline pauses are used to reuse existing related logic. This reduces area overhead at the cost of performance, avoiding excessive area consumption due to performance limitations in infrequent scenarios. In other words, in special cases, pipeline pauses are used to reuse related components, reducing the hardware design area.

[0012] Specifically, the present invention provides an area optimization method for a double-precision multiplier-accumulator based on the pipeline stall technology. In the multiplication and addition algorithm of the optimization method, after obtaining three operands a, b, and c, the product result of a*b is first calculated, the product result and the c operand, that is, the addend operand, are aligned in exponent, and then the mantissa summation operation is performed. After that, it enters the post-normalization part for normalization, and finally rounding, exception status judgment, and the final result are obtained;

[0013] The optimization method lies in the exponent alignment. Before exponent alignment, the product mantissa result, the product leading zero result, the exponent difference, and the c operand, that is, the addend operand, need to be obtained. Among them, the alignment shift amount of part of the exponent difference can offset the normalization shift amount of the product leading zero. The specific method of the exponent alignment includes:

[0014] (1) If: the multiplication exponent result > the exponent of the c operand:

[0015] a. The exponent difference > the product leading zero: The product result is the large exponent, and a left shift normalization with a shift amount of the product leading zero needs to be performed. The c operand is the small exponent, and a right shift alignment with a shift amount of the exponent difference - the number of product leading zeros needs to be performed. At this time, two shifts are required, and the multiplication result is still the large operand; if there is no product leading zero generated in the multiplication at this time, only the c operand needs to be shifted by the exponent difference;

[0016] b. The exponent difference < the product leading zero: Before shifting, the product result is the large exponent. First, a left shift normalization with a shift amount of the product leading zero is performed on the multiplication mantissa. At this time, because the exponent difference < the product leading zero, the product result instead becomes the small exponent. At this time, a right shift alignment with a shift amount of the product leading zero - the exponent difference still needs to be performed on the shifted multiplication mantissa;

[0017] From the overall effect, only the multiplication mantissa needs to be left-shifted by the exponent difference. At this time, the multiplication result becomes the small operand and needs to be exchanged;

[0018] c. The exponent difference = the product leading zero: At this time, only a left shift normalization with a shift amount of the product leading zero needs to be performed on the multiplication mantissa to complete the exponent alignment of the c operand and the multiplication result;

[0019] (2) If: the multiplication exponent result < the exponent of the c operand:

[0020] At this time, regardless of the relationship between the product leading zero statistics and the exponent difference, the multiplication result must be the small exponent. First, a left shift normalization with a shift amount of the product leading zero is performed on the multiplication mantissa. At this time, the exponent of the multiplication result is smaller, and a right shift alignment with a shift amount of the product leading zero + the exponent difference still needs to be performed on the shifted multiplication mantissa;

[0021] From the overall effect, only the multiplication mantissa needs to be right-shifted by the exponent difference. At this time, the multiplication result is still the small operand;

[0022] (3) If: the multiplication exponent result = the exponent of the c operand, and the exponent difference = 0: a. If the product leading zero = 0, the multiplication result and the c operand have been aligned and no shift is needed; b. If the product leading zero ≠ 0, the exponent difference is less than the product leading zero. First, the mantissa of the multiplication is shifted left by the product leading zero for normalization. After the shift is completed, the exponent difference is the product leading zero. Then, the adjusted mantissa result needs to be right-shifted by the product leading zero for alignment.

[0023] From an overall perspective, no repositioning is required;

[0024] The optimized method, in the process of performing double-precision floating-point multiplication and addition calculations, implements the pipeline as follows:

[0025] P0 stage, the first pipeline stage: performs multiplication, leading zero counting, and special value judgment modules; P1 stage, the second pipeline stage: performs alignment shifting and comparison operations.

[0026] P2 stage, the third pipeline stage: summation of mantissas after order alignment;

[0027] Level P3, the fourth pipeline stage: post-processing, rounding, final result processing, and final exception state judgment.

[0028] Therefore, this invention mainly focuses on optimizing the overall multiply-accumulate algorithm and uses a pipelined pause strategy to reduce the area, with the following advantages:

[0029] 1. Optimization of leading zeros in the post-rule:

[0030] After obtaining the sum of the mantissas, the present invention divides the result into two parts for subsequent leading zero counting. First, the number of leading zeros in the high 53 bits is counted. If all 53 bits in the high 53 bits are 0, the pipeline is paused. In the next cycle, this 53-bit leading zero counting module is reused to count the number of leading zeros in the low 53 bits.

[0031] Although the design of this invention will suffer some performance loss due to pipeline pauses, according to operator statistics, pipeline pauses caused by all high bits being zero are low-probability events. That is, sacrificing performance in some special cases yields the advantage of reduced leading zero statistical area in normal cases; 2. Shifter optimization:

[0032] A. Optimization of the Alignment Partial Shifter

[0033] (1) Optimize the alignment algorithm to ensure that the alignment shift can cancel out the alignment shift and the leading zero normalization shift to the greatest extent possible, so as to reduce the bit width and achieve the purpose of reducing the hardware design area.

[0034] In the alignment algorithm of this invention, pipelined pauses and shifter reuse are only required in special alignment cases. As analyzed earlier, the alignment algorithm requires left-shifting normalization of the product mantissa and right-shifting alignment of the c operand if and only if the multiplication exponent result > the c operand exponent and the exponent difference > the product leading zero (leading zero ≠ 0). From an application perspective, this is a low-probability, uncommon scenario; therefore, pipelined pauses and shifter reuse reduce the area overhead of the shifter.

[0035] (2) Use only right shifters, and implement left shifts using right shifters:

[0036] Analysis of the alignment algorithm reveals that right shifts far outnumber left shifts. Adding an extra shifter for left shifts would incur area overhead. Therefore, this invention uses only one right shifter in the alignment process, allowing left shifts to be performed using the right shifter. Specifically, it employs a reverse sequence: right shift, then reverse sequence again to obtain the corresponding left shift result. This reduces the area overhead of a single left shifter.

[0037] (3) Reduce the bit width of the shifter to reduce its area:

[0038] For shifter operations, the maximum required shift amount is 10⁵ (shifts exceeding 10⁵ are simply padded with 0s). However, based on actual operator statistics, shifts between 0 and 31 are sufficient for most computational scenarios. Therefore, the shifter bit width is set to (10⁵ + SHF_NUM)-bit. SHF_NUM is configurable; currently, based on existing operator statistics, SHF_NUM is set to 32, with a maximum shift amount of 31. If the shift exceeds this maximum, the pipeline pauses. For shifts less than 32 in the current cycle, for shifts greater than 32 in the next cycle, 0s are padded to the beginning to complete the shift. This approach avoids performance loss in common scenarios while reducing area overhead.

[0039] B. Optimization of the rear guide section shifter

[0040] The present invention reduces the bit width of the shifter by directly correcting the shift data in advance through the control circuit, provided that the timing permits.

[0041] The maximum shift per cycle is 53, which reduces the bit width of the shifter to 85 bits and the maximum shift amount to 32. The bit width reduction of the shifter does not rely on pipeline pauses, but is achieved by removing 32 bits of 0 from the high part of the shifted data in advance through internal control signals, and then adding 0 to the end to reduce the shift amount exceeding 32. Then the shifter is used to obtain the final shift result. The execution is as follows: (I) When the shift amount is < 32, the left shift shifter can be directly used for shifting.

[0042] (II) When the shift amount is greater than 32, the shift data adjustment module needs to be entered to process the shift data. 32 bits of 0 are removed from the front and 32 bits of 0 are added to the back. The processed data enters the left shifter for the remaining shift to obtain the final result.

[0043] In this way, the bit width of the shifter is reduced, thereby reducing the area overhead.

[0044] 3. Adder optimization

[0045] After obtaining the alignment result, the solution of this invention first enters a 9-bit low-half carry-detecting adder. If a carry occurs, the carry result is directly fed to a 55-bit adder to obtain the sum of the high-half result. If a carry is detected or a precise calculation result is required, the pipeline pauses, and the 55-bit adder is reused to calculate the low-half result. Through pipeline pauses, the 55-bit adder is reused multiple times, using a total of 64 bits of adders. The bit width of the low-half carry-detecting adder here is LSB_NUM+1, which is a configurable value. LSB_NUM is currently set to 8 because, in operator statistics, 9-bit carry detection is sufficient to meet most common cases.

[0046] From a practical application perspective, the desired precision can usually be obtained after the 64-bit adder is used. The probability of needing to use a 55-bit adder with pipelined pauses is relatively small. Therefore, in the mantissa summation part, this solution uses pipelined pauses to reuse the adder for low-probability special cases. Although some performance is sacrificed in special cases, the adder bit width is reduced while still ensuring basic performance in common scenarios, which significantly improves the adder area.

[0047] 4. Summary

[0048] In summary, this invention uses a single data path algorithm, which avoids incurring additional area costs for multiple different devices for the same logic. To ensure performance in common scenarios, it is combined with real-world application scenarios and statistical analysis of relevant operators to ensure that these common cases do not result in pipeline interruptions and performance losses. For special low-probability events, performance is sacrificed to reduce their area. This strategy achieves a significant area improvement compared to dual data paths, while essentially guaranteeing performance in common cases. Attached Figure Description

[0049] The accompanying drawings, which are provided to further illustrate the invention and form part of this application, are not intended to limit the scope of the invention.

[0050] Figure 1This is a schematic diagram of the pipeline implementation process corresponding to the method of the present invention.

[0051] Figure 2 This is a schematic diagram of the P0 level of the flow stage of the present invention.

[0052] Figure 3 This is a schematic diagram of the P1 stage of the flow stage of the present invention.

[0053] Figure 4 This is a schematic diagram illustrating the reduction of the shifter bit width and the reduction of area in the P1 stage of the flow stage of the present invention (3).

[0054] Figure 5 This is a schematic diagram of the P2 stage of the flow stage of the present invention.

[0055] Figure 6 This is a schematic diagram of the P3 level of the flow stage of the present invention. Detailed Implementation

[0056] To better understand the technical content and advantages of the present invention, the present invention will now be described in further detail with reference to the accompanying drawings.

[0057] This invention relates to the field of chips, and its main design aims to minimize area while maintaining the performance of double-precision floating-point operations. The application of this solution offers advantages such as reduced hardware area and lower power consumption.

[0058] In addition, this article contains the following terms:

[0059] (1) a, b, c operands, for three-operand instructions such as multiply-add instructions, represent a*b+c; (2) the product result exponent is the sum of the exponents of operands a and b - offset (the offset is 1023 for double-precision floating-point numbers), and the exponent difference mentioned in the text refers to the absolute value of the difference between the product result exponent and the exponent of operand c.

[0060] (3) The exponent alignment operation refers to aligning the mantissa of the smaller exponent operand with the mantissa of the larger exponent operand based on the exponent difference between two operands with different exponents.

[0061] (4) Postnormalization refers to the fact that after the floating-point calculation is completed, the exponent may exceed 0, but the mantissa result is a denormalized number. At this time, the floating-point number needs to be normalized.

[0062] (5) Leading zeros refer to the number of zeros that appear in the mantissa when the hidden bit is 0, up to a single 1; product leading zeros refer to the number of leading zeros in the mantissa result obtained after multiplying operands a and b; post-ruling leading zeros refer to the number of leading zeros generated in the mantissa of the result after post-ruling the floating-point calculation.

[0063] (6) The rounding part contains three bits, namely the guard bit, the round bit, and the sticky bit; the guard bit is the last bit of the mantissa, the round bit is the first bit after the last bit of the mantissa, and the sticky bit is the OR of the second bit and all subsequent bits after the last bit of the mantissa.

[0064] Specifically, the present invention proposes an area optimization method for a double-precision multiplier adder based on the pipeline stall technology.

[0065] The main body of the multiplication-addition algorithm of the present invention's solution:

[0066] After obtaining the three operands a, b, and c, first calculate the product result of a*b, align the product result with the c operand (addend operand), then perform the mantissa summation operation, enter the post-normalization part for normalization, and finally complete rounding, abnormal state judgment, and obtain the final result.

[0067] The content of the optimization method lies in alignment. Before alignment, it is necessary to obtain the mantissa result of the product, the leading zero result of the product, the exponent difference, and the c operand (addend operand). Among them, the alignment shift amount of part of the exponent difference can offset the normalization shift amount of the leading zero of the product. The specific alignment method is introduced as follows: (1) The multiplication exponent result > the exponent of the c operand

[0068] a. Exponent difference > leading zero of the product: The product result is the large exponent, and a left shift normalization with a shift amount equal to the leading zero of the product is required. The c operand is the small exponent, and a right shift alignment with a shift amount equal to the exponent difference - the number of leading zeros of the product is required. At this time, two shifts are required, and the multiplication result is still the large operand; if no leading zero of the product is generated at this time, only the c operand needs to be shifted by the exponent difference;

[0069] b. Exponent difference < leading zero of the product: Before shifting, the product result is the large exponent. First, perform a left shift normalization of the multiplication mantissa with a shift amount equal to the leading zero of the product. At this time, because the exponent difference < the leading zero of the product, the product result instead becomes the small exponent. At this time, a right shift alignment with a shift amount equal to the leading zero of the product - the exponent difference is still required for the shifted multiplication mantissa;

[0070] From the overall effect, only the multiplication mantissa needs to be left-shifted by the exponent difference. At this time, the multiplication result becomes the small operand and needs to be exchanged;

[0071] c. Exponent difference = leading zero of the product: At this time, only a left shift normalization of the multiplication mantissa with a shift amount equal to the leading zero of the product is required to complete the alignment of the c operand and the multiplication result;

[0072] (2) The multiplication exponent result < the exponent of the c operand

[0073] Regardless of the relationship between the leading zeros of the product and the exponent difference, the multiplication result will always be a small exponent. First, the mantissa of the multiplication is shifted left by the amount of the leading zeros of the product to normalize it. At this time, the exponent of the multiplication result is even smaller. It is still necessary to shift the mantissa of the multiplication after shifting by the amount of the leading zeros of the product plus the exponent difference to right to align the exponents. From the overall effect, it is only necessary to shift the mantissa of the multiplication to the right by the exponent difference. At this time, the multiplication result is still a small operand.

[0074] (3) Multiplication result = c operand exponent (exponent difference = 0)

[0075] a. If the product leading zero = 0, the multiplication result and the c operand have already been aligned and no shift is needed; b. If the product leading zero ≠ 0, the exponent difference is less than the product leading zero. First, the mantissa of the multiplication is shifted left by the product leading zero for normalization. After the shift, the exponent difference is the product leading zero. Then, the adjusted mantissa result needs to be right-shifted by the product leading zero for alignment. From the overall result, no shift is needed.

[0076] In the process of performing double-precision floating-point multiplication and addition calculations, such as Figure 1 As shown, the corresponding flow stage implementation of this invention is as follows:

[0077] P0 stage, the first pipeline stage: performs multiplication, leading zero counting, and special value judgment modules; P1 stage, the second pipeline stage: performs alignment shifting and comparison operations.

[0078] P2 stage, the third pipeline stage: summation of mantissas after order alignment;

[0079] Level P3, the fourth pipeline stage: post-processing, rounding, final result processing, and final exception state judgment.

[0080] The detailed plans for each flow stage are as follows:

[0081] The P0 level requires two clock cycles to implement, such as Figure 2 As shown:

[0082] The first pipeline stage yields three operands: a, b, and c; including:

[0083] 1) Special value judgment module:

[0084] The instruction control signal module (1-1) and the special value judgment module (1-2) jointly perform the judgment of internal special values;

[0085] (1) Introduce the concept of effective operation, and decompose the internal information of the instruction through the instruction control module (1-1). The instruction and the operand sign bit together determine whether the actual operation is addition or subtraction.

[0086]

[0087]

[0088] Note: For multiply-accumulate instructions, the sign bit of mul_res means the sign bit of the product result of the multiply-accumulate instruction, and the sign bit of oprc means the sign bit of the C operand;

[0089] The following is a detailed explanation of the four instructions of the multiplication-addition class in accordance with the table: FMADD: that is, a*b+c, where mul_res is the sign bit of the product result of a*b, and the input operation is +;

[0090] FMSUB: That is, a*bc, where the mul_res sign bit represents the sign bit of the product result of a*b, and the input operation is -;

[0091] FNMADD: That is, -a*bc, where the sign bit of mul_res represents the sign bit of the product result of -a*b, and the input operation is -;

[0092] FNMSUB: That is, -a*b+c, where the sign bit of mul_res represents the sign bit of the product result of -a*b, and the input operation is +;

[0093] (2) After obtaining a valid operation, a judgment is made on the internal special value;

[0094] Multiplication-addition instructions require the multiplication to be performed first, followed by the summation of the mantissas based on the valid operations. Therefore, the special value judgment is shown in the following three tables:

[0095] The table below shows the results of special value judgments for multiplication:

[0096]

[0097] The table below shows the results of special value judgments for valid operations that are addition:

[0098]

[0099]

[0100] The table below shows the results of special value judgments for valid operations that are subtraction:

[0101]

[0102] Note: (sub)norm is a general term for normalized and denormalized numbers. NaN numbers (Not a number, representing an inexpressible value) are divided into two categories: qNaN numbers and sNaN numbers.

[0103] sNaN is a number whose exponent is all 1s, whose first digit is 0, and whose overall mantissa is not 0.

[0104] qNaN is a value whose exponent is all 1s and whose mantissa is 1 in the first position.

[0105] RISC-V specifies that if the result of a floating-point operation is a NaN number, then a fixed NaN number should be used. The NaN value corresponding to double-precision floating-point is 0x7ff8_0000_0000_0000. Therefore, the qNaN assignment for the final result needs to be assigned a fixed value, i.e., qNaN = 64'h7ff8_0000_0000_0000;

[0106] The table crossed out by the horizontal line indicates that the result needs to be obtained through normal calculation, rather than a special value; for multiplication and addition instructions, firstly, the result of a*b needs to be assigned to |x| according to the special value table of multiplication, and then the special value result is obtained from the corresponding table according to the corresponding valid operation; if the above special value result is generated, a special value signal needs to be set to mark that the operation is a special case, and the result is assigned to the special value result obtained above, which is convenient for subsequent calculation; (3) After obtaining the valid operation, the invalidity exception of the special value is judged and left for use by P3 level;

[0107]

[0108]

[0109] 2) Product mantissa calculation module:

[0110] Since this module needs to calculate the product result, and one clock cycle is not enough to complete the operation, it is completed using two clock cycles:

[0111] Operands a and b need to enter the multiplier (1-3) to obtain two partial product results. The adder is used to sum the partial product results to obtain the product mantissa calculation result. The lower half partial product first enters the 53-bit adder (1-4), i.e., the lower half adder (1-4), to calculate the sum of the lower 52-bit partial products. The carry result generated by the lower half summation will be passed to the higher half. The partial products entering the higher half enter the 54-bit adder (1-5), i.e., the higher half adder (1-5), to obtain the product mantissa calculation result.

[0112] At this point, it is necessary to enter the selector module (1-6) that selects the final product mantissa result based on the instruction control signal and the special value judgment signal, and obtain the final product mantissa result;

[0113] 3) Pre-statistics module for leading zeros in product:

[0114] First, the selector (1-7) used to determine the denormalized number needs to be entered. Based on the operand situation, the selector (1-7) is selected to determine the denormalized number, and the mantissa data to be counted is obtained. Then, the 53-bit leading zero counting module (1-8) is entered to count the number of leading zeros of the denormalized data. Then, the next selector (1-9) used to determine the multiplier situation is entered. Based on the multiplier situation, the selector (1-9) adjusts the number of leading zeros. If both numbers are normalized, the statistical result is adjusted to 0. Otherwise, the number of leading zeros obtained from the previous leading zero counting module (1-8) is inherited to obtain the final product leading zero pre-statistical result.

[0115] 4) Exponent difference and comparison logic (1-10) module:

[0116] This module mainly compares the exponent of the product result with the exponent of the C operand, as well as the exponent difference with the leading zero of the product, thereby facilitating the exponent shift of the P1 level and initially determining the shift method required for the P1 level.

[0117] In summary, the P0 level requires a multiplier module with a product of 53-bit × 53-bit and a product of 106-bit, a 53-bit leading zero counting module, and a 107-bit adder. The counting of leading zeros in the product is completed in the P0 level.

[0118] The P1 level, such as Figure 3 As shown:

[0119] The input of the second pipeline stage yields the multiplication result, the comparison result between the product exponent and the exponent of the c operand, the comparison result between the exponent difference and the leading zero of the product, and the comparison result between the exponent difference and the leading zero of the product, which then enters the second pipeline stage for computation; after the second pipeline stage operation, the results of the two operands after exponent alignment are obtained;

[0120] 1) Comparison logic:

[0121] The mantissa result of the product and the mantissa of the c operand will enter the mantissa comparison logic (2-5). The size is initially roughly compared according to the comparison signal of the P0 level exponent, and then enters the shift module. For timing considerations, the mantissa comparison logic (2-5) needs to compare the higher half 53-bit mantissa, and merge to complete a more accurate comparison of the two numbers, so as to obtain the size of the higher half of the two numbers. This also facilitates the selection of mantissa update in the case of pipeline pause.

[0122] 2) Alignment part:

[0123] There are three important design points in the hardware design of the alignment section, as follows:

[0124] (1) For special alignment cases, when the flow stops, the shifter is reused to reduce area overhead:

[0125] Analysis of the alignment method reveals that if and only if the multiplication exponent result > the exponent of the c operand, and the exponent difference > the leading zero of the product, and the leading zero of the product ≠ 0, then the mantissa result of the product needs to be left-shifted for normalization, and the c operand needs to be right-shifted for alignment. From an application perspective, this is a low-probability and uncommon scenario. Therefore, a pipeline pause is implemented here, and the shifter is reused for shifting to reduce the area overhead of the shifter.

[0126] (2) Use only right shifters, and implement left shifts using right shifters:

[0127] The analysis of the alignment method shows that right shifts are far more common than left shifts. Adding another shifter for left shifts would incur additional area costs. Therefore, this method uses only one right shifter in the alignment part, and reverses the left shift, right shift, and then reverses the right shift to obtain the corresponding result.

[0128] (3) Reduce the bit width of the shifter to reduce its area:

[0129] For shifter shifting, the maximum required shift amount is 10⁵. Shift amounts exceeding 10⁵ are simply filled with 0.

[0130] Since the product result has a precision of 106 bits, a sticky bit is added at the end for subsequent rounding precision. Because the shift amount exceeds 10⁵, the shift amount is at least 10⁶. All bits of the product result will be shifted to the sticky bit. This right shift operation is equivalent to adding 106 bits of 0 at the beginning and then ORing the 106-bit product result to form a sticky bit for rounding. See below for details. Figure 4 As shown.

[0131] From the perspective of actual operator statistics, a shift range of 0-31 is sufficient for general computing scenarios. Therefore, the shifter bit width is set to (105+SHF_NUM)-bit. SHF_NUM is configurable and can be adjusted according to different application scenarios. Currently, based on existing operator statistics, SHF_NUM is set to 32, and the maximum shift range is 31. If the shift range exceeds this maximum, the pipeline will pause. For the portion of the shift less than 32 in the current cycle, for the portion greater than 32 in the next cycle, zeros will be added to the beginning to complete the shift.

[0132] In summary, the overall implementation of the order-pairing part is summarized as follows:

[0133] After the mantissa comparison logic (2-5) is passed, the size mantissa is obtained. According to the relevant shift control logic (2-11), the selector (2-7) used to obtain the shifted data selects the corresponding shifted data. If it is a left shift, the shifted data first enters the reverse order module (2-6) for reverse order operation. The shift amount is specifically determined by the shift amount adjustment logic (2-12). After the shifted data and shift amount are ready, it enters a 137-bit right shifter (2-8) to obtain the shift result. If it is a left shift, it also needs to enter a reverse order operation module (2-9) before the result is obtained. Finally, according to the shift control signal, the selector (2-10) used to select the mantissa result after shifting is used to obtain the final mantissa shift result.

[0134] If a shifter needs to be reused for pipeline pauses, the selector (2-1 / 2-2 / 2-3 / 2-4) is controlled according to the selector control logic (2-14) in the current pipeline. That is, selector (2-1) is used to update the mantissa result of the product after the pipeline pause, selector (2-2) is used to update the mantissa result of the C operand after the pipeline pause, selector (2-3) is used to update the leading zero of the product after the pipeline pause, and selector (2-4) is used to update the results of swaps, comparisons, exponent differences, etc. after the pipeline pause. Each input is updated, and the above shift operations are reused in the next pipeline to obtain the final result.

[0135] If the pipeline needs to be paused due to a shift amount exceeding 31 but less than 105, the shifter logic is not reused. After the pipeline completes the shift of the portion less than 32, the selector (2-1 / 2-2 / 2-3 / 2-4) is controlled according to the selector control logic (2-14). Specifically, selector (2-1) is used to update the product mantissa result after the pipeline pause, selector (2-2) is used to update the C operand mantissa result after the pipeline pause, selector (2-3) is used to update the product leading zero after the pipeline pause, and selector (2-4) is used to update the results of swap, comparison, exponent difference, etc. after the pipeline pause. Each input is updated. In the next pipeline, according to the control signal output by the shift control logic (2-11), the selector (2-10) used to select the mantissa result after the shift in the next pipeline directly performs relevant zero-adding processing control on the remaining shifted data to obtain the final result.

[0136] Accordingly, the exponent adjustment logic (2-13) is used in the exponent adjustment module to further adjust the exponent, and it is adjusted to exponent-product-leading zero only when the mantissa result of the multiplication needs to be left-shifted and normalized.

[0137] The specific scheme for the alignment part is as follows:

[0138] (1) The water flow is continuous

[0139] a. The multiplication exponent result < the c operand exponent, and the shift amount does not exceed 32;

[0140] b. The multiplication exponent result < the c operand exponent, and the shift amount exceeds 105;

[0141] c. The multiplication exponent result > the c operand exponent, the leading zeros of the product result are 0, and the shift amount does not exceed 32;

[0142] d. The multiplication exponent result > the c operand exponent, the leading zeros of the product result are 0, and the shift amount exceeds 105;

[0143] e. There are special values;

[0144] f. The multiplication exponent result = the c operand exponent;

[0145] (2) The pipeline stalls once

[0146] a. When the multiplication exponent result < the c operand exponent and the shift amount exceeds 31;

[0147] In this case, only the multiplication mantissa needs to be right-shifted by the exponent difference for alignment; however, since the shift amount exceeds 31, a pipeline stall is required at this time to complete the shift;

[0148] The first beat enters the right-shift shifter to perform the shift of the part where the shift amount is less than 32. After the shift is completed, it enters the selector and is placed in the small operand position; when entering the pipeline in the next beat, the shift amount in the shifter is 0. At this time, directly according to the control signal, add 0 to the high half part higher than 31 to ensure the right-shift result; finally, place the c operand in the large operand position and the aligned multiplication result operand in the small operand position;

[0149] b. When the multiplication exponent result > the c operand exponent and the exponent difference ≤ the leading zeros of the product, and the shift amount exceeds 31;

[0150] In this case, the multiplication exponent result needs to be left-shifted by the exponent difference for alignment; the multiplication result should be the small operand;

[0151] The first beat enters the shifter, selects the reverse-order data, and performs the right-shift of the part where the shift amount is less than 32. In this beat, directly transfer the right-shift result to the small operand position; when entering the pipeline in the next beat, the shift amount in the shifter is 0. Directly according to the control signal, add 0 to the part higher than 31, and then select the reverse-order data result to obtain the aligned result;

[0152] c. When the multiplication exponent result > the c operand exponent and the exponent difference > the leading zeros of the product, and both shift amounts do not exceed 31; the leading zeros of the product ≠ 0;

[0153] At this point, the multiplication exponent result needs to be shifted left by the exponent difference to normalize it; then the c operand result needs to be shifted right by the exponent difference to align the exponents. The right shift amount is the exponent difference minus the leading zeros of the product, and the multiplication result is still a large operand.

[0154] In the first step, the shifter is entered, reversed data is selected, and a right shift is performed. At the same time, the reversed data after the shift is selected in the last large operand. At this time, the next shift amount needs to be adjusted at the top level. In the next step, the c operand data is right-shifted to obtain the alignment result.

[0155] d. If the result of multiplication is greater than the exponent of operand c, the leading zero of the product is equal to 0, and the exponent difference is greater than 31;

[0156] At this point, the c operand needs to be right-shifted and aligned. The first step enters the shifter and directly performs the right shift. However, since the shift amount exceeds 32, the flow needs to be paused. In the next step, the control signal is added with 0 to obtain the final result.

[0157] (3) The water flow stopped twice.

[0158] a. The result of multiplication is greater than the exponent of operand C, and the exponent difference is greater than the leading zero of the product. The left shift amount exceeds 31 and the right shift amount does not exceed 31 and is not equal to 1.

[0159] At this point, the multiplication exponent result needs to be shifted left by the exponent difference to normalize it; then the c operand result needs to be shifted right by the exponent difference to align the exponents. The right shift amount is the exponent difference minus the leading zeros of the product, and the multiplication result is still a large operand.

[0160] In the first cycle, the shifter selects the reversed data and performs a right shift. Since the left shift exceeds 31, the pipeline needs to pause. The result of the multiplication shift is used on the last small operand. During the top-level selection, the multiplier selects the shifted result, while the c operand remains unchanged. In the second cycle, the shifter's shift amount is adjusted to 0, and zeros are added according to the control signal. At this point, the left shift is complete, and the reversed data is selected as the final result. At this point, the top-level shift amount needs to be adjusted to the exponent difference minus the product leading zero. After the third cycle begins, the c operand is right-shifted to obtain the exponent alignment result.

[0161] b. The result of multiplication is greater than the exponent of operand c, and the exponent difference is greater than the leading zero of the product. The left shift amount does not exceed 31 and the right shift amount exceeds 31.

[0162] At this point, the multiplication exponent result needs to be shifted left by the exponent difference to normalize it; then the c operand result needs to be shifted right by the exponent difference to align the exponents. The right shift amount is the exponent difference minus the leading zeros of the product, and the multiplication result is still a large operand.

[0163] In the first cycle, the data is entered into the shifter, reversed, and right shift is performed. The left shift amount does not exceed 31. After this cycle, the reverse shift result is selected to obtain the normalized multiplication result. The shifted result needs to be transmitted at the top layer, while the c operand remains unchanged. In the second cycle, an exponent shift is performed. Since the right shift amount exceeds 31, a pipeline pause is required, and the right shift of the portion less than 32 is performed first. In the third cycle, a control signal is added with 0s to complete the right shift and exponent shift result. The c multiplication exponent result is greater than the c operand exponent, and the exponent difference is greater than the leading zero of the product. The left shift amount does not exceed 31, and the right shift amount is 1.

[0164] In the first step, the product is shifted to the left by the multiplication exponent and normalized. In the second step, although the right shift is 1 and does not exceed 32, the two products may have inaccurate leading zeros. Therefore, a pipeline pause is required for a second comparison. There may be cases where the products are not equal before but are equal after the shift.

[0165] (4) The water flow stopped three times.

[0166] a. The result of multiplication is greater than the exponent of operand C, and the exponent difference is greater than the leading zero of the product. The left shift amount exceeds 31 and the right shift amount exceeds 31.

[0167] In the first cycle, the shifter selects the reversed data and performs a right shift. Since the left shift exceeds 31, a pipeline pause is required. The result of the multiplication shift is used on the last small operand. At the top-level selection, the multiplier selects the shifted result, while the C operand remains unchanged. In the second cycle, the shifter's shift amount is adjusted to 0, and zeros are added according to the control signal. The left shift is now complete, and the reversed data is selected as the final result. At this point, the top-level shift amount needs to be adjusted to the exponent difference minus the product's leading zeros. In the third cycle, an exponent alignment shift is performed. Since the right shift exceeds 31, a pipeline pause is required, and the right shift of less than 32 is performed first. In the fourth cycle, zeros are added to the control signal, completing the right shift alignment.

[0168] b. The result of multiplication is greater than the exponent of operand c, and the exponent difference is greater than the leading zero of the product. The left shift amount exceeds 31 and the right shift amount is 1.

[0169] In the first cycle, the shifter selects the reversed data and performs a right shift. Since the left shift exceeds 31, a pipeline pause is required. The result of the multiplication shift is used on the last small operand. During the top-level selection, the multiplier selects the shifted result, while the c operand remains unchanged. In the second cycle, the shifter's shift is adjusted to 0, and zeros are added according to the control signal. At this point, the left shift is complete, and the reversed data is selected as the final result. In the third cycle, although the right shift is 1, a pipeline pause is required to perform parallel operations before exponent comparison to eliminate the influence of leading zeros in the product and the exponent difference. The result is obtained in the fourth cycle through comparison.

[0170] In summary, the P1 stage requires a 137-bit shifter for alignment shifting. All alignment shifting is completed within this stage pipeline, without incurring additional alignment shifter area costs in other pipeline stages.

[0171] The P2 level, such as Figure 5 As shown:

[0172] The input of the third pipeline stage receives the multiplication result after alignment and the c operand result, and then enters the third pipeline stage for calculation; after the third pipeline stage operation, the result of mantissa summation is obtained;

[0173] 1) Sum of last digits:

[0174] There are three important design points in the hardware design of the mantissa summation part, as follows:

[0175] (1) The mantissa summation operation has two possibilities: addition or subtraction of the mantissas, which is determined by the valid operations obtained at level P0:

[0176] Adding the last two digits: The effective operation is addition; the two last two digits are directly fed into the adder for summation.

[0177] Subtraction of mantissas: The effective operation is subtraction. Since the previous alignment operation completed the comparison logic operation, this must be the larger mantissa minus the smaller mantissa. In this case, for the expression (xy), in order to use the adder for calculation, we can use the expression (xy) = (x + (~y) + 1) and use addition to complete the subtraction operation;

[0178] (2) A 9-bit carry-detecting adder (3-10) in the lower half of the bit is used to supplement the precision and detect possible carry in the 55-bit mantissa summation adder (3-6):

[0179] Addition case:

[0180] a. If operand c > product operand, since the product result is 106-bit, in this case, the lower 53 bits of operand c are all 0. The higher parts of the two operands need to be summed, while the lower parts of the two operands do not need to be summed and are directly the lower part of the multiplication result. Since the lower part does not generate carry output, the result can be calculated without pipeline interruption.

[0181] b. In other cases, we need to check whether the added 9-bit carry detection adder in the lower half can detect the possibility of a carry and whether a carry has occurred in the lower half, and then pause the pipeline accordingly, reuse the 55-bit adder to complete the summation of the lower half, thereby reducing the area.

[0182] That is, if the carry detector in the added lower half has already generated a carry during summation, the carry can be promptly propagated to the 55-bit adder in the higher half for summation. At this point, the result in the higher half is already accurate. As a summation case, there is no situation where the higher half is all 0 and requires post-regulation.

[0183] If the carry-detecting adder detects that a carry may be needed in the lower half of the data, the lower half of the data needs to be fully calculated to ensure the accuracy requirements. Therefore, a pipeline pause method is used to multiplex the 55-bit adder to obtain the accurate lower half result.

[0184] Subtraction:

[0185] a. When subtracting, but no leading zeros are found, the lower half of the full precision is not required; only the rounded part needs to be provided.

[0186] b. Subtraction results in a leading zero, requiring subsequent calibration. At this point, the pipeline needs to be paused, and the 55-bit adder is reused to calculate the precision of the lower half to ensure smooth subsequent calibration.

[0187] (3) The internal special module comments are as follows:

[0188] a. 9-bit low-half partial carry-detecting adder

[0189] Here, a 9-bit lower half partial carry detector is used. If the lower 5 bits are all 1, it is considered that there is a probability of a carry. The lower 5 bits are used for detection because, according to operator statistics, 5-bit detection can meet the majority of carry detection cases. In fact, the number of bits is adjustable here.

[0190] b. When the 55-bit adder is in subtraction mode and the c operand > the multiplication result, it is necessary to check the 9-bit of the sum of the mantissas in the high half. If the 9-bit of the sum of the mantissas in the high half is found to be 1, the calculation is considered to be complete.

[0191] The 9-bit detection is required here because if the 9-bit result of the summation of the mantissa in the high half contains 1, then the 9-bit adder can meet the accuracy required by the subsequent rule. Otherwise, it cannot meet the requirement. Therefore, a pipeline pause is needed to reuse the adder to obtain the entire calculation result accurately.

[0192] c. The bit width of the carry detection adder here is LSB_NUM+1, which is configurable data. LSB_NUM is currently set to 8 because in operator statistics, 9-bit carry detection is sufficient to meet most common cases.

[0193] The overall scheme for summing the last digits is implemented as follows:

[0194] First, the data to be summed needs to be selected according to the carry detection adder data selection module (3-9). If it is a subtraction operation, it needs to go through the inversion operation module (3-4) to get the opposite number; if it is an addition operation, no additional operation is required. The next step is to enter the (LSB_NUM+1)-bit carry detection adder (3-10). Its carry needs to be determined according to the data after inversion +1 in the case of subtraction. After obtaining the carry detector carry signal, it needs to enter the carry signal control logic (3-7) together with the external control signal to determine whether to carry to the high half 55-bit adder. At this time, the carry signal is obtained, and the adder data has been selected by the adder data selection module (3-5). At this time, it enters the 55-bit mantissa summation adder (3-6) to obtain the mantissa summation result. The mantissa summation result, the big mantissa, the little mantissa, the special value signal and the pipeline pause signal enter the data selection module (3-8) to obtain the final result.

[0195] If a pipeline pause is required at this point, the pipeline pause signal output from the carry detection adder (3-10) to the pipeline pause control logic module (3-11) is checked to determine whether a pipeline pause is needed, and the 55-bit adder is reused. If a pause is needed, the pipeline pause signal control selector (3-1 / 3-2), i.e., the selector (3-1) used to update the big mantissa after alignment after pipeline pause, and the selector (3-2) used to update the little mantissa after alignment after pipeline pause, selects to update the input result and performs the next cycle of operation.

[0196] 2) Complete all comparison operations:

[0197] The result after shifting needs to go through the comparison module (3-3) to compare the lower half of the mantissa, which is used to supplement the comparison result of the upper half of the mantissa of P1 level. At this time, it is necessary to generate a judgment on whether the two are opposite numbers or equal numbers, so as to facilitate the final sign bit judgment of the next pipeline.

[0198] In summary, the P2 stage requires a 64-bit adder in total. All mantissa summation operations are completed in this stage pipeline, without incurring additional summation adder area costs in other pipeline stages.

[0199] The specific execution plan for summing the last digits is as follows:

[0200] (1) The water flow is continuous:

[0201] a. The result is a special value;

[0202] b. If the c operand is greater than the multiplication result, and the difference between their exponents is 105, the larger operand is much larger than the smaller operand;

[0203] If it is a subtraction, there will be no requirement for normalization of the leading zero of the subsequent rule; the following 1 can be used as a sticky bit.

[0204] If it is an addition, since the c operand > the multiplication result, the lower half of the subsequent part is all 0, so there will be no carry and the calculation can be completed in one step;

[0205] c. If the operand c > the result of the multiplication, then the two are an addition operation;

[0206] If the difference between the two exponents exceeds 53, no carry will be generated, and the result will be completed in one step.

[0207] If the difference between the two exponents does not exceed 53, then if a carry occurs, it will be reflected in the addition of the higher half, and the result can be completed in one step.

[0208] d. If the c operand > the multiplication result, perform a subtraction operation. If a 1 is detected in the high 9 bits of the high half of the calculation result, there is no need to be precise for the low half, because the post-normalization with leading zeros does not require subsequent precision. The calculation is considered complete.

[0209] e. If the carry detection addition of the 9-bit lower half does not detect the carry probability, and the valid operation does not meet the condition that the mantissa of the lower half is followed by 1, then the subsequent part does not need to have full precision, and the calculation is considered complete.

[0210] (2) The water flow stops once:

[0211] a. The carry detection adder in the lower half of the 9-bit bit detects a probability of a carry, and a carry has already occurred in the first step;

[0212] In the first cycle, the 9-bit low half carry detection adder detects a probability of a carry, which may generate a carry in the high half. At this point, a pipeline pause is required. In the second cycle, the 55-bit adder is reused to calculate the low half to ensure data correctness.

[0213] If the first beat has already generated a carry in the high half, and the second beat pauses, although the low half will generate a carry, this carry has already been added to the sum of the high half in the first beat. Therefore, there is no need to pause a second time to increment the high half data.

[0214] b. The carry detection adder detects a probability of carrying in the lower half of the 9-bit bit, but no carry is generated in the second cycle;

[0215] In the first cycle, the 9-bit lower half carry detection adder detects a probability of a carry, which may result in a carry to the higher half. At this point, a pipeline pause is required. In the second cycle, the 55-bit adder is reused to perform summation on the lower half to ensure data correctness. If the summation result of the lower half calculated in the second cycle does not carry 1 to the higher half, the summation result of the higher half is accurate, and no pipeline pause is required again.

[0216] c. If the mantissa of the smaller operand contains a 1 in the subsequent bits, and the operation is a subtraction, and the summation of the lower half does not produce a carry;

[0217] If there is a 1 in the mantissa of the small operands that are not included in the calculation in the first step, and it is a subtraction, the whole result needs to be calculated completely to ensure that there is accurate data shift if there is a leading zero shift in the subsequent step. In the second step, since no carry operation will be generated, if a carry is generated, it can be detected in the first step, and the result obtained at this time is the accurate result.

[0218] (3) The water flow paused twice:

[0219] a. The carry detection adder in the lower half of the 9-bit bit detects a probability of carrying, and a carry is indeed generated in the lower half during the second clock cycle;

[0220] In the first cycle, the 9-bit low-half carry detection adder detects a probability of a carry, which may generate a carry in the high half. At this point, a pipeline pause is required. In the second cycle, the 55-bit adder is reused to calculate the low half to ensure data correctness. The sum of the low half calculated in the second cycle needs to be carried over to the high half. This indicates that the sum of the high half calculated in the previous cycle is inaccurate, and another pipeline pause is required. In the third cycle, the adder enters the high half and performs a +1 operation on the result.

[0221] The P3 level, such as Figure 6 As shown:

[0222] The input of the fourth pipeline stage yields the result of mantissa summation. The original exponent is the exponent result adjusted by the P1 stage. The exponent obtained through the P2 stage, the sign bit to be computed, and the comparison result are then fed into the fourth pipeline stage for calculation. After the calculation in the fourth pipeline stage, the final result and the abnormal status are obtained.

[0223] 1) Post-regulation section:

[0224] The adder data is obtained from the P2 pipeline stage. It consists of 2 hidden bits, 104 mantissa bits, 1 rounding bit, and 1 sticky bit, totaling 108 bits. The exponent should be the result of the exponent adjusted by the P1 stage. The exponent obtained through the P2 stage first enters the leading zero module for statistics and then performs a shift operation.

[0225] There are three important design points in the hardware design of the rear section, as follows:

[0226] (1) By pausing the flow, the leading zero statistics module is reused for uncommon situations, thereby reducing the area of ​​the leading zero statistics module.

[0227] Based on actual statistical results, the case where the high half is all 0 is rare. Therefore, a 53-bit leading zero statistics module can meet the needs of most scenarios. In special cases, pipeline pauses can be reused to achieve the purpose of reducing area.

[0228] After obtaining the mantissa sum, the mantissa needs to be divided into high and low parts. First, count the number of leading zeros in the 53-bit part of the high half. If a 1 appears in the high half, no pipeline pause is needed, and the leading zero result in the low half is checked. Otherwise, pipeline pause is needed, and the leading zero result in the low half is checked.

[0229] (2) Back gauge shifting uses only the left shifter;

[0230] The back-shift part only has one left shifter to perform the back-shift with leading zeros; for the right shift overflow case, as can be seen from the previous alignment algorithm analysis, the right shift here is at most one bit, which can be directly completed by bit concatenation;

[0231] (3) If timing permits, the shifter data can be corrected in advance by controlling the circuit to reduce the shifter bit width.

[0232] The maximum shift per cycle is 53, which reduces the bit width of the shifter to 85-bit and the maximum shift amount to 32. The bit width reduction of the shifter does not rely on pipeline pauses, but is achieved by removing 32 bits of 0 from the high part of the shifted data in advance through internal control signals, and then adding 0 to the end to reduce the shift amount exceeding 32. Then the shifter is used to obtain the final shift result. The execution is as follows: (I) When the shift amount is <32, the left shift shifter can be directly used for shifting.

[0233] (II) When the shift amount is greater than 32, the shift data adjustment module needs to be entered to process the shift data. 32 bits of 0 are removed from the front and 32 bits of 0 are added to the back. The processed data enters the left shifter for the remaining shift to obtain the final result.

[0234] The reason for reducing the shifter to below 32 is to ensure that the control circuit is as simple as possible; otherwise, the control circuit may be too complex, resulting in additional area overhead.

[0235] For cases where the exponent cannot satisfy the leading zero shift of the subsequent rule, a pipeline pause is required to meet the timing requirements, and the shift is performed in the next clock cycle using a shift amount of exponent - 1.

[0236] The overall solution for the post-guide section is as follows:

[0237] The mantissa summation result is divided into high and low parts. First, it enters the 53-bit leading zero statistics (4-7) to count the leading zeros of the high half. Then, based on the leading zero data and the exponent, it enters the shift amount calculation module (4-8) to obtain the shift amount. The shift data is obtained through the shift data adjustment module (4-9) and enters the 85-bit left shifter. At this time, the shift data is obtained and enters the mantissa selection module (4-13). Based on the signal obtained from the right shift control logic (4-14), the mantissa selection is controlled to determine whether it needs to be shifted right by one bit to obtain the final mantissa result. At the same time, it needs to be adjusted by the exponent adjustment module (4-11) and the rounding part adjustment module (4-12), and the sign bit needs to be calculated by the sign bit calculation module (4-4). These data enter the rounding operation, rounding adjustment and abnormal state judgment module (4-15) to complete the rounding operation, rounding adjustment and abnormal state judgment. Finally, it enters the final result selection (4-16) to obtain the final result.

[0238] For sections requiring a pause in the flow, the flow pause control logic (4-5) and the flow pause selector control logic (4-6) are used to control the selectors (4-1 / 4-2 / 4-3). Specifically, selector (4-1) is used to update the exponent result after the flow pause, selector (4-2) is used to update the high half of the mantissa sum result after the flow pause, and selector (4-3) is used to update the low half of the mantissa sum result after the flow pause. This updates the input result.

[0239] 2) Rounding adjustments:

[0240] The rounding adjustment and the decimal adjustment are performed simultaneously, and the rounding adjustment module (4-12) completes the corresponding functions;

[0241] 3) Exponent adjustment section:

[0242] The exponent adjustment module (4-11) performs the corresponding functions;

[0243] The exponent adjustment is performed synchronously with the subsequent rule, and there are a total of four possibilities: exponent + 1, exponent, exponent - leading zero of the subsequent rule, and 0.

[0244] 4) Rounding operation and post-rounding adjustment:

[0245] This logic is contained in the rounding operation, rounding adjustment and abnormal state judgment module (4-15);

[0246] The rounding is performed according to the rounding mode. If rounding requires +1, the carry in the 54-bit adder needs to be adjusted to 1; if rounding does not require +1, the carry in the 54-bit adder needs to be adjusted to 0. The final rounding result is then obtained, and the exponent and mantissa are adjusted again based on this rounding result: Exponent adjustment: If rounding +1 causes the mantissa to overflow by 1 bit, the exponent needs to be +1.

[0247] Arrangement of last digits: If rounding by +1 causes the last digits to overflow by 1 digit, the last digits need to be adjusted one digit to the right.

[0248] 5) Final sign bit calculation:

[0249] The sign bit calculation (4-11) completes the corresponding function;

[0250] (1) If a special value exists, assign the sign bit of the special value;

[0251] (2) The absolute values ​​of the two numbers are equal, that is, the product result after alignment is equal to the c operand, and the effective operation is subtraction, which is related to the rounding mode; if it is rounding to negative infinity, that is, the sign bit is negative; otherwise, the sign bit is positive.

[0252] (3) The remaining cases need to be determined based on the exchange signal and the subtraction signal, as shown in the table below:

[0253] Where A is the product result, B is the c operand, and mult_sign is the sign of the product result obtained from the P0-level adjustment; the actual operation here is consistent with the effective operation at the P0 level.

[0254] condition Practical operation mult_sign Final symbol |A|<|B| - + - |A|<|B| - - + |A|<|B| + + + |A|<|B| + - - |A|>|B| - + + |A|>|B| - - - |A|>|B| + + + |A|>|B| + - -

[0255] 6) Anomaly detection:

[0256] This logic is contained in the rounding operation, rounding adjustment and abnormal state judgment module (4-15);

[0257] (1) Invalid exception: Found in the special value judgment at the P0 level;

[0258] (2) Division by zero exception: None;

[0259] (3) Overflow exception: The result is greater than the maximum exponent value after the exponent is updated, and it is not an infinite, qNaN result or invalid exception at this time;

[0260] (4) Underflow anomaly: After rounding, the data is strictly between ± minimum normalized number (+ minimum normalized number is 64'h0010_0000_0000_0000, - minimum normalized number is 64'h8010_0000_0000_0000), and there is inaccuracy;

[0261] (5) Inaccuracy anomaly: The round bit or sticky bit is 1, or an overflow anomaly occurs at this time;

[0262] 7) Final result processing:

[0263] The final result should be selected as (4-16) to complete the corresponding function;

[0264] If an overflow exception occurs, special assignments are needed for different maxima depending on the rounding mode. In other cases, only the sign bit, exponent, and mantissa need to be concatenated normally to obtain the final result.

[0265] In summary, the P3 level requires a 53-bit back gauge leading zero statistics module and an 85-bit back gauge shifter.

[0266] The specific implementation plan for the post-regulation section is as follows:

[0267] (1) The water flow is uninterrupted:

[0268] a. The result produces a special value, and the final result is independent of the shifter;

[0269] b. The multiplication result and the c operand operation are opposites of each other, and the effective operation is subtraction, that is, the sum of the mantissas is all 0, and the final result is independent of the shifter;

[0270] c. The high half of the 53 bits is not all 0 and the exponent can also satisfy the shift amount. The maximum shift amount is 53. For the part exceeding 32, first add 32 bits of 0 to the end and then shift. If the shift amount is less than 32, then shift directly. The exponent needs to be adjusted to the value of the exponent minus the value of the leading zeros.

[0271] d. If the exponent result is 0, then a denormalized number has been generated, and no shifting is required.

[0272] (2) The water flow stops once:

[0273] a. After the first beat, the leading zero is greater than the exponent;

[0274] Since the leading zero of the post-normalization is greater than the exponent at this point, the exponent cannot satisfy the shift of the leading zero of the post-normalization. To meet the timing requirements, a pipeline pause is performed. In the next clock cycle, a left shift of the exponent minus 1 is performed. If the shift exceeds 32, the part exceeding 32 is first appended with 32 bits of 0 before the shift is performed. If the shift is less than 32, the shift is performed directly to obtain the final result. The final exponent result should be 0, which is a denormalized number.

[0275] Here the pipeline pauses because the top-level module still selects the high half of the data and the original exponent; b. In the first beat, the high half of the 53-bits are all 0, and the number of leading zeros in the subsequent rule is less than that of the exponent. In the next beat, it is found that the number of leading zeros in the low half of the subsequent rule is still less than that of the exponent.

[0276] Since the first cycle's high half (53 bits) is all 0, and the exponent can satisfy the shift of leading zeros in the subsequent cycle, a pipeline pause is required. At this point, the shifter's result will not affect the input of the next cycle. This pipeline pause occurs when the top-level module selects the low half of the data, simulating the shifting of the high 53 bits (0). In the next cycle, the following module is used to count the number of leading zeros in the low half. The exponent, after the pause adjustment, can still satisfy the shift of leading zeros in the low half. A left shift is performed with the shift amount equal to the leading zero. If the shift amount exceeds 32, the portion exceeding 32 is first appended with 32 bits of 0 before the shift. If the shift amount is less than 32, the shift is performed directly to obtain the final result. The final exponent result should be the exponent minus the value of the leading zeros in the subsequent cycle.

[0277] (3) The water flow pauses twice:

[0278] a. In the first step, the high half of the 53-bits is all 0, and the number of leading zeros is less than that of the exponent. In the second step, the number of leading zeros in the low half is greater than that of the exponent.

[0279] Since the first cycle's high half (53 bits) is all 0, and the exponent can satisfy the shift of leading zeros after normalization, a pipeline pause is required. This pause occurs in the top-level module after the first cycle when selecting data from the low half, simulating the shifting of the high 53 bits (0). In the second cycle, the leading zero counting module is reused to count the number of leading zeros in the low half. At this point, the exponent adjusted after the pause cannot satisfy the shift of leading zeros in the low half, so a pipeline pause is performed to meet timing requirements. The low half of the data is still selected. In the third cycle, the low half of the data is shifted left by the adjusted exponent minus 1. If the shift exceeds 32, the portion exceeding 32 is first appended with 32 bits of 0 before shifting. If the shift is less than 32, the shift is performed directly to obtain the final result. The final exponent should be 0, a denormalized number.

[0280] In summary, this application, considering the application scenarios of double-precision floating-point data, improves the multiplication-addition algorithm while meeting the performance requirements of most double-precision floating-point computation scenarios. It converts the dual data path to a single data path and reduces the bit width based on the actual statistical situation of the operators. By combining this with real-world application scenarios, it ensures that common situations do not result in performance loss due to pipeline pauses. For special low-probability events, performance is sacrificed by reducing the area of ​​the multiplication-addition module. Pipeline pause multiplexing logic blocks are used to improve the area of ​​the adder, shifter, and leading zero counting module, thereby improving the area of ​​the multiplication-addition module.

[0281] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for optimizing the area of ​​a double-precision multiply-accumulator based on flow-through pause technology, characterized in that, In the multiplication and addition algorithm of the optimization method, after obtaining three operands a, b, and c, the product result of a*b is first calculated. Then, the product result and the c operand, i.e., the addend operand, are aligned, and then the mantissa summation operation is performed. After that, it enters the post-normalization part for normalization, and finally, rounding, exception status judgment, and the final result are obtained. The optimization method lies in the alignment. Before alignment, the product mantissa result, the product leading zero result, the exponent difference, and the c operand, i.e., the addend operand, need to be obtained. Among them, the alignment shift amount of part of the exponent difference can offset the normalization shift amount of the product leading zero. The specific method of the alignment includes: (1) If: multiplication exponent result > c operand exponent: a. Exponent difference > product leading zero: The product result is the large exponent, and a left shift normalization with a shift amount of the product leading zero needs to be performed. While the c operand is the small exponent, a right shift alignment with a shift amount of the exponent difference - the number of product leading zeros needs to be performed. At this time, two shifts are required, and the multiplication result is still the large operand; if no product leading zero is generated in the multiplication at this time, only the c operand needs to be shifted by the exponent difference. b. Exponent difference < product leading zero: Before shifting, the product result is the large exponent. First, a left shift normalization with a shift amount of the product leading zero is performed on the multiplication mantissa. At this time, since the exponent difference < the product leading zero, the product result instead becomes the small exponent. At this time, a right shift alignment with a shift amount of the product leading zero - the exponent difference still needs to be performed on the shifted multiplication mantissa. From the overall effect, only the multiplication mantissa needs to be left shifted by the exponent difference. At this time, the multiplication result becomes the small operand and needs to be exchanged. c. Exponent difference = product leading zero: At this time, only a left shift normalization with a shift amount of the product leading zero needs to be performed on the multiplication mantissa to complete the alignment of the c operand and the multiplication result. (2) If: multiplication exponent result < c operand exponent: At this time, regardless of the relationship between the product leading zero count and the exponent difference, the multiplication result must be the small exponent. First, a left shift normalization with a shift amount of the product leading zero is performed on the multiplication mantissa. At this time, the exponent of the multiplication result is smaller, and a right shift alignment with a shift amount of the product leading zero + the exponent difference still needs to be performed on the shifted multiplication mantissa. From the overall effect, only the multiplication mantissa needs to be right shifted by the exponent difference, and the multiplication result is still the small operand. (3) If: multiplication exponent result = c operand exponent, exponent difference = 0: a. If the product leading zero = 0, at this time, the multiplication result and the c operand have been aligned and no shift is required. b. If the product leading zero ≠ 0, at this time, the exponent difference is less than the product leading zero. First, a left shift normalization with a shift amount of the product leading zero is performed on the multiplication mantissa. After the shift, the exponent difference is the product leading zero. At this time, a right shift alignment of the adjusted multiplication mantissa result by the product leading zero is required again. From the overall effect, no shift is required. In the process of completing the double-precision floating-point multiplication and addition calculation, the corresponding pipeline stages are implemented as follows: P0 stage, the first pipeline stage: complete the functions of multiplication, leading zero counting, and special value judgment module; P1 stage, the second pipeline stage: complete the alignment shift operation and comparison operation; P2 stage, the third pipeline stage: perform the mantissa summation operation after alignment. Level P3, the fourth pipeline stage: post-processing, rounding, final result processing, and final exception state judgment.

2. The method for optimizing the area of ​​a double-precision multiply-accumulator based on flow-through pause technology according to claim 1, characterized in that, The P0 level requires two clock cycles to implement: The first pipeline stage yields three operands: a, b, and c; including: 1) Special value judgment module: The instruction control signal module (1-1) and the special value judgment module (1-2) jointly perform the judgment of internal special values; (1) Introduce the concept of effective operation, and decompose the internal information of the instruction through the instruction control module (1-1). The instruction and the operand sign bit together determine whether the actual operation is addition or subtraction. Note: For multiply-accumulate instructions, the sign bit of mul_res means the sign bit of the product result of the multiply-accumulate instruction, and the sign bit of oprc means the sign bit of the C operand; The following is a detailed explanation of the four instructions in the multiplication-addition class, referring to this table: FMADD: That is, a*b+c, where the sign bit of mul_res represents the sign bit of the product result of a*b, and the input operation is +; FMSUB: That is, a*bc, where the mul_res sign bit represents the sign bit of the product result of a*b, and the input operation is -; FNMADD: That is, -a*bc, where the sign bit of mul_res represents the sign bit of the product result of -a*b, and the input operation is -; FNMSUB: That is, -a*b+c, where the sign bit of mul_res represents the sign bit of the product result of -a*b, and the input operation is +; (2) After obtaining a valid operation, a judgment is made on the internal special value; Multiplication-addition instructions require the multiplication to be performed first, followed by the summation of the mantissas based on the valid operations. Therefore, the special value judgment is shown in the following three tables: The table below shows the results of special value judgments for multiplication: The table below shows the results of special value judgments for valid operations that are addition: The table below shows the results of special value judgments for valid operations that are subtraction: Note: (sub)norm is a general term for normalized and denormalized numbers. NaN numbers (Not a number, representing an inexpressible value) are divided into two categories: qNaN numbers and sNaN numbers. sNaN is a value whose exponent is all 1s, whose first digit of the mantissa is 0, and whose overall mantissa is not 0; qNaN is a value whose exponent is all 1s, and whose first digit of the mantissa is 1. RISC-V specifies that if the result of a floating-point operation is a NaN number, then a fixed NaN number should be used. The NaN value corresponding to double-precision floating-point is 0x7ff8_0000_0000_0000. Therefore, the qNaN assignment for the final result needs to be assigned a fixed value, i.e., qNaN = 64'h7ff8_0000_0000_0000; The table crossed out by the horizontal line indicates that the result needs to be obtained through normal calculation, rather than a special value; for multiplication and addition instructions, firstly, the result of a*b needs to be assigned to |x| according to the special value table of multiplication, and then the special value result is obtained from the corresponding table according to the corresponding valid operation; if the above special value result is generated, a special value signal needs to be set to mark that the operation is a special case, and the result is assigned to the special value result obtained above, which is convenient for subsequent calculation; (3) After obtaining the valid operation, the invalidity exception of the special value is judged and left for use by P3 level; 2) Product mantissa calculation module: Since this module needs to calculate the product result, and one clock cycle is not enough to complete the operation, it is completed using two clock cycles: Operands a and b need to enter the multiplier (1-3) to obtain two partial product results. The adder is used to sum the partial product results to obtain the product mantissa calculation result. The lower half partial product first enters the 53-bit adder (1-4), i.e., the lower half adder (1-4), to calculate the sum of the lower 52-bit partial products. The carry result generated by the lower half summation will be passed to the higher half. The partial products entering the higher half enter the 54-bit adder (1-5), i.e., the higher half adder (1-5), to obtain the product mantissa calculation result. At this point, it is necessary to enter the selector module (1-6) that selects the final product mantissa result based on the instruction control signal and the special value judgment signal, and obtain the final product mantissa result; 3) Pre-statistics module for leading zeros in product: First, the selector (1-7) used to determine the denormalized number needs to be entered. Based on the operand situation, the selector (1-7) is selected to determine the denormalized number, and the mantissa data to be counted is obtained. Then, the 53-bit leading zero counting module (1-8) is entered to count the number of leading zeros of the denormalized data. Then, the next selector (1-9) used to determine the multiplier situation is entered. Based on the multiplier situation, the selector (1-9) adjusts the number of leading zeros. If both numbers are normalized, the statistical result is adjusted to 0. Otherwise, the number of leading zeros obtained from the previous leading zero counting module (1-8) is inherited to obtain the final product leading zero pre-statistical result. 4) Exponent difference and comparison logic (1-10) module: This module mainly compares the exponent of the product result with the exponent of the C operand, as well as the exponent difference with the leading zero of the product, thereby facilitating the exponent shift of the P1 level and initially determining the shift method required for the P1 level. In summary, the P0 level requires a multiplier module with a product of 53-bit × 53-bit and a product of 106-bit, a 53-bit leading zero counting module, and a 107-bit adder. The counting of leading zeros in the product is completed in the P0 level.

3. The method for optimizing the area of ​​a double-precision multiply-accumulator based on flow-through pause technology according to claim 2, characterized in that, The P1 level: The input of the second pipeline stage yields the multiplication result, the comparison result between the product exponent and the exponent of the c operand, the comparison result between the exponent difference and the leading zero of the product, and the comparison result between the exponent difference and the leading zero of the product, which then enters the second pipeline stage for computation; after the second pipeline stage operation, the results of the two operands after exponent alignment are obtained; 1) Comparison logic: The mantissa result of the product and the mantissa of the c operand will enter the mantissa comparison logic (2-5). The size is initially roughly compared according to the comparison signal of the P0 level exponent, and then enters the shift module. For timing considerations, the mantissa comparison logic (2-5) needs to compare the higher half 53-bit mantissa, and merge to complete a more accurate comparison of the two numbers, so as to obtain the size of the higher half of the two numbers. This also makes it convenient to update the mantissa in the case of pipeline pauses later. 2) Alignment part: There are three important design points in the hardware design of the alignment section, as follows: (1) For special alignment cases, when the flow stops, the shifter is reused to reduce area overhead: Analysis of the alignment method reveals that if and only if the multiplication exponent result > the exponent of the c operand, and the exponent difference > the leading zero of the product, and the leading zero of the product ≠ 0, then the mantissa result of the product needs to be left-shifted for normalization, and the c operand needs to be right-shifted for alignment. From an application perspective, this is a low-probability and uncommon scenario. Therefore, a pipeline pause is implemented here, and the shifter is reused for shifting to reduce the area overhead of the shifter. (2) Use only right shifters, and implement left shifts using right shifters: The analysis of the alignment method shows that right shifts are far more common than left shifts. Adding another shifter for left shifts would incur additional area costs. Therefore, this method uses only one right shifter in the alignment part, and reverses the left shift, right shift, and then reverses the right shift to obtain the corresponding result. (3) Reduce the bit width of the shifter to reduce its area: For shifter shifting, the maximum required shift amount is 10⁵. Shift amounts exceeding 10⁵ are simply filled with 0. Since the product result has a precision of 106-bit, a sticky bit is added at the end for subsequent rounding precision. Since the shift amount exceeds 105, the shift amount is at least 106. All the bits of the product result will be shifted to the sticky bit. The right shift operation at this time is equivalent to adding 106-bit 0 at the beginning and performing an auto-OR operation on the 106-bit product result to form a sticky bit for rounding. From the perspective of actual operator statistics, a shift range of 0-31 is sufficient for general computing scenarios. Therefore, the shifter bit width is set to (105+SHF_NUM)-bit. SHF_NUM is configurable and can be adjusted according to different application scenarios. Currently, based on existing operator statistics, SHF_NUM is set to 32, and the maximum shift range is 31. If the shift range exceeds this maximum, the pipeline will pause. For the portion of the shift less than 32 in the current cycle, for the portion greater than 32 in the next cycle, zeros will be added to the beginning to complete the shift. In summary, the overall implementation of the order-pairing part is summarized as follows: After passing through the mantissa comparison logic (2-5) to obtain the large and small mantissas, the selector (2-7) for obtaining the shifted data is controlled according to the relevant shift control logic (2-11) to select the corresponding shifted data. Here, if it is a left shift, the shifted data first enters the reverse order module (2-6) for reverse order operation; the shift amount is specifically determined by the shift amount adjustment logic (2-12); after the shifted data and the shift amount are both ready, it enters a 137-bit right shift shifter (2-8) to obtain the shifted result; at this time, if it is a left shift, it also needs to enter a reverse order operation module (2-9) before the result is obtained, and finally, according to the shift control signal, the selector (2-10) for selecting the mantissa result after shifting is used to select and obtain the final result of the mantissa shift. If it is necessary to reuse the shifter for pipeline stalls, then in the current pipeline stage, the selectors (2-1 / 2-2 / 2-3 / 2-4) are controlled according to the selector control logic (2-14), that is, the selector (2-1) for updating the product mantissa result after pipeline stalls, the selector (2-2) for updating the mantissa result of the c operand after pipeline stalls, the selector (2-3) for updating the leading zeros of the product after pipeline stalls, the selector (2-4) for updating the results such as exchange, comparison results, exponent difference, etc. after pipeline stalls, and the respective inputs are updated. In the next pipeline stage, the above shift operations are reused to obtain the final result. If it is necessary to stall the pipeline because the shift amount exceeds 31 and is less than 105, the shifter logic is not reused at this time; after the current pipeline stage completes the shift of the part less than 32, the selectors (2-1 / 2-2 / 2-3 / 2-4) are controlled according to the selector control logic (2-14), that is, the selector (2-1) for updating the product mantissa result after pipeline stalls, the selector (2-2) for updating the mantissa result of the c operand after pipeline stalls, the selector (2-3) for updating the leading zeros of the product after pipeline stalls, the selector (2-4) for updating the results such as exchange, comparison results, exponent difference, etc. after pipeline stalls, and the respective inputs are updated. In the next pipeline stage, according to the control signal output by the shift control logic (2-11), the remaining shifted data is directly controlled for relevant zero-padding processing by the selector (2-10) for selecting the mantissa result after shifting in the next pipeline stage, and finally the result is obtained. Correspondingly, in the exponent alignment module, the exponent adjustment logic (2-13) is used to further adjust the exponent, and it is only adjusted to the exponent - leading zeros of the product when the multiplication mantissa result needs to be left-shifted for normalization.

4. The method for optimizing the area of ​​a double-precision multiply-accumulator based on flow-through pause technology according to claim 3, characterized in that, The specific scheme for the exponent alignment part is as follows: (1) No pipeline stall a. The multiplication exponent result < the c operand exponent, and the shift amount does not exceed 32; b. The multiplication exponent result < the c operand exponent, and the shift amount exceeds 105; c. The multiplication exponent result > the c operand exponent, and the leading zeros of the product result are 0, and the shift amount does not exceed 32; d. The multiplication exponent result > the c operand exponent, and the leading zeros of the product result are 0, and the shift amount exceeds 105; e. There are special values; f. The multiplication exponent result = the c operand exponent; (2) Stall the pipeline once a. When the multiplication exponent result < the c operand exponent and the shift amount exceeds 31; In this case, only the multiplication mantissa needs to be right-shifted by the exponent difference for alignment; however, since the shift amount exceeds 31, a pipeline stall is required at this time to complete the shift; In the first cycle, it enters the right-shift shifter to perform the shift for the part where the shift amount is less than 32. After the shift is completed, it enters the selector and is placed at the small operand position; in the next cycle when it enters the pipeline, the shift amount in the shifter is 0. At this time, directly according to the control signal, add 0 to the higher half part higher than 31 to ensure the right-shift result; finally, place the c operand at the large operand position and the aligned multiplication result operand at the small operand position; b. When the multiplication exponent result > the c operand exponent and the exponent difference ≤ the leading zeros of the product and the shift amount exceeds 31; In this case, the multiplication exponent result needs to be left-shifted by the exponent difference for alignment; the multiplication result should be the small operand; In the first cycle, it enters the shifter, selects the reverse-order data, and performs the right-shift for the part where the shift amount is less than 32. In this cycle, directly transfer the right-shift result to the small operand position; in the next cycle when it enters the pipeline, the shift amount in the shifter is 0. Directly according to the control signal, add 0 to the part higher than 31, and then select the reverse-order data result to obtain the aligned result; c. When the multiplication exponent result > the c operand exponent and the exponent difference > the leading zeros of the product and both shift amounts do not exceed 31; The leading zeros of the product ≠ 0; At this time, the multiplication exponent result needs to be left-shifted by the exponent difference for normalization; then the c operand result is right-shifted for alignment. At this time, the right-shift amount is the exponent difference - the leading zeros of the product, and the multiplication result is still the large operand; In the first cycle, it enters the shifter, selects the reverse-order data, and performs the right-shift. At the same time, select the reverse-order data after the shift for the large operand at the end; at this time, the next shift amount needs to be adjusted at the top layer, and in the next cycle, the c operand data is right-shifted to obtain the aligned result; d. When the multiplication exponent result > the c operand exponent, the leading zeros of the product is equal to 0, and the exponent difference > 31; At this time, the c operand needs to be right-shifted for alignment. In the first cycle, it enters the shifter and directly performs the right-shift. However, since the shift amount exceeds 32, a pipeline stall is required at this time, and add 0 according to the control signal in the next cycle to obtain the final result; (3) Pipeline stall twice a. When the multiplication exponent result > the c operand exponent and the exponent difference > the leading zeros of the product, the left-shift amount exceeds 31 and the right-shift amount does not exceed 31 and is not equal to 1; At this time, the multiplication exponent result needs to be left-shifted by the exponent difference for normalization; then the c operand result is right-shifted for alignment. At this time, the right-shift amount is the exponent difference - the leading zeros of the product, and the multiplication result is still the large operand; In the first cycle, the shifter selects the reversed data and performs a right shift. Since the left shift exceeds 31, the pipeline needs to pause. The result of the multiplication shift is used on the last small operand. During the top-level selection, the multiplier selects the shifted result, while the c operand remains unchanged. In the second cycle, the shifter's shift amount is adjusted to 0, and zeros are added according to the control signal. At this point, the left shift is complete, and the reversed data is selected as the final result. At this point, the top-level shift amount needs to be adjusted to the exponent difference minus the product leading zero. After the third cycle begins, the c operand is right-shifted to obtain the exponent alignment result. b. The result of multiplication is greater than the exponent of operand c, and the exponent difference is greater than the leading zero of the product. The left shift amount does not exceed 31 and the right shift amount exceeds 31. At this point, the multiplication exponent result needs to be shifted left by the exponent difference to normalize it; then the c operand result needs to be shifted right by the exponent difference to align the exponents. The right shift amount is the exponent difference minus the leading zeros of the product, and the multiplication result is still a large operand. In the first cycle, the data is entered into the shifter, reversed order is selected, and a right shift is performed. At this time, the left shift amount does not exceed 31. After this shift is completed, the reverse shift result is selected to obtain the multiplication normalized result. The shifted result needs to be transmitted at the top level, while the c operand part remains unchanged. In the second cycle, the order shift is performed. Since the right shift amount exceeds 31, the pipeline needs to be paused at this time. The right shift of less than 32 is performed first. In the third cycle, the control signal is filled with 0 to complete the right shift order shift result. c. The result of multiplication is greater than the exponent of operand c, and the exponent difference is greater than the leading zero of the product. The left shift amount does not exceed 31 and the right shift amount is 1. In the first step, the product is shifted to the left by the multiplication exponent and normalized. In the second step, although the right shift is 1 and does not exceed 32, the two products may have inaccurate leading zeros. Therefore, a pipeline pause is required for a second comparison. There may be cases where the products are not equal before but are equal after the shift. (4) The water flow stopped three times. a. The result of multiplication is greater than the exponent of operand C, and the exponent difference is greater than the leading zero of the product. The left shift amount exceeds 31 and the right shift amount exceeds 31. In the first cycle, the shifter selects the reversed data and performs a right shift. Since the left shift exceeds 31, a pipeline pause is required. The result of the multiplication shift is used on the last small operand. At the top-level selection, the multiplier selects the shifted result, while the C operand remains unchanged. In the second cycle, the shifter's shift amount is adjusted to 0, and zeros are added according to the control signal. The left shift is now complete, and the reversed data is selected as the final result. At this point, the top-level shift amount needs to be adjusted to the exponent difference minus the product's leading zeros. In the third cycle, an exponent alignment shift is performed. Since the right shift exceeds 31, a pipeline pause is required, and the right shift of less than 32 is performed first. In the fourth cycle, zeros are added to the control signal, completing the right shift alignment. b. The result of multiplication is greater than the exponent of operand c, and the exponent difference is greater than the leading zero of the product. The left shift amount exceeds 31 and the right shift amount is 1. In the first cycle, the shifter selects the reversed data and performs a right shift. Since the left shift exceeds 31, a pipeline pause is required. The result of the multiplication shift is used on the last small operand. During the top-level selection, the multiplier selects the shifted result, while the c operand remains unchanged. In the second cycle, the shifter's shift is adjusted to 0, and zeros are added according to the control signal. At this point, the left shift is complete, and the reversed data is selected as the final result. In the third cycle, although the right shift is 1, a pipeline pause is required to perform parallel operations before exponent comparison to eliminate the influence of leading zeros in the product and the exponent difference. The result is obtained in the fourth cycle through comparison. In summary, the P1 stage requires a 137-bit shifter for alignment shifting. All alignment shifting is completed within this stage pipeline, without incurring additional alignment shifter area costs in other pipeline stages.

5. The method for optimizing the area of ​​a double-precision multiply-accumulator based on flow-through pause technology according to claim 4, characterized in that, The P2 level: The input of the third pipeline stage receives the multiplication result after alignment and the c operand result, and then enters the third pipeline stage for calculation; after the third pipeline stage operation, the result of mantissa summation is obtained; 1) Sum of last digits: There are three important design points in the hardware design of the mantissa summation part, as follows: (1) The mantissa summation operation has two possibilities: addition or subtraction of the mantissas, which is determined by the valid operations obtained at level P0: Adding the last two digits: The effective operation is addition; the two last two digits can be directly added together by the adder. Subtraction of mantissas: The effective operation is subtraction. Since the previous alignment operation completed the comparison logic operation, this must be the larger mantissa minus the smaller mantissa. In this case, for the expression (xy), in order to use the adder for calculation, we can use the expression (xy) = (x + (~y) + 1) and use addition to complete the subtraction operation. (2) A 9-bit carry-detecting adder (3-10) in the lower half of the bit is used to supplement the precision and detect possible carry in the 55-bit mantissa summation adder (3-6): Addition case: a. If operand c > product operand, since the product result is 106-bit, in this case, the lower 53 bits of operand c are all 0. The higher parts of the two operands need to be summed, while the lower parts of the two operands do not need to be summed and are directly the lower part of the multiplication result. Since the lower part does not generate carry output, the result can be calculated without pipeline interruption. b. In other cases, we need to check whether the added 9-bit carry detection adder in the lower half can detect the possibility of a carry and whether a carry has occurred in the lower half, and then pause the pipeline accordingly, reuse the 55-bit adder to complete the summation of the lower half, thereby reducing the area. That is, if the carry detector in the added lower half has already generated a carry during summation, the carry can be promptly propagated to the 55-bit adder in the higher half for summation. At this point, the result in the higher half is already accurate. As a summation case, there is no situation where the higher half is all 0 and requires post-regulation. If the carry-detecting adder detects that a carry may be needed in the lower half of the data, the lower half of the data needs to be fully calculated to ensure the accuracy requirements. Therefore, a pipeline pause method is used to multiplex the 55-bit adder to obtain the accurate lower half result. Subtraction: a. When subtracting, but no leading zeros are found, the lower half of the full precision is not required; only the rounded part needs to be provided. b. Subtraction results in a leading zero, requiring subsequent calibration. At this point, the pipeline needs to be paused, and the 55-bit adder is reused to calculate the precision of the lower half to ensure smooth calibration. (3) The internal special module comments are as follows: a. 9-bit low-half partial carry-detecting adder Here, a 9-bit lower half partial carry detector is used. If the lower 5 bits are all 1, it is considered that there is a probability of a carry. The lower 5 bits are used for detection because, according to operator statistics, 5-bit detection can meet the majority of carry detection cases. In fact, the number of bits is adjustable here. b. When the 55-bit adder is in subtraction mode and the c operand > the multiplication result, it is necessary to check the 9-bit of the sum of the mantissas in the high half. If the 9-bit of the sum of the mantissas in the high half is found to be 1, the calculation is considered to be complete. The 9-bit detection is required here because if the 9-bit result of the summation of the mantissa in the high half contains 1, then the 9-bit adder can meet the accuracy required by the subsequent rule. Otherwise, it cannot meet the requirement. Therefore, a pipeline pause is needed to reuse the adder to obtain the entire calculation result accurately. c. The bit width of the carry detection adder here is LSB_NUM+1, which is configurable data. LSB_NUM is currently set to 8 because in operator statistics, 9-bit carry detection is sufficient to meet most common cases. The overall scheme for summing the last digits is implemented as follows: First, the data to be summed needs to be selected according to the carry detection adder data selection module (3-9). If it is a subtraction operation, it needs to go through the inversion operation module (3-4) to get the opposite number; if it is an addition operation, no additional operation is required. The next step is to enter the (LSB_NUM+1)-bit carry detection adder (3-10). Its carry needs to be determined according to the data after inversion +1 in the case of subtraction. After obtaining the carry detector carry signal, it needs to enter the carry signal control logic (3-7) together with the external control signal to determine whether to carry to the high half 55-bit adder. At this time, the carry signal is obtained, and the adder data has been selected by the adder data selection module (3-5). At this time, it enters the 55-bit mantissa summation adder (3-6) to obtain the mantissa summation result. The mantissa summation result, big mantissa, little mantissa, special value signal and pipeline pause signal enter the data selection module (3-8) to obtain the final result. If a pipeline pause is required at this point, the pipeline pause signal output from the carry detection adder (3-10) to the pipeline pause control logic module (3-11) is checked to determine whether a pipeline pause is needed, and the 55-bit adder is reused. If a pause is needed, the pipeline pause signal control selector (3-1 / 3-2), i.e., the selector (3-1) used to update the big mantissa after alignment after pipeline pause, and the selector (3-2) used to update the little mantissa after alignment after pipeline pause, selects to update the input result and performs the next cycle of operation. 2) Complete all comparison operations: The result after shifting needs to go through the comparison module (3-3) to compare the lower half of the mantissa, which is used to supplement the comparison result of the upper half of the mantissa of P1 level. At this time, it is necessary to generate a judgment on whether the two are opposite numbers or equal numbers, so as to facilitate the final sign bit judgment of the next pipeline. In summary, the P2 stage requires a 64-bit adder in total. All mantissa summation operations are completed in this stage pipeline, without incurring additional summation adder area costs in other pipeline stages.

6. The method for optimizing the area of ​​a double-precision multiply-accumulator based on flow-through pause technology according to claim 5, characterized in that, The specific execution plan for summing the last digits is as follows: (1) The water flow is continuous: a. The result is a special value; b. If the c operand is greater than the multiplication result, and the difference between their exponents is 105, the larger operand is much larger than the smaller operand; If it is a subtraction, there is no need for normalization of leading zeros after the rule, and the subsequent 1 can be used as a sticky bit; if it is an addition, since the c operand > the multiplication result, the subsequent lower half is all 0, there will be no carry, and the calculation can be completed in one step. c. If the operand c > the result of the multiplication, then the two are an addition operation; If the difference between the two exponents exceeds 53, no carry will be generated, and the result will be completed in one step. If the difference between the two exponents does not exceed 53, then if a carry occurs, it will be reflected in the addition of the higher half, and the result can be completed in one step. d. If the c operand > the multiplication result, perform a subtraction operation. If a 1 is detected in the high 9 bits of the high half of the calculation result, there is no need to be precise for the low half, because the post-normalization with leading zeros does not require subsequent precision. The calculation is considered complete. e. If the carry detection addition of the 9-bit lower half does not detect the carry probability, and the valid operation does not meet the condition that the mantissa of the lower half is followed by 1, then the subsequent part does not need to have full precision, and the calculation is considered complete. (2) The water flow stops once: a. The carry detection adder in the lower half of the 9-bit bit detects a probability of a carry, and a carry has already occurred in the first step; In the first cycle, the 9-bit low half carry detection adder detects a probability of a carry, which may generate a carry in the high half. At this point, a pipeline pause is required. In the second cycle, the 55-bit adder is reused to calculate the low half to ensure data correctness. If the first beat has already generated a carry in the high half, and the second beat pauses, although the low half will generate a carry, this carry has already been added to the sum of the high half in the first beat. Therefore, there is no need to pause a second time to increment the high half data. b. The carry detection adder detects a probability of carrying in the lower half of the 9-bit bit, but no carry is generated in the second cycle; In the first cycle, the 9-bit lower half carry detection adder detects a probability of a carry, which may result in a carry to the higher half. At this point, a pipeline pause is required. In the second cycle, the 55-bit adder is reused to perform summation on the lower half to ensure data correctness. If the summation result of the lower half calculated in the second cycle does not carry 1 to the higher half, the summation result of the higher half is accurate, and no pipeline pause is required again. c. If the mantissa of the smaller operand contains a 1 in the subsequent bits, and the operation is a subtraction, and the summation of the lower half does not produce a carry; If there is a 1 in the mantissa of the small operands that are not included in the calculation in the first step, and it is a subtraction, the whole result needs to be calculated completely to ensure that there is accurate data shift if there is a leading zero shift in the subsequent step. In the second step, since no carry operation will be generated, if a carry is generated, it can be detected in the first step, and the result obtained at this time is the accurate result. (3) The water flow paused twice: a. The carry detection adder in the lower half of the 9-bit bit detects a probability of carrying, and the lower half does indeed generate a carry in the second cycle; In the first cycle, the 9-bit low-half carry detection adder detects a probability of a carry, which may generate a carry in the high half. At this point, a pipeline pause is required. In the second cycle, the 55-bit adder is reused to calculate the low half to ensure data correctness. The sum of the low half calculated in the second cycle needs to be carried over to the high half. This indicates that the sum of the high half calculated in the previous cycle is inaccurate, and another pipeline pause is required. In the third cycle, the adder enters the high half and performs a +1 operation on the result.

7. The method for optimizing the area of ​​a double-precision multiply-accumulator based on flow-through pause technology according to claim 6, characterized in that, The P3 level: The input of the fourth pipeline stage yields the result of mantissa summation. The original exponent is the exponent result adjusted by the P1 stage. The exponent obtained through the P2 stage, the sign bit to be computed, and the comparison result are then fed into the fourth pipeline stage for calculation. After the calculation in the fourth pipeline stage, the final result and the abnormal status are obtained. 1) Post-regulation section: The adder data is obtained from the P2 pipeline stage. It consists of 2 hidden bits, 104 mantissa bits, 1 rounding bit, and 1 sticky bit, totaling 108 bits. The exponent should be the result of the exponent adjusted by the P1 stage. The exponent obtained through the P2 stage first enters the leading zero module for statistics and then performs a shift operation. There are three important design points in the hardware design of the rear section, as follows: (1) By pausing the flow, the leading zero statistics module is reused for uncommon situations, thereby reducing the area of ​​the leading zero statistics module. Based on actual statistical results, the case where the high half is all 0 is rare. Therefore, a 53-bit leading zero statistics module can meet the needs of most scenarios. In special cases, pipeline pauses can be reused to achieve the purpose of reducing area. After obtaining the mantissa summation result, the mantissa needs to be divided into high and low parts. First, count the number of leading zeros after the 53-bit part of the high half. If there is a 1 in the high half, then there is no need to stop the pipeline and check the leading zero result of the low half. Conversely, the flow needs to be stopped to detect the leading zeros in the lower half; (2) Back gauge shifting uses only the left shifter; The back-shift part only has one left shifter to perform the back-shift with leading zeros; for the right shift overflow case, as can be seen from the previous alignment algorithm analysis, the right shift here is at most one bit, which can be directly completed by bit concatenation; (3) If timing permits, the shifter data can be corrected in advance by controlling the circuit to reduce the shifter bit width. The maximum shift per cycle is 53, which reduces the bit width of the shifter to 85-bit and the maximum shift amount to 32. The bit width reduction of the shifter does not rely on pipeline pauses, but is achieved by removing 32 bits of 0 from the high part of the shifted data in advance through internal control signals, and then adding 0 to the end to reduce the shift amount exceeding 32. Then the shifter is used to obtain the final shift result. The execution is as follows: (I) When the shift amount is <32, the left shift shifter can be directly used for shifting. (II) When the shift amount is greater than 32, the shift data adjustment module needs to be entered to process the shift data. 32 bits of 0 are removed from the front and 32 bits of 0 are added to the back. The processed data enters the left shifter for the remaining shift to obtain the final result. The reason for reducing the shifter to below 32 is to ensure that the control circuit is as simple as possible; otherwise, the control circuit may be too complex, resulting in additional area overhead. For cases where the exponent cannot satisfy the leading zero shift of the subsequent rule, a pipeline pause is required to meet the timing requirements, and the shift is performed using an amount of exponent -1 in the next clock cycle. The overall solution for the post-guide section is as follows: The mantissa summation result is divided into high and low parts. First, it enters the 53-bit leading zero statistics (4-7) to count the leading zeros of the high half. Then, based on the leading zero data and the exponent, it enters the shift amount calculation module (4-8) to obtain the shift amount. The shift data is obtained through the shift data adjustment module (4-9) and enters the 85-bit left shifter. At this time, the shift data is obtained and enters the mantissa selection module (4-13). Based on the signal obtained from the right shift control logic (4-14), the mantissa selection is controlled to determine whether it needs to be shifted right by one bit to obtain the final mantissa result. At the same time, it needs to be adjusted by the exponent adjustment module (4-11) and the rounding part adjustment module (4-12), and the sign bit needs to be calculated by the sign bit calculation module (4-4). These data enter the rounding operation, rounding adjustment and abnormal state judgment module (4-15) to complete the rounding operation, rounding adjustment and abnormal state judgment. Finally, it enters the final result selection (4-16) to obtain the final result. For sections requiring a pause in the flow, the flow pause control logic (4-5) and the flow pause selector control logic (4-6) are used to control the selectors (4-1 / 4-2 / 4-3). Specifically, selector (4-1) is used to update the exponent result after the flow pause, selector (4-2) is used to update the high half of the mantissa sum result after the flow pause, and selector (4-3) is used to update the low half of the mantissa sum result after the flow pause. This updates the input result. 2) Rounding adjustments: The rounding adjustment and the decimal adjustment are performed simultaneously, and the rounding adjustment module (4-12) completes the corresponding functions; 3) Exponent adjustment section: The exponent adjustment module (4-11) performs the corresponding functions; The exponent adjustment is performed synchronously with the subsequent rule, and there are a total of four possibilities: exponent + 1, exponent, exponent - preceding zero of the subsequent rule, and 0. 4) Rounding operation and post-rounding adjustment: This logic is contained in the rounding operation, rounding adjustment and abnormal state judgment module (4-15); The rounding is performed according to the rounding mode. If rounding requires +1, the carry in the 54-bit adder needs to be adjusted to 1; if rounding does not require +1, the carry in the 54-bit adder needs to be adjusted to 0. The final rounding result is then obtained, and the exponent and mantissa are adjusted again based on this rounding result: Exponent adjustment: If rounding +1 causes the mantissa to overflow by 1 bit, the exponent needs to be +1. Arrangement of last digits: If rounding by +1 causes the last digits to overflow by 1 digit, the last digits need to be adjusted one digit to the right. 5) Final sign bit calculation: The sign bit calculation (4-11) completes the corresponding function; (1) If a special value exists, assign the sign bit of the special value; (2) The absolute values ​​of the two numbers are equal, that is, the product result after alignment is equal to the c operand, and the effective operation is subtraction. This is related to the rounding mode. If it is rounding to negative infinity, the sign bit is negative; otherwise, the sign bit is positive. (3) The remaining cases need to be determined based on the exchange signal and the subtraction signal, as shown in the table below: Where A is the product result, B is the c operand, and mult_sign is the sign of the product result obtained from the P0-level adjustment; the actual operation here is consistent with the effective operation at the P0 level. 6) Anomaly detection: This logic is contained in the rounding operation, rounding adjustment and abnormal state judgment module (4-15); (1) Invalid exception: Found in the special value judgment at the P0 level; (2) Division by zero exception: None; (3) Overflow exception: The result is greater than the maximum exponent value after the exponent is updated, and it is not an infinite, qNaN result or invalid exception at this time; (4) Underflow anomaly: After rounding, the data is strictly between ± minimum normalized number, that is, + minimum normalized number is 64'h0010_0000_0000_0000, - minimum normalized number is 64'h8010_0000_0000_0000, and there is inaccuracy; (5) Inaccuracy anomaly: The round bit or sticky bit is 1, or an overflow anomaly occurs at this time; 7) Final result processing: The final result should be selected as (4-16) to complete the corresponding function; If an overflow exception occurs, special assignments are needed for different maxima depending on the rounding mode. In other cases, only the sign bit, exponent, and mantissa need to be concatenated normally to obtain the final result. In summary, the P3 level requires a 53-bit back gauge leading zero statistics module and an 85-bit back gauge shifter.

8. The method for optimizing the area of ​​a double-precision multiply-accumulator based on flow-through pause technology according to claim 7, characterized in that, The specific implementation plan for the post-regulation section is as follows: (1) The water flow is uninterrupted: a. The result produces a special value, and the final result is independent of the shifter; b. The multiplication result and the c operand operation are opposites of each other, and the effective operation is subtraction, that is, the sum of the mantissas is all 0, and the final result is independent of the shifter; c. The high half of the 53 bits is not all 0 and the exponent can also satisfy the shift amount. The maximum shift amount is 53. For the part exceeding 32, first add 32 bits of 0 to the end and then shift. If the shift amount is less than 32, then shift directly. The exponent needs to be adjusted to the value of the exponent minus the value of the leading zeros. d. If the exponent result is 0, then a denormalized number has been generated, and no shifting is required. (2) The water flow stops once: a. After the first beat, the leading zero is greater than the exponent; Since the leading zero of the post-normalization is greater than the exponent at this point, the exponent cannot satisfy the shift of the leading zero of the post-normalization. To meet the timing requirements, a pipeline pause is performed. In the next clock cycle, a left shift of the exponent minus 1 is performed. If the shift exceeds 32, the part exceeding 32 is first appended with 32 bits of 0 before the shift is performed. If the shift is less than 32, the shift is performed directly to obtain the final result. The final exponent result should be 0, which is a denormalized number. The flow pauses here because the top-level module still selects the high half of the data and the original exponent; b. In the first beat, the high half of the 53-bits is all 0, and the number of leading zeros in the subsequent rule is less than that of the exponent. In the next beat, it is found that the number of leading zeros in the low half of the subsequent rule is still less than that of the exponent. Since the first step's high half of 53 bits is all 0, and the exponent can satisfy the shift of the leading zero in the subsequent step, a pipeline pause is required at this time. At this time, the shifter shift result will not affect the input of the next step. The pipeline pause here is when the top-level module selects the low half of the data, that is, simulates the high 53 bits of 0 being shifted away. In the next multiplexing module, the number of leading zeros in the lower half of the exponent is counted. At this point, the exponent after the pause adjustment still satisfies the shift of leading zeros in the lower half. A left shift is performed with the shift amount equal to the leading zeros in the lower half. If the shift amount exceeds 32, the part exceeding 32 is first appended with 32 bits 0 before shifting. If the shift amount is less than 32, the shift is performed directly to obtain the final result. The final exponent result should be the exponent minus the value of the leading zeros in the lower half. (3) The water flow pauses twice: a. In the first step, the high half of the 53-bits is all 0, and the number of leading zeros is less than that of the exponent. In the second step, the number of leading zeros in the low half is greater than that of the exponent. Since the first pulse has all 53 bits of the high half of the data as 0, and the exponent can satisfy the shift of the leading zero in the subsequent rule, a pipeline pause is required. The pipeline pause here is when the top-level module selects the low half of the data after the first pulse ends, which simulates the high 53 bits of 0 being shifted away. In the second cycle, the leading zero counting module is reused to count the number of leading zeros in the lower half. At this point, the exponent after the pause adjustment cannot satisfy the shift of leading zeros in the lower half. To meet the timing requirements, a pipeline pause is performed, and the lower half of the data is still selected. In the third cycle, the lower half of the data is shifted left by the adjusted exponent minus 1. If the shift amount exceeds 32, the part exceeding 32 is first appended with 32 bits 0 before shifting. If the shift amount is less than 32, the shift is performed directly to obtain the final result. At this point, the final result of the exponent should be 0, a denormalized number.

9. The method for optimizing the area of ​​a double-precision multiply-accumulator based on flow-through pause technology according to claim 1, characterized in that, The method includes: (1) a, b, c operands, for three-operand instructions such as multiply-add instructions, represent a*b+c; (2) The exponent of the product result is the sum of the exponents of operands a and b and the offset. For double-precision floating-point numbers, the offset is 1023. The exponent difference mentioned in the text refers to the absolute value of the difference between the exponent of the product result and the exponent of operand c. (3) The exponent alignment operation refers to aligning the mantissa of the smaller exponent operand with the mantissa of the larger exponent operand based on the exponent difference between two operands with different exponents. (4) Postnormalization refers to the fact that after the floating-point calculation is completed, the exponent may exceed 0, but the mantissa result is a denormalized number. At this time, the floating-point number normalization operation needs to be performed. (5) Leading zeros refer to the number of zeros in the mantissa up to the first 1 when the hidden bit is 0; product leading zeros refer to the number of leading zeros in the mantissa result after multiplying operands a and b; post-regulation leading zeros refer to the number of leading zeros generated in the mantissa of the result after post-regulation of floating-point calculation. (6) The rounding part contains three bits, namely the protection bit, the rounding bit, and the sticky bit; the protection bit is the last bit of the mantissa, the rounding bit is the first bit after the last bit of the mantissa, and the sticky bit is the second bit after the last bit of the mantissa and all subsequent bits.

10. The method for optimizing the area of ​​a double-precision multiply-accumulator based on flow-through pause technology according to claim 1, characterized in that, The method is applied to floating-point operations during double-precision floating-point multiplication and addition calculations. It optimizes the multiplication and addition algorithm, improves the dual data path to a single data path, and reduces the bit width based on the actual statistical situation of the operator. By combining with real-world application scenarios, it adopts pipelined pause multiplexing logic blocks to improve the area of ​​the adder, shifter, and leading zero statistics module, thereby improving the area of ​​the multiplication and addition module.

Images