Corelet interrupt management circuit and multi-corelet system
By designing a chip interrupt management circuit, the scalability and latency issues of interrupt collection technology in multi-chip systems are solved, achieving flexible configuration and low-latency interrupt management, avoiding repeated triggering and loss, and being compatible with the RISC-V PLIC specification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHUANZHI YIXIN INFORMATION TECHNOLOGY (SHANGHAI) CO LTD
- Filing Date
- 2026-05-18
- Publication Date
- 2026-06-30
AI Technical Summary
In multi-core heterogeneous integrated systems, traditional interrupt collection techniques suffer from problems such as a fixed number of interrupt inputs, poor scalability, large delay in priority decision-making, repeated triggering or loss, lack of independent gateway latching for interrupt status, and incompatibility with the RISC-V PLIC specification.
A chip interrupt management circuit was designed, including an interrupt gateway latch unit, an independent register group, a priority decision unit, a multi-threshold comparison unit, and a status linkage unit, to realize multi-level parallel comparison and multi-threshold filtering, and to support flexible configuration and low-latency interrupt management.
It improves the scalability and compatibility of interrupt management circuitry, reduces latency, avoids repeated interrupt triggering and loss, supports flexible interrupt scheduling for multi-target chips, and is compatible with the RISC-V PLIC specification.
Smart Images
Figure CN122308913A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a chip interrupt management circuit and a multi-chip system. Background Technology
[0002] In a multi-chip heterogeneous integrated system, each functional chip works independently and generates a large number of local interrupts. These interrupts need to be efficiently collected, latched, and prioritized before they can be transmitted and processed across chips through inter-chip interconnection.
[0003] However, traditional interrupt collection techniques have the following drawbacks: 1) The number of interrupt inputs is fixed, making it impossible to flexibly configure 2-1024 interrupts, resulting in poor scalability; 2) Priority determination uses serial comparison, which results in large combinational logic delays and slow interrupt response speed; 3) The interrupt state lacks independent gateway latching and single-source single-suspend constraints, which easily leads to repeated triggering or loss of interrupts; 4) The register layout is incompatible with the RISC-V PLIC (Reduced Instruction Set Computer) platform-level interrupt controller specification, resulting in high software porting and adaptation costs; 5) The threshold configuration is limited and cannot achieve differentiated interrupt output for multiple target cores.
[0004] Therefore, it is necessary to provide a chip interrupt management circuit and a multi-chip system to effectively solve the above problems. Summary of the Invention
[0005] This invention provides a chip interrupt management circuit and a multi-chip system.
[0006] This invention provides a chip interrupt management circuit, comprising: Interrupt gateway latch unit, there are multiple interrupt gateway latch units, each used to receive an external interrupt signal and form a corresponding gateway latch signal; An independent register group, connected to the interrupt gateway latch unit, includes multiple registers, the number of which is the same as the number of interrupt gateway latch units and corresponds one-to-one, and is used to store the management rules corresponding to the interrupt signal; The priority decision unit is connected to the interrupt gateway latch unit and the independent register group, and is used to perform multi-level parallel comparisons based on each of the gateway latch signals and the corresponding management rules to obtain the highest priority interrupt signal among the interrupt signals. A multi-threshold comparison unit, connected to the priority decision unit and the independent register group, includes multiple threshold comparison units with different thresholds, used to determine whether the highest priority interrupt signal has reached the output condition under a preset scenario using the corresponding threshold comparison unit; The status linkage unit, connected to the multi-threshold comparison unit and the independent register group, is used to suspend the highest priority interrupt signal and output the information of the highest priority interrupt signal when the highest priority interrupt signal reaches the output condition.
[0007] Preferably, the management rules for the interrupt signal include the priority, enable, threshold, response, and completion rules for the interrupt signal.
[0008] Preferably, the number of interrupt signals is less than or equal to 1024, and the number of interrupt gateway latch units and registers is also 1024, with each interrupt signal having at least one corresponding register. Preferably, the number of interrupt gateway latch units and associated registers is the same as the number of interrupt signals. For example, when the number of interrupt signals is 1024, the corresponding number of interrupt gateway latch units and associated registers is 1024; when the number of interrupt signals is less than 1024, such as 288, the corresponding number of interrupt gateway latch units and associated registers is 288, and there may be no redundant circuit units.
[0009] Preferably, the number of priority decision units is 1023, and the priority decision units are used to compare the priorities of each interrupt signal pairwise to obtain the highest priority interrupt signal.
[0010] Preferably, the priority decision unit is used to output information about the interrupt signal with the smaller interrupt ID when the two interrupt signals have the same priority.
[0011] Preferably, the number of threshold comparison units is 8.
[0012] Preferably, each of the threshold comparison units has a different threshold. The threshold comparison unit is used to compare the priority of the highest priority interrupt signal with the threshold corresponding to the preset scenario. If the priority of the highest priority interrupt signal is greater than the threshold corresponding to the preset scenario, it is determined that the highest priority interrupt signal has reached the output condition.
[0013] Preferably, the chip interrupt management circuit further includes an IPSO packetization module, which is connected to the status linkage unit and the independent register group. The IPSO packetization module is used to package the information of the highest priority interrupt signal into a data packet and output it to the target chip.
[0014] Preferably, the data packet includes the gateway latch signal of the highest priority interrupt signal, the priority, and the interrupt ID.
[0015] The present invention also provides a multi-core system, including multiple cores and a core interrupt management circuit as described in any one of the claims, wherein each core is connected to the core interrupt management circuit and outputs the interrupt signal to the core interrupt management circuit respectively.
[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: The chip interrupt management circuit and multi-chip system provided in this invention embodiment are configurable, low-latency, and compatible with RISC-CV PLIC chiplet on-chip interrupt collection circuits, enabling interrupt gateway latching, independent configuration, parallel priority decision-making, multi-threshold filtering, and state closed-loop management. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention, but not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A schematic diagram of the chip interrupt management circuit provided in one embodiment of the present invention; Figure 2 A schematic diagram of the chip interrupt management circuit provided in another embodiment of the present invention; Figure 3 A circuit diagram of a priority decision unit provided in one embodiment of the present invention. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0021] To address the problems existing in the prior art, this invention provides a chip interrupt management circuit and a multi-chip system.
[0022] Figure 1 This is a schematic diagram of a chip interrupt management circuit provided according to an embodiment of the present invention. Figure 1 As shown, a chip interrupt management circuit includes an interrupt gateway latch unit 11, an independent register group 12, a priority decision unit 13, a multi-threshold comparison unit 14, and a status linkage unit 15.
[0023] The number of interrupt gateway latch units 11 is multiple ( Figure 1 Only one interrupt gateway latch unit is shown, each used to receive an external interrupt signal and form a corresponding gateway latch signal. An independent register group 12 is connected to the interrupt gateway latch unit 11. The independent register group 12 includes multiple registers, the number of which is the same as and corresponds one-to-one with the number of interrupt gateway latch units 11, used to store the management rules for the corresponding interrupt signals. A priority decision unit 13 is connected to the interrupt gateway latch unit 11 and the independent register group 12, used to perform multi-level parallel comparisons based on each gateway latch signal and its corresponding management rules to obtain the highest priority interrupt signal among all interrupt signals. A multi-threshold comparison unit 14 is connected to the priority decision unit 13 and the independent register group 12, including multiple threshold comparison units with different thresholds, used to determine whether the highest priority interrupt signal has reached the output condition under a preset scenario. A status linkage unit 15 is connected to the multi-threshold comparison unit 14 and the independent register group 12, used to suspend the highest priority interrupt signal and output the information of the highest priority interrupt signal when the highest priority interrupt signal reaches the output condition.
[0024] The interrupt gateway latch unit 11 in the chip interrupt management circuit provided in this application has multiple interrupt gateway latch units 11, each used to receive an external interrupt signal, thereby enabling the chip interrupt management circuit input to support multi-channel parameterized configuration and significantly improving scalability. The priority decision unit 13 performs multi-level parallel comparisons based on each gateway latch signal and its corresponding management rules to obtain the highest priority interrupt signal among all interrupt signals, reducing the latency of the chip interrupt management circuit compared to traditional serial schemes. Each interrupt gateway latch unit 11 receives an external interrupt signal and forms a corresponding gateway latch signal. The status linkage unit 15 suspends the highest priority interrupt signal when the output condition is met, preventing duplicate interrupt triggering and loss. The number of registers in the independent register group 12 is the same as the number of interrupt gateway latch units 11 and corresponds one-to-one, improving register compatibility. The multiple threshold comparison units 14 with different thresholds enable multi-channel independent threshold configuration, supporting flexible interrupt scheduling for multi-target chips.
[0025] In some implementations, the number of interrupt signals is less than or equal to 1024, and the number of interrupt gateway latch units 11 and the number of registers are both 1024, with each interrupt signal having at least a corresponding register. That is, the interrupt input supports 2–1024 parameterized configurable channels, significantly improving scalability.
[0026] Specifically, such as Figure 2 As shown, the PLIC10 in this embodiment includes the aforementioned interrupt gateway latching unit 11, priority decision unit 13, multi-threshold comparison unit 14, and status linkage unit 15. The interrupt gateway latching unit 11 latches the input level of each interrupt signal, generating an interrupt request (IRQ) gateway latching signal irq_gateway. The gateway latching signal IRQ_GATEWAY is a stable interrupt status signal generated after each interrupt signal IRQ[x] is latched by an independent gateway. There can be 1024 channels, each corresponding one-to-one with the external interrupt signal IRQ[x] input, used to implement single interrupt source single suspension constraint and reliable interrupt acquisition. Only one suspension request is allowed for the same interrupt source at the same time. In this embodiment, each interrupt gateway latching unit 11 latches the 1024 externally input interrupt signals IRQ[0]~IRQ
[1023] into a gateway latching signal irq_gateway[x].
[0027] Specifically, the inputs to the interrupt gateway latch unit 11 may include the level input value of the interrupt signal, and the interrupt priority irq_prio, enable irq_enable, threshold irq_thod, claim, and complete signals input to the register. The outputs of this circuit include the gateway latch signal irq_gateway (which can be read from the register), the interrupt pending irq_pending signal, and the threshold-filtered interrupt priority signal irq_prio_masked. The threshold filtering here can be the threshold filtering function of the PLIC10 itself. The specific interrupt gateway latch unit 11 can employ any specific circuit well known in the art, provided that the conditions of this embodiment are met.
[0028] The input interrupt signal of the interrupt gateway latch unit 11 is latched in the gateway register (irq_gateway register) by the status latch circuit, and updated to the pending register (irq_pending register). After threshold comparison, if the threshold is exceeded, it is output to the subsequent circuit; otherwise, it is not output to the subsequent circuit.
[0029] In some implementations, the management rules for interrupt signals include the priority, enable, threshold, acknowledgement, and completion rules of the interrupt signals. In this implementation, each interrupt signal IRQ[x] is configured with a corresponding register, and the priority, enable, threshold, acknowledgement, and completion rules of the corresponding interrupt signal IRQ[x] are stored in the independently configured registers.
[0030] Specifically, each register can be configured with corresponding priority sub-registers, enable sub-registers, threshold sub-registers, acknowledge sub-registers, and completion sub-registers to store corresponding information. In other embodiments, each register may also have corresponding priority storage areas, enable storage areas, threshold storage areas, acknowledge storage areas, and completion storage areas to store corresponding information.
[0031] In some implementations, the number of priority decision units 13 is 1023. The priority decision units 13 are used to compare the priorities of each interrupt signal pairwise to obtain the highest priority interrupt signal.
[0032] In some implementations, the priority decision unit 13 is used to output information about the interrupt signal with the smaller interrupt ID when two interrupt signals have the same priority.
[0033] In some implementations, n MSI Tx paths are set, namely, MSI Tx[0] to MSI Tx[n-1] paths, where n is configurable from 1 to 8, and each path has the same MSI Tx function. Taking MSI Tx[0] as an example, the function of MSI Tx[0] is to send and output the interrupt data after being "IRQ Packetized" by the IPSO packing module 20 to the target chip. The interrupt data has a length of 120 bits, which is divided into 4 32-bit data. When the MSI Tx path confirms that the receiving mailbox of the target chip is accessible, it sends these 4 32-bit data in order of address from low to high.
[0034] In some implementations, a timeout counter is set up. The timeout counter starts counting each time MSITx sends a new interrupt data. If the current interrupt data is correctly received and processed by the receiver of the target chip before reaching the timeout threshold, the counter is cleared and waits for new interrupt data to be sent. Otherwise, when the timeout threshold is reached, an error interrupt is issued and waits for the upper-layer system software to process it.
[0035] Specifically, such as Figure 1 , 2As shown in Figure 3, the priority decision unit 13 selects the highest priority interrupt signal among the 1024 interrupt signals IRQ [0] to IRQ
[1023] by comparing the priority rules of the irq_gateway [x] signal given by each interrupt gateway latch unit 11 with the corresponding IRQ [x] stored in the register.
[0036] Specifically, such as Figure 3 As shown, the input to the priority decision unit 13 is 1024 interrupts that have been threshold-filtered, and the output of this circuit is the highest priority interrupt obtained through comparison. The basic working principle is that the priority Irq_Priority of the 1024 interrupt signals passes through a 10-stage comparator circuit. Each stage compares the priority of the interrupt signals pairwise. The first stage (N=10) has 512 comparators (Comp), the second stage (N=9) has 256 comparators (Comp), the third stage (N=8) has 128 comparators (Comp), and the remaining (N=7, 6, 5...1) have 64, 32, 16, 8, 4, 2, and 1 comparators (Comp) respectively for comparison, for a total of 10 stages and 1023 comparators (Comp).
[0037] In some implementations, when the number of input interrupts is less than 1024, only comparators with actual input interrupt signals are generated into the actual circuit; comparators without input interrupt signals are connected to 0 at their input terminals and will be optimized away during synthesis. For example, if the number of input interrupt signals is 288, then there will be 287 actual comparator circuits, and so on.
[0038] In some implementations, the number of threshold comparison units is eight.
[0039] In some implementations, each threshold comparison unit has a different threshold. The threshold comparison unit compares the priority of the highest priority interrupt signal with the threshold corresponding to a preset scenario. If the priority of the highest priority interrupt signal is greater than the threshold corresponding to the preset scenario, it is determined that the highest priority interrupt signal has reached the output condition. Different preset scenarios are directed towards corresponding targets.
[0040] Specifically, based on the usage scenario, select the threshold comparison unit corresponding to the usage scenario from the 8 independent configurable thresholds. The threshold comparison unit compares the priority value of the highest priority interrupt in the 1024 interrupt signals IRQ [0]~IRQ
[1023] with the corresponding threshold. If it is greater than the threshold, the interrupt request is allowed to be output to the corresponding target.
[0041] In some implementations, such as Figure 1 and 2As shown, the chip interrupt management circuit also includes an IPSO packet module 20. The IPSO packet module 20 is connected to the status linkage unit 15 and the independent register group 12. The IPSO packet module 20 is used to package the information of the highest priority interrupt signal into a data packet and output it to the target chip.
[0042] In some implementations, the data packet includes the gateway latch signal of the highest priority interrupt signal, the priority, and the interrupt ID.
[0043] Specifically, such as Figure 1 As shown, when an output interrupt is allowed to the corresponding target, the status linkage unit 15 suspends the interrupt and no other suspension requests are allowed at this time (i.e., only one suspension request is allowed at the same time, completely avoiding repeated interrupt triggering and loss). It then performs a response and completion operation. Specifically, the response operation involves using the gateway latch signal irq_gateway[x] corresponding to the interrupt as IRQ_IN as the input to the "IRQ Packetized" function of the IPSO packing module 20, using the interrupt ID x corresponding to the interrupt signal as the "IRQ_ID" input signal of the "IRQ Packetized" function of the IPSO packing module 20, and using the priority value corresponding to the interrupt signal as the "IRQ_PRIO" input signal of the "IRQ Packetized" function of the IPSO packing module 20. Completing this operation completes the closed loop.
[0044] "IRQ Packetized" sends a corresponding interrupt request to the target chip based on the source chip ID (SRC_CHIPLET_ID) (from the register), the target chip ID (DEST_CHIPLET_ID) (from the register), the target address (DEST_ADDRESS) (from the register), and the input IRQ_ID, IRQ_PRIO signals stored in the register corresponding to the interrupt signal. This interrupt request is triggered in the form of a message. Specifically, the message format of the interrupt request can be any order and form well known in the art, based on the relevant information of the interrupt signal.
[0045] This application also provides a multi-core system, including multiple cores and a core interrupt management circuit as in any embodiment of this application, wherein each core is connected to the core interrupt management circuit and outputs an interrupt signal to the core interrupt management circuit respectively.
[0046] The multi-core system provided in this application has multiple interrupt gateway latch units in its core interrupt management circuit, each used to receive an external interrupt signal. This allows the core interrupt management circuit input to support multi-path parameterized configuration, significantly improving scalability. The priority decision unit performs multi-level parallel comparisons based on each gateway latch signal and its corresponding management rules to obtain the highest priority interrupt signal, reducing latency compared to traditional serial schemes. Each interrupt gateway latch unit receives an external interrupt signal and generates a corresponding gateway latch signal. Furthermore, the status linkage unit suspends the highest priority interrupt signal when the output condition is met, preventing duplicate interrupt triggering and loss. The number of registers in the independent register group is the same as the number of interrupt gateway latch units, and they correspond one-to-one, improving register compatibility. Multiple threshold comparison units with different thresholds in the multi-threshold comparison unit enable multi-path independent threshold configuration, supporting flexible interrupt scheduling for multi-target cores.
[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A chip interrupt management circuit, characterized in that, include: Interrupt gateway latch unit, there are multiple interrupt gateway latch units, each used to receive an external interrupt signal and form a corresponding gateway latch signal; An independent register group, connected to the interrupt gateway latch unit, includes multiple registers, the number of which is the same as the number of interrupt gateway latch units and corresponds one-to-one, and is used to store the management rules corresponding to the interrupt signal; The priority decision unit is connected to the interrupt gateway latch unit and the independent register group, and is used to perform multi-level parallel comparisons based on each of the gateway latch signals and the corresponding management rules to obtain the highest priority interrupt signal among the interrupt signals. A multi-threshold comparison unit, connected to the priority decision unit and the independent register group, includes multiple threshold comparison units with different thresholds, used to determine whether the highest priority interrupt signal has reached the output condition under a preset scenario using the corresponding threshold comparison unit; The status linkage unit, connected to the multi-threshold comparison unit and the independent register group, is used to suspend the highest priority interrupt signal and output the information of the highest priority interrupt signal when the highest priority interrupt signal reaches the output condition.
2. The chip interrupt management circuit according to claim 1, characterized in that, The management rules for interrupt signals include the priority, enable, threshold, response, and completion rules for the interrupt signals.
3. The chip interrupt management circuit according to claim 1, characterized in that, The number of interrupt signals is less than or equal to 1024, the number of interrupt gateway latch units and the number of registers are both 1024, and each interrupt signal is configured with at least one corresponding register.
4. The chip interrupt management circuit according to claim 3, characterized in that, The number of priority decision units is 1023. The priority decision units are used to compare the priorities of each interrupt signal pairwise to obtain the highest priority interrupt signal.
5. The chip interrupt management circuit according to claim 4, characterized in that, The priority decision unit is used to output information about the interrupt signal with the smaller interrupt ID when two interrupt signals have the same priority.
6. The chip interrupt management circuit according to claim 1, characterized in that, The number of threshold comparison units is 8.
7. The chip interrupt management circuit according to claim 1, characterized in that, Each threshold comparison unit has a different threshold. The threshold comparison unit is used to compare the priority of the highest priority interrupt signal with the threshold corresponding to the preset scenario. If the priority of the highest priority interrupt signal is greater than the threshold corresponding to the preset scenario, it is determined that the highest priority interrupt signal has reached the output condition.
8. The chip interrupt management circuit according to claim 1, characterized in that, The chip interrupt management circuit also includes an IPSO packetization module, which is connected to the status linkage unit and the independent register group. The IPSO packetization module is used to package the information of the highest priority interrupt signal into a data packet and output it to the target chip.
9. The chip interrupt management circuit according to claim 8, characterized in that, The data packet includes the gateway latch signal of the highest priority interrupt signal, the priority, and the interrupt ID.
10. A multi-core particle system, characterized in that, It includes multiple chips and a chip interrupt management circuit as described in any one of claims 1 to 9, wherein each chip is connected to the chip interrupt management circuit and outputs the interrupt signal to the chip interrupt management circuit respectively.