A method of value prediction for a sequential execution processor

Abstract

This invention belongs to the field of processor architecture and microarchitecture optimization technology, and relates to a value prediction method for sequential execution processors. It includes: constructing a step value prediction table; recording the most recent true result after the first execution of the target instruction, and forming step information after subsequent executions; generating a predicted value based on the most recent true result and step information when encountering the same static instruction later; writing the predicted value into the corresponding scoreboard entry and propagating it to dependent instructions during the instruction issue phase; writing the true result back to the scoreboard and comparing it with the predicted value after the target instruction is executed; maintaining the existing speculative execution result when the prediction is correct, and pausing front-end instruction fetching, preserving the scoreboard state, and performing a partial reissue recovery on the affected instructions when the prediction is incorrect, before resuming pipeline progression. This invention, while ensuring execution correctness, eliminates some waiting caused by real data dependencies in advance, improving the processor's ability to utilize potential instruction-level parallelism.

Description

Technical Field

[0001] This invention belongs to the field of processor architecture and microarchitecture optimization technology, specifically relating to a value prediction method for sequential execution processors. Background Technology

[0002] With the slowdown in processor clock speed increases and the persistent existence of memory-level latency issues, the limitations of long-latency instructions on pipeline performance are becoming increasingly prominent. In sequentially executing processors, subsequent dependent instructions often have to pause and wait before the current instruction produces a result, causing real data dependencies to directly translate into pipeline bubbles and reduced throughput. Especially in embedded and lightweight processors, due to limited hardware resources, it is usually impossible to fully hide such waiting through large-scale out-of-order scheduling, complex register renaming, or large window dynamic scheduling mechanisms. Therefore, how to alleviate long-latency data dependencies at a low cost has become one of the key issues in the microarchitecture optimization of such processors. The uploaded paper points out that long-latency operations and real data dependencies together limit the realization of instruction-level parallelism, and simply increasing the instruction fetch width, expanding the queue, or adding execution resources cannot consistently achieve the desired benefits.

[0003] Value prediction is a data-dependent microstructure optimization method. Its basic idea is to predict the current result of a static instruction based on its past execution history before the actual result is generated, and then provide this prediction to dependent instructions in advance, thereby speculatively relaxing the correlation with the actual data. If the prediction is correct, it can drive the execution of subsequent related instructions in advance, hiding some long latency overhead; if the prediction is incorrect, a verification and recovery mechanism is needed to eliminate the impact of the erroneous prediction.

[0004] Existing value predictors can be broadly categorized into context-based predictors and computational predictors. Context-based predictors typically infer the result of the current instruction by leveraging control flow history, data flow history, or a combination of both; computational predictors, on the other hand, obtain new predicted values ​​by performing a function transformation on the results previously generated by the same static instruction. In contrast, the stride value predictor is a typical computational predictor, with a relatively simple structure, making it more suitable for resource-constrained and complexity-sensitive processor scenarios. The uploaded paper points out that the stride predictor has a good ability to capture cyclic inductive variable updates, address generation, and other regular numerical sequences, and has therefore long been considered one of the most practical forms of value prediction.

[0005] However, deploying value prediction to lightweight sequential processors still faces the following challenges: Firstly, traditional sequential execution processors generally do not reserve a dedicated path for propagating predicted values. If value prediction logic is directly inserted, it is often necessary to modify the decoding, issuing, execution, writing back, and related state management structures simultaneously, resulting in a high degree of coupling in the design.

[0006] Secondly, value prediction not only needs to generate predicted values, but also must have mechanisms for recording prediction results, verifying actual results, and recovering from erroneous predictions. If the recovery mechanism is not designed properly, the additional costs of erroneous predictions may outweigh the benefits of correct predictions.

[0007] Third, in lightweight embedded processors, the hardware budget is relatively limited, making it impossible to use overly large history tables, complex multi-level confidence mechanisms, or large-scale selection logic. Therefore, a solution that balances implementation costs and predictive benefits is needed.

[0008] Fourth, many existing studies mainly focus on high-performance out-of-order processors, while there are relatively few low-overhead value prediction methods applicable to sequential processors, especially those that can work with scoreboard structures. The uploaded paper explicitly emphasizes that it differs from most studies that focus on high-performance out-of-order processors, focusing instead on an implementation on the lightweight open-source EH1 processor.

[0009] Therefore, proposing a value prediction method that is suitable for sequential execution processors, can naturally cooperate with existing scoreboard state management structures, and can achieve prediction, verification, and local recovery under controllable hardware overhead is of great practical significance. Summary of the Invention

[0010] To address the aforementioned technical problems, this invention provides a value prediction method for sequential execution processors. This method introduces a step value predictor into the processor pipeline and extends the scoreboard structure, enabling the processor to generate predicted results for use by dependent instructions before the actual result of the target instruction is returned. Simultaneously, prediction verification is performed upon the return of the actual result. In the event of a misprediction, only the affected speculative execution instructions are partially restored. This improves pipeline utilization efficiency and reduces the overhead of pipeline flushing while maintaining execution correctness.

[0011] The technical solution adopted in this invention is a value prediction method for a sequential execution processor, comprising the following steps: Step S1: The processor fetches, decodes, and identifies the target instruction; Step S2: Construct a stride value predictor. The stride value predictor adopts a table-driven structure, with the core being the stride value prediction table. Query the stride value prediction table. If the query is successful and the corresponding table entry is valid, read the most recent real result value and the stride value to generate a predicted value and write it to the scoreboard. Step S3: Subsequent dependent instructions read the predicted value from the scoreboard and continue execution; Step S4: After the target instruction is executed, the actual result is written back to the scoreboard. The actual result is compared with the predicted value. If the prediction is correct, the process proceeds normally. If the prediction is incorrect, the local recovery mechanism is triggered, the front-end instruction fetching is paused, the relevant instruction status information in the scoreboard is retained, and the affected speculative execution instructions are re-emitted and re-executed starting from the incorrectly predicted instruction. Step S5: Once the affected instruction has been re-executed, the front-end pause state is lifted, and the processor resumes normal instruction fetching and pipeline progression.

[0012] Furthermore, each entry in the step value prediction table includes a valid bit, a flag bit, the most recent true result value, and a step value; the valid bit indicates whether the entry has formed a usable history; the flag bit is used to resolve conflicts between different instruction mappings; the most recent true result value is used to store the result of the previous round of actual execution; and the step value is used to store the difference between two consecutive results of the current static instruction.

[0013] Furthermore, the specific working process of the step value predictor is as follows: (1) When a static instruction is executed for the first time and the actual result is written back, there is not enough historical information in the prediction table. Only the most recent actual result value is written, and no prediction is generated. (2) When the static instruction is executed for the second time, the step value is obtained by subtracting the previous real result from the current real result and written into the table entry; (3) When the processor encounters the static instruction for the third time or more, if the prediction table is hit and the entry is valid, the prediction result is generated according to the method of prediction value = most recent true result value + step value. (4) If the table entry is invalid, the tag does not match, or the hit fails, the current instruction will not use value prediction and will instead wait for the actual result according to the baseline method.

[0014] Furthermore, the scoreboard is an extended scoreboard. In addition to retaining the original destination register, instruction status, completion status, and commit status information, the extended scoreboard also adds a prediction value field, a prediction validity field, a prediction source field, a verification status field, and a recovery control field, so as to complete prediction verification during write-back and perform local retransmission based on the context information saved in the scoreboard in case of erroneous prediction.

[0015] Furthermore, the specific process of the local recovery mechanism is as follows: The first step is to immediately pause instruction fetching when a target instruction prediction error is detected, preventing new instructions from entering the pipeline. The second step is to retain the recorded instruction context information, including instruction identity, dependencies, prediction status, and stage information, instead of clearing the existing entries in the scoreboard. The third step is to take the instruction that made the erroneous prediction as the starting point for recovery and identify all speculative execution instructions that are directly or indirectly affected by its predicted value. The fourth step is to re-issue these affected instructions from the scoreboard according to the recovery strategy, so that they are re-executed using the actual results; The fifth step is to rewrite the new actual results back to the corresponding scoreboard entries after the re-launch, so as to gradually correct the execution state on the dependency chain of subsequent instructions; Step 6: Once all affected instructions have been re-executed, release the front-end pause and resume normal instruction fetching and pipeline operation.

[0016] The local recovery does not involve directly clearing the entire pipeline after detecting a misprediction. Instead, it pauses the front-end instruction fetching and uses the state saved by the scoreboard to re-issue the affected speculative execution instructions starting from the mispredicted instructions, thereby narrowing the recovery scope and reducing control recovery overhead.

[0017] The beneficial effects of this invention are: (1) This invention is designed for sequential execution processors and combines value prediction technology with scoreboard state management mechanism. Without introducing a complex out-of-order scheduling structure, it breaks the waiting of some real data by predicting values ​​in advance, which is suitable for the low complexity implementation requirements of lightweight processors.

[0018] (2) The present invention uses a step value predictor as the core prediction structure and generates prediction values ​​by utilizing the difference between the continuous results of the same static instruction. It has good adaptability to rule change patterns such as cyclic inductive update and address generation, and is more likely to obtain usable prediction benefits under limited hardware budget.

[0019] (3) This invention saves the predicted value and related control state by expanding the scoreboard entries, so that the prediction generation, dependency propagation, result verification and recovery control form a unified and coordinated path, which reduces the need to add a dedicated large-scale recovery structure and improves the structural consistency of the implementation.

[0020] (4) In the event of an error prediction, the present invention uses a partial re-launch recovery based on a scoreboard instead of directly clearing the entire pipeline. This can preserve the execution state of the unaffected parts, thereby reducing the recovery cost and improving actual availability.

[0021] (5) This invention is applicable to open-source RISC-V lightweight processors such as VeeR EH1, and can also be extended to other processors with sequential execution, dependency tracking and write-back verification capabilities, and has good application versatility. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of the overall pipeline structure of the method of this invention; Figure 2 This is a schematic diagram of the stride value prediction table structure in this invention; Figure 3 This is a schematic diagram of the extended scoreboard and partial re-encoder recovery process in this invention; Figure 4 This is a schematic diagram of the median prediction accuracy results of this invention; Figure 5 This is a schematic diagram of the cycle performance speedup results in this invention. Detailed Implementation

[0024] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to embodiments and accompanying drawings. The content mentioned in the embodiments is not intended to limit the present invention.

[0025] like Figure 1 As shown, the present invention provides a value prediction method for a sequential execution processor, comprising the following steps: Step S1: The processor fetches, decodes, and identifies the target instruction; It should be further noted that the processor is an open-source RISC-V VeeR EH1 processor or an embedded lightweight processor with the same or similar sequential execution and scoreboard dependency management features.

[0026] Step S2: Construct a stride value predictor. The stride value predictor adopts a table-driven structure, with the core being the stride value prediction table. Query the stride value prediction table. If the query is successful and the corresponding table entry is valid, read the most recent real result value and the stride value to generate a predicted value and write it to the scoreboard. It should be further explained that the stride prediction function adopts a table-driven structure, with the stride prediction table at its core, such as... Figure 2As shown. This prediction table is indexed by the current instruction's program counter (PC) or several of its lower bits to distinguish different static instructions. Each entry includes a valid bit, a flag bit, the most recent true result value, and a step value. The valid bit indicates whether the entry has been included in the available history; the flag bit resolves mapping conflicts between different instructions; the most recent true result value stores the result of the previous execution round; and the step value stores the difference between two consecutive results for the current static instruction. The step value predictor works as follows: (1) When a static instruction is executed for the first time and the actual result is written back, there is not enough historical information in the prediction table. Therefore, only the most recent actual result value is written and no prediction is generated. (2) When the static instruction is executed for the second time, the step value is obtained by subtracting the previous real result from the current real result and written into the table entry; (3) When the processor encounters the static instruction for the third time or more, if the prediction table is hit and the table entry is valid, the prediction result is generated according to the method of "predicted value = most recent true result value + step value". (4) If the table entry is invalid, the tag does not match, or the hit fails, the current instruction will not use value prediction and will instead wait for the actual result according to the baseline method.

[0027] The step size predictor is suitable for instructions whose results exhibit relatively regular trends. For example, scenarios such as updating inductive variables within loops, address calculations, and incrementing fixed-step counters often involve stable differences between two consecutive results, making step size prediction suitable. However, if the instruction result is irregular, the predictor may produce incorrect predictions even after a successful hit. Therefore, this invention further ensures correct execution through scoreboard verification and local recovery mechanisms.

[0028] To ensure that the predicted values ​​can be effectively utilized by subsequent instructions, this embodiment expands the processor scoreboard structure. In addition to retaining the original destination register, instruction status, completion status, and commit status information, the expanded scoreboard entries also add the following fields: (1) Prediction value field, used to store the prediction results obtained by the current instruction during the launch phase; (2) Predicted valid field, used to indicate whether the predicted value can be used as a temporary substitute for the actual result; (3) Prediction source field, used to identify that the predicted value comes from the stride value predictor, which is convenient for subsequent statistics and debugging; (4) Verification status field, used to record whether the predicted value has been verified in the actual write-back stage; (5) Recovery control field, used to indicate whether the entry needs to enter the re-launch recovery process in the event of an error prediction.

[0029] Through the above expansion, the scoreboard no longer only undertakes the function of managing the in-flight status of instructions, but further becomes the core state carrier for predictive value propagation, verification and partial recovery.

[0030] During the processor decoding and launch phase, when a static instruction is identified as eligible for value prediction, the step value prediction table is first queried using the instruction's program counter. If the query is successful and the corresponding entry is valid, the most recent actual result value and step value are read, and the prediction result is calculated. Subsequently, the prediction result is written into the scoreboard entry corresponding to the current instruction, and the prediction validity flag is set.

[0031] For subsequent instructions that depend on the result of this target instruction, when reading the source operand, it is not necessary to wait for the producer instruction to produce a real write-back result. Instead, it first checks whether there is a usable predicted value in the scoreboard entry corresponding to the dependent producer. If so, the predicted value is sent as a temporary source operand to the subsequent execution path. As a result, some instructions in the dependency chain can be advanced, thereby reducing the blocking time of long-latency instructions on subsequent instructions.

[0032] The key to this approach is that the predicted value is only used as a temporary substitute during execution. All subsequent results based on this value are logically speculative execution results and must be ultimately based on the verification results from the producer's actual write-back phase. If the verification passes, these speculative results are legally valid; if the verification fails, these results calculated based on erroneous values ​​must be recalculated.

[0033] Step S3: Subsequent dependent instructions read the predicted value from the scoreboard and continue execution; Step S4: After the target instruction is executed, the actual result is written back to the scoreboard. The actual result is compared with the predicted value. If the prediction is correct, the process proceeds normally. If the prediction is incorrect, the local recovery mechanism is triggered, the front-end instruction fetching is paused, the relevant instruction status information in the scoreboard is retained, and the affected speculative execution instructions are re-emitted and re-executed starting from the incorrectly predicted instruction. Specifically, after the target instruction is calculated by the execution unit and a true result is generated, the true result is written back to its corresponding scoreboard entry. At this point, the comparison logic reads the pre-saved predicted value from that entry and performs an equal comparison between the predicted value and the true result.

[0034] If the two are equal, the prediction is correct. At this point, the prediction verification pass flag can be set, allowing subsequent related instructions based on this prediction value to continue to maintain their original execution state and proceed normally along the original submission path.

[0035] If the two are not equal, it indicates that the target instruction has been incorrectly predicted. Since subsequent dependent instructions may have already completed part or all of their execution based on the incorrect prediction value, these speculative execution results are no longer reliable and a recovery process is required.

[0036] It should be further explained that, unlike the traditional method of directly clearing the entire pipeline after an incorrect prediction, this invention adopts a local recovery mechanism based on scoreboard state preservation, the process of which is as follows: Figure 3 As shown.

[0037] The local recovery mechanism process is as follows: The first step is to immediately pause instruction fetching when a target instruction prediction error is detected, preventing new instructions from entering the pipeline. The second step is to retain the recorded instruction context information, including instruction identity, dependencies, prediction status, and stage information, instead of clearing the existing entries in the scoreboard. The third step is to take the instruction that made the incorrect prediction as the starting point for recovery and identify all speculative execution instructions that are directly or indirectly affected by its predicted value. The fourth step is to re-issue these affected instructions from the scoreboard according to the recovery strategy, so that they are re-executed using the actual results; The fifth step is to rewrite the new actual results back to the corresponding scoreboard entries after the re-launch, so as to gradually correct the execution state on the dependency chain of subsequent instructions; Step 6: Once all affected instructions have been re-executed, release the front-end pause and resume normal instruction fetching and pipeline operation.

[0038] In this way, this embodiment can avoid unnecessary damage to the execution state of unaffected parts, while reducing the control costs caused by the flushing of the rectifier line.

[0039] Step S5: Once the affected instruction has been re-executed, the front-end pause state is lifted, and the processor resumes normal instruction fetching and pipeline progression.

[0040] To verify the feasibility of the method of this invention, experiments were conducted on the open-source VeeR EH1 processor platform, using Dhrystone, CoreMark, and Embench as the test suites. The uploaded paper also employs these three benchmark tests to cover typical integer operations, representative embedded computations, and various lightweight application modes.

[0041] During the experiment, the following indicators were statistically analyzed: (1) Prediction accuracy, which is the proportion of correct predictions to the total number of predictions; (2) Execution cycle number, i.e., mcycle when the program finishes running; (3) Performance improvement or degradation under different workloads.

[0042] like Figure 4As shown, the step size prediction mechanism employed in this invention exhibits significant differences in prediction accuracy across different workloads, indicating that its overall performance is closely related to the numerical variation patterns of the program itself. For some workloads with strong regular value variation characteristics, the predictor can achieve high accuracy. For example, the test programs embedd-edn, embedd-qrduino, and embedd-ud all demonstrate high prediction accuracy, with some programs achieving prediction accuracy close to or exceeding 90%. This indicates that some static instructions in these workloads exhibit relatively stable step size variation characteristics during dynamic execution, and thus can be effectively captured by the step size predictor in this invention.

[0043] Meanwhile, the prediction accuracy of most test programs ranged from 20% to 40%, indicating that the current step size predictors still have limited adaptability to general embedded workloads. For example, programs such as dhrystone, embedd-crc32, and embedd-matmult-int only showed moderate prediction accuracy. This suggests that only some instruction result variations in these programs can be described by a fixed step size model, while the result variations of the remaining instructions are more irregular and difficult to accurately represent using simple step size relationships.

[0044] Regarding execution cycle performance, this embodiment further compares the mcycle results of the EH1 processor with and without the introduction of a value prediction mechanism. For example... Figure 5 As shown in the experimental results, the value prediction mechanism proposed in this invention can reduce program execution cycles under certain workloads. For example, programs such as dhrystone, coremark, embedd-aha-mont64, embedd-cubic, embedd-huffbench, embedd-matmult-int, and embedd-sglib-combined all showed varying degrees of reduction in mcycles after enabling the value prediction mechanism. This indicates that the step value prediction and scoreboard collaboration mechanism proposed in this invention can reduce pipeline downtime caused by data correlation in these programs, thereby improving execution efficiency.

[0045] In summary, by adopting the technical solution of this invention, based on a step value predictor and extending the scoreboard structure, the processor, while maintaining the basic framework of sequential execution, possesses the following capabilities: First, a predicted value is generated based on historical results before the target instruction has been actually executed. Second, the predicted value is written to the scoreboard and read by subsequent dependent instructions, thereby relieving some data waiting in advance. Third, the correctness of the prediction is verified when the actual result is written back. Fourth, when an incorrect prediction occurs, the instruction context information saved on the scoreboard is used to trigger a partial recovery.

[0046] The above embodiments are preferred implementations of the present invention. In addition, the present invention can be implemented in other ways. Any obvious substitutions without departing from the concept of the present technical solution are within the protection scope of the present invention.

[0047] To facilitate understanding by those skilled in the art of the improvements of this invention over the prior art, some of the accompanying drawings and descriptions have been simplified, and for clarity, some other elements have been omitted from this application. Those skilled in the art should realize that these omitted elements may also constitute the content of this invention.

Claims

1. A value prediction method for a sequentially executing processor, characterized in that, Includes the following steps: Step S1: The processor fetches, decodes, and identifies the target instruction; Step S2: Construct a stride value predictor. The stride value predictor adopts a table-driven structure, with the core being the stride value prediction table. Query the stride prediction table. If the query is successful and the corresponding entry is valid, read the most recent actual result value and the stride value to generate a predicted value and write it to the scoreboard. Step S3: Subsequent dependent instructions read the predicted value from the scoreboard and continue execution; Step S4: After the target instruction is executed, the actual result is written back to the scoreboard. The actual result is compared with the predicted value. If the prediction is correct, the process proceeds normally. If the prediction is incorrect, the local recovery mechanism is triggered, the front-end instruction fetching is paused, the relevant instruction status information in the scoreboard is retained, and the affected speculative execution instructions are re-emitted and re-executed starting from the incorrectly predicted instruction. Step S5: Once the affected instruction has been re-executed, the front-end pause state is lifted, and the processor resumes normal instruction fetching and pipeline progression.

2. The value prediction method for a sequential execution processor as described in claim 1, characterized in that, Each entry in the step value prediction table includes a valid bit, a flag bit, the most recent true result value, and a step value; the valid bit indicates whether the entry has been formed into a usable history; the flag bit is used to resolve conflicts between different instruction mappings; the most recent true result value is used to store the result of the previous round of actual execution; The step size is used to store the difference between two consecutive results of the current static instruction.

3. The value prediction method for a sequential execution processor as described in claim 2, characterized in that, The specific working process of the stride value predictor is as follows: (1) When a static instruction is executed for the first time and the actual result is written back, there is not enough historical information in the prediction table. Only the most recent actual result value is written, and no prediction is generated. (2) When the static instruction is executed for the second time, the step value is obtained by subtracting the previous real result from the current real result and written into the table entry; (3) When the processor encounters the static instruction for the third time or more, if the prediction table is hit and the entry is valid, the prediction result is generated according to the method of prediction value = most recent true result value + step value. (4) If the table entry is invalid, the tag does not match, or the hit fails, the current instruction will not use value prediction and will instead wait for the actual result according to the baseline method.

4. The value prediction method for a sequential execution processor as described in claim 2, characterized in that, The scoreboard is an extended scoreboard. In addition to retaining the original destination register, instruction status, completion status, and submission status information, the extended scoreboard also adds a prediction value field, a prediction validity field, a prediction source field, a verification status field, and a recovery control field.

5. A value prediction method for a sequential execution processor as described in claim 3 or 4, characterized in that, The specific process of the local recovery mechanism is as follows: The first step is to immediately pause instruction fetching when a target instruction prediction error is detected, preventing new instructions from entering the pipeline. The second step is to retain the recorded instruction context information, including instruction identity, dependencies, prediction status, and stage information, instead of clearing the existing entries in the scoreboard. The third step is to take the instruction that made the incorrect prediction as the starting point for recovery and identify all speculative execution instructions that are directly or indirectly affected by its predicted value. The fourth step is to re-issue these affected instructions from the scoreboard according to the recovery strategy, so that they are re-executed using the actual results; The fifth step is to rewrite the new actual results of the re-launched instructions back to the corresponding scoreboard entries in order to gradually correct the execution status on the dependency chain of subsequent instructions. Step 6: Once all affected instructions have been re-executed, release the front-end pause and resume normal instruction fetching and pipeline operation.

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