Die and plane level failure recovery schemes

Abstract

A data storage device includes a memory die failure anticipation system that proactively determines when a plane of memory dies and / or the memory dies themselves can fail. To proactively determine whether a memory die can fail, the memory die failure anticipation system periodically monitors a performance characteristic of one or more voltage pumps of the memory die. If the memory die failure anticipation system determines that the memory die is in failure based on the performance characteristic, the memory die failure anticipation system initiates a reseating operation that transfers data stored on the failing memory die to another memory die.

Description

Background Technology

[0001] Data storage devices are susceptible to various failures. In some cases, these failures are correctable. For example, data storage devices typically use error-correcting codes (ECC) to correct bit errors that occur when writing data to and / or reading data from the data storage device. In other cases, one or more memory blocks of the data storage device may fail. In these cases, the data storage device may utilize bad block management and / or reserved space to help ensure the relocation of data stored on the failed blocks.

[0002] However, if a plane of the memory die in a data storage device fails, or if the memory die itself fails, there is no recovery scheme to recover the data on the failed plane and / or on the memory die. Such failures can occur due to manufacturing process issues and / or normal wear and tear on the data storage device.

[0003] Therefore, it would be beneficial to anticipate when a memory die plane or the memory die itself might fail and to take proactive steps to relocate data to another plane of the data storage device and / or the memory die. Summary of the Invention

[0004] This disclosure describes a data storage device, such as a NAND data storage device, having a memory die failure prediction system. The memory die failure prediction system is configured to proactively determine when a failure will occur in the plane of the memory die and / or the memory die itself. In one example, the failure may be the result of manufacturing defects (e.g., due to variations in materials and / or manufacturing) and / or wear caused by various stresses and / or program / erase (P / E) cycles.

[0005] To proactively determine whether a memory die (or a plane of a memory die) is faulty or about to fail, a memory die fault prediction system tracks or periodically monitors the performance characteristics of one or more voltage pumps on the memory die. For example, after a threshold number of P / E cycles, the memory die fault prediction system determines the pump rate (or other performance characteristics of one or more voltage pumps associated with a particular memory die) and determines, at least in part, whether the memory die is faulty or likely to fail based on that performance characteristic. If the memory die fault prediction system determines that the memory die is faulty based on that performance characteristic, it initiates a relocation operation that transfers data stored on the faulty memory die to another memory die.

[0006] The relocation operation involves determining whether the data storage device has a sufficient number of available memory blocks for the relocation operation. If so, the memory die failure prediction system causes data to be read from the failed memory die and also causes the read data to be written to the available memory blocks. The memory die failure prediction system also updates the links pointing to the new memory blocks and marks the old memory blocks associated with the failed memory die as growing bad blocks.

[0007] However, if the memory die failure prediction system determines that there are not enough available memory blocks for the relocation operation, it causes the data to be read from the failed memory die and written to any available memory block. In one example, this involves writing data to an available single-level cell (SLC) memory block, but operating that SLC memory block in multi-level cell (MLC) mode. After the relocation operation is complete, the memory die failure prediction system updates the links associated with the memory block in the mapping table. The memory die failure prediction system may also put the data storage device into read-only mode.

[0008] Therefore, examples of this disclosure describe a method comprising: determining at least one performance characteristic of at least one voltage pump of a memory device at a first instance; comparing the at least one performance characteristic of the at least one voltage pump of the memory device to a performance characteristic threshold; determining the at least one performance characteristic of the at least one voltage pump of the memory device at a second instance based at least in part on determining that the at least one performance characteristic of the at least one voltage pump of the memory device is lower than the performance characteristic threshold; comparing the performance characteristic of the at least one voltage pump of the memory device at the first instance with the performance characteristic of the at least one voltage pump of the memory device at the second instance; selecting a plurality of memory blocks of the memory device associated with the at least one voltage pump and erasing each of the plurality of memory blocks based at least in part on the matching of the performance characteristic of the at least one voltage pump of the memory device at the first instance with the performance characteristic of the at least one voltage pump of the memory device at the second instance; determining the state of each of the plurality of memory blocks; and then determining whether to initiate a relocation operation based at least in part on the determined state of each of the plurality of memory blocks.

[0009] Examples of this disclosure also describe a data storage device including a controller and a memory die failure prediction system communicatively coupled to the controller. The memory die failure prediction system is operable to periodically determine a first performance characteristic of at least one voltage pump associated with the data storage device, and to initiate a first memory die failure prediction operation based at least in part on the first performance characteristic matching a second performance characteristic of the at least one voltage pump associated with the data storage device. The memory die failure prediction system is also operable to initiate a second memory die failure prediction operation based at least in part on the difference between the first performance characteristic and the second performance characteristic.

[0010] Other examples describe a data storage device having components for determining a performance characteristic of at least one voltage supply device associated with the data storage device and components for comparing the performance characteristic of the at least one voltage supply device with a performance characteristic threshold. The data storage device also includes components for determining whether a plurality of memory blocks associated with the voltage supply device have failed. In one example, the components for determining whether the plurality of memory blocks associated with the voltage supply device have failed are at least partially based on the comparison of the performance characteristic of the at least one voltage supply device with the performance characteristic threshold. The data storage device also includes components for initiating a relocation operation. In one example, the components for initiating the relocation operation are at least partially based on the components for determining whether the plurality of memory blocks associated with the voltage supply device have failed determining that a plurality of memory blocks have failed.

[0011] The purpose of this invention is to introduce some concepts in a simplified form, which will be further described in the detailed embodiments below. This invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0012] The following figures illustrate examples of non-restrictive and non-exhaustive properties.

[0013] Figure 1 It is a block diagram of a system including host devices and data storage devices, based on the example.

[0014] Figure 2A The example illustrates how a memory die can comprise multiple memory blocks.

[0015] Figure 2B The example illustrates how a memory block can comprise one or more pages.

[0016] Figure 3An example method is illustrated for identifying memory dies that are faulty and / or may be faulty based on the performance characteristics determined by the voltage pump.

[0017] Figure 4 An example is provided for determining whether a memory die is faulty.

[0018] Figure 5 An example of a method for determining whether a memory die is faulty is illustrated below.

[0019] Figure 6 The first relocation operation based on the example is illustrated.

[0020] Figure 7 The second relocation operation based on the example is illustrated.

[0021] Figure 8 This is a perspective view of a storage device including three-dimensional (3D) stacked non-volatile memory, based on an example.

[0022] Figure 9 It is a block diagram of the storage device based on the example. Detailed Implementation

[0023] The following detailed description is illustrated with reference to the accompanying drawings, which form part of the detailed description. These aspects may be combined, other aspects may be utilized, and structural changes may be made without departing from this disclosure. Therefore, the following detailed description should not be considered limiting, and the scope of this disclosure is defined by the appended claims and their equivalents.

[0024] As mentioned earlier, data storage devices are susceptible to various failures. While some of these failures are correctable, others are not. For example, error-correcting codes (ECC) can be used to correct bit errors that occur when writing data to and / or reading data from the data storage device. In other examples, bad block management and / or reserved space operations help ensure the relocation of data stored on failed memory blocks.

[0025] However, if the plane of the memory die fails and / or if the memory die itself fails, data cannot be recovered from the memory die. Therefore, if the plane of the memory die fails and / or if the memory die itself fails, data will be lost.

[0026] To address this problem, this disclosure describes a data storage device having a memory die failure prediction system. The memory die failure prediction system is operable to proactively determine when the plane of the memory die and / or the memory die itself is in a state of failure and / or is likely to fail.

[0027] To proactively determine whether a memory die (or a plane of the memory die) is faulty or likely to be faulty, a memory die fault prediction system tracks or periodically monitors one or more performance characteristics of one or more voltage pumps associated with the memory die. For example, after a threshold number of P / E cycles have occurred, the memory die fault prediction system determines the pump rate (or other performance characteristics of one or more voltage pumps associated with a particular memory die). In one example, the performance characteristics of one or more voltage pumps of the memory die (also referred to as the first performance characteristic) are determined at a first instance (e.g., when a particular voltage pump is disconnected or detached from the memory cell array of the memory die).

[0028] If the first performance characteristic is below the performance threshold, the performance characteristic of the specific voltage pump (also referred to as the second performance characteristic) is determined at the second instance. In one example, the second instance is at a second time or under a second configuration (e.g., when the specific voltage pump is connected to a memory cell array).

[0029] If the first performance characteristic obtained at the first instance matches the second performance characteristic obtained at the second instance, the memory die failure prediction system determines whether a single memory block or multiple memory blocks are faulty (thus indicating that the memory die (or plane) is faulty). If the memory die failure prediction system determines that the memory die is faulty, it initiates a relocation operation that transfers the data stored on the faulty memory die to another memory die.

[0030] As will be explained in more detail herein, the relocation operation includes determining whether the data storage device has a sufficient number of spare / available memory blocks for the relocation operation. If so, the memory die failure prediction system causes data to be read from the failed memory die and also causes the read data to be written to the available memory blocks. The memory die failure prediction system also updates the links pointing to the new memory blocks and marks the memory blocks associated with the failed memory die as growing bad blocks.

[0031] However, if the memory die failure prediction system determines that there are not enough spare / available memory blocks for the relocation operation, it causes the system to read data from the failed memory die and write the data to any available memory block. In one example, this involves writing data to all single-level cell (SLC) memory blocks, but operating the SLC memory block in multi-level cell (MLC) mode. After the relocation operation is complete, the memory die failure prediction system updates the links in the mapping table. The memory die failure prediction system also puts the data storage device into read-only mode.

[0032] According to the above method, many technical benefits can be achieved, including but not limited to reducing or eliminating the risk of data loss and / or damage due to faulty planes and / or faulty memory dies, and increasing the reliability of data storage devices by actively identifying memory dies that will develop into bad blocks and stopping the use of memory dies before data loss.

[0033] These benefits, along with other examples, will be discussed in the section on... Figures 1 to 9 The content is shown and described in more detail.

[0034] Figure 1 This is a block diagram of a system 100 including a host device 105 and a data storage device 110, based on an example. In one example, the host device 105 includes a processor 115 and memory 120 (e.g., main memory). Memory 120 may include an operating system 125, a kernel 130, and / or applications 135, or otherwise associate with them.

[0035] Processor 115 executes various instructions, such as those from operating system 125 and / or application 135. Processor 115 may include circuitry such as microcontrollers, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), hardwired logic, analog circuitry, and / or various combinations thereof. In one example, processor 115 may include a system-on-a-chip (SoC).

[0036] In one example, memory 120 may be used by host device 105 to store data used or executed by processor 115. The data stored in memory 120 may include instructions provided by data storage device 110 via communication interface 140. The data stored in memory 120 may also include data for executing instructions from operating system 125 and / or one or more applications 135. Memory 120 may be a single memory or may include multiple memories, such as, for example, one or more non-volatile memories, one or more volatile memories, or combinations thereof.

[0037] In one example, operating system 125 may create virtual address spaces for application 135 and / or other processes executed by processor 115. The virtual address spaces may be mapped to locations in memory 120. Operating system 125 may also include kernel 130 or otherwise associated with it. Kernel 130 may include instructions for managing various resources of host device 105 (e.g., memory allocation), processing read and write requests, etc.

[0038] Communication interface 140 communicatively couples host device 105 and data storage device 110. Communication interface 140 can be a Serial Advanced Technology Accessory (SATA), PCI Express (PCIe) bus, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Ethernet, Fibre Channel, or Wi-Fi interface. This allows host device 105 and data storage device 110 to communicate via networks such as a Local Area Network (LAN) or Wide Area Network (WAN) (e.g., the Internet) without requiring physical co-location. Furthermore, host device 105 can interface with data storage device 110 using logical interface specifications such as Non-Volatile Memory Fast Channel (NVMe) or Advanced Host Controller Interface (AHCI).

[0039] Data storage device 110 includes a controller 150 and a memory device 155. In one example, the controller 150 is communicatively coupled to the memory device 155. In one example, the memory device 155 includes one or more memory dies (e.g., a first memory die 165 and a second memory die 170). Although memory dies are specifically mentioned, the memory device 155 may include any non-volatile memory device, storage device, storage element, or storage medium, including NAND flash memory cells and / or NOR flash memory cells.

[0040] The memory cells may take the form of solid-state (e.g., flash memory) memory cells and may be programmable once, less-programmable, or programmable multiple times. Additionally, the memory cells may be single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), five-level cells (PLC), and / or use any other memory technology. The memory cells may be arranged in a two-dimensional or three-dimensional configuration.

[0041] In one example, data storage device 110 is connected to or embedded within host device 105. In another example, data storage device 110 is implemented as an external or portable device communicatively or selectively coupled to host device 105. In yet another example, data storage device 110 is a component (e.g., a solid-state drive (SSD)) of a network-accessible data storage system, a network-connected storage system, a cloud data storage system, etc.

[0042] As indicated above, the memory device 155 of the data storage device 110 includes a first memory die 165 and a second memory die 170. Although two memory dies are shown, the memory device 155 may include any number of memory dies (e.g., one memory die, two memory dies, eight memory dies, or other number of memory dies).

[0043] In one example, each memory die includes one or more voltage pumps or is otherwise associated with one or more voltage pumps. For example, a first memory die 165 includes voltage pump 185, and a second memory die 170 includes voltage pump 190. In examples where a memory die includes multiple voltage pumps, at least one voltage pump is associated with and / or shared across all planes in a plane of the memory die, and at least one voltage pump is associated with a corresponding plane of the memory die.

[0044] For example, each memory die includes a first voltage pump (e.g., a UMSYS voltage pump) and a second voltage pump (e.g., a VMSYS voltage pump). For instance, the first voltage pump is associated with a first type of voltage signal (e.g., VPGM and / or VERA voltage pump signals) and is shared by all planes across the memory die. Similarly, the second voltage pump is associated with a second type of signal (e.g., a VREAD pump signal) and is not shared by all planes across the memory die. Instead, the second voltage pump is dedicated to a specific plane of the memory die.

[0045] As will be explained in more detail herein, once the performance characteristics of the first voltage pump (and / or one or more pump signals associated with the first voltage pump) are determined, these performance characteristics may indicate that a particular memory die (e.g., the first memory die 165) is faulty or may be faulty. However, once the performance characteristics of the second voltage pump are determined, the performance characteristics of the second voltage pump (and / or the voltage pump signals associated with the second voltage pump) may indicate that a particular plane of the memory die (e.g., the first plane of the first memory die 165) is faulty or may be faulty.

[0046] The memory device 155 also includes support circuitry. In one example, the support circuitry includes read / write circuitry 160. Read / write circuitry 160 supports the operation of the memory die of memory device 155. Although read / write circuitry 160 is depicted as a single component, it may be divided into separate components, such as, for example, read circuitry and write circuitry. Read / write circuitry 160 may be external to the memory die of memory device 155. In another example, one or more memory dies in the memory die may include a corresponding read / write circuitry 160 operable to read data from a memory element within a single memory die and / or write data to that memory element independently of other read and / or write operations on any memory die in other memory dies.

[0047] In one example, one or more of the first memory die 165 and the second memory die 170 include one or more planes, and each plane may have one or more memory blocks. In one example, each memory block includes one or more memory cells. A memory cell block is the minimum number of memory cells that can be physically erased together. In one example, and to increase parallelism, each of these blocks may be operated on or organized within a larger block or meta-block. For example, a block of memory cells from different planes may be logically linked together to form a meta-block.

[0048] For example, refer to Figure 2A The memory device 200 (e.g., a memory element, a memory die, a non-volatile memory device) includes four planes or subarrays (e.g., a first plane 205, a second plane 210, a third plane 215, and a fourth plane 220). In one example, these planes are integrated on a single memory die, provided on two different memory dies (e.g., two planes on each memory die), or provided on four separate memory dies. Although four planes are shown and described, the memory device 200 may have any number of planes and / or memory dies.

[0049] Additionally, and as previously described, voltage pumps may be associated with memory device 200. For example, one or more voltage pumps may be shared across each of the four planes, while one or more voltage pumps may be associated with a single plane.

[0050] In one example, these planes are divided into memory blocks consisting of memory cells. For example... Figure 2AAs shown, rectangles represent each memory block, such as memory block 225, memory block 230, memory block 235, and memory block 240. Dozens or hundreds of memory blocks may exist in each plane of the memory device 200. In one example, each memory block is an erase unit and is sometimes referred to as an erase block. For example, memory blocks 225, 230, 235, and 240 comprise the minimum number of memory cells that are erased together.

[0051] Furthermore, various memory blocks can be logically linked or grouped together (e.g., using a table in controller 150 or a table that can be otherwise accessed by the controller) to form meta-blocks. Meta-blocks can be treated as single units to which write, read, and / or erase operations can be performed. For example, memory blocks 225, 230, 235, and 240 can form a first meta-block, while memory blocks 245, 250, 255, and 260 can form a second meta-block. The memory blocks used to form meta-blocks do not need to be confined to the same relative positions within their respective planes.

[0052] In one example, for operational purposes, each memory block can be divided into several pages of memory units, such as... Figure 2B As illustrated in the example. For instance, the memory cells of memory blocks 225, 230, 235, and 240 are divided into N different pages (shown as P0-PN). Although Figure 2B The specific number of pages is shown, but a memory block can have any number of memory cells within each memory block.

[0053] In one example, a page is a unit of data programming within a memory block. Each page contains the smallest amount of data that can be programmed at one time. The smallest unit of data that can be read at one time may be less than a page. Metapage 270 in... Figure 2B The memory block is illustrated as being formed by one physical page each in memory block 225, memory block 230, memory block 235, and memory block 240. In the example shown, metapage 270 comprises page P1 in each of the four memory blocks. However, the individual pages of metapage 270 do not need to be located in the same relative position within each memory block. Metapage 270 can be the largest programming unit within a memory block.

[0054] Figures 2A to 2BThe memory blocks disclosed herein are referred to as physical memory blocks because they involve groups of physical memory cells. As used herein, a logical memory block is defined as a virtual address space unit having the same size as a physical memory block. Each logical memory block includes a series of logical memory block addresses (LBAs) associated with data received from the host. These LBAs are then mapped to one or more physical memory blocks in data storage device 110 used for physically storing this data.

[0055] As indicated above, each memory block may include any number of memory cells. The design, size, and organization of the memory block may depend on the architecture, design, and application required for each memory die. In one example, a memory block comprises a set of contiguous memory cells sharing multiple word lines and bit lines. Word lines may be used as single-level cell (SLC) word lines, multi-level cell (MLC) word lines, three-level cell (TLC) word lines, four-level cell (QLC) word lines, five-level cell (PLC) word lines, etc. Additionally, each memory cell may be programmed to indicate a state that represents one or more values ​​(e.g., a threshold voltage in a flash memory configuration or a resistance state in a resistive memory configuration).

[0056] As previously described, the data storage device 110 also includes a controller 150. Although a single controller 150 is shown, the data storage device 110 may include multiple controllers. In such an example, a first controller executes a first number and / or type of commands, while a second controller executes a second number and / or type of commands. The controllers may operate in parallel and / or independently.

[0057] The controller 150 is communicatively coupled to the memory device 155 via a bus, interface, or other communication circuitry. In one example, the communication circuitry may include one or more channels enabling the controller 150 to communicate with a first memory die 165 and / or a second memory die 170 of the memory device 155. In another example, the communication circuitry may include multiple different channels enabling the controller 150 to communicate independently with the first memory die 165 of the memory device 155 and / or in parallel with the second memory die 170 of the memory device.

[0058] Controller 150 receives data and / or instructions from host device 105. Controller 150 also transmits data to host device 105. For example, controller 150 transmits data to host device 105 via communication interface 140 and / or receives data from host device 105. Controller 150 also transmits data and / or commands to memory device 155 and / or receives data from memory device 155.

[0059] The controller 150 transmits data and a corresponding write command to the memory device 155, causing the memory device 155 to store the data at a specified address. In one example, the write command specifies a portion of the physical address of the memory device 155.

[0060] Controller 150 also transmits data and / or commands associated with one or more background scan operations, garbage collection operations, and / or wear leveling operations. Controller 150 also transmits one or more read commands to memory device 155. In one example, a read command specifies a physical address of a portion of memory device 155 where data is stored. Controller 150 may also track the number of programming / erase cycles or other programming operations that have been performed on or by memory device 155 and / or on or by the memory die of memory device 155.

[0061] Controller 150 may also include or otherwise associate with a memory die failure prediction system 180. In one example, the memory die failure prediction system 180 is a packaged functional hardware unit designed for use with other components / systems. In another example, the memory die failure prediction system 180 is part of program code (e.g., software or firmware) executable by a processor or processing circuitry. In yet another example, the memory die failure prediction system 180 is a self-contained hardware and / or software component that interfaces with other components and / or systems. Although the memory die failure prediction system 180 is shown as part of controller 150, the memory die failure prediction system 180 may be decoupled from controller 150.

[0062] In one example, the memory die fault prediction system 180, together with the controller 150, is operable to determine whether one or more planes of one or more memory dies in the memory die are faulty and / or likely to be faulty, and / or whether one or more memory dies are faulty and / or likely to be faulty. In one example, the memory die fault prediction system 180 determines whether one or more memory dies in the memory die are faulty or likely to be faulty based at least in part on monitoring and / or determining one or more performance characteristics of the voltage pump associated with each memory die in the memory die.

[0063] For example, during programming and / or erasing operations, voltage pump 185 of the first memory die 165 and / or voltage pump 190 of the second memory die 170 should reach a target voltage threshold (e.g., at least fifteen volts). However, if one or more of the voltage pumps fail to reach the target voltage threshold, the memory die and / or the plane of the memory die (depending on the monitored voltage pump) may be faulty or may fail.

[0064] Therefore, in order to anticipate voltage pump failures, plane failures, and / or memory die failures, the memory die failure prediction system 180 periodically monitors one or more performance characteristics of one or more voltage pumps in the voltage pumps of each memory die. In one example, the memory die failure prediction system 180 monitors or determines one or more performance characteristics based on a specific frequency (e.g., after a specific number of P / E cycles have occurred).

[0065] For example, the memory die failure prediction system 180 determines the performance characteristics of one or more voltage pumps in the voltage pumps every 1,000 P / E cycles, every 5,000 P / E cycles, every 7,000 P / E cycles, etc. Although a specific number of P / E cycles is mentioned, the memory die failure prediction system 180 can determine the performance characteristics of a specific voltage pump associated with a particular memory die and / or a specific plane of the memory die after any number of P / E cycles have occurred. In one example, the number of P / E cycles is dynamic and / or at least partially based on the aging degree and / or type / quality of the memory die. In another example, the number of P / E cycles is static and / or predetermined.

[0066] In one example, the memory die failure prediction system 180 determines one or more performance characteristics (also referred to as first performance characteristics) of a particular voltage pump at a first instance or at a first time. In one example, the first instance is when the particular voltage pump is disconnected and / or detached from the memory cell (or NAND array) of the memory die.

[0067] In one example, the first performance characteristic is the voltage (or voltage signal) supplied to the memory die and / or the plane of the memory die. In another example, the first performance characteristic is the clock count associated with the voltage pump. In yet another example, the first performance characteristic of the voltage pump is the pump rate. Although specific performance characteristics are mentioned, other performance characteristics may also be used.

[0068] Once the first performance characteristic has been determined, the memory die failure prediction system 180 compares the first performance characteristic with a performance characteristic threshold. If the memory die failure prediction system 180 determines, at least in part, based on this comparison, that the first performance characteristic has reached or exceeded the performance characteristic threshold, then the memory die failure prediction system 180 can determine that the memory die and / or voltage pump are functioning and / or performing as expected. Therefore, no further action is taken until another series of P / E cycles has been completed.

[0069] However, if the memory die failure prediction system 180 determines, at least in part, based on the comparison, that a first performance characteristic has dropped below a performance characteristic threshold, the memory die failure prediction system 180 is operable to determine whether the memory die is in a state of failure and / or is likely to fail.

[0070] To determine this, the memory die failure prediction system 180 determines the performance characteristics of the voltage pump at a second instance and / or at a second time. In the example below, the performance characteristics determined and / or monitored at the second instance are referred to as the second performance characteristics. In one example, the second instance is when the voltage pump is connected to a memory cell of the memory die.

[0071] Then, the memory die fault prediction system 180 determines whether a first performance characteristic of the voltage pump at the first instance matches a second performance characteristic of the voltage pump at the second instance. For example, if the performance characteristic is pump speed, the memory die fault prediction system 180 checks the pump speed of the voltage pump when the voltage pump is disconnected from the memory cell (e.g., using a clock counting method), and also checks the pump speed of the voltage pump when the voltage pump is connected to the memory cell. The memory die fault prediction system 180 then determines whether the total number of clock counts determined in the first instance matches the total number of clock counts determined in the second instance.

[0072] If the memory die failure prediction system 180 determines that a first performance characteristic associated with a first instance matches a second performance characteristic of a second instance, the memory die failure prediction system 180 determines whether to initiate a relocation operation.

[0073] In determining whether to initiate a relocation operation, the memory die fault prediction system 180 determines whether a memory block of the memory die is faulty, or whether the memory die and / or the memory plane of the memory die is faulty or likely to fail. To determine this, the memory die fault prediction system 180 selects multiple memory blocks of the memory die (e.g., multiple memory blocks of the first memory die 165). In one example, the memory blocks are randomly selected. Each memory block in the selected memory blocks is erased, and the memory die fault prediction system 180 determines the state of each memory block (e.g., whether a single memory block has failed or whether multiple memory blocks have failed). In one example, the state of each memory block may be based at least in part on monitored voltage signals (e.g., read voltage signals and / or programming voltage signals). For example, if the voltage signal applied to a memory block is below a threshold, the memory block may have failed. In other examples, other fault detection mechanisms may be used.

[0074] If the memory die fault prediction system 180 determines that a single memory block has failed, the memory die fault prediction system 180 marks the single memory block as a growing bad block. The memory die fault prediction system 180 can then repeat the aforementioned operation based on a determined frequency.

[0075] However, if the memory die fault prediction system 180 determines that multiple memory blocks of the memory die have failed, the memory die fault prediction system 180 may determine that the memory die and / or the plane of the memory die is faulty or may fail (and / or one or more voltage pumps associated with the memory die are faulty or may fail). Therefore, the memory die fault prediction system 180 initiates a relocation operation. In one example, and depending on the number of available memory blocks in the memory device 150, the memory die fault prediction system 180 may initiate different relocation operations.

[0076] For example, if the number of available memory blocks in memory device 150 exceeds a certain threshold, or if memory die failure prediction system 180 determines that data storage device 110 (or memory device 155) has a sufficient number of memory blocks, memory die failure prediction system 180 will initiate a first relocation operation. Regarding Figure 6 The first relocation operation will be described in more detail.

[0077] However, if the number of available memory blocks in memory device 150 is below a certain threshold, or if memory die failure prediction system 180 determines that data storage device 110 (or memory device 155) does not have a sufficient number of memory blocks, memory die failure prediction system 180 will initiate a second relocation operation. Regarding Figure 7 The second relocation operation is described in more detail.

[0078] In one example and as used herein, the term “sufficient” means that the data storage device has enough space in one or more healthy memory dies and / or memory blocks to store all data that will be relocated from faulty memory dies and / or from the fault plane of the memory dies.

[0079] In another example, the memory die failure prediction system 180 may determine that a first performance characteristic associated with a first instance does not match a second performance characteristic of a second instance. However, in one example, even if the first performance characteristic does not match the second performance characteristic, the memory die failure prediction system 180 may still determine whether to initiate a relocation operation.

[0080] When determining whether to initiate a relocation operation in the event that the first performance characteristics associated with the first instance do not match the second performance characteristics of the second instance, the memory die failure prediction system 180 determines whether a memory block of a particular memory die (e.g., the first memory die 165) is faulty, or whether the memory die and / or the memory plane of the memory die is faulty or may be faulty.

[0081] To determine this, the memory die fault prediction system 180 selects (e.g., randomly selects) one or more memory blocks across different planes of the memory die. The memory die fault prediction system 180 erases each memory block in the selected memory blocks and determines the fault bit count (FBC) for each memory block. If the memory die fault prediction system 180 determines that the FBC of a particular memory block exceeds an FBC threshold, the memory die fault prediction system 180 increases the voltage level (e.g., read voltage level and / or programming voltage) provided by the voltage pump associated with each memory block whose FBC exceeds the FBC threshold.

[0082] If the FBC of a single memory block increases, the memory die fault prediction system 180 will mark that particular memory block as a growing bad block. The memory die fault prediction system 180 can then repeat the aforementioned operation.

[0083] However, if the FBC of multiple memory blocks increases with the applied voltage (e.g., read voltage), the memory die and / or the plane of the memory die may be faulty or may fail. Therefore, the memory die fault prediction system 180 initiates a relocation operation. In one example and depending on the number of available memory blocks in the memory device 150, the memory die fault prediction system 180 may initiate different relocation operations.

[0084] For example, if the number of available memory blocks in memory device 150 exceeds a certain threshold, or if memory die failure prediction system 180 determines that data storage device 110 (or memory device 155) has a sufficient number of memory blocks, memory die failure prediction system 180 will initiate a first relocation operation. Regarding Figure 6 The first relocation operation is described in more detail. However, if the number of available memory blocks in memory device 150 falls below a certain threshold, or if the memory die failure prediction system 180 determines that data storage device 110 (or memory device 155) does not have a sufficient number of memory blocks, the memory die failure prediction system 180 will initiate a second relocation operation. Regarding Figure 7 The second relocation operation is described in more detail.

[0085] Figure 3 A method 300 is illustrated for identifying a memory die that is faulty and / or likely to fail, based on the performance characteristics determined by the voltage pump. Although method 300 is explained in relation to a memory die, it can also be used to determine whether one or more planes of a particular memory die are faulty or likely to fail.

[0086] For example, a memory die can be identified as faulty or potentially faulty based on one or more performance characteristics of one or more voltage pumps shared by multiple planes across a memory die. However, a plane of the memory die can be identified as faulty or potentially faulty based on one or more performance characteristics of one or more voltage pumps associated with a plane of the memory die (e.g., voltage pumps not shared across planes of the memory die). In one example, method 300 is based on a memory die fault prediction system of a data storage device (such as, for example, regarding...). Figure 1 The memory die failure prediction system 180 shown and described is executed.

[0087] In one example, method 300 first tracks (310) a specific memory die of the data storage device (e.g., the first memory die 165). Figure 1The number of P / E cycles is then determined by the memory die fault prediction system (320). The system then determines whether a threshold number of P / E cycles has occurred.

[0088] In one example, the threshold number of P / E cycles is based, at least in part, on the required frequency at which the memory die failure prediction system checks whether the memory die is faulty or likely to fail. In one example, the threshold number of P / E cycles is one thousand. In another example, the threshold number of P / E cycles is three thousand. Although a specific number of P / E cycles is given, the threshold can be any number of P / E cycles.

[0089] If the memory die fault prediction system determines (320) that the threshold number of P / E cycles has not yet been reached, the memory die fault prediction system continues to track (310) the number of P / E cycles associated with the memory die. However, if the memory die fault prediction system determines (320) that the threshold number of P / E cycles has been reached, the memory die fault prediction system monitors or determines (330) the performance characteristics (or determines a first performance characteristic) of at least one voltage pump associated with the memory die at the first instance.

[0090] In one example, the first performance characteristic is a determination of the pump strength of at least one voltage pump associated with the memory die. Although pump strength is specifically described, the first performance characteristic can be any measurable and / or determinable metric (e.g., pump speed) associated with the voltage pump and / or the memory die. In some examples, the first performance characteristic of the voltage pump is determined when the voltage pump is disconnected from the memory cell of the memory die.

[0091] After measuring the first performance characteristic, the memory die failure prediction system determines (340) whether the first performance characteristic exceeds a performance threshold. In one example, the performance threshold is a voltage provided by a voltage pump, but other thresholds may also be used.

[0092] If the memory die failure prediction system determines that the first performance characteristic has reached or exceeded the performance characteristic threshold, then method 300 is repeated. However, if the memory die failure prediction system determines (340) that the first performance characteristic has dropped below the performance characteristic threshold, then the memory die failure prediction system determines whether the memory die is in a state of failure and / or may fail.

[0093] To determine this, the memory die failure prediction system monitors or determines (350) the performance characteristics (or determines a second performance characteristic) of at least one voltage pump associated with the memory die at a second instance. In one example, the second instance is when the voltage pump is connected to a memory cell of the memory die.

[0094] Then, the memory die fault prediction system determines (360) whether the first performance characteristic matches the second performance characteristic. For example, and as previously stated, if the first performance characteristic is pump speed, the memory die fault prediction system checks the pump speed of the voltage pump when the voltage pump is disconnected from the memory cell (e.g., using a clock counting method), and also checks the pump speed of the voltage pump when the voltage pump is connected to the memory cell. The memory die fault prediction system then determines whether the total number of clock counts determined in the first instance matches the total number of clock counts determined in the second instance.

[0095] If the memory die fault prediction system determines (360) that the first performance characteristic matches the second performance characteristic, then it initiates a first memory die fault determination method (400) (indicated by the letter A). However, if the memory die fault prediction system determines (360) that the first performance characteristic does not match the second performance characteristic, then it initiates a second memory die fault determination method (500), indicated by the letter B. The first memory die fault determination method 400 will... Figure 4 The description is provided, and the second memory die fault determination method 500 will be about... Figure 5 Describe it.

[0096] Figure 4 An example of a method 400 for determining whether a memory die is in a fault state is illustrated. In one example, method 400 is based on a memory die fault prediction system for a data storage device (such as, for example, regarding...). Figure 1 The memory die failure prediction system 180 shown and described is executed. In one example, method 400 is also used to determine whether to initiate a relocation operation.

[0097] When determining whether to initiate a relocation operation, the memory die failure prediction system selects (410) the memory die being analyzed (e.g., the first memory die 165). Figure 1 One or more memory blocks. Each memory block is erased (420), and the memory die failure anticipation system checks and / or determines (430) the failure status of each memory block in the one or more memory blocks as previously described.

[0098] Then, the memory die fault prediction system determines (440) whether a single memory block or multiple memory blocks have failed based on the fault status. If the memory die fault prediction system determines (440) that a single memory block has failed, the memory die fault prediction system marks (450) that single memory block as a growing bad block. The process can then be repeated regarding... Figure 3 Method 300 is shown and described.

[0099] However, if the memory die failure prediction system determines (440) that multiple memory blocks have failed, the memory die failure prediction system will initiate a first relocation operation or a second relocation operation. In one example, the determination of which relocation operation to perform is based at least in part on the number of available memory blocks in the data storage device.

[0100] For example, the memory die failure prediction system determines (460) the number and / or quantity of available memory blocks on the data storage device. Then, the memory die failure prediction system determines (470) whether the number of available memory blocks is sufficient. For example, the memory die failure prediction system determines whether that number of available memory blocks can store the amount of data to be relocated from the memory die.

[0101] If the memory die failure prediction system determines (470) that there are sufficient available memory blocks and / or memory dies in the data storage device, the memory die failure prediction system executes or initiates a process to determine whether to proceed with the failure. Figure 6 The first relocation operation 600 (indicated by the letter C) is shown and described. However, if the memory die failure prediction system determines (470) that there is not a sufficient amount of available memory blocks, the memory die failure prediction system executes or initiates an operation that will... Figure 7 The second relocation operation 700 (indicated by the letter D) is shown and described.

[0102] Re-reference Figure 3 Furthermore, as previously discussed, the memory die failure prediction system can determine (360) that a first performance characteristic associated with the first instance does not match a second performance characteristic of the second instance. Therefore, the memory die failure prediction system performs an action regarding... Figure 5 Method 500 is shown and described.

[0103] Figure 5 A method 500 for determining whether a memory die is faulty, according to another example, is illustrated. In one example, method 500 is based on a memory die fault prediction system for a data storage device (such as, for example, regarding...). Figure 1 The memory die failure prediction system 180 shown and described is executed. In one example and similar to the one about Figure 4 Method 400, shown and described, and method 500 are also used to determine whether to initiate a relocation operation.

[0104] When determining whether to initiate a relocation operation, the memory die failure is expected to occur across the specific memory die being analyzed (e.g., the first memory die 165). Figure 1(510) Select one or more memory blocks from different planes. The memory die fault prediction system erases (520) each memory block in the selected memory blocks and determines the fault bit count (FBC) for each memory block. Then, the memory die fault prediction system determines (540) whether the FBC of a particular memory block exceeds an FBC threshold. If the memory die fault prediction system determines (540) that the FBC of the selected memory block does not exceed the FBC threshold, the next memory block is selected and the FBC of the selected memory block is determined (530). This process can be repeated for each selected memory block.

[0105] In one example, if none of the selected memory blocks have an FBC exceeding the FBC threshold, method 500 terminates. However, if the memory die fault prediction system determines (540) that the FBC of one of the memory blocks exceeds the FBC threshold, the memory die fault prediction system increases the voltage level (e.g., read voltage and / or programming voltage) provided by the voltage pump associated with each memory block whose FBC exceeds the FBC threshold.

[0106] If the FBC of a single memory block increases (but the FBC of other selected memory blocks does not increase), the memory die fault prediction system marks (560) that particular memory block as a growing bad block. The memory die fault prediction system 180 can then repeat the process regarding... Figure 3 Method 300 is shown and described.

[0107] However, if the memory die fault prediction system determines that the FBC of multiple memory blocks (550) increases with voltage rise, the memory die may be faulty or may fail. Therefore, the memory die fault prediction system initiates a relocation operation.

[0108] For example, the memory die failure prediction system determines (570) the number and / or quantity of available memory blocks on the data storage device. Then, the memory die failure prediction system determines (580) whether the number of available memory blocks is sufficient. For example, the memory die failure prediction system determines whether that number of available memory blocks can store the amount of data to be relocated from the memory die.

[0109] If the memory die failure prediction system determines (580) that there are sufficient available memory blocks, the memory die failure prediction system executes or initiates a process to determine whether or not a failure is expected. Figure 6 The first relocation operation 600 (indicated by the letter C) is shown and described. However, if the memory die failure prediction system determines (580) that there is not a sufficient amount of available memory blocks, the memory die failure prediction system executes or initiates an operation that will... Figure 7 The second relocation operation 700 (indicated by the letter D) is shown and described.

[0110] Figure 6 The illustration shows a first relocation operation 600 according to an example. In one example, the first relocation operation 600 is initiated by a memory die failure anticipation system (such as, for example, regarding...). Figure 1 The memory die failure prediction system 160 shown and described is executed. Additionally, and in one example, when the memory die failure prediction system determines that the data storage device has a sufficient number of available memory blocks, the memory die failure prediction system performs a first relocation operation.

[0111] Method 600 begins when the memory die failure prediction system reads (610) data from a memory block of a memory die that is faulty or may fail. Once the data is read, the memory die failure prediction system writes the data to an available memory block (620).

[0112] In one example, the memory die failure prediction system also modifies and / or updates (630) one or more links associated with a newly written memory block (e.g., in a logical-to-physical mapping table). For example, the memory die failure prediction system relinks pointers associated with older memory blocks to point to new memory blocks on which data has been written. The memory die failure prediction system then marks (640) the memory block associated with the memory die as a growing bad block.

[0113] Figure 7 An example of a second relocation operation 700 according to the example is illustrated. In one example, the second relocation operation 700 is initiated by a memory die failure anticipation system (such as, for example, regarding...). Figure 1 The memory die failure prediction system 160 shown and described is executed. Additionally, and in one example, when the memory die failure prediction system determines that the data storage device does not have a sufficient number of available memory blocks for the relocation operation, the memory die failure prediction system executes a second relocation operation.

[0114] Method 700 begins when the memory die failure prediction system reads (710) data from a memory block of a memory die that is faulty or may fail. Once the data is read, the memory die failure prediction system writes the data to (720) available memory blocks. In one example, the memory die failure prediction system writes the data to any and / or all available SLC memory blocks. However, in some examples, the memory die failure prediction system operates the SLC memory blocks in MLC mode.

[0115] In one example, the memory die failure prediction system also modifies and / or updates (730) one or more links associated with a newly written memory block (e.g., in a logical-to-physical mapping table). For example, the memory die failure prediction system relinks pointers associated with older memory blocks to point to new memory blocks on which data has been written.

[0116] Then, the memory die fault prediction system marks (740) the memory blocks associated with the memory die as growing bad blocks. The memory die fault prediction system can also put the data storage device into read-only mode (750). In one example, the memory die fault prediction system puts the data storage device into read-only mode when the second relocation operation exhausts all SLC memory blocks.

[0117] Figures 8 to 9 Example storage devices are described that can be used with or otherwise implement the various features described herein. For example, regarding... Figures 8 to 9 The storage devices shown and described may include those related to... Figure 1 Various systems and components similar to those shown and described. For example, regarding... Figure 9 The controller 922 shown and described may be similar to Figure 1 The controller 150. Similarly, the memory die 908 can be similar to... Figure 1 The first memory die 165 and / or the second memory die 170.

[0118] Figure 8 This is a perspective view of a storage device 800 including a three-dimensional (3D) stacked non-volatile memory, according to an example. In this example, the storage device 800 includes a substrate 810. Blocks of memory cells are included on or above the substrate 810. These blocks include a first block (BLK0820) and a second block (BLK1830). Each block is formed by memory cells (e.g., non-volatile memory elements). The substrate 810 also includes a peripheral region 840 having support circuitry used by the first and second blocks.

[0119] The substrate 810 also carries circuitry beneath the block and one or more lower metal layers patterned as conductive paths to carry signals from the circuitry. In one example, these blocks are formed in a central region 850 of the memory device 800. The memory device also includes an upper region 860. The upper region 860 includes one or more upper metal layers patterned as conductive paths to carry signals from the circuitry. Each memory cell block includes a stacked region of memory cells. In one example, alternating stack levels represent word lines. Although two blocks are depicted, additional blocks may be used, and these blocks extend in the x and / or y directions.

[0120] In one example, the length of the plane of substrate 810 in the x-direction represents the direction in which the signal path of the word line or control gate line extends (e.g., word line or drain-end select gate (SGD) line direction), and the width of the plane of substrate 810 in the y-direction represents the direction in which the signal path of the bit line extends (e.g., bit line direction). The z-direction represents the height of memory device 800.

[0121] Figure 9 This is based on the functional block diagram of the example storage device 900. In one example, storage device 900 is similar to... Figure 8 The 3D stacked non-volatile storage device 800 shown and described. In one example, Figure 9 The components depicted are circuits. In one example, the storage device 900 includes one or more memory dies 905. Each memory die 905 includes a three-dimensional memory structure 910 of memory cells (e.g., a 3D array of memory cells), control circuitry 915, and read / write circuitry 920. In another example, a two-dimensional array of memory cells may be used. The memory structure 910 may be addressed via word lines using a first decoder 925 (e.g., a row decoder) and via bit lines using a second decoder 930 (e.g., a column decoder). The read / write circuitry 920 may also include a plurality of sensing blocks 935, including SB1, SB2…SBp (e.g., sensing circuitry), which allow parallel reading or programming of pages of memory cells. The sensing blocks 935 may include bit line drivers.

[0122] In one example, controller 940 is included in the same storage device 900 as one or more memory dies 905. In another example, controller 940 is formed on a die bonded to memory dies 905, in which case each memory die 905 may have its own controller 940. In yet another example, the controller die controls all memory dies 905. Although a single controller 940 is shown, storage device 900 may include multiple controllers, each responsible for different operations described herein.

[0123] Commands and data are transmitted between the host 945 and the controller 940 via data bus 950. Additionally, commands and data are transmitted between the controller 940 and one or more memory dies in memory die 905 via line 955. In one example, memory die 905 includes a set of input and / or output (I / O) pins connected to line 955.

[0124] The memory structure 910 also includes one or more memory cell arrays. The memory cells are arranged in a three-dimensional or two-dimensional array. The memory structure 910 includes any type of non-volatile memory formed on one or more physical-level memory cell arrays having active regions disposed on a silicon substrate. The memory structure 910 may reside in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is on or within the substrate.

[0125] Control circuitry 915 works in conjunction with read / write circuitry 920 to perform memory operations (e.g., erase, program, read, and other operations) on memory structure 910. Control circuitry 915 may include registers, ROM fuses, and other devices for storing default values ​​such as base voltage and other parameters.

[0126] The control circuitry 915 also includes a state machine 960, an on-chip address decoder 965, and a power control module. The state machine 960 provides chip-level control for various memory operations, such as selecting the memory block for programming. The state machine 960 can be programmed by software. In another example, the state machine 960 is implemented entirely in hardware (e.g., circuitry) without using software.

[0127] The on-chip address decoder 965 provides an address interface between the addresses used by the host 945 and / or controller 940 and the hardware addresses used by the first decoder 925 and the second decoder 930. The power control module 970 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control module 970 may include drivers for word line layers in a 3D configuration, select-gate transistors (e.g., SGS transistors and SGD transistors), and source lines. The power control module 970 may include one or more charge pumps for generating voltage. In one example, the power control module 970 helps ensure that word lines for growing bad blocks, as described herein, are programmed at the desired levels.

[0128] Control circuit 915, state machine 960, on-chip address decoder 965, first decoder 925, second decoder 930, power control module 970, sensing block 935, read / write circuit 920 and / or controller 940 may be regarded as one or more control circuits and / or management circuits performing some or all of the operations described herein.

[0129] In one example, controller 940 may be on-chip or off-chip circuitry. Additionally, controller 940 may include one or more processors 980, ROM 985, RAM 990, memory interface 995, and host interface 997, all of which are interconnectable. In one example, one or more processors 980 are an example of control circuitry. Other examples may use state machines or other custom circuitry designed to perform one or more functions. Devices such as ROM 985 and RAM 990 may include code such as instruction sets. One or more processors in processor 980 are operable to execute instruction sets to provide some or all of the functionality described herein.

[0130] Alternatively or additionally, one or more processors in processor 980 may access code from memory devices in memory structure 910, such as reserved areas of memory cells connected to one or more word lines. A memory interface 995 communicating with one or more processors in ROM 985, RAM 990, and processor 980 may be circuitry providing an electrical interface between controller 940 and memory die 905. For example, memory interface 995 may modify signal format or timing, provide buffering, surge isolation, latch I / O, etc.

[0131] One or more processors 980 may use memory interface 995 to issue commands to control circuitry 915 or to any other component of memory die 905. Host interface 997, which communicates with ROM 985, RAM 990, and one or more processors 980, may be circuitry providing an electrical interface between controller 940 and host 945. For example, host interface 997 may modify signal format or timing, provide buffering, surge isolation, latch I / O, etc. Commands and data from host 945 are received by controller 940 through host interface 997. Data sent to host 945 may be transmitted using data bus 950.

[0132] Multiple memory elements in memory structure 910 can be configured such that they are connected in series or that each element can be accessed individually. As a non-limiting example, a flash memory device (e.g., NAND flash memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a group of memory cells and select-gate transistors connected in series.

[0133] NAND flash memory arrays can also be configured such that the array comprises multiple NAND strings. In one example, a NAND string comprises multiple memory cells that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each memory element can be accessed individually (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory cells may have other configurations.

[0134] Memory cells can be arranged in an ordered array (such as by multiple rows and / or columns) within a single memory device level. However, memory elements can be arranged in an irregular configuration, a non-orthogonal configuration, or a structure that is not considered an array.

[0135] In one example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, such as along the y-direction), each column containing multiple memory cells. The vertical columns can be arranged in a two-dimensional arrangement of the memory cells, where the memory cells are on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a 3D memory array.

[0136] In another example, in a 3D NAND memory array, memory elements can be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other 3D configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. 3D memory arrays can also be designed in NOR and ReRAM configurations.

[0137] Based on the foregoing, this disclosure describes an example of a method comprising: determining at least one performance characteristic of at least one voltage pump of a memory device at a first instance; comparing the at least one performance characteristic of the at least one voltage pump of the memory device to a performance characteristic threshold; determining the at least one performance characteristic of the at least one voltage pump of the memory device at a second instance based at least in part on determining that the at least one performance characteristic of the at least one voltage pump of the memory device is lower than the performance characteristic threshold; comparing the performance characteristic of the at least one voltage pump of the memory device at the first instance with the performance characteristic of the at least one voltage pump of the memory device at the second instance; and performing the following operations based at least in part on the matching of the performance characteristic of the at least one voltage pump of the memory device at the first instance with the performance characteristic of the at least one voltage pump of the memory device at the second instance: selecting a plurality of memory blocks of the memory device associated with the at least one voltage pump; erasing each of the plurality of memory blocks; determining a state of each of the plurality of memory blocks; and determining whether to initiate a relocation operation based at least in part on the determined state of each of the plurality of memory blocks. In one example, the relocation operation is initiated based at least in part on the plurality of memory blocks having a fault state. In one example, the method further includes identifying the number of available memory blocks in the memory device; and continuing the relocation operation using a first relocation method based at least in part on the fact that the number of available memory blocks in the memory device exceeds an available memory block threshold. In one example, the first method includes: reading data from memory blocks associated with the plurality of memory blocks having the fault state; writing the data from the memory blocks associated with the plurality of memory blocks having the fault state to the available memory blocks in the memory device; updating a mapping table associated with the memory blocks; and marking the memory blocks associated with the plurality of memory blocks having the fault state and the memory blocks having the fault state as growing bad blocks. In one example, the method further includes continuing the relocation operation using a second relocation method based at least in part on the fact that the number of available memory blocks in the memory device decreases below the available memory block threshold.In one example, the second method includes: reading data from memory blocks associated with the plurality of memory blocks having the fault state; writing the data from the memory blocks associated with the plurality of memory blocks having the fault state to available memory blocks in the memory device, at least one of the available memory blocks having switched from a first mode to a second mode; updating a mapping table associated with the memory blocks; and marking the memory device as a read-only memory device. In one example, the first mode is a single-level cell (SLC) mode, and wherein the second mode is a multi-level cell (MLC) mode. In one example, the method further includes marking a single memory block as a growing bad block based at least in part on a determined state of a single memory block among the plurality of memory blocks. In one example, the method further includes checking the fault bit count of the plurality of memory blocks of the memory device associated with the at least one voltage pump based at least in part on the difference between the performance characteristics of the at least one voltage pump of the memory device at the first instance and the performance characteristics of the at least one voltage pump of the memory device at the second instance. In one example, the method further includes determining whether to initiate a relocation operation based at least in part on the fact that the fault bit count of the plurality of memory blocks exceeds a fault bit count threshold.

[0138] The example also describes a memory device including: a controller; and a memory die failure prediction system communicatively coupled to the controller and operable to: periodically determine a first performance characteristic of at least one voltage pump associated with the memory device; initiate a first memory die failure prediction operation based at least in part on the first performance characteristic matching a second performance characteristic of the at least one voltage pump associated with the memory device; and initiate a second memory die failure prediction operation based at least in part on the first performance characteristic differing from the second performance characteristic. In one example, the memory die failure prediction system determines the first performance characteristic of the at least one voltage pump associated with the memory device when the memory device has executed a threshold number of program / erase cycles. In one example, the first performance characteristic of the at least one voltage pump is the output voltage of the at least one voltage pump. In one example, the first performance characteristic of the at least one voltage pump is the pump speed of the at least one voltage pump. In one example, the at least one voltage pump is associated with a plane of a memory die of the memory device. In one example, the at least one voltage pump is associated with a memory die of the memory device. In one example, the anticipated operation for a first memory die failure includes: determining whether a plurality of memory blocks associated with the at least one voltage pump have failed; determining whether the number of available memory blocks in the memory device exceeds an available memory block threshold; and, at least in part based on the determination that the plurality of memory blocks associated with the at least one voltage pump have failed and that the number of available memory blocks in the memory device exceeds the available memory block threshold, performing the following operations: writing data from the memory blocks associated with the plurality of memory blocks having the failed state to the available memory blocks in the memory device; updating a mapping table associated with the memory blocks; and marking the memory blocks associated with the plurality of memory blocks having the failed state and the memory blocks having the failed state as growing bad blocks. In one example, the second memory die failure anticipated operation includes: determining whether a plurality of memory blocks associated with the at least one voltage pump have failed; and, based at least in part on the determination that the plurality of memory blocks associated with the at least one voltage pump have failed, performing the following operations: determining a fault bit count associated with each of the plurality of memory blocks; increasing the voltage applied to each of the plurality of memory blocks; determining whether the fault bit count associated with each of the plurality of memory blocks has increased; and marking at least a portion of the memory die associated with each of the plurality of memory blocks as faulty.

[0139] The example also describes a memory device comprising: components for determining a performance characteristic of at least one voltage supply device associated with the memory device; components for comparing the performance characteristic of the at least one voltage supply device with a performance characteristic threshold; components for determining whether a plurality of memory blocks associated with the voltage supply device have failed, wherein the components for determining whether the plurality of memory blocks associated with the voltage supply device have failed are at least partially based on the comparison of the performance characteristic of the at least one voltage supply device with the performance characteristic threshold; and components for initiating a relocation operation, wherein the components for initiating the relocation operation are at least partially based on the components for determining whether the plurality of memory blocks associated with the voltage supply device have failed determining that the plurality of memory blocks have failed. In one example, the memory device further includes components for marking a single memory block among the plurality of memory blocks as a growing bad block, wherein the components for marking the single memory block among the plurality of memory blocks as a growing bad block are at least partially based on the components for determining whether the plurality of memory blocks associated with the voltage supply device have failed in order to mark the single memory block as a growing bad block.

[0140] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, but rather encompass many related memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0141] The descriptions and illustrations of one or more aspects provided in this disclosure are not intended to limit or restrict the scope of this disclosure in any way. The aspects, examples, and details provided in this disclosure are considered sufficient to convey ownership and enable others to implement and use the best practices of the claimed disclosure.

[0142] The claimed disclosure should not be construed as being limited to any aspect, example, or detail provided herein. Whether shown and described in combination or separately, various features (both structural and methodological features) are intended to be selectively rearranged, included, or omitted to produce examples with a particular set of features. Having obtained the descriptions and examples in this disclosure, those skilled in the art can conceive of variations, modifications, and alternatives that fall within the broader scope of the overall inventive concept embodied in this disclosure and do not depart from the broader scope of the claimed disclosure.

[0143] The foregoing has described aspects of this disclosure with reference to schematic flowcharts and / or schematic block diagrams of methods, apparatus, systems, and computer program products according to examples of this disclosure. It should be understood that each block of the schematic flowcharts and / or schematic block diagrams, and combinations of blocks in the schematic flowcharts and / or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a computer processor or other programmable data processing apparatus to produce a machine, such that, upon execution via the processor or other programmable data processing apparatus, these instructions create components for implementing the functions and / or actions specified in the blocks of the schematic flowcharts and / or schematic block diagrams.

[0144] The use of names such as "first" and "second" to refer to elements in this document does not generally limit the number or order of these elements. Rather, these names serve as a way to distinguish two or more elements or instances of elements. Therefore, referring to a first element and a second element does not imply that only two elements can be used or that the first element precedes the second element. Additionally, unless otherwise stated, a group of elements may include one or more elements.

[0145] As used in this specification or claims, the terms "at least one of A, B, or C" or "A, B, C, or any combination thereof" mean "A, B, or C, or any combination of these elements." For example, the term may include A, B, C, A and B, A and C, A and B and C, 2A, 2B, 2C, 2A and B, etc. As an additional example, "at least one of A, B, or C" is intended to cover A, B, C, AB, AC, BC, and ABC, as well as multiple identical members. Similarly, "at least one of A, B, and C" is intended to cover A, B, C, AB, AC, BC, and ABC, as well as multiple identical members.

[0146] Similarly, as used herein, phrases referring to a list of items used with “and / or” refer to any combination of those items. For example, “A and / or B” is intended to cover A alone, B alone, or A and B together. As another example, “A, B and / or C” is intended to cover A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B and C together.

Claims

1. A method, the method comprising: At the first instance, at least one performance characteristic of at least one voltage pump of the memory device is determined; The at least one performance characteristic of the at least one voltage pump of the memory device is compared with a performance characteristic threshold; The at least one performance characteristic of the at least one voltage pump of the memory device is determined at a second instance based at least in part on the determination that the at least one performance characteristic of the at least one voltage pump of the memory device is lower than the performance characteristic threshold; The performance characteristics of the at least one voltage pump of the memory device at the first instance are compared with the performance characteristics of the at least one voltage pump of the memory device at the second instance; as well as The following operations are performed, at least in part, based on the matching of the performance characteristics of the at least one voltage pump of the memory device at the first instance with the performance characteristics of the at least one voltage pump of the memory device at the second instance: Select multiple memory blocks of the memory device associated with the at least one voltage pump; Erase each of the plurality of memory blocks; Determine the state of each of the plurality of memory blocks; as well as Whether to initiate a relocation operation is determined at least in part based on the determined state of each of the plurality of memory blocks.

2. The method of claim 1, wherein the relocation operation is initiated at least in part based on the fact that one or more of the plurality of memory blocks are in a fault state.

3. The method according to claim 2, further comprising: Identify the number of available memory blocks in the memory device; as well as The relocation operation continues using a first relocation method, at least in part, based on the fact that the number of available memory blocks in the memory device exceeds the available memory block threshold.

4. The method according to claim 3, wherein the first method comprises: Data is read from the memory blocks associated with the plurality of memory blocks having the fault state; The data from the memory blocks associated with the plurality of memory blocks having the fault state is written into the available memory blocks in the memory device; Update the mapping table associated with the memory block; as well as The memory blocks associated with the plurality of memory blocks having the aforementioned fault state and the memory blocks having the aforementioned fault state are marked as growing bad blocks.

5. The method of claim 3, further comprising continuing the relocation operation using a second relocation method, at least in part based on the fact that the number of available memory blocks in the memory device has decreased to below the available memory block threshold.

6. The method of claim 5, wherein the second method comprises: Data is read from the memory blocks associated with the plurality of memory blocks having the fault state; The data from the memory blocks associated with the plurality of memory blocks having the fault state is written into the available memory blocks in the memory device, at least one of the available memory blocks having switched from a first mode to a second mode; Update the mapping table associated with the memory block; as well as The memory device is marked as a read-only memory device.

7. The method of claim 6, wherein the first mode is a single-cell (SLC) mode, and wherein the second mode is a multi-cell (MLC) mode.

8. The method of claim 1, further comprising marking a single memory block as a growing bad block based at least in part on a determined state of the single memory block among the plurality of memory blocks.

9. The method of claim 1, further comprising checking the fault bit count of a plurality of memory blocks of the memory device associated with the at least one voltage pump based at least in part on the difference between the performance characteristics of the at least one voltage pump of the memory device at the first instance and the performance characteristics of the at least one voltage pump of the memory device at the second instance.

10. The method of claim 9, further comprising determining whether to initiate a relocation operation based at least in part on the fault bit count of the plurality of memory blocks exceeding a fault bit count threshold.

11. A memory device, the memory device comprising: Controller; as well as A memory die failure prediction system, the memory die failure prediction system being communicatively coupled to the controller and operable to: Periodically determine the first performance characteristics of at least one voltage pump associated with the memory device; The first memory die failure anticipation operation is initiated at least in part based on the first performance characteristic matching the second performance characteristic of the at least one voltage pump associated with the memory device; as well as The second memory die failure prediction operation is initiated at least in part based on the difference between the first performance characteristic and the second performance characteristic.

12. The memory device of claim 11, wherein when the memory device has executed a threshold number of programming / erasing cycles, the memory die failure prediction system determines the first performance characteristic of the at least one voltage pump associated with the memory device.

13. The memory device of claim 11, wherein the first performance characteristic of the at least one voltage pump is the output voltage of the at least one voltage pump.

14. The memory device of claim 11, wherein the first performance characteristic of the at least one voltage pump is the pumping speed of the at least one voltage pump.

15. The memory device of claim 11, wherein the at least one voltage pump is associated with a plane of the memory die of the memory device.

16. The memory device of claim 11, wherein the at least one voltage pump is associated with a memory die of the memory device.

17. The memory device of claim 11, wherein the first memory die failure anticipated operation includes: Determine whether any of the multiple memory blocks associated with the at least one voltage pump have failed; Determine whether the number of available memory blocks in the memory device exceeds the available memory block threshold; as well as The following actions are performed, at least in part, based on the determination that multiple memory blocks associated with the at least one voltage pump have failed and that the number of available memory blocks in the memory device exceeds an available memory block threshold: Data from the memory blocks associated with the plurality of memory blocks having a faulty state is written to the available memory blocks in the memory device; Update the mapping table associated with the memory block; as well as The memory blocks associated with the plurality of memory blocks having the aforementioned fault state and the memory blocks having the aforementioned fault state are marked as growing bad blocks.

18. The memory device of claim 11, wherein the second memory die failure anticipation operation includes: Determine whether any of the multiple memory blocks associated with the at least one voltage pump have failed; The following operations are performed, at least in part, based on the determination that the plurality of memory blocks associated with the at least one voltage pump have failed: Determine the fault bit count associated with each of the plurality of memory blocks; Increase the voltage applied to each of the plurality of memory blocks; Determine whether the fault bit count associated with each of the plurality of memory blocks has increased; and At least a portion of the memory die associated with each of the plurality of memory blocks is marked as faulty.

19. A memory device, the memory device comprising: Components for determining the performance characteristics of at least one voltage supply device associated with the memory device; A component for comparing the performance characteristics of the at least one voltage supply device with a performance characteristic threshold; A component for determining whether a plurality of memory blocks associated with the voltage supply device have failed, wherein the component for determining whether the plurality of memory blocks associated with the voltage supply device have failed is based at least in part on the comparison of the performance characteristics of the at least one voltage supply device with the performance characteristic threshold. as well as The component for initiating the relocation operation, wherein the component for initiating the relocation operation is at least partially based on the component for determining whether a plurality of memory blocks associated with the voltage supply device have failed, thereby initiating the relocation operation.

20. The memory device of claim 19, further comprising means for marking a single memory block among the plurality of memory blocks as a growing bad block, wherein the means for marking the single memory block as a growing bad block is at least in part based on the means for determining whether the plurality of memory blocks associated with the voltage supply device have failed in order to mark the single memory block as a growing bad block.

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