Fault Injection Test Optimization Method and Apparatus Based on Test Vector Analysis
By using a test vector analysis method, effective fault test points of the circuit are identified and circuit test cases are optimized. This solves the problem of insufficient fault test point prediction in existing technologies and improves the efficiency and coverage of circuit testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING CORE THINKING TECH CO LTD
- Filing Date
- 2026-03-05
- Publication Date
- 2026-06-30
AI Technical Summary
Existing fault injection testing methods cannot effectively predict fault test points in circuit design, resulting in low testing efficiency and difficulty in further optimization.
By using a test vector analysis method, a set of test cases for the circuit is obtained, functional simulation is performed and trigger information is collected, and the information is marked on the circuit topology diagram. Observable cone search, logic suppression analysis and logic equivalence analysis are performed to determine effective fault test points. The results are summarized and analyzed to determine the target test case set with the largest coverage and the smallest number of test cases, and fault injection testing is performed.
It achieves in-depth optimization of circuit testing, reduces the amount of testing and time overhead, and improves the efficiency of fault injection testing.
Smart Images
Figure CN122309269A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit testing technology, specifically to a fault injection test optimization method and apparatus based on test vector analysis. Background Technology
[0002] Fault Injection Testing (FIT) in circuit design refers to the process of injecting failure modes into a circuit using simulation tools during the circuit design phase. This verifies whether the safety mechanisms can correctly detect functional errors caused by the faults and whether they can be executed correctly as expected. During FIT testing, tools typically employ an exhaustive approach, selecting all circuit nodes in the circuit under test that could affect the functional output ports as fault test points. These points are then subjected to fault injection simulation tests one by one to detect whether the injected faults affect the functional output results and whether the circuit's safety mechanisms detect the abnormal functional output and take appropriate action.
[0003] However, as circuit design scales continue to grow, the number of fault test points and the amount of simulation required for testing also increase rapidly, making test efficiency the primary bottleneck for Fit-In Testing (FIT). Furthermore, since a single test case typically covers only a limited number of functional modules and logical behaviors, FIT testing usually needs to be performed under many test cases to ensure the completeness of functional testing. This further increases the amount of simulation required for FIT testing.
[0004] In existing FIT testing, tools typically perform static topology analysis on the circuit under test to reduce the number of faulty test points and optimize the circuit, thereby reducing the test scale. This reduction and optimization of faulty test points is usually performed during the circuit establishment phase, before simulation testing begins. Optimizations such as logic suppression can only handle signals explicitly declared as constants, and cannot effectively predict real-time changes during simulation, making further optimization difficult. Summary of the Invention
[0005] In view of the above problems, this application proposes a fault injection test optimization method and apparatus based on test vector analysis to solve the following problems: existing fault test point reduction optimization methods cannot make effective predictions and are difficult to perform in-depth optimization.
[0006] According to one aspect of the embodiments of this application, a fault injection test optimization method based on test vector analysis is provided, including: Obtain the set of test cases for the circuit under test; For each test case in the test case set, functional simulation is performed based on the test case and the simulation data of the circuit under test, and trigger information generated after the fault injection time is collected during the functional simulation process; The trigger information is marked on the circuit topology diagram of the circuit under test. The marked circuit topology diagram is analyzed to determine the set of valid fault test points corresponding to the test case. The set of valid fault test points corresponding to each test case is summarized and analyzed. The test case set with the most fault test point coverage and the fewest test cases is determined from the test case set and used as the target test case set. Based on the target test cases in the target test case set and the set of valid fault test points corresponding to each target test case, fault injection testing is performed on the circuit under test.
[0007] Furthermore, before performing functional simulation based on the simulation data of the circuit under test for each test case in the test case set, the method further includes: Obtain the circuit design source file of the circuit under test, compile the circuit based on the circuit design source file, and generate simulation data and circuit topology diagram of the circuit under test.
[0008] Furthermore, the collection of triggering information generated after the fault injection moment during functional simulation further includes: The simulator initiates functional simulation and performs circuit initialization. After the circuit initialization is completed, starting from the fault injection moment, the circuit node information whose values have changed and the logic branch information that has been triggered to execute are recorded as trigger information.
[0009] Furthermore, the marked circuit topology is analyzed to determine the set of valid fault test points corresponding to this test case, which further includes: Observable cone search, logic suppression analysis and logic equivalence analysis are performed on the marked circuit topology to determine the fault test points covered by the test case; The fault test points covered by the test case are summarized to form a set of valid fault test points corresponding to the test case.
[0010] Furthermore, the set of valid fault test points corresponding to each test case is summarized and analyzed. From the test case set, the set of test cases with the largest number of fault test point coverage and the smallest number of test cases is determined, and this set is used as the target test case set, which further includes: Based on the set of valid fault test points corresponding to each test case, draw a coverage diagram of valid fault test points corresponding to each test case; Analyze the overlap between the effective fault test point coverage maps corresponding to each test case, and determine the test case set with the most fault test point coverage and the fewest test cases from the test case set; Use the set of test examples as the target test case set, and mark the duplicate fault test points among the target test cases in the target test case set.
[0011] Furthermore, based on the target test cases in the target test case set and the set of valid fault test points corresponding to each target test case, the fault injection test of the circuit under test further includes: The simulator performs fault injection testing on the fault test points in the set of valid fault test points corresponding to each target test case.
[0012] According to another aspect of the embodiments of this application, a fault injection test optimization apparatus based on test vector analysis is provided, comprising: The acquisition module is suitable for acquiring a set of test cases for the circuit under test; The functional simulation module is suitable for performing functional simulation for each test case in the test case set, based on the simulation data of the test case and the circuit under test, and collecting trigger information generated after the fault injection moment during the functional simulation process; The circuit topology analysis module is suitable for marking trigger information onto the circuit topology diagram of the circuit under test, analyzing the marked circuit topology diagram, and determining the set of valid fault test points corresponding to the test case. The set analysis module is suitable for summarizing and analyzing the set of valid fault test points corresponding to each test case, determining the set of test cases with the most fault test point coverage and the fewest test cases from the set of test cases, and using it as the target set of test cases. The testing module is suitable for performing fault injection testing on the circuit under test based on the target test cases in the target test case set and the set of valid fault test points corresponding to each target test case.
[0013] According to another aspect of the embodiments of this application, a computing device is provided, including: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; The memory is used to store at least one executable instruction, which causes the processor to perform the operation corresponding to the fault injection test optimization method based on test vector analysis described above.
[0014] According to another aspect of the embodiments of this application, a computer storage medium is provided, wherein at least one executable instruction is stored in the storage medium, the executable instruction causing a processor to perform the operation corresponding to the fault injection test optimization method based on test vector analysis described above.
[0015] According to another aspect of the embodiments of this application, a computer program product is provided, including at least one executable instruction, which causes a processor to perform operations corresponding to the fault injection test optimization method based on test vector analysis described above.
[0016] According to the technical solution provided in this application, test cases are systematically analyzed and statistically analyzed through functional simulation. Based on the specific behavior of each test case during the functional simulation process, the set of observable effective fault test points for that test case is determined. By comprehensively analyzing the set of effective fault test points corresponding to all test cases, the target test case set with the largest number of fault test point coverage and the smallest number of test cases can be accurately determined for use in fault injection testing. This solution can effectively cope with real-time changes during the simulation process, accurately achieve effective reduction and optimization of the test case set and the fault test points corresponding to each test case, obtain a deeper optimization effect, significantly reduce the amount of testing, reduce the test scale, greatly reduce the time cost required for fault injection testing, and improve the testing efficiency of fault injection testing.
[0017] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of the embodiments of this application are described below. Attached Figure Description
[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A flowchart illustrating a fault injection test optimization method based on test vector analysis according to an embodiment of this application is shown. Figure 2 A schematic diagram illustrating the principle of a fault injection test optimization method based on test vector analysis according to an embodiment of this application is shown. Figure 3 A schematic diagram of combinational logic is shown; Figure 4 A schematic diagram of a sequential logic is shown; Figure 5 A schematic diagram of the coverage of valid fault test points corresponding to multiple test cases is shown; Figure 6 A structural block diagram of a fault injection test optimization apparatus based on test vector analysis according to an embodiment of this application is shown; Figure 7 A schematic diagram of the structure of a computing device according to an embodiment of this application is shown. Detailed Implementation
[0019] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0020] Figure 1 A flowchart illustrating a fault injection test optimization method based on test vector analysis according to an embodiment of this application is shown, as follows: Figure 1 As shown, the method includes the following steps: Step S101: Obtain the test case set for the circuit under test.
[0021] Obtain a set of pre-written test cases for fault injection testing of the circuit under test. The test case set contains multiple test cases. Each test case includes information such as test case ID, test purpose description, type of fault injected, fault injection time, fault injection location, initial conditions, test steps, and failure mode.
[0022] In the testing phase of circuit design, to ensure comprehensive test coverage, many test cases are often required for the same circuit under test. However, each test case typically only covers a portion of the circuit's functionality and logic. For other modules or states not activated by test cases, fault injection testing often fails to trigger observable functional output differences. Therefore, this application conducts targeted analysis of individual test cases, thereby reducing and optimizing the test case set, which can significantly improve the efficiency of fault injection testing.
[0023] Step S102: For each test case in the test case set, perform functional simulation based on the test case and the simulation data of the circuit under test, and collect the trigger information generated after the fault injection time during the functional simulation process.
[0024] To facilitate fault injection testing and optimization, the circuit design source file of the circuit under test must be obtained before starting the functional simulation. The circuit is then compiled based on the circuit design source file to generate simulation data and circuit topology diagram of the circuit under test. Figure 2 A schematic diagram illustrating the principle of a fault injection test optimization method based on test vector analysis according to an embodiment of this application is shown, such as... Figure 2 As shown, the circuit design source file is obtained, read by the compiler, and the circuit is compiled to generate the simulation data required for simulation, as well as the circuit topology diagram. The circuit design source file refers to the editable project file generated by the circuit design software, containing design information such as the circuit schematic, PCB layout, component library, netlist, and design rules. The generated simulation data of the circuit under test refers to the data file required by the simulator during simulation, and is usually event-driven. The circuit topology diagram records the circuit connection relationships, specifically the point-to-point topological connections.
[0025] like Figure 2 As shown, the simulator reads the test cases from the test case set one by one. It also reads the simulation data and performs functional simulation based on the simulation data of each test case and the circuit under test. During the functional simulation, it collects trigger information generated from the moment of fault injection, such as signal change information and statement trigger information. After the functional simulation is completed, the simulator sends the collected trigger information to the fault analysis tool.
[0026] Specifically, the simulator initiates functional simulation and performs circuit initialization. After the circuit initialization is completed, starting from the fault injection moment, the circuit node information whose values have changed and the logic branch information that has been triggered to execute are recorded as trigger information.
[0027] The functional simulation process of the circuit under test (DUT) typically includes a circuit initialization phase, such as power-on, register initialization, and instruction set reading. Functional testing only begins after circuit initialization is complete. Therefore, fault injection usually occurs after circuit initialization. Trigger information collection also begins after circuit initialization, at the user-specified fault injection time.
[0028] During the simulation, when an event modifies the value of a circuit node, that is, when the value of the circuit node changes, it indicates that the test case will trigger a change in the signal value of this circuit node, and the information of that circuit node is recorded.
[0029] When a conditional branch of a sequential circuit is executed, it indicates that the test case will trigger the execution of this state branch; otherwise, it indicates that the test case does not cover this state branch. Record the information of the logic branches that are triggered.
[0030] Step S103: Mark the trigger information onto the circuit topology diagram of the circuit under test, analyze the marked circuit topology diagram, and determine the set of valid fault test points corresponding to the test case.
[0031] like Figure 2 As shown, the fault analysis tool reads the circuit topology diagram of the circuit under test and marks the circuit node information where the values sent by the simulator change and the triggered logic branch information, etc., onto the circuit topology diagram. By analyzing the marked circuit topology diagram, the circuit topology structure is optimized. For example, observable cone search, logic suppression analysis, and logic equivalence analysis are performed on the marked circuit topology diagram to determine the fault test points covered by the test case. Then, the fault test points covered by the test case are summarized to form the set of valid fault test points corresponding to the test case.
[0032] 1) Observable Cone Search: Starting from the functional output port, fault injection testing is only required for circuit nodes within its observable cone. Signals outside the observable cone will not affect the functional output port. 2) Logic Suppression Analysis: Due to the circuit's logic characteristics, some circuits are suppressed by other logic, preventing fault injection from propagating to the functional output port. 3) Logic Equivalence Analysis: Injecting faults into some circuit nodes has the same effect and does not require repeated testing.
[0033] Specifically, circuit nodes whose values do not change can be considered constants, and their values can be used for logic masking and equivalent optimization. Conditional or branch logic that has not been triggered can also be equivalently masked. Based on this information, the fault analysis tool performs topology analysis to obtain the circuit nodes that can be observed by the functional output ports, i.e., the fault test points that the test case can cover.
[0034] Figure 3 A schematic diagram of combinational logic is shown, such as... Figure 3As shown, "gand" represents an AND gate, and "gor" represents an OR gate. Taking the AND gate "gand" as an example, when the data at input port A is always 0 during functional simulation, the AND gate is closed. In this case, faults injected at input port B and earlier cannot propagate through the AND gate, and the relevant fault injection points are always suppressed. Furthermore, SA0 (Stuck-At-0, fixed at 0) type faults cannot be injected into input port A because the fault value and the normal value remain the same, and the functional output port cannot detect the difference. However, when the data at input port A is always 1 during functional simulation, the AND gate is open. In this case, faults injected at input ports B and D have the same effect on the functional output port, and the fault injection points are equivalent. Other types of combinational logic can achieve similar suppression, equivalence, or undetectable effects, which will not be elaborated here.
[0035] Figure 4 A schematic diagram of a sequential logic is shown, such as... Figure 4 As shown, for sequential circuits, each timing block can correspond to a state machine. The execution of the timing block reflects the transition relationships of the state machine. Figure 4 For example, if states B and D are not triggered during functional simulation, the control transition conditions will never be met, resulting in the related statements not being executed. Therefore, the inputs related to states B and D will always be suppressed. In this case, the relevant circuit nodes do not require fault injection testing.
[0036] Step S104: Summarize and analyze the set of valid fault test points corresponding to each test case, and determine the set of test cases with the most fault test point coverage and the fewest test cases from the set of test cases, and use it as the target test case set.
[0037] After completing the functional analysis of each test case, a set of valid fault test points for fault injection testing can be obtained for each test case. However, the sets of valid fault test points for different test cases may overlap. The fault analysis tool summarizes and analyzes the sets of valid fault test points for each test case, accurately identifying the test case set with the highest fault test point coverage and the lowest number of test cases. This test case set is then used as the final target test case set for fault injection testing, achieving optimization by reducing the test case set.
[0038] Specifically, based on the set of valid fault test points corresponding to each test case, a coverage diagram of valid fault test points for each test case is drawn. For example, during the drawing process, the fault test points in the set of valid fault test points corresponding to all test cases can be marked on a plan view first. Then, based on the set of valid fault test points corresponding to each test case, the coverage diagram of valid fault test points is drawn by delineating the fault test points included in the plan view.
[0039] Next, the overlap between the effective fault test point coverage maps corresponding to each test case is analyzed. The test case set with the most fault test point coverage and the fewest test cases is determined from the test case set. Then, this test case set is used as the target test case set, and the repeated fault test points between the target test cases in the target test case set are marked. This avoids repeated testing of repeated fault test points when performing fault injection testing based on the target test case set, further reducing the test scale.
[0040] Figure 5 This diagram illustrates the coverage of valid fault test points for multiple test cases. Taking a test case set including test case A to test case E as an example, the coverage of valid fault test points for test case A to test case E is shown below. Figure 5 As shown, the fault test points covered by test cases C and D are completely covered by other test cases. Therefore, test cases C and D do not need to be run separately for fault injection testing. The set of test cases with the largest number of fault test point coverages and the smallest number of test cases is the set formed by test cases A, B, and E. This set of test cases is taken as the target test case set, and test cases A, B, and E are called target test cases. Furthermore, it is possible to identify which fault test points are repeated among the fault test points covered by different target test cases. For example, for test case A, it is possible to identify which fault test points covered by test case A are repeated with test case B, and which are repeated with test case E.
[0041] Optionally, by summarizing and analyzing the set of valid fault test points corresponding to each test case, fault test points that cannot be covered by existing test cases can also be identified. For these fault test points, users can supplement and improve the test cases so that the fault injection test can cover all fault test points and achieve complete test coverage.
[0042] Step S105: Perform fault injection testing on the circuit under test based on the target test cases in the target test case set and the set of valid fault test points corresponding to each target test case.
[0043] After determining the target test case set, such as Figure 2 As shown, the target test case set and the set of valid fault test points corresponding to each target test case are stored in the fault injection test database. When fault injection testing needs to be initiated, the simulator performs fault injection testing only on the fault test points in the set of valid fault test points corresponding to each target test case, thereby completing the FIT test. During the testing process for this target test case, there is no need to test other fault test points that do not belong to its corresponding set of valid fault test points. This achieves both the reduction and optimization of the test case set and the reduction and optimization of the fault test points corresponding to each test case, significantly reducing the test scale. For duplicate fault test points covered by different target test cases, the user can select which target test case to test according to their needs, avoiding repeated testing of duplicate fault test points, further reducing the test scale. The test results of the fault injection test are stored in the fault injection test database for subsequent fault injection test analysis.
[0044] According to the fault injection test optimization method based on test vector analysis provided in this application, test cases are systematically analyzed and statistically analyzed through functional simulation. Based on the specific behavior of each test case during the functional simulation process, the set of observable effective fault test points for that test case is determined. By comprehensively analyzing the set of effective fault test points corresponding to all test cases, the target test case set with the largest number of fault test point coverage and the smallest number of test cases can be accurately determined for use in fault injection testing. This scheme can effectively cope with real-time changes during the simulation process, accurately realize the effective reduction and optimization of the test case set and the fault test points corresponding to each test case, obtain a deeper optimization effect, significantly reduce the amount of testing, reduce the test scale, greatly reduce the time cost required for fault injection testing, and improve the testing efficiency of fault injection testing.
[0045] Figure 6 A structural block diagram of a fault injection test optimization apparatus based on test vector analysis according to an embodiment of this application is shown, as follows: Figure 6 As shown, the device includes: an acquisition module 610, a functional simulation module 620, a circuit topology analysis module 630, a set analysis module 640, and a test module 650.
[0046] The acquisition module 610 is suitable for: acquiring a set of test cases for the circuit under test.
[0047] The functional simulation module 620 is suitable for: performing functional simulation for each test case in the test case set, based on the simulation data of the test case and the circuit under test, and collecting trigger information generated after the fault injection time during the functional simulation process.
[0048] The circuit topology analysis module 630 is suitable for: marking trigger information onto the circuit topology diagram of the circuit under test, analyzing the marked circuit topology diagram, and determining the set of valid fault test points corresponding to the test case.
[0049] The set analysis module 640 is suitable for: summarizing and analyzing the set of valid fault test points corresponding to each test case, determining the set of test cases with the largest number of fault test point coverage and the smallest number of test cases from the set of test cases, and using it as the target set of test cases.
[0050] Test module 650 is suitable for performing fault injection testing on the circuit under test based on the target test cases in the target test case set and the set of valid fault test points corresponding to each target test case.
[0051] Optionally, the acquisition module 610 is further adapted to: acquire the circuit design source file of the circuit under test, compile the circuit according to the circuit design source file, and generate simulation data and circuit topology diagram of the circuit under test.
[0052] Optionally, the functional simulation module 620 is further adapted to: initiate functional simulation by the simulator and perform circuit initialization processing; after the circuit initialization is completed, starting from the fault injection moment, record the circuit node information whose values have changed and the logic branch information that has been triggered as trigger information.
[0053] Optionally, the circuit topology analysis module 630 is further adapted to: perform observable cone search, logic suppression analysis, and logic equivalence analysis on the marked circuit topology diagram to determine the fault test points covered by the test case; and summarize the fault test points covered by the test case to form a set of valid fault test points corresponding to the test case.
[0054] Optionally, the set analysis module 640 is further adapted to: draw a valid fault test point coverage map for each test case based on the valid fault test point set corresponding to each test case; analyze the overlap between the valid fault test point coverage maps corresponding to each test case, and determine the test case set with the most fault test point coverage and the fewest test cases from the test case set; use the test case set as the target test case set, and mark the repeated fault test points between the target test cases in the target test case set.
[0055] Optionally, the test module 650 is further adapted to: perform fault injection testing on the fault test points in the set of valid fault test points corresponding to each target test case by the simulator.
[0056] The descriptions of the above modules refer to the corresponding descriptions in the method embodiments, and will not be repeated here.
[0057] According to the fault injection test optimization device based on test vector analysis provided in this application embodiment, test cases are systematically analyzed and statistically analyzed through functional simulation. Based on the specific behavior of each test case during the functional simulation process, the set of observable effective fault test points for that test case is determined. By comprehensively analyzing the set of effective fault test points corresponding to all test cases, the target test case set with the largest number of fault test point coverage and the smallest number of test cases can be accurately determined for use in fault injection testing. This scheme can effectively cope with real-time changes during the simulation process, accurately realize the effective reduction and optimization of the test case set and the fault test points corresponding to each test case, obtain a deeper optimization effect, significantly reduce the amount of testing, reduce the test scale, greatly reduce the time cost required for fault injection testing, and improve the testing efficiency of fault injection testing.
[0058] This application provides a non-volatile computer storage medium storing at least one executable instruction or computer program that enables a processor to perform the operation corresponding to the fault injection test optimization method based on test vector analysis in any of the above method embodiments.
[0059] This application provides a computer program product, which includes at least one executable instruction or computer program that enables a processor to perform the operation corresponding to the fault injection test optimization method based on test vector analysis in any of the above method embodiments.
[0060] Figure 7 The diagram shows a structural schematic of a computing device according to one embodiment of the present application. The specific embodiments of the present application do not limit the specific implementation of the computing device.
[0061] like Figure 7 As shown, the computing device may include: a processor 702, a communications interface 704, a memory 706, and a communications bus 708.
[0062] The processor 702, communication interface 704, and memory 706 communicate with each other via communication bus 708. Communication interface 704 is used to communicate with other network elements such as clients or other servers. Processor 702 executes program 710, specifically performing the relevant steps in the above-described embodiment of the fault injection test optimization method for computing devices based on test vector analysis.
[0063] Specifically, program 710 may include program code that includes computer operation instructions.
[0064] The processor 702 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The computing device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.
[0065] Memory 706 is used to store program 710. Memory 706 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.
[0066] Specifically, program 710 can be used to cause processor 702 to execute the fault injection test optimization method based on test vector analysis in any of the above method embodiments. The specific implementation of each step in program 710 can be found in the corresponding descriptions of the steps and units in the above-described fault injection test optimization embodiments based on test vector analysis, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.
[0067] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, the embodiments of this application are not directed to any particular programming language. It should be understood that the contents of the embodiments of this application described herein can be implemented using various programming languages, and the above description of specific languages is for the purpose of disclosing the best implementation of the embodiments of this application.
[0068] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0069] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various inventive aspects, in the foregoing description of exemplary embodiments of the present application, various features of the present application embodiments are sometimes grouped together into a single embodiment, figure, or description thereof. However, this approach to disclosure should not be construed as reflecting an intention that the claimed embodiments of the present application require more features than expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the present application.
[0070] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.
[0071] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are meant to be within the scope of the embodiments of this application and form different embodiments. For example, in the following claims, any one of the claimed embodiments can be used in any combination.
[0072] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components according to the embodiments of this application. The embodiments of this application can also be implemented as device or apparatus programs (e.g., computer programs and computer program products) for performing part or all of the methods described herein. Such programs implementing the embodiments of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.
[0073] It should be noted that the above embodiments are illustrative of the embodiments of this application and not limiting of the embodiments of this application, and those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Embodiments of this application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.
Claims
1. A fault injection test optimization method based on test vector analysis, characterized in that, include: Obtain the set of test cases for the circuit under test; For each test case in the test case set, functional simulation is performed based on the test case and the simulation data of the circuit under test, and trigger information generated after the fault injection time is collected during the functional simulation process; The trigger information is marked on the circuit topology diagram of the circuit under test, and the marked circuit topology diagram is analyzed to determine the set of valid fault test points corresponding to the test case. The effective fault test point set corresponding to each test case is summarized and analyzed. The test case set with the most fault test point coverage and the fewest test cases is determined from the test case set and used as the target test case set. Based on the target test cases in the target test case set and the set of valid fault test points corresponding to each target test case, the circuit under test is subjected to fault injection testing.
2. The method according to claim 1, characterized in that, Before performing functional simulation based on the test case and the simulation data of the circuit under test for each test case in the set of test cases, the method further includes: Obtain the circuit design source file of the circuit under test, compile the circuit based on the circuit design source file, and generate simulation data and circuit topology diagram of the circuit under test.
3. The method according to claim 1, characterized in that, The collection of trigger information generated after the fault injection moment during the functional simulation further includes: The simulator initiates functional simulation and performs circuit initialization. After the circuit initialization is completed, starting from the fault injection moment, the circuit node information whose values have changed and the logic branch information that has been triggered to execute are recorded as the trigger information.
4. The method according to claim 1, characterized in that, The step of analyzing the marked circuit topology to determine the set of valid fault test points corresponding to the test case further includes: Observable cone search, logic suppression analysis and logic equivalence analysis are performed on the marked circuit topology to determine the fault test points covered by the test case; The fault test points covered by the test case are summarized to form a set of valid fault test points corresponding to the test case.
5. The method according to claim 1, characterized in that, The process of summarizing and analyzing the set of valid fault test points corresponding to each test case, and determining the set of test cases with the largest number of fault test point coverage and the smallest number of test cases from the set of test cases, and using this set as the target test case set, further includes: Based on the set of valid fault test points corresponding to each test case, draw a coverage diagram of valid fault test points corresponding to each test case; Analyze the overlap between the effective fault test point coverage maps corresponding to each test case, and determine the test case set with the most fault test point coverage and the fewest test cases from the test case set. The set of test examples is used as the target test case set, and the repeated fault test points among the target test cases in the target test case set are marked.
6. The method according to any one of claims 1-5, characterized in that, The step of performing fault injection testing on the circuit under test based on the target test cases in the target test case set and the set of valid fault test points corresponding to each target test case further includes: The simulator performs fault injection testing on the fault test points in the set of valid fault test points corresponding to each target test case.
7. A fault injection test optimization device based on test vector analysis, characterized in that, include: The acquisition module is suitable for acquiring a set of test cases for the circuit under test; The functional simulation module is adapted to perform functional simulation for each test case in the test case set, based on the test case and the simulation data of the circuit under test, and to collect trigger information generated after the fault injection time during the functional simulation process. The circuit topology analysis module is adapted to mark the trigger information onto the circuit topology diagram of the circuit under test, analyze the marked circuit topology diagram, and determine the set of valid fault test points corresponding to the test case. The set analysis module is suitable for summarizing and analyzing the set of valid fault test points corresponding to each test case, determining the set of test cases with the largest number of fault test point coverage and the smallest number of test cases from the set of test cases, and using it as the target set of test cases. The testing module is adapted to perform fault injection testing on the circuit under test based on the target test cases in the target test case set and the set of valid fault test points corresponding to each target test case.
8. A computing device, comprising: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store at least one executable instruction, which causes the processor to perform the operation corresponding to the fault injection test optimization method based on test vector analysis as described in any one of claims 1-6.
9. A computer storage medium storing at least one executable instruction that causes a processor to perform an operation corresponding to the fault injection test optimization method based on test vector analysis as described in any one of claims 1-6.
10. A computer program product comprising at least one executable instruction that causes a processor to perform an operation corresponding to the fault injection test optimization method based on test vector analysis as described in any one of claims 1-6.