A memory address mapping method, a memory controller, a processor, and an electronic device.

Abstract

This application relates to a memory address mapping method, a memory controller, a processor, and an electronic device. The method includes: receiving a target physical address to be accessed and mapping the target physical address to a memory particle address; if a gap exists in the memory particle address, determining whether the bit value corresponding to a first address bit in the memory particle address is an arbitrary first target value; wherein the first address bit is the address bit that needs to be remapped synchronously when the bit value of the gap needs to be remapped; the first target value is the value that the first address bit is remapped to when the first address bit is synchronously remapped; if the gap is not found, remapping the bit value corresponding to at least one address bit in the memory particle address to ensure that the remapped memory particle address is a unique memory particle address. This method improves the versatility of memory address remapping in the presence of gaps.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, and in particular to a memory address mapping method, a memory controller, a processor, and an electronic device. Background Technology

[0002] The address translation module in the memory controller is generally used to translate physical addresses into memory chip addresses, where the memory chip address is the address of the smallest storage unit (cell) in the memory chip.

[0003] When gaps exist in memory chip addresses, address mapping needs to address how to effectively utilize memory space and avoid memory access failures due to address gaps. Current related technologies handle gaps in memory chip addresses by mapping the gap to the lower bits of the physical address, and then swapping the value of the gap with the highest bit when the gap value is invalid, thus remapping to ensure the swapped memory chip address remains unique and valid. While this approach is simple in design and universally applicable in address translation, it relies on the premise that the invalid value of the gap is a valid value for the highest bit. However, due to memory organization and address mapping relationships, not all memory meets this condition. Therefore, this method has a limited applicability. Summary of the Invention

[0004] Therefore, it is necessary to provide a memory address mapping method, a memory controller, a processor, and an electronic device to address the aforementioned technical problems.

[0005] Firstly, this application provides a memory address mapping method. The method includes:

[0006] Receive the target physical address to be accessed, and map the target physical address to a memory granular address;

[0007] If there is a gap in the memory chip address, determine whether the bit value corresponding to the first address bit in the memory chip address is any first target value; wherein, the first address bit is the address bit that needs to be remapped synchronously when the bit value of the gap bit needs to be remapped; the first target value is the value that the first address bit is remapped to when the first address bit is synchronously remapped.

[0008] When the condition is met, the bit value corresponding to at least one address bit in the memory particle address is remapped to ensure that the memory particle address after the remapping process is a unique memory particle address.

[0009] In one embodiment, the method further includes:

[0010] If the bit value of the first address is not any of the first target values, and the bit value of the hole corresponding to the memory particle address is an illegal value, the bit value of the hole is remapped to the second target value corresponding to the bit value of the first address, and the bit value of the first address is remapped to the first target value corresponding to the illegal value.

[0011] In one embodiment, the remapping process for the bit value corresponding to at least one address bit in the memory granule address includes:

[0012] The bit values ​​of the second address bit and the empty bit bit are swapped; wherein, after the memory particle address is initially mapped, if the bit value of the first address bit is any first target value, the maximum value of the second address bit is less than any second target value.

[0013] In one embodiment, the first address bit is the address bit where a third target value exists among all legal values. The third target value is a legal value that is greater than or equal to the target address value. The target address value is the maximum value of the memory particle address in the first address bit after the initial mapping. The first target value is selected from the third target value.

[0014] In one embodiment, the method further includes:

[0015] Determine whether the bit value of the corresponding hole in the memory particle address is greater than the preset maximum legal value of the hole;

[0016] If the bit value of the corresponding hole in the memory chip address is greater than the maximum valid value, the bit value of the corresponding hole in the memory chip address is determined to be an invalid value; or,

[0017] If the bit value of the corresponding empty bit in the memory particle address is less than or equal to the maximum valid value, the bit value of the corresponding empty bit in the memory particle address is determined to be a valid value.

[0018] In one embodiment, the method further includes:

[0019] If the bit value corresponding to the first address in the memory particle address is not any of the first target values, and the bit value corresponding to the empty bit in the memory particle address is a valid value, then memory is accessed based on the memory particle address.

[0020] In one embodiment, mapping the target physical address to a memory granular address includes:

[0021] According to the preset address mapping table, the target physical address is mapped to the memory particle address; wherein, the highest N bits of the target physical address in the address mapping table are mapped to the highest N bits of the row address, and N is an integer greater than or equal to 1.

[0022] Secondly, this application also provides a memory controller, including:

[0023] The address translation module is used to receive the target physical address to be accessed and map the target physical address to the memory particle address;

[0024] The address processing module is used to determine whether the bit value corresponding to the first address bit in the memory particle address is any first target value if there is a hole bit in the memory particle address; if yes, it performs remapping processing on the bit value corresponding to at least one address bit in the memory particle address to ensure that the memory particle address after remapping processing is a unique memory particle address.

[0025] Wherein, the first address bit is the address bit that needs to be remapped synchronously when the bit value of the hole bit needs to be remapped; the first target value is the value that the first address bit is remapped to when the first address bit is synchronously remapped.

[0026] In one embodiment, the address processing module is further configured to: remap the bit value of the empty bit to a second target value corresponding to the bit value of the first address bit, and remap the bit value of the first address bit to a first target value corresponding to the illegal value, when the bit value of the first address bit is not any first target value and the bit value of the empty bit corresponding to the memory particle address is an illegal value; or swap the bit value of the second address bit and the bit value of the empty bit when the bit value of the first address bit is any first target value; wherein, after the initial mapping of the memory particle address, when the bit value of the first address bit is any first target value, the maximum value of the second address bit is less than any second target value.

[0027] Thirdly, embodiments of this application also provide a processor, including: a memory management unit (MMU) and a memory controller as provided in any possible implementation of the second aspect embodiments and / or in combination with the second aspect embodiments, wherein the MMU and the memory controller are connected, and the MMU is configured to send memory access requests to the memory controller.

[0028] Fourthly, embodiments of this application also provide an electronic device, including: a memory and a processor as provided in the third aspect of the embodiments above, wherein the processor is connected to the memory.

[0029] In the aforementioned memory address mapping method, memory controller, processor, and electronic device, when a memory chip address gap exists, it is determined whether the bit value of the corresponding first address bit in the mapped memory chip address is the first target value. If so, the bit values ​​of certain address bits in the memory chip address are remapped to ensure that the remapped memory chip address is unique and does not overlap with any previous memory chip address. The first address bit is the address bit that needs to be synchronously remapped when the gap bit needs to be remapped due to an invalid value, to ensure the uniqueness of the remapped memory chip address. The first target value is the value that the first address bit is remapped to in this situation. Synchronously remapping the first address bit when a gap bit needs to be remapped ensures that the first address bit is not limited to the highest bit of the memory chip address. Furthermore, since the first target value can be any value, this method does not require that an invalid value of the gap bit be a valid value of the first address bit. However, since this remapping method may cause the remapped memory particle address to overlap with other memory particle addresses, when the first target value is obtained at the first address bit, it is also necessary to remap the memory particle address to ensure that the addresses of each memory particle and the addresses to which each memory particle address is remapped do not overlap. The embodiments of this application are applicable to memory using arbitrary address mapping tables and memory organization structures, thus improving the versatility of the memory address mapping method. Attached Figure Description

[0030] Figure 1 This is a flowchart illustrating a memory address mapping method in one embodiment;

[0031] Figure 2 This is a flowchart illustrating the memory address mapping method in another embodiment;

[0032] Figure 3 This is a block diagram of the memory controller in one embodiment;

[0033] Figure 4 This is a diagram of the internal structure of an electronic device in one embodiment. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0035] In one embodiment, such as Figure 1 As shown, a memory address mapping method is provided. This embodiment illustrates the application of this method to a memory controller, including the following steps:

[0036] S1, receive the target physical address to be accessed, and map the target physical address to the memory particle address.

[0037] When the Memory Management Unit (MMU) needs to access memory, it sends a memory access request to the memory controller. This request includes the target physical address (i.e., the memory address) to be accessed. Memory address mapping is the mapping between physical addresses and memory granular addresses.

[0038] In one implementation, the memory controller maps the target physical address to the memory chip address according to a preset address mapping table. Specifically, the highest N bits of the row address in the address mapping table are mapped to the highest N bits of the target physical address, where N is an integer greater than or equal to 1. A characteristic of the memory controller is that it must open a row before issuing any read or write command, and then read or write one of the columns of that row. Each array can only enable one row at a time. If subsequent access is to an already opened row, then read / write access can be performed directly according to the column address; if the address to be accessed is not in the currently opened row, the currently opened row must be closed, and then a new row must be opened before read / write access can be performed according to the column address. Frequently changing between different rows of the same array for access, and frequently opening / closing different rows, consumes a significant amount of time, resulting in bandwidth loss. Furthermore, the lower bits of the target physical address change more frequently than the higher bits. Therefore, mapping the higher bits of the target physical address to the row address can reduce the frequency of row address changes and improve read / write efficiency.

[0039] S2, if there is a hole in the memory chip address, determine whether the bit value of the corresponding first address bit in the memory chip address is any first target value; where the first address bit is the address bit that needs to be remapped synchronously when the bit value of the hole bit needs to be remapped; the first target value is the value that the first address bit is remapped to when the first address bit is synchronously remapped.

[0040] To better understand, before introducing the implementation principle of S2, we will first explain the principles of the empty bits and memory address mapping involved in this application, as well as the operations performed when the empty bit value is invalid.

[0041] A gap is a bit in a memory chip's address space that has restrictions; it cannot take any value, but only a partial value. Gaps in memory chip addresses are usually caused by the memory's storage capacity not being a power of 2, leading to non-contiguous address spaces, or address gaps.

[0042] Taking HBM3 (High Bandwidth Memory 3) memory as an example, the storage capacity of a single physical channel of HBM3 is 1.5GB, the number of banks (arrays) is 48, the number of rows is 16384, the number of columns is 32, the number of PCs (pseudo channels) is 2, and the access granularity is 32 bytes. 48 banks require 6 bits for addressing, but theoretically, 6 bits can address 64 banks. The range of bank_id (bank address) for 48 banks is only 6'b:000000~10 1111 (47). Among the 6 bits, B0, B1, B2, and B3 can take any value of 0 or 1. However, B5 and B4 can only take the values: 2'b00, 2'b01, and 2'b10 (valid values), and cannot take the value 2'b11 (illegal value). Therefore, B5 and B4 are empty bits.

[0043] If gaps in the memory chip address space are not handled, it may lead to incorrect memory access using the memory chip address. Ignoring the impact of gaps, for access efficiency, the optimal address mapping relationship is shown in Table 1. The shaded (or gray) parts represent gaps, address bits starting with C represent column addresses, address bits starting with R represent row addresses, and address bits starting with B represent array addresses. B5 and B4 are mapped to bits 9 and 8 of the physical address, respectively (this is just one example). When accessing a physical address such as 26'b10 0000 0000 0000 0011 0000 0000, since B5 and B4 have a value of 2'b11, which does not exist in the memory chip address space, the above physical address cannot be accessed normally and needs to be skipped, thus causing the problem of discontinuous physical addresses.

[0044] Table 1

[0045]

[0046] Continuing with the example of a single physical channel in HBM3 with a storage capacity of 1.5GB and 48 arrays, the physical address range is: 0~26'b10 1111 1111 1111 1111 1111 1111 1111. From the physical address range, it can be seen that the highest two bits of the physical address can be at most 2'b10, which matches the valid values ​​of B5 and B4. This is because in the above example, in HBM3, except for the number of arrays, the number of rows, columns, PCs, and access granularity are all powers of 2. Therefore, the storage capacity of a single physical channel can be written as the number of arrays × 2. n The corresponding physical addressing range is 0 to (number of arrays × 2). nConverting the array size to binary (i.e., subtracting 1 from the binary representation of the array size, shifting it left by n bits, and filling the lowest n bits with 1s) gives the range of array address values. Therefore, the highest N bits of the physical address (where N represents the binary length of the array address) will not exceed this range. When an array address is invalid, swapping the invalid value with the corresponding bit in the highest N bits resolves the issue. Furthermore, since the highest N bits are mapped to the row address, which has no invalid values, swapping the invalid array address with the highest N bits allows for correct memory access.

[0047] However, other memory types do not always satisfy the condition that the illegal value of a hole bit is the legal value of the highest bit. For example, in HBM3E (High Bandwidth Memory 3 Enhanced) memory, the number of rows may not be a power of 2. HBM3E memory can have 24576 rows, the maximum legal row address is 15b'101 11111111 1111, and the physical address range is 0~27'b100 0111 1111 1111 1111 1111 1111. Considering optimal access efficiency, a possible address mapping relationship is shown in Table 2:

[0048] Table 2

[0049]

[0050] It is evident that when R14 and R13 are mapped to the highest two bits, since R14 and R13 are also illegal values ​​when they are 2'b11, swapping B5 and B4 with the highest two bits when B5 and B4 are 2'b11 still results in the problem of memory particle addresses not being able to access memory correctly.

[0051] The following section first explains the operations performed when a hole bit has an invalid value, to illustrate the necessity of executing S2 and S3. In this application, a hole bit is a set of consecutive address bits with restricted values. For example, using the aforementioned HBM3 memory example, the hole bits are B5 and B4. It should be noted that in this example, the hole bits can actually be any consecutive address bit containing B5 and B4, such as B5, B4, and B3 (B5, B4, and B3 cannot be 3b'111, which also satisfies the condition of being consecutive and having restricted values). However, the fewer the number of address bits corresponding to the hole bit, the simpler the remapping relationship. Therefore, the hole bit can be determined based on the principle of minimizing the number of address bits corresponding to the hole bit.

[0052] In one possible implementation, after receiving a memory access request, the memory controller can determine whether there are empty bits in the memory chip address by obtaining the configuration in the register group.

[0053] Before determining whether the bit value of the corresponding hole in the memory chip address is invalid, it is necessary to first obtain the bit value of the corresponding hole in the memory chip address. In one possible implementation, the process of obtaining the bit value of the corresponding hole in the memory chip address may include: obtaining the address bit of the corresponding hole in the memory chip address based on the mapping distribution of hole bits on the memory chip address in the address mapping table; obtaining the bit value corresponding to the address bit of the hole in the memory chip address, thereby obtaining the bit value of the corresponding hole in the memory chip address (hereinafter referred to as the bit value of the hole).

[0054] Taking the target physical address as 27'b100 0111 1111 1111 1111 1111 1111 as an example, after mapping the target physical address to the memory chip address based on the address mapping table shown in Table 2, it can be seen from the mapping distribution of the hole bits on the memory chip address that the hole bits B5 and B4 are located at bit 9 and bit 8, respectively. Therefore, the bit values ​​corresponding to the hole bits B5 and B4 are 1 and 1, respectively.

[0055] In one implementation, determining whether the bit value of a corresponding hole in a memory chip address is invalid can include: determining whether the bit value of the corresponding hole in the memory chip address is greater than a preset maximum valid value for a hole; if the bit value of the corresponding hole in the memory chip address is greater than the maximum valid value, determining that the bit value of the corresponding hole in the memory chip address is invalid; or if the bit value of the corresponding hole in the memory chip address is less than or equal to the maximum valid value, determining that the bit value of the corresponding hole in the memory chip address is valid. Generally, memory organization unit address codes are continuous, therefore there exists a range of valid values ​​from 0 to the maximum valid value. Values ​​exceeding the maximum valid value are invalid. Therefore, the above method can be used to determine whether the bit value of the corresponding hole in the memory chip address is invalid.

[0056] The first address bit corresponding to a hole is one or more address bits that are not holes, and the first address bit does not have to be contiguous. The first address bit can be other holes. For example, taking the HBM3E memory example mentioned above, the first address bits corresponding to B5 and B4 can be hole bits R14 and R13, or any other address bit that is not a hole (such as R12 and R11).

[0057] It should be noted that, for non-contiguous address bits, the "value" refers to the binary value formed by arranging the bits in descending order of their values. For example, if the first address bits are R14 and R12, where R14 has a bit value of 1 and R12 has a bit value of 0, then the value of the first address bit is 2b'10. The meaning of "value" when referring to the second non-contiguous address bit later in the text is the same as here, and will not be repeated.

[0058] When an invalid value is found in a gap, this application remaps the value of the gap to a valid value and simultaneously remaps the value of the first address bit to the first target value, thereby ensuring that the memory chip address is unique after remapping. The reason for simultaneously remapping the first address bit is that if only the value of the gap is remapped, the memory chip address will obviously overlap with the memory chip address when the gap has a valid value.

[0059] The first target value is a valid value for the first address bit. There can be a one-to-one correspondence between the first target value and invalid values. The first target value can also be a value outside the possible range of the initial memory address mapping. The initial mapping refers to the mapping from the target physical address to the memory address; subsequent modifications to the bit values ​​corresponding to the memory address bits are called remapping. The possible range of values ​​for the initial mapping is also the possible range of values ​​for the target physical address.

[0060] In one implementation, the first address bit is the address bit among all legal values ​​where a third target value exists. The third target value is a legal value greater than or equal to the target address value, and the target address value is the maximum value of the memory particle address in the first address bit after the initial mapping. The first target value is selected from the third target value. By setting the first target value in this way, the probability that the bit value of the first address bit corresponding to the memory particle address is the first target value can be reduced. For example, taking the first address bits in the aforementioned HBM3 memory as R13 and R12, and R13 and R12 having no illegal values, the highest two bits of the target physical address can be 2'b01, 2'b00, and 2'b10. Then, the maximum value of the memory particle address in the first address bit after the initial mapping is 2'b10. Therefore, the third target value is 2'b10 and 2'b11, and the first target value can be selected from these two legal values. When 2'b11 is used as the first target value, since the highest two bits of the memory particle address will not be 2'b11 after the initial mapping, there will not even be a situation where the bit value corresponding to the first address bit in the memory particle address is taken as the first target value, so S3 does not need to be executed.

[0061] However, if there is no first target value outside the range of values ​​after the initial mapping of the memory particle address, the problem of overlapping memory particle addresses will occur if the first address bit takes the first target value. In this case, S2 is needed to determine whether to execute S3 to avoid this situation. When the memory particle address meets the condition of S2, it means that the memory particle address may overlap with the previously remapped memory particle address. In this case, S3 is executed to remap the memory particle address as well to avoid address overlap.

[0062] The implementation principle of S2 will be explained below.

[0063] After receiving a memory access request, if there is a gap in the memory chip address, the memory controller determines whether the bit value of the corresponding first address bit in the memory chip address is any first target value. Here, the first address bit is the address bit that needs to be remapped synchronously when the bit value of the gap bit needs to be remapped. The first target value is the value that the first address bit is remapped to when the first address bit is synchronously remapped.

[0064] In one possible implementation, after receiving a memory access request, the memory controller can obtain the configuration in the register group to find out the first address bit corresponding to the hole bit in the memory chip address.

[0065] If the memory controller determines that there is a gap in the memory chip address, it then determines whether the bit value corresponding to the first address bit in the memory chip address is any first target value. In one possible implementation, after receiving a memory access request, the memory controller can obtain the configuration in the register group to know the bit position of the first address bit and the first target value corresponding to the first address bit. The memory controller then compares whether the bit value of the first address bit position and the first target value are consistent.

[0066] If the bit value corresponding to the first address in the memory chip address is not the first target value, the memory controller determines whether the value of the empty bit is illegal using the method described above. If the value of the empty bit is illegal, the controller performs the aforementioned operation of remapping the value of the empty bit to a legal value and simultaneously remapping the value of the first address bit to the first target value.

[0067] In one implementation, if the bit value corresponding to the first address bit in the memory particle address is not an arbitrary first target value, and the bit value corresponding to the hole bit in the memory particle address is a valid value, the memory controller directly accesses the memory based on the memory particle address.

[0068] If the bit value corresponding to the first address in the memory chip is the first target value, then execute S3.

[0069] S3, remap the bit value corresponding to at least one address bit in the memory particle address to ensure that the memory particle address after remapping is a unique memory particle address.

[0070] The memory controller can select any address bit value for remapping, as long as the remapped memory chip address cannot overlap with any memory chip address to which the memory controller previously mapped the target physical address.

[0071] In one possible implementation, the address bit to be remapped can be any address bit other than the first address bit. The reason for not remapping the first address bit is to ensure that the memory particle address has been remapped only when the first address bit takes the first target value, and therefore has the potential to overlap with other memory particle addresses. This facilitates setting the judgment conditions involved in S2 in practical applications.

[0072] It should be noted that this is also why a fixed first address bit and hole bit need to be remapped together: if the address bit and hole bit are randomly selected for remapping when remapping the hole bit, it becomes difficult to determine which addresses might overlap. In the application, a large amount of storage space needs to be reserved to store the address to which the memory chip address is remapped when the hole bit value is invalid. Furthermore, every time the memory chip address is obtained, it is necessary to compare whether the address matches the remapped address to determine whether the memory chip address needs to be remapped. The memory address mapping efficiency is very low.

[0073] Since target physical addresses are generally continuous, meaning that the target physical addresses received sequentially by the memory controller usually follow an increasing or decreasing pattern, it is possible to configure the memory controller to set the value of any target address bit to 1 when the value of the first address bit corresponding to the memory chip address is the first value after the initial mapping, in the case of increasing target physical addresses. The bit corresponding to the target address bit in the target physical address is located in a higher bit of the target bit, and the target bit is the highest bit currently set to 1 in the target physical address.

[0074] When the target physical address is decremented, the memory controller sets the value of any target address bit to 0. The bit corresponding to the target address in the target physical address is located in a higher bit position within the target bit set, and the target bit is the least significant bit among the bits that are consecutively set to 1 starting from the most significant bit in the target physical address. This ensures that after executing S3, the remapped memory chip address will not overlap with the previous memory chip address. Since ensuring that the remapped memory chip address does not overlap with the previous memory chip address during each remapping process effectively guarantees the uniqueness of the memory chip address.

[0075] Those skilled in the art may also employ other strategies to execute S3 as appropriate to ensure that the memory particle address after remapping is a unique memory particle address. This application does not limit this approach.

[0076] The implementation of S3 can also be related to how the memory controller handles situations where the bit value of a void bit is invalid. See one implementation method... Figure 2 As shown, when the bit value of the corresponding hole in the memory chip address is an illegal value and the bit value of the first address bit is not the first target value, the memory controller obtains the first address bit corresponding to the hole bit, remaps the bit value of the hole bit to the second target value corresponding to the bit value of the first address bit, and remaps the bit value of the first address bit to the first target value corresponding to the illegal value.

[0077] The second target value is a valid value for the empty bit. The correspondence between the bit values ​​of the first address bit and the second target value, as well as the correspondence between the bit values ​​of the first address bit and the first target value, can be set by those skilled in the art.

[0078] In one possible implementation, after obtaining the first address bit, the memory controller can also obtain the bit value corresponding to the first address bit in the memory chip address, and obtain the configuration in the register group to obtain the second target value corresponding to the bit value of the first address bit, and the first target value corresponding to the illegal value.

[0079] In one implementation, the second target value and the first target value satisfy the following conditions: the second target value corresponding to different bit values ​​of the first address is different, and the first target value corresponding to different illegal values ​​is different, so as to avoid different memory particle addresses being remapped to the same address, which would require additional processing for this situation. Taking the aforementioned HBM3E memory example, if the hole bits are B5 and B4 and the value 2'b11 is illegal, and the first address bits are R14 and R13 and the value 2'b11 is illegal, the bit values ​​of the first address bits and the second target value, as well as the correspondence between illegal values ​​and the first target value, can be set as follows: when R14 and R13 are 2'b00, the second target value is 2'b01; when R14 and R13 are 2'b01, the second target value is 2'b10; when the illegal value is 2'b11, the first target value is 2'b10. Whether R14, R13, B5, and B4 need to be remapped under some possible values ​​is shown in Table 3. The grayed-out rows in the table are the cases where remapping is required:

[0080] Table 3

[0081]

[0082] If the aforementioned conditions are violated, for example, by modifying the correspondence between the bit values ​​of the first address and the second target value so that the second target value is 2'b01 regardless of the values ​​of R14 and R13, then the grayed-out rows in the aforementioned table will be remapped to: R14 and R13 taking the value 2'b10, and B5 and B4 taking the value 2'b01, resulting in address duplication. To solve this problem, further remapping is required. For example, after remapping the bit values ​​of the empty bits to the second target value corresponding to the bit values ​​of the first address, and remapping the bit values ​​of the first address to the first target value corresponding to the illegal value, the bit values ​​of another address bit are then remapped to the third target value corresponding to the bit values ​​of the first address and the illegal value. In practical applications, this would be more complex to implement.

[0083] When using this illegal value handling method, in one implementation, S3 includes:

[0084] The bit values ​​of the second address bit and the empty bit bit are swapped; where, after the memory particle address is initially mapped, if the bit value of the first address bit is any first target value, the maximum value of the second address bit is less than any second target value.

[0085] If the bit value corresponding to the first address in the memory chip address is the first target value, then there may be a problem that this memory chip address has been occupied by the memory chip address after remapping during the illegal value processing. Taking the example corresponding to Table 3 above, based on the remapping strategy in Table 3, assuming that the second target value corresponding to R14 and R13 taking the value 2b'10 is 2b'00, then whether R14 and R13 need to be remapped under all possible values, and the remapping results after remapping, are shown in Table 4:

[0086] Table 4

[0087]

[0088] As can be seen, the bolded rows in the table have duplicate addresses.

[0089] To solve this problem, the bit values ​​of the second address bit and the hole bit are swapped. The goal is to ensure that in the resulting memory chip address, the hole bit value will not be any of the second target values ​​corresponding to the first target value. It's important to further clarify that if the hole bit takes an invalid value, the first address bit will be remapped to the first target value. However, because different bit values ​​of the first address bit correspond to different second target values, a situation may arise where one first target value corresponds to multiple second target values.

[0090] To achieve this goal, the address bit whose maximum value is less than any second target value needs to be selected as the second address bit, provided that the bit value of the first address bit in the initially mapped memory particle is the first target value. The second address bit has the same number of bits as the hole bit, but the second address bit does not have to be a consecutive address bit. The reason for this condition is that if the maximum value of the second address bit can be less than any second target value, then the second address bit cannot take the second target value under any circumstances. Also, because of the consecutive address encoding mentioned earlier, the illegal value of the hole bit is greater than all legal values, so the second address bit cannot take the illegal value of the hole bit either. After swapping the bit values ​​of the second address bit and the hole bit, the bit value of the hole bit cannot take either any of the second target values ​​corresponding to the first target value, nor can it take an illegal value. Therefore, when performing address remapping, the bit values ​​of the second address bit and the hole bit can be directly swapped without considering whether the address will be duplicated or illegal after the swap, making the implementation simpler in applications.

[0091] The existence of such a second address bit can be achieved by setting the second target value, the first address bit, and the first target value. For example, the smallest legal value among all legal values ​​of the empty space can be reserved as the target bit value for the second address bit, and then legal values ​​greater than the target bit value can be used as the second target value. Then, address bits whose number of legal values ​​is greater than or equal to the number of second target values ​​can be selected as the first address bits. From these legal values, the first target value can be selected, and it can be determined whether a second address bit with a maximum value equal to the target bit value exists when the bit value of the corresponding first address bit in the initially mapped memory particle address is the first target value. If it does not exist, at least one of the following strategies—changing the target bit value, changing the first address bit, or changing the first target value—can be adopted until the second address bit exists.

[0092] Let's continue with the HBM3E memory example. Since the HBM3E array has 48 bits, the illegal value for B5 and B4 is 2'b11, and the legal values ​​are 2'b00, 2'b01, and 2'b10. We can first reserve the smallest legal value, 2'b00, as the target bit value for the second address, and use 2'b01 and 2'b10 as the second target values. R14 and R13 can be used as the first address bits, and R12 and R11 as the second address bits. It can be noted that the maximum value of the target physical address of HBM3E is 27'b1000111 1111 1111 1111 1111 1111. If R14 and R13 are used as the first address bits and 2'b10 is used as the first target value, then R12 and R11 can only take a maximum of 2'b00 when the bit value of the first address bit corresponding to the memory particle address in the initial mapping is the first target value. This exactly matches the target bit value reserved for the second address bit.

[0093] Furthermore, the correspondence between the values ​​of the first address bit and the second target value can be set. For example, the first address bit can be set to 2'b00, corresponding to the second target value 2'b01, and the first address bit can be set to 2'b01, corresponding to the second target value 2'b10. It should be noted that 2'b00 can also correspond to 2'b10, and 2'b01 can also correspond to 2'b01, as long as the values ​​of the first address bit and the second target value can correspond one-to-one.

[0094] After writing all the information into the memory controller's registers—that B5 and B4 are empty bits, the corresponding first address bits R14 and R13 and second address bits R12 and R11, the illegal value judgment conditions for B5 and B4, the second target values ​​for B5 and B4, the correspondence between the second target values ​​and the values ​​of the first address bits, and the correspondence between illegal values ​​and the first target values—the memory controller can then perform memory address mapping according to the aforementioned S1 to S3 in practical applications. Whether the memory controller needs to perform address remapping / swapping for each possible value of R14~R11 and B5 and B4 can be found in Table 5, where "*" represents 0 or 1.

[0095] Table 5

[0096]

[0097] As can be seen from Table 5, there are no duplicate addresses, which solves the problem of possible address duplication after remapping memory particle addresses when the value of the empty bit is illegal.

[0098] After obtaining the memory granule address after remapping, memory can be accessed based on the memory granule address.

[0099] The memory address mapping method provided in this application determines whether the bit value of the corresponding first address bit in the mapped memory particle address is a first target value when a memory particle address gap exists. If so, the bit values ​​of certain address bits in the memory particle address are remapped to ensure that the remapped memory particle address is unique and does not overlap with any previous memory particle address. The first address bit is the address bit that needs to be remapped synchronously when the gap bit is invalid and needs to be remapped to ensure the uniqueness of the remapped memory particle address. The first target value is the value that the first address bit is remapped to in this situation. Synchronously remapping the first address bit when a gap bit needs to be remapped ensures that the first address bit is not limited to the highest bit of the memory particle address. Furthermore, since the first target value can be any value, this method does not require that an invalid value of the gap bit be a valid value of the first address bit. However, since this remapping method may cause the remapped memory particle address to overlap with other memory particle addresses, when the first target value is obtained at the first address bit, it is also necessary to remap the memory particle address to ensure that the addresses of each memory particle and the addresses to which each memory particle address is remapped do not overlap. The embodiments of this application are applicable to memory using arbitrary address mapping tables and memory organization structures, thus improving the versatility of the memory address mapping method.

[0100] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0101] This application also provides a memory controller (MC) in its embodiments, which will be described below in conjunction with... Figure 3 The memory controller provided in the embodiments of this application will be described. The memory controller includes an address processing module and an address translation module, and the address translation module is connected to the address processing module. Figure 1 In the memory address mapping method shown, S1 can be implemented by the address translation module, and S2 to S3 can be implemented by the address processing module.

[0102] The address translation module is used to receive the target physical address to be accessed and map the target physical address to a memory particle address.

[0103] The address processing module is used to determine whether the bit value corresponding to the first address bit in the memory particle address is any first target value if there is a hole bit in the memory particle address; if yes, it performs remapping processing on the bit value corresponding to at least one address bit in the memory particle address to ensure that the memory particle address after remapping processing is a unique memory particle address.

[0104] Wherein, the first address bit is the address bit that needs to be remapped synchronously when the bit value of the hole bit needs to be remapped; the first target value is the value that the first address bit is remapped to when the first address bit is synchronously remapped.

[0105] The address translation module has a pre-defined address mapping table, such as a register set, to store the address mapping table. During address translation, the address must be translated according to the address mapping table.

[0106] In one implementation, the address processing module is further configured to: remap the bit value of the empty bit to a second target value corresponding to the bit value of the first address bit, and remap the bit value of the first address bit to a first target value corresponding to the illegal value, when the bit value of the first address bit is not any first target value and the bit value of the empty bit corresponding to the memory particle address is an illegal value; or swap the bit value of the second address bit and the bit value of the empty bit when the bit value of the first address bit is any first target value; wherein, after the initial mapping of the memory particle address, when the bit value of the first address bit is any first target value, the maximum value of the second address bit is less than any second target value.

[0107] In one implementation, the address processing module is further configured to access memory based on the memory particle address when the bit value corresponding to the first address bit in the memory particle address is not any of the first target values ​​and the bit value corresponding to the hole bit in the memory particle address is a valid value.

[0108] The address processing module can include two functions: configuration of empty bits, first address bits, and second address bits, and processing of empty bits, first address bits, and second address bits. In one implementation, for example, the address processing module includes a register group and an address processing unit. The configuration of the register group is used to implement the related functions of configuring empty bits, first address bits, and second address bits, and the address processing unit is used to implement the functions of processing empty bits, first address bits, and second address bits.

[0109] The register group is used to store the mapping distribution of the empty bits, the first address bit, and the second address bit in the address mapping table on the memory particle address, as well as the preset maximum legal value of the empty bit, the correspondence between the illegal value of the empty bit and the first target value, and the correspondence between the value of the first address bit and the second target value.

[0110] The address processing unit is used to obtain the bit value of the corresponding first address bit in the memory particle address according to the mapping distribution of the first address bit in the address mapping table stored in the register group on the physical address; and to determine whether the bit value of the corresponding first address bit in the memory particle address is any first target value according to the bit value of the first address bit and the first target value stored in the register group.

[0111] In one implementation, the address processing unit is further configured to: obtain the bit value of the corresponding empty bit in the memory particle address based on the mapping distribution of empty bits in the address mapping table stored in the register group on the physical address; and determine that the bit value of the corresponding empty bit in the memory particle address is an illegal value if the bit value of the corresponding empty bit in the memory particle address is greater than the maximum legal value; or determine that the bit value of the corresponding empty bit in the memory particle address is a legal value if the bit value of the corresponding empty bit in the memory particle address is less than or equal to the maximum legal value.

[0112] In one implementation, the address translation module is further configured to map the target physical address to a memory granular address according to a preset address mapping table; wherein, the highest N bits of the target physical address in the address mapping table are mapped to the highest N bits of the row address, and N is an integer greater than or equal to 1.

[0113] The address processing unit described above can be implemented using logic circuits or programmable devices.

[0114] The implementation principle and technical effects of the memory controller embodiment are the same as those of the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the memory controller embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0115] This application also provides a processor, which includes a memory management unit (MMU) and the aforementioned memory controller. The MMU and the memory controller are connected, and the MMU accesses memory through the memory controller. For example, the MMU can send a memory access request to the memory controller to access the memory. The processor can be various general-purpose processors, embedded processors, system-on-a-chip (SoC) mobile device processors, server processors, etc.

[0116] In one implementation, the processor can be a general-purpose processor including a central processing unit (CPU), network processor (NP), graphics processing unit (GPU), accelerated processing unit (AP), multimedia application processor (MAP), microprocessor, etc.; it can also be a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Alternatively, the processor can be any conventional processor.

[0117] This application also provides an electronic device, which includes the aforementioned processor and memory. The memory includes, but is not limited to, DRAM memory and HBM memory. Furthermore, the memory can be replaced with other storage devices. The electronic device provided in this application includes, but is not limited to, mobile phones, tablets, laptops, computers, servers, and other devices.

[0118] In one implementation, the structural block diagram of the electronic device can be as follows: Figure 4 As shown, the device includes a transceiver, a memory, a communication bus, and a processor. The transceiver, memory, and processor are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected via one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory is used to store data, which may include computer programs. These computer programs may include at least one software functional module that can be stored in the memory as software or firmware or embedded in the operating system (OS) of the electronic device. The processor is used to execute the software functional modules or computer programs stored in the memory. For example, the processor is used to execute the memory address mapping method described above.

[0119] The memory may be, but is not limited to, Random Access Memory (RAM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0120] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A memory address mapping method, characterized in that, The method includes: Receive the target physical address to be accessed, and map the target physical address to a memory granular address; If there is a gap in the memory chip address, determine whether the bit value corresponding to the first address bit in the memory chip address is any first target value; wherein, the first address bit is the address bit that needs to be remapped synchronously when the bit value of the gap bit needs to be remapped; the first target value is the value that the first address bit is remapped to when the first address bit is synchronously remapped. When the condition is met, the bit value corresponding to at least one address bit in the memory particle address is remapped to ensure that the memory particle address after the remapping process is a unique memory particle address.

2. The method according to claim 1, characterized in that, The method further includes: If the bit value of the first address is not any of the first target values, and the bit value of the hole corresponding to the memory particle address is an illegal value, the bit value of the hole is remapped to the second target value corresponding to the bit value of the first address, and the bit value of the first address is remapped to the first target value corresponding to the illegal value.

3. The method according to claim 2, characterized in that, The remapping process for the bit value corresponding to at least one address bit in the memory granule address includes: The bit values ​​of the second address bit and the empty bit bit are swapped; wherein, after the memory particle address is initially mapped, if the bit value of the first address bit is any first target value, the maximum value of the second address bit is less than any second target value.

4. The method according to any one of claims 1 to 3, characterized in that, The first address is the address where a third target value exists among all legal values. The third target value is a legal value that is greater than or equal to the target address value. The target address value is the maximum value of the memory particle address in the first address after the initial mapping. The first target value is selected from the third target value.

5. The method according to claim 2, characterized in that, The method further includes: Determine whether the bit value of the corresponding hole in the memory particle address is greater than the preset maximum legal value of the hole; If the bit value of the corresponding hole in the memory chip address is greater than the maximum valid value, the bit value of the corresponding hole in the memory chip address is determined to be an invalid value; or, If the bit value of the corresponding empty bit in the memory particle address is less than or equal to the maximum valid value, the bit value of the corresponding empty bit in the memory particle address is determined to be a valid value.

6. The method according to claim 5, characterized in that, The method further includes: If the bit value corresponding to the first address in the memory particle address is not any of the first target values, and the bit value corresponding to the empty bit in the memory particle address is a valid value, then memory is accessed based on the memory particle address.

7. The method according to claim 1, characterized in that, The step of mapping the target physical address to memory granular addresses includes: According to the preset address mapping table, the target physical address is mapped to the memory particle address; wherein, the highest N bits of the target physical address in the address mapping table are mapped to the highest N bits of the row address, and N is an integer greater than or equal to 1.

8. A memory controller, characterized in that, include: The address translation module is used to receive the target physical address to be accessed and map the target physical address to the memory particle address; The address processing module is used to determine whether the bit value corresponding to the first address bit in the memory particle address is any first target value if there is a hole bit in the memory particle address; if yes, it performs remapping processing on the bit value corresponding to at least one address bit in the memory particle address to ensure that the memory particle address after remapping processing is a unique memory particle address. Wherein, the first address bit is the address bit that needs to be remapped synchronously when the bit value of the hole bit needs to be remapped; the first target value is the value that the first address bit is remapped to when the first address bit is synchronously remapped.

9. The memory controller according to claim 8, characterized in that, The address processing module is further configured to, when the bit value of the first address bit is not any of the first target values ​​and the bit value corresponding to the hole bit in the memory particle address is an illegal value, remap the bit value of the hole bit to a second target value corresponding to the bit value of the first address bit, and remap the bit value of the first address bit to a first target value corresponding to the illegal value; or when the bit value of the first address bit is any of the first target values, swap the bit value of the second address bit and the bit value of the hole bit; wherein, after the initial mapping of the memory particle address, when the bit value corresponding to the first address bit is any of the first target values, the maximum value of the second address bit is less than any of the second target values.

10. A processor, characterized in that, include: The memory management unit (MMU) and the memory controller as described in claim 8 or 9 are connected. The MMU is used to send memory access requests to the memory controller.

11. An electronic device, characterized in that, include: The memory and the processor as described in claim 10, wherein the processor is connected to the memory.

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