A motherboard burning control method, device and system

Abstract

This invention relates to the field of motherboard programming, and in particular to a motherboard programming control method, device, and system. The method includes, during the programming process, controlling the level changes of the cache state machine and the block addressing state machine to determine whether the two state machines will simultaneously be in a metastable state during state updates. If so, a micropulse is generated and inserted into the oscillation half-cycle, so that the time when the two state machines are simultaneously in a metastable state is staggered from the clock edge before data is written. This avoids data rejection due to the continuous metastable state of the two state machines, effectively ensuring the integrity of data writing and thus guaranteeing the quality of motherboard programming.

Description

Technical Field

[0001] This invention relates to the field of motherboard programming, and in particular to a motherboard programming control method, apparatus and system. Background Technology

[0002] Current motherboard chipsets integrate page cache state machines and block addressing state machines, which are responsible for data buffer scheduling and storage area permission verification, respectively, to ensure the orderly execution of the burning process.

[0003] Normally, during the programming process, both the page cache state machine and the block addressing state machine report a pass signal (a pass signal corresponds to a high level, and a deny signal corresponds to a low level). Only then will the chip's internal "write path" be activated, allowing data to be written; otherwise, the data will be rejected. However, during the state machine's level changes, it may briefly be in an intermediate level, i.e., a metastable state that is neither high nor low. Since the signals of the two state machines are updated and reported at each clock edge (every half-cycle of an oscillator arrives at a clock edge), when both state machines are simultaneously in a metastable state and at a clock edge, neither state machine reports a pass signal nor a deny signal. This results in the "write path" not being activated, and no write rejection warning being output, causing the programming process to continue, but data cannot be written to the chip. Summary of the Invention

[0004] Therefore, it is necessary to provide a motherboard programming control method, device, and system to address the above-mentioned problems.

[0005] This invention is implemented as follows: a motherboard programming control method, the method comprising: S1: Determine the oscillator half-cycle of the chip, where the chip passes through one clock edge for each oscillator half-cycle; S2: Send a no-data state probe command to the chip in real time to monitor the level changes of the page cache state machine and the block addressing state machine; S3: Before entering the next half-cycle of oscillation, determine whether the two state machines will be in a metastable state at the same time when updating the state based on the monitored level changes; S4: If not, proceed directly with data writing; S5: If so, generate a micropulse based on the level change trend of the two state machines, and insert the micropulse when entering the next oscillation half-cycle, so that the time when the two state machines are simultaneously in the metastable state is staggered from the clock edge, and then write the data to avoid the continuous metastable state of the two state machines causing the data to be rejected.

[0006] In one embodiment, the present invention provides a motherboard programming control device, the device comprising: The first processing module is used to determine the oscillator half-cycle of the chip, wherein the chip passes through one clock edge for each oscillator half-cycle. The second processing module is used to send no-data state probe commands to the chip in real time to monitor the level changes of the page cache state machine and the block addressing state machine. The third processing module is used to determine whether the two state machines will be in a metastable state at the same time when updating the state, based on the monitored level changes before entering the next oscillation half-cycle. The fourth processing module, if the judgment result is negative, is used to directly write data; If the judgment result is yes, the fifth processing module generates a micropulse based on the level change trend of the two state machines, and inserts the micropulse when entering the next oscillation half-cycle, so that the time when the two state machines are simultaneously in the metastable level is staggered from the clock edge, and then writes data, avoiding the continuous metastable level of the two state machines causing data to be rejected.

[0007] In one embodiment, the present invention provides a motherboard programming control system, the system comprising: Motherboard; A programming device, connected to the motherboard, is used to execute the motherboard programming control method described above.

[0008] This invention provides a motherboard programming control method, apparatus, and system. The method includes determining the oscillator half-cycle of the chip; sending a data-free state probe command to the chip in real time to monitor the level changes of the page cache state machine and the block addressing state machine; before entering each next oscillation half-cycle, determining whether the two state machines will be simultaneously in a metastable state when updating their states based on the monitored level changes; if not, directly writing data; if so, generating a micropulse based on the level change trend of the two state machines, and inserting the micropulse when entering the next oscillation half-cycle, so that the time when the two state machines are simultaneously in a metastable state is synchronized with the clock. After the clock edge is staggered, data is written to avoid data rejection due to the continuous metastability of the two state machines. In this application, during the programming process, the level changes of the cache state machine and the block addressing state machine can be implemented to determine whether the two state machines will be in a metastable state at the same time when updating the state. If so, a micropulse is generated and inserted into the oscillation half-cycle, so that the time when the two state machines are in a metastable state at the same time is staggered from the clock edge before data is written. This avoids data rejection due to the continuous metastability of the two state machines, effectively ensuring the integrity of data writing and thus ensuring the quality of motherboard programming. Attached Figure Description

[0009] Figure 1 A flowchart of a motherboard programming control method provided in one embodiment; Figure 2 This is an application environment diagram of the motherboard programming control method in one embodiment; Figure 3 This is a module flowchart of the motherboard programming control device in one embodiment; Figure 4 This is a block diagram of the internal structure of a programming device in one embodiment. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0011] It is understood that the terms "first," "second," etc., used in this invention may be used to describe various elements herein, but unless specifically stated otherwise, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this invention, a first script may be referred to as a second script, and similarly, a second script may be referred to as a first script.

[0012] like Figure 1 As shown, in one embodiment, a motherboard programming control method is proposed, the method comprising: S1: Determine the oscillator half-cycle of the chip, where the chip passes through one clock edge for each oscillator half-cycle; S2: Send a no-data state probe command to the chip in real time to monitor the level changes of the page cache state machine and the block addressing state machine; S3: Before entering the next half-cycle of oscillation, determine whether the two state machines will be in a metastable state at the same time when updating the state based on the monitored level changes; S4: If not, proceed directly with data writing; S5: If so, generate a micropulse based on the level change trend of the two state machines, and insert the micropulse when entering the next oscillation half-cycle, so that the time when the two state machines are simultaneously in the metastable state is staggered from the clock edge, and then write the data to avoid the continuous metastable state of the two state machines causing the data to be rejected.

[0013] In this embodiment, as Figure 2 As shown, this method is executed in a programming device, which can be an independent physical server or terminal, or a server cluster consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud servers, cloud databases, cloud storage and CDN. The programming device connects to the motherboard during programming, thereby enabling interaction with the chips in the motherboard to execute this method.

[0014] In this embodiment, the chip oscillator half-cycle is half the duration of the clock signal output by the internal ring oscillator of the chip. It is the most basic timing reference unit inside the chip. Every time an oscillator half-cycle passes, the chip generates a clock edge, driving the state machine such as the page buffer and block address to complete a state update.

[0015] In this embodiment, determining the oscillator half-cycle of the chip includes: Send n sets (e.g., 20 sets) of clock pulses with no data to the chip; For each clock pulse, the delay time from clock trigger to bus feedback is collected. The clock trigger time is the rising edge of the bus clock pin after the chip receives the pulse. Calculate the average of each delay duration. and standard deviation Thus, the standard interval is obtained. ; Excluding delay durations outside the standard range, determine the variance of the remaining delay durations. ; The oscillator half-cycle is determined based on the mean and variance of the delay duration. .

[0016] The core of the above process is to trigger internal timing synchronization of the chip through an external no-data clock pulse, and then use the statistical characteristics of the synchronization delay to inversely calculate the oscillator half-cycle. The no-data clock pulse only flips the rising edge of the SCK (serial clock) pin and does not transmit data. After the chip receives the pulse, the internal oscillator needs to align with the external SCK clock. The delay of this synchronization process directly maps to the actual value of the oscillator half-cycle; the oscillator half-cycle is the chip's internal timing reference, and its tiny fluctuations will be directly reflected in the synchronization delay.

[0017] Where k is the calibration coefficient, physically meaning "the oscillator half-cycle correction per unit delay variance," used to convert the quantized value of delay fluctuation into the actual correction value of the oscillator half-cycle. k needs to be determined through full-condition calibration of the target chip: the actual half-cycle value of the oscillator is measured using a high-precision oscilloscope across the entire range of the chip's rated voltage (3.3V±0.1V) and operating temperature (-40℃~125℃), while simultaneously acquiring the corresponding mean delay μ and variance. The optimal value of k is obtained by fitting using the least squares method (e.g., 0.8ns / ns² for 65nm automotive-grade Flash). Before mass production, the fitting error needs to be verified to be ≤0.01ns and then solidified into the programming tool. It can be finely adjusted as needed to adapt to the process deviations of different batches of chips.

[0018] In this embodiment, the page cache state machine is the core logic unit for managing page write data cache, responsible for buffering data to be written and counting cache fill amount; the block protection addressing state machine is the core logic unit for determining block protection areas and verifying addressing permissions, mainly performing operations such as reading block protection masks and verifying addressing validity; the state transitions of the page cache state machine and the block protection addressing state machine depend on the clock edge of the internal oscillator. If they fall into a metastable state synchronously with the page cache state machine, it will cause timing synchronization lock-up, resulting in neither the two state machines sending up a pass signal nor a prohibit signal, so that the "write path" is neither turned on nor outputs a write rejection reminder, causing the programming process to continue, but data cannot be written to the chip.

[0019] In this application, during the programming process, the level changes of the cache state machine and the block addressing state machine can be implemented to determine whether the two state machines will be in a metastable state at the same time when updating the state. If so, a micro-pulse is generated and inserted into the oscillation half-cycle, so that the time when the two state machines are in a metastable state at the same time is staggered from the clock edge before writing data. This avoids the continuous metastable state of the two state machines causing data to be rejected, effectively ensuring the integrity of data writing and thus ensuring the quality of motherboard programming.

[0020] In a preferred embodiment, the state probe instruction is an empty instruction that only triggers state machine state updates and does not trigger data writing / reading; Monitoring the level changes of the page cache state machine and the block addressing state machine includes: The level change curve of the page cache state machine is traced back to determine the period of the level change curve and the period position of the latest monitored level. The level change curve is then extended by an extension segment to obtain the first extension segment. The first extension segment represents the level change trend of the page cache state machine in the next two oscillator half-cycles. The time span of the first extension segment is two oscillator half-cycles. The level change curve of the block addressing state machine is traced back to determine the period of the level change curve and the period position of the latest monitored level. The level change curve is then extended by an extension segment to obtain a second extension segment. The second extension segment represents the level change trend of the block addressing state machine in the next two oscillator half-cycles. The time span of the second extension segment is two oscillator half-cycles. The first and second extension segments are used to determine whether the two state machines will be in a metastable state at the same time.

[0021] In this embodiment, after the programming device is connected to the motherboard, it can perform real-time level monitoring, sending a no-data state probe command to the chip (only triggering state machine updates, without writing data), maintaining a valid low level on the CS pin, providing a timing reference for SCK, and keeping the SI / SO pins in a high-impedance state. A high-precision level sampling module with a sampling rate ≥200MHz is enabled to acquire the level signal fed back from the SO pin (passive response of the state machine), and synchronously record the timestamp aligned with the SCK clock edge. Wavelet thresholding is used to denoise the raw level data, and threshold offset caused by voltage / temperature is calibrated. Features such as level value, fluctuation variance, and instantaneous phase are extracted. Furthermore, during the acquisition of level values, the device is programmed to generate level change curves of two state machines in real time. The level change curves of the state machines are traced back, that is, the level change curves before the current moment are retrieved, and then the change period of the change curve is identified (the curve will change cyclically according to the period). Then, the position of the current moment in the latest change period is identified, and then the level change curve is extended from the current moment according to the curve change trend of the previous change period. The time span of the extension segment is two oscillator half-cycles. Therefore, the time span of the extension segment is the change trend of the level in the next two oscillator half-cycles without the application of disturbance.

[0022] As a preferred embodiment, determining whether two state machines will simultaneously be in a metastable state when updating their states based on monitored level changes includes: Align the first extension segment with the second extension segment; Identify the midpoint of the time span corresponding to the two extended segments. ; Retrieve preset effective update duration ; Determine the starting point of the target time range ; Determine the end point of the target time range ,in, For adjustment coefficients; Extract the first local curve corresponding to the first extended segment within the target time range and the second local curve corresponding to the second extended segment within the target time range; Determine whether the first local curve and the second local curve are both completely within the set fuzzy level range. If so, the two state machines will be in a level metastable state simultaneously when updating the state. Otherwise, the two state machines will not be in a level metastable state simultaneously when updating the state.

[0023] In this embodiment, since the duration of the two extended segments is two oscillator half-cycles, the midpoint of the time span corresponding to the two extended segments corresponds exactly to the end of a half-cycle. At this moment, the two state machines will change state. If the two state machines are simultaneously in a metastable state, it will cause the two state machines to neither upload a pass signal nor an inhibit signal when updating their state. This will result in the "write path" not being turned on and no write rejection reminder being output, causing the burning process to continue, but the data cannot be written to the chip.

[0024] In this embodiment, the effective update duration can be 2ns; adjustment coefficient The value range is 0.7~0.9, with 0.8 being preferred; the effective update duration is the time required for the state to be successfully updated, therefore Data cannot be written to the chip only if both state machines are simultaneously in a metastable state for more than the effective update duration. In this embodiment, the target time range is shorter than the effective update duration. Therefore, as long as the two state machines are not completely simultaneously in a metastable state within the target time range, data writing failure will definitely not occur. Conversely, even if both state machines are completely simultaneously in a metastable state within the target time range, there is still a probability that data writing failure will not occur (for example, if the duration of the complete simultaneous metastable state is 0.9 seconds). ~1.0 (In cases where the time is between 1.0 and 1.0), it will likely result in data being unable to be written (e.g., the duration of the simultaneous metastable state is greater than 1.0). (For safety reasons, all cases in which the two state opportunities are completely and simultaneously in a metastable state within the target time range are considered as cases in which the two state opportunities are simultaneously in a metastable state when updating their states.)

[0025] In this embodiment, the ambiguity level range is the level range between high and low levels; a level higher than 2.7V can be considered a high level, and a level lower than 1.2V can be considered a low level, so the ambiguity level range is 1.2V~2.7V.

[0026] As a preferred embodiment, generating micropulses based on the level change trend of the two-state machine includes: S51: Determine the insertion time of the micropulse; S52: Determine whether only one micropulse or two micropulses need to be generated based on the positional relationship between the two extended segments; S53: If only one micropulse needs to be generated, determine the minimum pulse strength that makes the two extended segments not simultaneously in a metastable state. S54: If two micropulses need to be generated, determine the pulse intensity of the two micropulses respectively, so that the total pulse intensity is minimized and the two extended segments are not simultaneously in a metastable state. S55: Generate a micropulse with the determined pulse intensity and assign the micropulse the determined insertion time.

[0027] Determining the insertion time of the micropulse includes: Determine the target time period in which both the first and second extended segments are within the fuzzy level range; Determine the starting time of the target time period, and subtract the preset buffer time from the starting time to obtain the insertion time.

[0028] Determining whether only one micropulse or two micropulses need to be generated based on the positional relationship between the two extended segments includes: S521: Select one of the first and second extended segments as a candidate extended segment; S522: Adjust the target extension segment at the corresponding point of the insertion time according to the intensity of each pulse in the set micropulse intensity range, and determine whether the two extension segments are still in a metastable state after adjustment. If so, determine the candidate extension segment as the target extension segment. S523: Select another extension segment as a candidate extension segment and execute step S522; S524: Determine whether at least one of the first and second extended segments is the target extended segment. If so, only one micropulse needs to be generated; otherwise, two micropulses need to be generated.

[0029] The minimum pulse intensity required to cause the two extended segments to not be simultaneously in a metastable state includes: Determine all pulse intensities that prevent the extended segment corresponding to the micropulse needle from being simultaneously in a metastable level with another extended segment, and then determine the lowest pulse intensity among them; Determining the pulse intensity of each of the two micropulses includes: All pulse intensity combinations are determined based on the pulse intensity range. Each pulse intensity combination includes a pulse intensity corresponding to a first extended segment and a pulse intensity corresponding to a second extended segment. The pulse intensities in any two pulse intensity combinations are not exactly the same. For each pulse intensity combination, at the insertion time, the corresponding extension segment is adjusted according to each pulse intensity in the pulse intensity combination, and it is determined whether the first extension segment and the second extension segment after adjustment are still in a metastable state at the same time. If so, the pulse intensity combination is screened out. Determine the total intensity of each screened pulse intensity combination, and identify the pulse intensity combination with the lowest total intensity as the target intensity combination. The two pulse intensities in the target intensity combination are the pulse intensities of the two micropulses.

[0030] In this embodiment, the buffer duration can be 2ns. Setting the buffer duration can advance the action of the micropulse and change the level of the state machine to ensure timely adjustment of the level.

[0031] In this embodiment, only one micropulse is generated when only one micropulse is needed. If it is impossible to adjust the level using only one micropulse, two micropulses are generated to simplify the adjustment process as much as possible. Furthermore, regardless of whether one or two micropulses are generated, the micropulse with the lowest pulse intensity is selected to minimize energy consumption.

[0032] In this embodiment, the micropulse is a pulse voltage (the micropulse intensity ranges from 0.1 to 1.5V, and the interval between two adjacent pulse intensities is 0.1V). When the phase of the micropulse is the same as the phase of the level, the micropulse can be superimposed on the level; conversely, when the phase of the micropulse is opposite to the phase of the level, the micropulse can cancel out the level. The candidate extension segment is adjusted at the corresponding point of the insertion time. That is, the corresponding point of the candidate extension segment at the insertion time is first found, and then the pulse intensity of the micropulse is adjusted as a whole for the local segment of the candidate extension segment after that corresponding point. Since the level of the state machine is in a metastable state, it means that the level is changing from a high level to a low level. The adjustment direction is determined based on the changing trend of the corresponding extended segment within the target time range. If the extended segment gradually decreases within the target time range, the adjustment direction is upward (that is, the local segment of the candidate extended segment after the insertion time is shifted upward as a whole, and the magnitude of the shift increases the voltage value of the micropulse at the vertical coordinate of each point in the local segment, so that the micropulse is superimposed on the level). If the extended segment gradually increases within the target time range, the adjustment direction is downward (that is, the local segment of the candidate extended segment after the insertion time is shifted downward as a whole, and the magnitude of the shift decreases the voltage value of the micropulse at the vertical coordinate of each point in the local segment, so that the micropulse is canceled out by the level).

[0033] In this embodiment, when two micropulses need to be generated, all pulse intensity combinations are determined based on the pulse intensity range, meaning that the pulse intensity in all determined pulse intensity combinations falls within the pulse intensity range. The pulse intensity range is 0.1V to 1.5V, with a total of 15 selectable pulse intensities: 0.1V, 0.2V, 0.3V, ..., 1.5V. Each pulse intensity combination includes a pulse intensity corresponding to a first extension segment (first pulse intensity) and a pulse intensity corresponding to a second extension segment (second pulse intensity). There are 15 possibilities for both the first and second pulse intensities, therefore the total number of pulse intensity combinations is 15. 15 = 225; After determining all the pulse intensity combinations, for each pulse intensity combination, adjust the corresponding extension segment according to the two pulse intensities in the combination. The adjustment method is the same as the aforementioned method for adjusting one extension segment, and will not be repeated here.

[0034] In this embodiment, the generated micropulse includes parameters such as pulse intensity, phase, and insertion time. After the micropulse is generated, it is inserted into the corresponding state machine at the insertion time and continues until the end of the aforementioned target time range.

[0035] like Figure 2 As shown, in one embodiment, a motherboard programming control device is provided, the device comprising: The first processing module is used to determine the oscillator half-cycle of the chip, wherein the chip passes through one clock edge for each oscillator half-cycle. The second processing module is used to send no-data state probe commands to the chip in real time to monitor the level changes of the page cache state machine and the block addressing state machine. The third processing module is used to determine whether the two state machines will be in a metastable state at the same time when updating the state, based on the monitored level changes before entering the next oscillation half-cycle. The fourth processing module, if the judgment result is negative, is used to directly write data; If the judgment result is yes, the fifth processing module generates a micropulse based on the level change trend of the two state machines, and inserts the micropulse when entering the next oscillation half-cycle, so that the time when the two state machines are simultaneously in the metastable level is staggered from the clock edge, and then writes data, avoiding the continuous metastable level of the two state machines causing data to be rejected.

[0036] In this embodiment, the process by which each module in the motherboard programming control device provided in this application implements its respective function can be specifically referred to the foregoing. Figure 1 The description of the illustrated embodiment will not be repeated here.

[0037] like Figure 3 As shown, in one embodiment, a motherboard programming control system is proposed, the system comprising: Motherboard; A programming device, connected to the motherboard, is used to execute the motherboard programming control method described above.

[0038] In this application, during the programming process, the level changes of the cache state machine and the block addressing state machine can be implemented to determine whether the two state machines will be in a metastable state at the same time when updating the state. If so, a micro-pulse is generated and inserted into the oscillation half-cycle, so that the time when the two state machines are in a metastable state at the same time is staggered from the clock edge before writing data. This avoids the continuous metastable state of the two state machines causing data to be rejected, effectively ensuring the integrity of data writing and thus ensuring the quality of motherboard programming.

[0039] Figure 4 An internal structural diagram of a programming device in one embodiment is shown. Figure 4 As shown, the programming device includes a processor, a memory, a network interface, an input device, and a display screen connected via a system bus. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and may also store a computer program. When executed by the processor, this computer program enables the processor to implement the motherboard programming control method provided in this embodiment of the invention. The internal memory may also store a computer program, which, when executed by the processor, enables the processor to execute the motherboard programming control method provided in this embodiment of the invention. The display screen of the programming device can be a liquid crystal display or an electronic ink display. The input device of the programming device can be a touch layer covering the display screen, or buttons, a trackball, or a touchpad mounted on the casing of the programming device, or an external keyboard, touchpad, or mouse, etc.

[0040] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the programming device to which the present invention is applied. A specific programming device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0041] In one embodiment, the motherboard programming control device provided by this invention can be implemented as a computer program, and the computer program can be implemented as follows: Figure 4 The programming device shown operates on this device. The memory of the programming device can store the various program modules that make up the motherboard programming control unit, for example, Figure 3 The first, second, third, fourth, and fifth processing modules are shown. The computer program comprised of these modules causes the processor to execute the steps of the motherboard programming control method described in the various embodiments of the present invention.

[0042] For example, Figure 4 The programming device shown can be used as follows Figure 3The first processing module in the motherboard programming control device shown executes step S1; the programming device can execute step S2 through the second processing module; the programming device can execute step S3 through the third processing module; the programming device can execute step S4 through the fourth processing module; and the programming device can execute step S5 through the fifth processing module.

[0043] In one embodiment, a programming device is provided, the programming device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps: S1: Determine the oscillator half-cycle of the chip, where the chip passes through one clock edge for each oscillator half-cycle; S2: Send a no-data state probe command to the chip in real time to monitor the level changes of the page cache state machine and the block addressing state machine; S3: Before entering the next half-cycle of oscillation, determine whether the two state machines will be in a metastable state at the same time when updating the state based on the monitored level changes; S4: If not, proceed directly with data writing; S5: If so, generate a micropulse based on the level change trend of the two state machines, and insert the micropulse when entering the next oscillation half-cycle, so that the time when the two state machines are simultaneously in the metastable state is staggered from the clock edge, and then write the data to avoid the continuous metastable state of the two state machines causing the data to be rejected.

[0044] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, causes the processor to perform the following steps: S1: Determine the oscillator half-cycle of the chip, where the chip passes through one clock edge for each oscillator half-cycle; S2: Send a no-data state probe command to the chip in real time to monitor the level changes of the page cache state machine and the block addressing state machine; S3: Before entering the next half-cycle of oscillation, determine whether the two state machines will be in a metastable state at the same time when updating the state based on the monitored level changes; S4: If not, proceed directly with data writing; S5: If so, generate a micropulse based on the level change trend of the two state machines, and insert the micropulse when entering the next oscillation half-cycle, so that the time when the two state machines are simultaneously in the metastable state is staggered from the clock edge, and then write the data to avoid the continuous metastable state of the two state machines causing the data to be rejected.

[0045] It should be understood that although the steps in the flowcharts of the various embodiments of the present invention are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the various embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0046] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0047] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0048] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A motherboard programming control method, characterized in that, The method includes: S1: Determine the oscillator half-cycle of the chip, where the chip passes through one clock edge for each oscillator half-cycle; S2: Sends a no-data state probe command to the chip in real time to monitor the level changes of the page cache state machine and the block addressing state machine; S3: Before entering the next half-cycle of oscillation, determine whether the two state machines will be in a metastable state at the same time when updating the state based on the monitored level changes; S4: If not, proceed directly with data writing; S5: If so, generate a micropulse based on the level change trend of the two state machines, and insert the micropulse when entering the next oscillation half-cycle, so that the time when the two state machines are simultaneously in the metastable state is staggered from the clock edge, and then write the data to avoid the continuous metastable state of the two state machines causing the data to be rejected.

2. The method according to claim 1, characterized in that, The state probe instruction is an empty instruction that only triggers state machine state updates and does not trigger data writing / reading; Monitoring the level changes of the page cache state machine and the block addressing state machine includes: The level change curve of the page cache state machine is traced back to determine the period of the level change curve and the period position of the latest monitored level. The level change curve is then extended by an extension segment to obtain the first extension segment. The first extension segment represents the level change trend of the page cache state machine in the next two oscillator half-cycles. The time span of the first extension segment is two oscillator half-cycles. The level change curve of the block addressing state machine is traced back to determine the period of the level change curve and the period position of the latest monitored level. The level change curve is then extended by an extension segment to obtain a second extension segment. The second extension segment represents the level change trend of the block addressing state machine in the next two oscillator half-cycles. The time span of the second extension segment is two oscillator half-cycles. The first and second extension segments are used to determine whether the two state machines will be in a metastable state at the same time.

3. The method according to claim 2, characterized in that, Determining whether two state machines will simultaneously be in a metastable state when updating their states based on monitored level changes includes: Align the first extension segment with the second extension segment; Identify the midpoint of the time span corresponding to the two extended segments. ; Retrieve preset effective update duration ; Determine the starting point of the target time range ; Determine the end point of the target time range ,in, For adjustment coefficients; Extract the first local curve corresponding to the first extended segment within the target time range and the second local curve corresponding to the second extended segment within the target time range; Determine whether the first local curve and the second local curve are both completely within the set fuzzy level range. If so, the two state machines will be in a level metastable state simultaneously when updating the state. Otherwise, the two state machines will not be in a level metastable state simultaneously when updating the state.

4. The method according to claim 2, characterized in that, Generating micropulses based on the level change trend of the two-state machine includes: S51: Determine the insertion time of the micropulse; S52: Determine whether only one micropulse or two micropulses need to be generated based on the positional relationship between the two extended segments; S53: If only one micropulse needs to be generated, determine the minimum pulse strength that makes the two extended segments not simultaneously in a metastable state. S54: If two micropulses need to be generated, determine the pulse intensity of the two micropulses respectively, so that the total pulse intensity is minimized and the two extended segments are not simultaneously in a metastable state. S55: Generate a micropulse with the determined pulse intensity and assign the micropulse the determined insertion time.

5. The method according to claim 4, characterized in that, Determining the insertion time of the micropulse includes: Determine the target time period in which both the first and second extended segments are within the fuzzy level range; Determine the starting time of the target time period, and subtract the preset buffer time from the starting time to obtain the insertion time.

6. The method according to claim 4, characterized in that, Determining whether only one micropulse or two micropulses need to be generated based on the positional relationship between the two extended segments includes: S521: Select one of the first and second extended segments as a candidate extended segment; S522: Adjust the candidate extension segment at the corresponding point of the insertion time according to the intensity of each pulse in the set micropulse intensity range, and determine whether the two extension segments are still in a metastable state after adjustment. If so, determine the candidate extension segment as the target extension segment. S523: Select another extension segment as a candidate extension segment and execute step S522; S524: Determine whether at least one of the first and second extended segments is the target extended segment. If so, only one micropulse needs to be generated; otherwise, two micropulses need to be generated.

7. The method according to claim 6, characterized in that, The minimum pulse intensity required to cause the two extended segments to not be simultaneously in a metastable state includes: Determine all pulse intensities that prevent the extended segment corresponding to the micropulse needle from being simultaneously in a metastable level with another extended segment, and then determine the lowest pulse intensity among them; Determining the pulse intensity of each of the two micropulses includes: All pulse intensity combinations are determined based on the pulse intensity range. Each pulse intensity combination includes a pulse intensity corresponding to a first extended segment and a pulse intensity corresponding to a second extended segment. The pulse intensities in any two pulse intensity combinations are not exactly the same. For each pulse intensity combination, at the insertion time, the corresponding extension segment is adjusted according to each pulse intensity in the pulse intensity combination, and it is determined whether the first extension segment and the second extension segment after adjustment are still in a metastable state at the same time. If so, the pulse intensity combination is screened out. Determine the total intensity of each screened pulse intensity combination, and identify the pulse intensity combination with the lowest total intensity as the target intensity combination. The two pulse intensities in the target intensity combination are the pulse intensities of the two micropulses.

8. A motherboard programming control device, characterized in that, The device includes: The first processing module is used to determine the oscillator half-cycle of the chip, wherein the chip passes through one clock edge for each oscillator half-cycle. The second processing module is used to send no-data state probe commands to the chip in real time to monitor the level changes of the page cache state machine and the block addressing state machine. The third processing module is used to determine whether the two state machines will be in a metastable state at the same time when updating the state, based on the monitored level changes before entering the next oscillation half-cycle. The fourth processing module, if the judgment result is negative, is used to directly write data; If the judgment result is yes, the fifth processing module generates a micropulse based on the level change trend of the two state machines, and inserts the micropulse when entering the next oscillation half-cycle, so that the time when the two state machines are simultaneously in the metastable level is staggered from the clock edge, and then writes data, avoiding the continuous metastable level of the two state machines causing data to be rejected.

9. A motherboard programming control system, characterized in that, The system includes: Motherboard; A programming device, connected to the motherboard, is used to execute the motherboard programming control method as described in any one of claims 1-7.

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