Methods and devices for facilitating write misses in cache systems

Abstract

This application relates to methods and apparatus for facilitating write miss caches in a caching system. Example methods, apparatuses, systems, and articles of art are provided for facilitating write miss caches in a caching system. One example apparatus (110) includes: a first cache storage area (214); a second cache storage area (218), wherein the second cache storage area (218) includes a first portion and a second portion for storing a first set of data evicted from the first cache storage area (214); a cache controller (222) coupled to the first cache storage area (214) and the second cache storage area (218), and configured to: receive a write operation; determine that the write operation has resulted in a miss in the first cache storage area (214); and, in response to the miss in the first cache storage area (214), provide write miss information associated with the write operation to the second cache storage area (218) for storage in the second portion.

Description

[0001] Divisional application This application is a divisional application of the invention patent application filed on May 26, 2020, with application number 202080038198.6 and entitled "Method and apparatus for facilitating write miss cache in cache system". Technical Field

[0002] This specification generally relates to computer architecture, and more specifically, to methods and apparatus for implementing data caching. Background Technology

[0003] A computing system contains one or more processing cores that execute instructions by accessing data stored in memory. However, the time it takes for a processing core to access data from memory can be very long. Therefore, most computing systems include a cache that stores a certain amount of data from memory (e.g., typically less than the total amount of data in memory) that is highly likely to be accessed by the processing core in the future. Thus, when a processing core calls for data, the cache can provide the data to the processing core faster than the processing core retrieves data from memory, thereby improving the speed and efficiency of the computing system. Summary of the Invention

[0004] According to one aspect of the present invention, an apparatus is provided. The apparatus includes: a first cache storage area; a second cache storage area, wherein the second cache storage area includes a first portion and a second portion for storing a first set of data evicted from the first cache storage area; a cache controller coupled to the first cache storage area and the second cache storage area, and configured to: receive a write operation; determine that the write operation results in a miss in the first cache storage area; and, in response to the miss in the first cache storage area, provide write miss information associated with the write operation to the second cache storage area for storage in the second portion.

[0005] According to another aspect of the present invention, a system is provided. The system includes: a central processing unit (CPU) configured to output a write command corresponding to a memory address; a first cache memory configured to output write miss information from the first cache memory to a second cache memory when the first cache memory does not store data at the memory address; and a second cache memory comprising a first portion and a second portion for storing a first set of data evicted from the first cache memory, the second cache memory being configured to store the write miss information in a dedicated section of the second cache memory, the dedicated section being dedicated to the write miss information.

[0006] According to another aspect of the present invention, a method is provided. The method includes: receiving a write operation; determining that the write operation produces a miss in a first cache memory; and in response to the miss in the first cache memory, verifying write miss information associated with the write operation to a second cache memory element having a first portion and a second portion for storage in the second portion, the first portion storing a first set of data evicted from the first cache memory. Attached Figure Description

[0008] Figure 1 This is an instance computing system described in conjunction with the examples described in this article.

[0009] Figure 2 yes Figure 1 A block diagram of the instance-level cache of the instance computing system.

[0010] Figures 3A-3D Show Figure 1 An example circuit implementation scheme for the first-level cache of an example computing system.

[0011] Figure 4A yes Figures 3A-3D An example circuit implementation scheme for the main cache storage queue.

[0012] Figure 4B It is a combination Figures 3A-4A An example circuit implementation scheme for the data forwarding logic of the main cache storage queue.

[0013] Figure 4C It is an additional instance circuit implementation of the main cache storage queue and / or the victim cache storage queue.

[0014] Figure 4D yes Figure 4A Example hardware implementation of the merging circuit.

[0015] Figure 5 Show Figures 3A-3D The first-level cache instance is based on the victim cache segment.

[0016] Figure 6 Showing the implementation Figures 3A-3D The first and second tables of instances of the replacement strategy component for instance 5.

[0017] Figure 7A This illustrates an instance of an encapsulated data caching system that includes a victim cache storage queue and a victim storage area.

[0018] Figure 7B This illustrates another instance of an encapsulated data cache system that includes a main cache storage queue and a main storage area.

[0019] Figure 7C The instance victim cache group structure is shown.

[0020] Figure 7D The instance's main cache group structure is shown.

[0021] Figure 7E This shows the instance of the unified cache group structure.

[0022] Figure 8A A schematic diagram illustrating an example implementation of a victim cache tag random access memory.

[0023] Figure 8B Show Figure 8A Another schematic illustration of an instance implementation of a victim cache tag random access memory.

[0024] Figures 9A-9B (Collectively referred to as Figure 9) illustrates the instance instruction service workflow.

[0025] Figure 10A-1 and 10A-2 (Collectively referred to as Figure 10A) shows the instance data cache system.

[0026] Figure 10B-1 and 10B-2 (Collectively referred to as Figure 10B) shows the second instance data cache system.

[0027] Figure 11A yes Figures 3A-3D An example circuit implementation scheme for a victim cache storage queue.

[0028] Figure 11B-1 and 11B-2 (Collectively referred to as Figure 11B) is an example circuit implementation scheme for the instance unified cache storage queue.

[0029] Figure 12-33 It indicates that it can be implemented through execution. Figure 1-3D A flowchart of machine-readable instructions in the L1 cache.

[0030] Figure 34 It is structured for execution Figures 3A-3D The instructions are thus implemented. Figure 1-3D A block diagram of the instance processing platform for the first-level cache. Detailed Implementation

[0031] These figures are not drawn to scale. Instead, the thickness of layers or regions may be enlarged in the figures. Generally, the same reference numerals will be used throughout the figures and the accompanying written description to refer to the same or similar parts. As used in this patent, a statement that any part (e.g., layer, film, region, area, or plate) is on another part in any way (e.g., positioned thereon, located thereon, disposed thereon, or formed thereon, etc.) indicates that the referenced part is either in contact with the other part or that the referenced part is above the other part with one or more intermediate parts located between them. Unless otherwise indicated, connection references (e.g., attachment, coupling, connection, and joining) should be interpreted broadly and may include intermediate parts between sets of elements and relative movement between elements. Therefore, a connection reference does not necessarily imply that two elements are directly connected and have a fixed relationship with each other. A statement that any part is "in contact" with another part means that there is no intermediate part between the two parts. Although layers and regions with clearly defined lines and boundaries are shown in the figures, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be invisible, mixed, and / or irregular.

[0032] The term "coupled" is used throughout this specification in various forms. These terms may cover connection, communication, or signal paths that achieve a functional relationship consistent with the description herein. For example, if device A generates a signal to control device B to perform an action, in a first instance device, A is coupled to device B via a direct connection, or in a second instance device, A is coupled to device B via an intermediate component C (if the intermediate component C does not alter the functional relationship between device A and device B), thereby allowing device B to be controlled by device A via control signals generated by device A.

[0033] Consistent with this specification, the term "configured as" describes the structural and functional characteristics of one or more tangible, non-transitory components. For example, a device "configured as" to perform a function means that the device has a specific configuration designed or dedicated to performing a particular function. If a device contains tangible, non-transitory components that can be enabled, activated, or powered to perform a particular function, then such a device is "configured as" to perform said particular function. While the term "configured as" can be encompassed as configurable, this term is not limited to this narrow definition. Therefore, when used to describe a device, the term "configured as" does not require that the described device be configurable at any given point in time.

[0034] Furthermore, the term "example" used herein to mean serving as an example, illustration, etc., is not necessarily advantageous. And, although this description has been shown and described with respect to one or more embodiments, equivalent changes and modifications will be apparent from reading and understanding this specification and the accompanying drawings. All such modifications and changes are fully supported by the specification and limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the foregoing components (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe these components correspond to any component that performs the specified function of the described component (e.g., a functionally equivalent component), even if structurally not equivalent to the described structure. Furthermore, while a particular feature may be described with respect to only one of several embodiments, such feature may be combined with one or more other features of other embodiments, provided that it is necessary and advantageous for any given or particular application.

[0035] While this specification contains numerous details, these details should not be construed as limiting the scope of possible claims, but rather as descriptions of features that may be specific to particular embodiments. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although the foregoing features may be described as operating in certain combinations, even if such combinations are initially claimed, in some cases one or more claimed combinations may be removed from the combination, and the claimed combination may involve sub-combinations or variations thereof.

[0036] Similarly, although operations are depicted in the accompanying drawings in an instance-specific order, this does not require that such operations be performed in the instance-specific order or sequential order, or that all illustrated operations be performed to obtain the desired result, unless such order is recited in one or more claims. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the above embodiments does not require such separation in all embodiments.

[0037] When identifying multiple elements or components that can be individually mentioned, this document uses descriptors such as “first,” “second,” “third,” etc. Unless otherwise stated or understood in the context of their use, such descriptors do not imply any priority, physical order, or arrangement, or chronological order in the list, but serve merely as labels to refer to multiple elements or components separately for ease of understanding of the described instance. In some instances, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to by different descriptors in the claims, such as “second” or “third.” In such cases, the use of such descriptors is solely for the convenience of referring to multiple elements or components.

[0038] A central processing unit (CPU) is an electronic circuit system that executes instructions that make up a program or workload. A CPU may contain one or more processor cores for executing instructions by accessing data from main memory (e.g., via extended memory). Because accessing data from main memory takes time, the one or more processor cores may obtain data from memory and store it locally in local memory (e.g., a data cache). Local memory is smaller and faster than main memory. In this way, the processor cores can use and / or manipulate data locally instead of interfacing with main memory. Because the latency of reading and / or correcting data (e.g., the amount of time required to read data from memory and / or write data to memory) is smaller when accessing a cache, storing data from extended memory in a cache increases the speed and efficiency of the computing system.

[0039] Some local memory devices (e.g., caches) contain one or more victim caches. A victim cache is an additional storage area contained within or attached to a cache. A victim cache improves (e.g., reduces) cache miss rates, specifically, reduces conflict misses, by storing data recently evicted from its corresponding cache. Adding a victim cache can have a similar impact on cache performance. The benefits are most pronounced when adding a victim cache to a direct-mapped cache, as direct-mapped caches have a relatively high conflict miss rate.

[0040] Some examples described in this article involve improved data caching and victim caching architectures that reduce overall cache latency. In some alternative cache designs, the victim cache sits at the end of the cache controller. When a line is evicted from the cache controller (e.g., removed to make room for additional data) rather than having the evicted line sent all the way to the next level of cache (e.g., L2) for storage, the victim cache holds the evicted line (e.g., the victim data) until it is justified for evicting due to capacity or other reasons. In such a system, when a subsequent miss occurs in the corresponding cache (e.g., L1 cache), the victim cache can service the miss and return the line to the corresponding cache, thus returning it to the requesting processor core, thereby reducing read miss latency. However, because some instance systems include a victim cache contiguous with the main cache, the victim cache must wait for the main cache to determine that it does not contain data corresponding to a memory operation from the CPU (also referred to herein as a memory instruction, memory request, and / or memory transaction (e.g., read operation, instruction, request, and / or transaction, write operation, instruction, request, and / or transaction, read-modify-write operation, instruction, request, and / or transaction, atomic operation, instruction, and / or transaction, histogram operation, instruction, request, and / or transaction, etc.) before the victim cache can determine whether the memory address is stored in the victim cache. The instances described herein include caching systems that reduce latency (e.g., increase speed), reduce the number of cycles required to perform write operations, atomic operations (e.g., manipulating data stored at a location to increment, decrement, exchange with other data, etc.), and / or histogram operations (e.g., determining the total number of values ​​for each cache line), and / or improve the efficiency of computing systems containing caches.

[0041] Figure 1 An instance computing system 100 is shown. The instance computing system 100 includes an instance CPU 102, instance processing cores 104a-104n, instance extended memory 106, and instance data cache 108. The instance data cache 108 includes an instance level 1 (L1) cache 110, an instance level 2 (L2) cache 112, and an instance level 3 (L3) cache 114. Although... Figure 1 The instance computing system 100 includes N The instance computing system 100 may contain any number of processing cores and / or cache levels. Furthermore, one or more instance components in the computing system 100 may be implemented on the same die and / or different dies in the same chip and / or different chips.

[0042] Figure 1The instance CPU 102 includes instance processing cores 104a-104n. Processing cores 104a-104n may be incorporated into the same die or separate dies (e.g., connected via one or more interfaces). The CPU 102 is connected to the instance data cache 108 via one or more interfaces. For example, instance core 104a of the instance CPU 102 may be connected to the data cache 108 via a scalar interface (e.g., a 64-bit wide bidirectional and / or unidirectional interface) and / or a vector interface (e.g., a 512-bit wide interface). The use of scalar and vector interfaces may be based on interface utilization, data size, and / or other considerations. For example, a scalar read operation may be transferred via a scalar data transfer, while the corresponding data may be transferred via a vector interface. Furthermore, both the scalar and / or vector interfaces may be used when the other interface is busy. In some instances, the CPU 102 may use different numbers and / or different types of interfaces to connect to the data cache 108.

[0043] Figure 1 The processing cores 104a-104n access data from the instance via extended memory 106 and / or instance cache 108 to execute instructions stored in the instance via extended memory 106 and / or instance data cache 108. Instance cores 104a-104n can execute different processes simultaneously to accelerate the execution of tasks (e.g., instructions) of the computing system 100. For example, cores 104a-104n can execute instructions from application workloads by writing data to and / or reading data from the via extended memory 106 and / or data cache 108. Because the data cache 108 contains copies of some data stored in the instance via extended memory 106, when an instance core 104a needs to access (e.g., read and / or write) data from the via extended memory 106, the instance core 104a transmits read and / or write instructions to the instance data cache 108. As further described below, if data cache 108 contains data corresponding to instructions from core 104a (e.g., corresponding to a cache hit), then data cache 108 fulfills requests and / or instructions from processing core 104a. If data cache 108 does not contain data corresponding to instructions from core 104a (e.g., corresponding to a cache miss), then data cache 108 is interfaced with the instance via extended memory 106 to execute transactions from core 104a.

[0044] Figure 1The instance via memory 106 is connected to the instance data cache 108 via an interface (e.g., a 1024-bit wide via memory interface). However, different numbers and / or different types of interfaces may be used alternatively. The instance via memory 106 stores all data accessible to the computing system 100. The instance via memory 106 may be incorporated into the computing system 100 and / or may be external memory (e.g., off-chip memory). In some instances, the via memory 108 interacts with the controller of the highest cache (e.g., instance L3 cache 114), and the highest cache (e.g., L3 cache 114) interacts with the second highest cache (e.g., instance L2 cache 112), and so on. In such instances, the CPU 102 transfers memory operations to instance L1 cache 110, and if the memory operation cannot be serviced by L1 cache 110, L1 cache 110 transfers the memory operation to L2 cache 112, and so on. Figure 1 In an example, if L3 cache 114 (e.g., the highest-level cache) cannot perform a read or write transaction (e.g., because the memory address is not located in the local memory area of ​​L3 cache 114), then L3 cache 114 interacts with extended memory 106 to read or write the corresponding data to the memory address. Extended memory 106 can be on-chip or off-chip memory (e.g., DDR), and the interface to extended memory can be 2... N Bits, where N depends on the type of extended memory used. In some instances, a prefetcher and / or preload mechanism may exist in either data cache to pull data from the instance via extended memory 106 before execution, so that it is stored locally in the cache before the CPU 102 executes any instructions. Memory 106 provides a copy of the data stored in memory to the instance data cache 108. Data cache 108 may periodically, irregularly, and / or on triggers, based on instructions from the CPU 102, request additional information and / or instruct the extended memory 106 to adjust the data stored in extended memory 106.

[0045] Figure 1The instance data cache 108 stores data blocks from the instance extended memory 106 (e.g., a cached subset of data stored in extended memory 106) to reduce the time required for the instance CPU 102 to access the cached subset, thereby improving system performance. For optimal performance, the data in the data cache 108 is intended to correspond to the data most likely to be used by the CPU 102. During a cache hit, when requested by the CPU 102 (e.g., when the requested data is in the data cache 108), the data cache 108 provides access to the cached data. If the CPU 102 requests data not contained in the data cache 108 (e.g., a cache miss), the data cache 108 retrieves the corresponding data from extended memory 106. For example, if the CPU 102 transfers a read operation corresponding to a specific address in extended memory 106, the data cache 108 determines whether the data corresponding to that specific address in extended memory 106 is cached in the data cache 108. If data cache 108 determines that data is cached, it provides the data to CPU 102 for reading. If data cache 108 determines that data is not cached, it retrieves the data from extended memory 106 and returns it to CPU 102. Furthermore, instance data cache 108 may update cached data based on cache misses (e.g., thereby reducing future cache misses). For write transactions from CPU 102, instance data cache 108 may temporarily store the corresponding data and then provide it to update earlier data stored in extended memory 106.

[0046] Instance data cache 108 includes instance L1 cache 110, instance L2 cache 112, and instance L3 cache 114. The cache levels can be based on speed and / or size. For example, instance L1 cache 110 could be the fastest and smallest cache, followed by L2 112 (e.g., slower and larger than L1 110) and L3 114 (e.g., slower and larger than L2 112). The most frequently used data is often stored in L1 110, followed by L2 112 and L3 114. Therefore, when CPU 102 needs an address to write to or read from, instructions from CPU 102 are first sent to L1 cache 110, and if the corresponding data is not stored in L1 cache 110, the instruction is sent to L2 cache 112. If the corresponding data is not stored in L2 cache 112, the instruction is sent to L3 cache 114. If the corresponding data is not stored in L3 cache 114, the instance data cache 108 accesses the data from extended memory 106.

[0047] As described further below, Figure 1 The instance L1 cache 110 includes a main cache and a victim cache for parallel execution of instructions from CPU 102. The victim cache stores victim data (e.g., data evicted from the main cache to make room for new data corresponding to other address locations via extended memory 106). In this way, when a cache miss occurs at the L1 level, the main L1 cache evicts a first set of data (e.g., victim data) to make room for a second set of data corresponding to the transaction that caused the cache miss. The victim cache then stores the first set of data removed from the main cache to make room for the second set of data in the main cache.

[0048] Figure 2 yes Figure 1 The instance block diagram of the L1 cache 110. The instance L1 cache 110 includes an instance CPU interface 202, instance tag random access memory (RAM) access 204, 206, instance tag RAM 208, 210, instance main cache storage queue 212, instance main storage area 214 (also known as main cache storage area or main cache), instance victim cache storage queue 216, instance victim storage area 218 (also known as victim cache storage area or victim cache), instance cache controller 220, instance main cache controller 222, instance victim cache controller 224, and instance L2 interface 228.

[0049] The instance CPU interface 202 connects the CPU 102 (e.g., CPU 102 cores 104a-104n) to the L1 cache 110. The CPU interface 202 connects to tag RAM accesses 204 and 206 and the cache controller 220. The instance CPU interface 202 receives instructions from the instance cores 104a-104n of the instance CPU 102. Instructions may include read instructions, write instructions, read-modify-write instructions, atomic instructions, etc. When the CPU interface 202 receives an instruction corresponding to specific data stored at a specific address, the CPU interface 202 interfaces with the cache controller 220 and the main tag RAM access 204 to determine whether the corresponding data is stored in the main memory area 214 and / or the victim memory area 218 to execute a transaction. Furthermore, for some types of transactions (e.g., read transactions), the instance CPU interface 202 returns the corresponding data to the instance CPU 102. Furthermore, when the CPU interface 202 receives an instruction corresponding to data at a specific address, the master components (e.g., instance master tag RAM access 204, instance tag RAM 208, instance master cache queue 212, instance master memory 214, and instance master cache controller 222) and the victim components (e.g., instance tag RAM access 206, instance tag RAM 210, instance victim cache queue 216, instance victim memory 218, and instance victim cache controller 224) operate in parallel (e.g., simultaneously) to determine whether the data from the corresponding address is stored in master memory 214 and / or victim memory 218.

[0050] Figure 1The primary tag RAM access 204 is coupled to tag RAM 208 and cache controller 220. The victim tag RAM access 206 is coupled to tag RAM 210 and cache controller 220. The primary tag RAM access 204 accesses tag RAM 208 to determine if data corresponding to a memory address from an instruction from CPU 102 exists in main memory 214. In parallel with the primary tag RAM access 204, the victim tag RAM access 206 accesses tag RAM 210 to determine if data corresponding to a memory address from an instruction from CPU 102 exists in victim memory 218. In some instances, the primary tag RAM access 204 is implemented in tag RAM 208, and the victim tag RAM access 206 is implemented in tag RAM 210. When the primary tag RAM access 204 and / or the victim tag RAM access 206 determine that the address corresponding to the instruction from the CPU 102 exists in the corresponding tag RAM 208, 210, the primary tag RAM access 204 and / or the victim tag RAM access 206 transfer the result (e.g., determination and / or any corresponding data) to the instance cache controller 220.

[0051] In some instances, main memory is directly mapped. Therefore, in such instances, a specific CPU memory address might only be stored at a specific location in main memory 214. Thus, instance tag RAM 208 could potentially have a fixed memory address for a given CPU instruction. In a directly mapped cache, a given address is stored at a specific location in tag RAM 208.

[0052] Figure 2The instance tag RAM 208 is coupled to the instance cache controller 220 and the instance main memory 214. The instance tag RAM 208 stores a table recording entries in the instance main memory 214 corresponding to memory addresses in the extended memory 106. In this way, the instance main tag RAM access 204 can check the table to determine whether data corresponding to instructions from the CPU 102 is available in the main memory 214. The instance tag RAM 210 is coupled to the instance cache controller 220 and the instance victim memory 218. The instance tag RAM 210 stores a table recording entries in the instance victim memory 218. In this way, the instance victim tag RAM access 206 can check the table to determine whether data corresponding to instructions from the CPU 102 is available in the victim memory 218. When data in the main memory 214 is updated, the instance tag RAM 208 can update the table to reflect any changes to the entries. For example, if main memory 214 removes the first set of data corresponding to a first memory address in extended memory 106 and replaces it with a second set of data corresponding to a second memory address in extended memory 106, then instance tag RAM 208 updates its table to reflect that the first set of data at the first memory address is no longer stored in main memory 214, and the second set of data at the second memory address is now stored in main memory 214. Similarly, when data from a first address location in victim memory 218 changes to data from a second address location, instance tag RAM 210 may update its table to reflect any changes to the entries.

[0053] The instance victim-side tag RAM 210 can be content-addressable memory (CAM). In some instances, the victim memory area 218 is fully associative (e.g., any location in the victim memory area 218 can be used to store data from any CPU address). Therefore, when the instance CPU 102 provides a memory address to the instance L1 cache 110, the instance victim tag RAM 210 compares the provided memory address with all entries in the tag RAM 210. If the provided address matches an entry stored in the tag RAM 210, the address of the corresponding location in the victim memory area 218 is output by the tag RAM 210. This address is used to retrieve data corresponding to a CPU instruction from the victim memory area 218.

[0054] Figure 2The instance main cache queue 212 is coupled to the instance main memory 214 and the instance cache controller 220. The instance main cache queue 212 is used when the CPU 104 issues a storage operation (e.g., a write operation, atomic compare-and-swap, atomic operation, etc.). The instance main cache queue 212 can implement a read-modify-write function. The read-modify-write function involves storing data in local memory, which needs to read an earlier version of the written data already present in the main memory 214 for reasons such as containing updated error correction code data. In this way, when a read operation is being performed to obtain a copy of earlier data from the main memory 214, new bits contained in the write portion of the read-modify-write transaction from the CPU 102 are buffered in the main cache queue 212. When the earlier data becomes available, only the new bits that the CPU 102 is overwriting are updated in the storage queue buffer, and the updated (e.g., merged) data is written back to the main memory 214. For example, new bits (containing the corresponding memory address) being overwritten by CPU 102 in the write portion of a read-modify-write transaction (e.g., from CPU 102) are buffered in main cache memory queue 212 until the old data corresponding to the write (e.g., store) instruction is read from main memory 214. When the new bits contained in the write portion of the read-modify-write transaction are merged with the old data from main memory 214, the updated (e.g., merged) data is written back to main memory 214. Additional pipelined use for store instructions provided by main cache memory queue 212 allows instructions from CPU 104 to continue execution while a previous store instruction is waiting for load data from main memory 214 to become available. In some instances, main memory 214 contains SRAM, as further described below in conjunction with sections 5 and 16. Example main cache memory queue 212 is described below in conjunction with... Figure 3A , 3B 4. Further description.

[0055] Figure 2The instance victim cache queue 216 is coupled to the instance victim memory area 218 and the instance cache controller 220. The instance victim cache queue 216 buffers data to be stored in the instance victim memory area 218. For example, a victim value containing the corresponding memory address and / or stored data from a store instruction (e.g., from the cache controller 220) is buffered in the victim cache queue 216 until a previous or old value of the corresponding store instruction is read from the victim memory area 218. When the stored byte is merged with previous / old data from the victim memory area 218, the value is written back to the victim memory area 218. Although victim cache queue 216 can handle read, modify, and / or write operations from cache controller 220 transferred in response to a deregistration point (e.g., when one or more cache lines are removed from L1 cache 110 to L2 cache 112), in other instances described herein, victim cache queue 216 can handle read, modify, and / or write operations from cache controller 220 transferred directly from CPU 102. Example victim cache queue 216 is further described below.

[0056] Figure 2 The instance main memory 214 is coupled to the instance tag RAM 208, the instance main cache queue 212, and the instance cache controller 220. The instance main memory 214 stores data (e.g., entries) corresponding to memory address locations in extended memory 106. The main memory 214 stores data that has a high probability of being invoked by the instance CPU 102. The stored data can be updated, for example, when the CPU 102 attempts to access (e.g., read, write, etc.) data not cached in the instance main memory 214. The instance main memory 214 can be or contains static RAM (SRAM) and / or any other type of memory providing single-cycle access to the stored data.

[0057] Figure 2 The instance victim memory 218 is coupled to the instance tag RAM 210, the instance victim cache queue 216, and the instance cache controller 220. The instance victim memory 218 stores data (e.g., entries) corresponding to memory address locations that have been removed from the instance main memory 214 to make room for data from other address locations recently accessed or more likely to be accessed by the CPU 102. The instance victim memory 218 may be or contain a register file, static RAM (SRAM), and / or any other type of memory.

[0058] In operation, initially, instance main memory 214 stores data from different addresses in instance extended memory 106 based on usage possibilities. If instance CPU 102 sends an instruction corresponding to a memory address stored in main memory 214, instance cache controller 220 controls the execution of transactions. For example, cache controller 220 may transmit instructions to main cache queue 212 for subsequent processing and storage in main memory 214. If instance CPU 102 sends an instruction corresponding to a memory address not stored in main memory (e.g., stored in victim memory 218), instance main memory 214 may store data at the corresponding memory address after retrieving data from another memory location. Main memory 214 removes some data corresponding to one or more memory address locations to free up space for data. The removed data and corresponding memory address locations are referred to as victims or evict lines. The data selected as victims is based on various parameters according to an alternative strategy. After being removed from main memory 214, victims are stored in instance victim memory 218. If victim storage area 218 is full, data (e.g., the second victim) is removed from victim storage area 218 to make room for the victim from main storage area 214. After the second victim is removed from victim storage area 218, the second victim is transferred to L2 cache 112 for storage.

[0059] although Figure 1The instance L1 cache 110 includes a main cache queue 212 with a corresponding main memory area 214 and an instance victim cache queue 216 with a corresponding victim memory area 218. However, the instance main cache queue 212 and / or the instance victim cache queue 216 may contain multiple queues corresponding to multiple memory areas. For example, the main memory area 214 and / or the victim memory area 218 may be divided into multiple independently addressable groups (e.g., any number of storage devices with any number of linewidths, rows, etc.), where each group may have its own corresponding queue. For example, the main memory area 214, consisting of 256 rows (each row with a linewidth of 1024 bits), may be divided into 16 main memory areas (e.g., groups), with each row in a particular group having 64 bits, where each group may have its own main queue. In this example, if the vector data of a read and / or write request hitting L1 cache 110 is 512 bits wide, the cache controller 220 can process the request as eight parallel writes and / or reads to the eight groups. In such a multi-group setup, read and / or write operations can be sent to groups in parallel, and the groups arbitrate their own processes in response to the read and / or write operations. The multi-group approach is more efficient than a single main memory area by operating independently (e.g., because the entire cache line is not locked when a request is received, and only the portion of the cache line allocated to the group receiving such a request is locked), at the cost of greater complexity and / or greater dispersion.

[0060] Figure 2The instance cache controller 220 is coupled to components of L1 to control how data is read from and / or written to instance stores 214, 216 and / or how data is updated in instance stores 214, 218. For example, when a read request, write request, atomic request, read-modify-write request, etc., is received at instance CPU interface 202, the cache controller 220 receives the request and instructs other components accordingly. For example, during a read request for data at a specific location in extended memory 106, the instance cache controller 220 instructs main tag RAM access 204 to access tag RAM 208 to determine whether main memory 214 is storing data corresponding to the location in extended memory 106 from the read request. If primary tag RAM access 204 determines that an entry is located in primary memory 214 (e.g., a cache hit), cache controller 220 determines the location of the specific entry based on data in tag RAM 208 and interfaces with primary cache queue 212 to read the value from instance primary memory 214 and return the value to CPU 102 via CPU interface 202. Instance cache controller 220 includes primary cache controller 222 for controlling primary cache components (e.g., instance primary tag RAM access 204, instance tag RAM 208, instance primary cache queue 212, and instance primary memory 214), and instance victim cache controller 224 for controlling victim cache components (e.g., instance victim tag RAM access 206, instance tag RAM 210, instance victim cache queue 216, and instance victim memory 218) in parallel with primary cache controller 222 controlling primary cache components. In some instances, cache controllers 222 and 224 may be separate controllers and / or operate in combination within a single controller.

[0061] Figure 2The instance cache controller 220 interfaces with the instance L2 interface 228 to obtain data to be stored in the instance main memory 214 (e.g., initially, after a cache miss, etc.). Furthermore, when new data is written (e.g., when old data is overwritten), the instance cache controller 220 can transmit updates to the data in the main memory 214 and / or the victim memory 218 to the L2 cache 112, causing read instructions from the CPU 102 to propagate to the L2 cache 112 via the L2 interface 228. The instance cache controller 220 interfaces with the instance L2 interface 228 to transfer and / or receive data from the L2 cache 112 and / or the L3 cache 114 (e.g., directly or via the L2 cache 112). For example, when main memory 214 and victim memory 218 do not contain memory address locations corresponding to data from instructions from CPU 102 (e.g., corresponding to cache misses), instance cache controller 220 transmits instructions to instance L2 cache 112 via L2 interface 228. If the data is stored in L2 cache 112 or L3 cache 114, cache controller 220 can receive the corresponding data from L2 cache 112 via L2 interface 228. In this example, cache controller 220 can store the corresponding information from L2 cache 112 in main memory 214. In some instances, when victim memory 218 needs to remove data from a specific location (e.g., old victims) to make room for new victims from main memory 214, instance cache controller 220 can transfer old victims to L2 cache 112 via L2 interface 228 for storage in the L2 cache.

[0062] Figures 3A-3D Show Figure 1 An example circuit implementation scheme for the L1 cache 110 of the example computing system 100. Figures 3A-3D The example implementation includes Figure 2 The instance CPU interface 202, instance tag RAM 208, 210, instance main cache storage queue 212, instance main storage area 214, instance victim cache storage queue 216, instance victim storage area 218 and instance cache controller 220. Figures 3A-3D The instance implementation further includes instance modification, exclusive, shared, invalid (MESI) RAM 300, instance address processing components 302a-c, instance group processing logic 303, instance hit / miss comparison logic 304, 306, instance replacement strategy component 308, instance flush engine 309, instance error correction code (ECC) logic 310, 312, instance data multiplexer (MUX) circuitry 314, 316, instance MUX 318, 320, and instance latch 322.

[0063] exist Figures 3A-3D In one example implementation, the instance CPU interface 202 includes two interfaces (e.g., a scalar interface and a vector interface, each of which has two parts, one for inputting data from the CPU 102 and the other for outputting data to the CPU 102). Figures 3A-3D The input CPU interface 202 includes a flexible buffer for buffering incoming data from the CPU 102, a multiplexer for selecting between buffered data from the flexible buffer when there are pending CPU instructions in the flexible buffer and instructions directly from the CPU 102 when the flexible buffer queue is empty, and divides the incoming instructions into corresponding addresses, operations (e.g., read, write, etc.) and write data (e.g., if the instruction corresponds to a write operation). Figures 3A-3D The output CPU interface 202 transmits data back to CPU 102.

[0064] Figures 3A-3D The instance primary cache queue 212 contains blocks corresponding to the primary cache queue 212. For example, primary cache queue 212 contains blocks that perform read-modify-write operations, write merging, write data forwarding, write operations, complete checksum block writes, weighted histogram operations, load and increment operations, and compare and swap operations. The instance primary cache queue 212 is described below in conjunction with... Figure 4A Further description. The instance main cache storage queue 212 is combined with the instance main storage area 214 for operations. Figures 3A-3D In this example, main memory area 214 is data RAM (DRAM).

[0065] Figures 3A-3D The instance victim cache queue 216 contains blocks corresponding to operations performed on the victim cache queue 216. For example, the victim cache queue 216 contains blocks implementing read-modify-write operations, write merges, write data forwarding, write operations, full checksum block writes, load and increment operations, and compare and swap operations. The instance victim cache queue 216 is described below in conjunction with... Figure 5 Further description. The instance victim cache storage queue 216 operates in conjunction with the instance victim storage area 218. In Figures 3A-3D In this example, main memory area 214 is the register file.

[0066] Figures 3A-3DThe instance MESI RAM 300 is connected to the command line of the instance CPU interface 202 and the instance DRAM 214. The instance MESI RAM 300 tracks the data status in the instance main memory 214 based on commands from the CPU 102. For example, the MESI RAM 300 tracks the status of cache lines by marking them as modified, exclusive, shared, or invalid. Modified or invalid corresponds to a cache line containing data that is not stored in any other cache of similar level and the data has been modified from its value in main memory (e.g., causing a read of data in extended memory 106 to be marked or permitted because it is not up-to-date or valid). Exclusive is a cache line containing data that is not stored in any other cache of similar level and the data is clean (e.g., matching data in extended memory 106). Shared indicates that the cache line contains clean data that can be stored in another cache (e.g., the line can be discarded because it exists in another cache). Invalid indicates that the cache line is invalid or unused. When updating main memory 214 and / or via extended memory 106, MESI RAM 300 may be invoked. The victim cache instance MESI RAM 300 is implemented in conjunction with instance tag RAM 210.

[0067] Figures 3A-3D The instance MESI RAM 300 adds consistency to the system through tracking, tagging, and marking. The state of memory addresses prevents data writes at specific times, ensuring that data mismatches do not occur at different cache levels. The state tracked by the MESI RAM 300 can be transferred in the event of a cache miss, allowing higher-level caches to understand what the data at the memory address will be used for. For example, if the L1 cache issues a cache miss for a read operation, the cache miss contains shared state, letting higher-level caches know that the data will be read but not manipulated. If the L1 cache 110 issues a cache miss for a write operation, the cache miss contains exclusive state, letting higher-level caches know that the data will be modified. When a victim is evicted from instance main memory 214 and / or victim memory 218, the state from instance MESI RAM 300 can be used to figure out how to evict it. For example, if the data is shared, main memory 214 and / or victim memory 218 can simply be discarded (e.g., because the data at the memory address is already in a higher cache). If the data is monopolized or modified, the cache controller 220 instructs the interface 228 to transfer the victim to a higher-level cache (e.g., because the data at the memory address is not in a higher-level cache, or is in a higher-level cache but is outdated).

[0068] Figures 3A-3D The instance address processing components 302a-c are connected to and interconnected with the CPU interface 202, instance main memory 214, instance main cache queue 212 (e.g., via MUX 318), and instance victim memory 218 (e.g., via instance MUX 320). The instance address processing components 302a-c include instance first address processing component 302a, second address processing component 302b, and third address processing component 302c. The first address processing component 302a performs address translation, the second address processing component 302b performs data rotation, and the third address processing component 302c facilitates group organization. Alternatively, one or more of the first address processing component 302a, second address processing component 302b, and third address processing component 302c may be contained in the same hardware, logic circuitry, integrated circuit, etc. The instance address processing components 302a-c organize the data to be written to the instance main memory 214 and victim memory 218 according to a specific storage protocol, ensuring that the data is stored correctly. For example, in multiple instances (e.g., where main cache queue 212, main memory 214, victim cache queue 216, and victim memory 218 are divided into multiple groups), address processing components 302a-c can use memory addresses from CPU operations to determine which of the main cache queue 212, main memory 214, victim cache queue 216, and victim memory 218 is divided into the multiple groups required for a given CPU operation.

[0069] Instance group processing logic 303 is coupled to CPU interface 202, instance main memory 214, instance main cache queue 212 (e.g., via MUX 318), and instance victim memory 218 (e.g., via instance MUX 320). In operation, group processing logic 303 is configured to analyze read, modify, and / or write instructions from CPU interface 202. In this way, group processing logic 303 is configured to determine the nature of the read, modify, and / or write instructions to facilitate efficient partial group read, modify, and / or write instructions. In the example described herein, group processing logic 303 detects whether an incoming write instruction indicates a write to the entire group or a write to a portion of the group. In this way, group processing logic 303 can indicate whether to operate a read-modify-write operation when a read instruction is negated. An example description of the operation of group processing logic 303 is described below.

[0070] Figures 3A-3DThe instance hit / miss comparison logic 304 is connected to the input CPU interface 202, tag RAM 208, main memory 214, main cache queue 212, cache controller 220, and / or instance MUX circuitry 314 (e.g., via a data forwarding latch). The hit / miss comparison logic 304 takes an address from tag RAM 208 and an address of an instruction from CPU 102, and compares them (e.g., using XNOR logic) to determine whether the address from the instruction is a hit or a miss (e.g., whether the data corresponding to that address is stored in instance DRAM 214). The instance hit-miss comparison logic 304 includes tag comparison logic for outputting the comparison result to instance main cache queue 212, instance cache controller 220, and / or instance MUX circuitry 314.

[0071] Figures 3A-3D The instance hit / miss comparison logic 306 is connected to the input CPU interface 202, the tag RAM 210, the victim cache storage queue 216, and / or the instance replacement policy component 308. The hit / miss comparison logic 306 obtains the entry number (e.g., location) of the victim cache from the tag RAM 210 and the address of the instruction from the CPU interface 202, and compares these two to determine whether the access (e.g., the instruction from the CPU interface 202) is a hit or a miss (e.g., whether the data corresponding to the address is stored in the instance victim storage area 218). The instance hit-miss comparison logic 306 outputs the result to the replacement policy component 308, the address encoder 326, the multiplexer 330, and / or the victim cache storage queue 216.

[0072] Figures 3A-3D The address encoder 326 is connected to the tag RAM 210 (via hit / miss comparison logic 306) and the multiplexer 330. The address encoder 326 encodes the addresses of the tag RAM 210 into a form that can be interpreted by the victim memory area 218. For example, the tag RAM 210 may store a 16-bit memory address, while the victim memory area 218 stores a 4-bit memory address corresponding to the 16-bit memory address. Therefore, the address encoder 326 can transform the 16-bit memory address into a 4-bit memory address to locate and / or enter the corresponding memory address in the victim memory area 218. Alternatively and additionally, the address encoder 326 may encode the memory address into any bit value. The address encoder 326 is coupled to the instance multiplexer 330 such that the address encoder 326 provides the encoded address to the multiplexer 330.

[0073] Figures 3A-3DThe instance replacement policy component 308 is connected to the hit-miss comparison logic 306 and the replacement address encoder 328. In some instances, the replacement policy component 308 is connected to the tag RAM 210. The instance replacement policy component 308 controls the replacement policy for data stored in the instance victim memory 218 (e.g., data moved outside the victim cache if a new victim would be stored in the victim memory 218). In some instances, the instance main memory 214 may have a replacement policy component. However, the replacement policy does not need to be cached via a direct mapping cache (e.g., if the instance main memory 214 is directly mapped, because a particular address will only appear in one location). An instance flush engine (e.g., a flush engine component) 309 is coupled to the replacement policy 308. In some instances, the flush engine 309 is used and / or otherwise invoked at predefined intervals to flush write misses stored inside the victim memory 218.

[0074] Figures 3A-3D An alternative address encoder 328 is coupled to multiplexer 330, such that the alternative address encoder 328 provides an encoded alternative address to multiplexer 330. The alternative address encoder 328 encodes the address selected by the alternative strategy component 308. For example, the alternative strategy component 308 outputs a 16-bit alternative memory address to the alternative address encoder 328, and the alternative address encoder 328 transforms the 16-bit alternative memory address into a 4-bit alternative memory address. Alternatively and additionally, the alternative address encoder 328 encodes the alternative memory address into any bit value.

[0075] Figures 3A-3D Multiplexer 330 is connected to hit / miss comparison logic 306, address encoder 326, alternative address encoder 328, and address read 332. Multiplexer 330 selects an encoded address based on the result of hit / miss comparison logic 306 (e.g., based on whether an access was hit or missed). Multiplexer 330 provides the selected memory address to address read 332 to read into victim memory 218. For example, multiplexer 330 outputs the location of victim memory 218, which CPU instructions can use to read data from or, in the case of write instructions, to store data.

[0076] Figures 3A-3DThe instance error correction code (ECC) logic 310 is connected to the instance main memory 214 and multiplexing circuitry 314 via latch 322. If the instance L1 cache 110 supports ECC memory, the instance main memory 214 stores data in blocks and a set of ECC check bits corresponding to each block. When a read operation is received, the instance main memory 214 can provide the stored data block and the corresponding ECC check bits to the ECC logic 310. The instance ECC logic 310 can regenerate the ECC check bits based on the data block read from the main memory 214 and compare the regenerated ECC check bits with the previously stored bits. The instance ECC logic 310 can determine that a data block has been read incorrectly if a discrepancy exists and can correct the error in the data block.

[0077] Figures 3A-3D The instance error correction code (ECC) logic 312 is connected to the instance victim memory 218 and the MUX circuitry 316 via latch 324. The instance ECC logic 312 performs ECC correction logic in a similar manner to the instance ECC logic 310. However, the instance ECC logic 312 performs an ECC checksum comparison relative to the instance victim memory 218.

[0078] Figures 3A-3D The instance master data MUX circuit 314 is connected to the main cache storage queue 212, ECC logic 310, the output of hit / miss comparison logic 304 (e.g., via a latch), the instance output CPU interface 202 (e.g., via instance latch 322), the instance victim data MUX 316, and the instance cache controller 220. The instance master data MUX circuit 314 has the inverse operation of instance address processing components 302a-c to translate data in the data address for transfer to the instance CPU 102. The MUX within the instance MUX circuit 314 is controlled by the cache controller 220 via corresponding selection inputs.

[0079] Figures 3A-3D The instance victim data MUX circuit 316 is connected to the victim cache storage queue 216, ECC logic 312, instance master data MUX circuit 314, L2 cache 112 (e.g., via latches), and instance cache controller 220. The instance master data MUX circuit 314 has the reverse operation of instance address processing components 302a-c to translate data in the data address for transfer to the instance CPU 102. The MUX within the instance MUX circuit 316 is controlled by the cache controller 220 via corresponding selection inputs.

[0080] Figures 3A-3DThe instance MUX 318 is connected to the L2 cache 112, connected to the instance CPU interface 202 via a latch, and connected to the address processing components 302a-c, the main cache storage queue 212, the main memory area 214, and the cache controller 220. The instance cache controller 220 controls the MUX 318 to control all ways in which data can be written to or read from the instance main memory area 214 (e.g., via direct memory access (DMA), listener transactions (e.g., when the L2 cache 112 wants data from the L1 cache 110), the main cache storage queue 212, read hit buffers, etc.). The instance MUX 320 is connected to the instance main memory area 214 (e.g., via an evict line for storing victims), the address processing components 302a-c (e.g., via write streams and / or CPU load), the instance L2 cache 112 (e.g., via L2W and / or listener lines), the victim memory area 218, and / or the cache controller 220. Instance cache controller 220 controls MUX 320 to control all methods by which data can be written to or read from instance victim memory 218 (e.g., via direct memory access (DMA), listener transactions, victim cache memory queue 216, evicting from instance main memory 214, via L2 cache 112, etc.). Instance MUX 318, 320 are controlled by instance cache controller 220 via corresponding selection inputs.

[0081] Figure 3A and 3B The elements are arranged in a way that represents a transaction flow. The time elements are represented by levels E1-E5. Each level represents a discrete time period, and in some instances, each level represents one clock cycle or an integer number of clock cycles.

[0082] Write miss cache in L1 data cache

[0083] In operation, instance CPU 102 transmits instructions (e.g., returning data based on a read operation, writing data to a specific memory location). When instance CPU 102 first requests data at a specific memory address, if the data at that memory address is not stored in main memory 214, tag RAM 208 will output a read miss, and L1 cache will issue a read miss message (e.g., sent to L2 cache 112, L3 cache 114, and / or via extended memory 106) for servicing (e.g., returning data corresponding to the address requested from CPU 102). L1 cache 110 can then perform a read allocation. The read allocation is performed after L1 cache 110 stores data in main memory 214, updates tag RAM 208, etc., thereby identifying that the data at the address is now stored in main memory. L1 cache 110 can return the data to CPU 102 and / or wait for CPU 102 to send a subsequent read request for the same address. If CPU 102 issues a subsequent read request for the same address, tag RAM 208 will recognize that the data at that address now exists in main memory 214, thus generating a read hit. If CPU 102 proceeds to a write to the same address, tag RAM 208 will recognize a write hit because the address is stored in main memory 214. For a write hit, CPU 102 will provide data for writing, and L1 cache 110 will write the data to the main memory 214 corresponding to the address.

[0084] If an initial action (or a subsequent action from CPU 102) results in a write miss (e.g., the memory address that CPU 102 attempts to write to is not stored in the instance's main memory), L1 cache 110 may perform a write miss. During a write miss, L1 cache 110 sends the write miss to a higher-level cache (e.g., L2 cache 112, L3 cache 114, etc.) and / or retrieves the data from the memory address via extended memory 106, stores the data in main memory 214, and then writes the data from CPU 102 to the location in main memory 214 corresponding to the memory address.

[0085] However, when the CPU 102 performs a write operation, the information it writes immediately is often not needed. Therefore, some instance cache systems include a write buffer to store write instructions from the CPU in case the CPU stops (e.g., by attempting to load memory addresses from higher caches before writing data). In this way, while the L1 cache interfaces with higher-level caches to obtain data in the buffer corresponding to the memory address of the write instruction, the CPU can continue sending instructions, storing data in main memory, and writing data (e.g., in the write buffer), in parallel with subsequent instructions from the CPU. However, the CPU may only write a few bytes per write instruction, and the interface between the L1 cache and higher-level caches and / or extended memory can send large numbers of bytes (e.g., 64-byte bandwidth). Therefore, transferring a few bytes per cycle on a large-byte interface is inefficient.

[0086] exist Figures 3A-3D In this system, a segment of victim storage 218 is dedicated to writing miss information, rather than implementing a write buffer. Therefore, instance victim storage 218 is both a victim cache and a write miss buffer. This segment of the victim storage is called the write miss cache. In some instances, the write miss cache may be implemented additionally or alternatively in main storage 214. In some instances, the write miss cache is a 128-byte cache line. The write miss cache stores all write miss data until the write miss cache is completely full and / or the number of bytes that can be sent to higher-level caches and / or via extended memory exceeds a first threshold. Once the write miss cache is full or a first threshold amount of write miss data is added to the write miss cache, victim memory 218 combines a second threshold amount of write miss data in the write miss cache into a signal, which is sent to a higher-level cache (e.g., via instance L2 interface 228) for writing to addresses stored in the higher-level cache (e.g., L2 cache 112) and / or via extended memory 106. In this way, most or all of the interface bandwidth can be used for a given period. The second threshold may be the same as or different from the first threshold. Furthermore, the write data is stored locally in main memory 214 or victim memory 218. Therefore, if an additional read or write operation is sent from the CPU 102 before the write operation is passed to a higher cache (e.g., L2 cache 112, instance L3 cache 114, etc.) and / or via extended memory 106, the cache controller 220 may read and / or write data to the corresponding address in the write-miss cache and then transfer it to a higher-level cache and / or via extended memory 106.

[0087] In some instances, the write miss cache structure in victim memory 218 includes a byte enable register file representing the value bytes of write miss information (e.g., the bytes to be written). For example, if a write miss corresponding to the first and third bytes of data at a write memory address is stored in the write miss cache, victim memory 218 stores the first and third bytes of write miss data in conjunction with the memory address, and fills the corresponding entries in the byte enable register file with a first value (e.g., '1') corresponding to the entry elements of the first and third bytes and a second value (e.g., '0') for the remaining elements of the entry. In this way, when write miss data is sent to a higher-level cache, the byte enable bits of the entry are included in the transmission, allowing the higher-level cache to know which data is valid (e.g., which bytes to write) and which data is invalid (e.g., which bytes should not be written).

[0088] In some cases, if a read or write request is a hit in primary memory 214, the result in victim memory 218 can be ignored. When primary memory 214 is configured as a unidirectional associative cache, cache request conflicts across multiple data paths are direct. A data path is one or more logical circuits that, during execution and / or other invocation, implement the transfer or delivery of data (e.g., logical signals, bit vectors, etc.) from source to destination. Cache request conflicts from said multiple data paths can be problematic for victim memory 218 because victim memory 218 is fully associative and can store write misses as well as cache entries. Cache request conflicts between two data paths can be handled as described in the following examples. It is worth noting that in the following examples, cache operations are described in the context of a specific data path. However, the examples are combinations of specific cache operations, and it is not important which data path the specific cache operation is on.

[0089] In the first instance, a cache read miss occurs on the first data path, and a cache write hit occurs on the second data path, both having different memory addresses. In some cases where victim memory 218 is fully associated, cache requests can be redirected to any location within victim memory 218. (See reference...) Figure 3A-D, address generation for locations within victim memory 218 and address lookup in victim cache tag RAM 210 are performed at the E2 pipeline level. Therefore, address generation for locations within the victim cache is performed before it is known whether the cache request address is a hit or a miss. After controller 220 determines that a read miss exists on main memory 214, a request for the memory address of the read request is sent to a higher-level cache or memory. In the case that main memory 214 is unidirectionally associated, the memory address of the read request for the first data path is mapped to a single location in main memory 214. If cached data exists in said single location, said cached data is evicted from main memory 214 to victim memory 218, reaching a pre-generated location within victim memory 218. If this pre-generated location is the same as the location of a cache write hit for the second data path, a conflict occurs. This conflict can be detected by cache controller 220. As noted above, address generation for a location within victim storage area 218 occurs before it is known whether a cache request address is a hit or a miss. Therefore, before determining that a cache write is a hit, a second address is generated for a location within victim storage area 218 for cache writes to a second data path. Based on the detected conflict, this second location within the victim cache can be used to store data evicted from main storage area 214 by a read miss.

[0090] In another instance, the first data path may have a cache read miss, and the second data path may have a cache write hit, as in the first instance. In this instance, due to the read miss, a request for the memory address of the read request is sent to a higher-level cache or memory, and cached data is evicted from main memory 214 to victim memory 218, reaching a pre-generated location within victim memory 218, here location A. In this instance, the cache write of the second data path also hits location A within victim memory 218, resulting in a configuration conflict. One possible solution to such a conflict is to directly load the requested read miss from the higher-level cache or memory to a separate location in the victim cache. Another solution to the conflict is to have the cache controller 220 stop read misses, such that cached data is evicted to victim memory 218 only after the cache write of the second data path to location A is completed and location A is evicted to the higher-level cache or memory. In some cases, this stopping may occur while waiting for the higher-level cache or memory to return read miss data.

[0091] As another example, a first cache write may be received on a first data path for victim memory 218, and a second cache write may also be received on a second data path for victim memory 218. If the first cache write and the second cache write address different memory addresses, the two cache writes may be performed in parallel to victim memory 218. If both the first cache write and the second cache write address the same memory address and both are cache misses, the victim cache controller 224 allocates a single location in the allocated victim cache miss memory and merges the first cache write and the second cache write in the victim cache storage queue 216. The merged data, along with merged byte enable, priority, and color tag information, may then be written to the victim cache miss memory. If both the first cache write and the second cache write address the same memory address and both are cache hits, the first cache write and the second cache write are merged into the hit location in the cache.

[0092] As another example, cache reads may be received on a first data path for victim memory 218, and cache writes may be received on a second data path for victim memory 218. When a cache read is a hit and a cache write is a hit at a different location within victim memory 218, the cache read and cache write proceed in parallel without conflict. When a cache read is a hit and a cache write is a miss at a different location within victim memory 218, the cache read and cache write also proceed in parallel without conflict. When a cache read is a miss and a cache write is a hit at a different location within victim memory 218, the cache read may use an address generated for the cache write targeting a location within victim memory 218, as described above. When a cache read is a miss and a cache write is a miss at a different location within victim memory 218, both the cache read and cache write use addresses generated for locations within victim memory 218.

[0093] In another instance, cache reads may be received on a first data path for victim memory 218, and cache writes may be received on a second data path for victim memory 218. In some cases, a cache read may be a hit at a first address in a set of addresses stored in victim memory 218. A cache write may also be a hit at a second address in the same set of addresses stored in victim memory 218. In this case, cache reads and cache writes can be performed in parallel without conflict. In another instance, a cache read may be a hit at a first address in a set of addresses stored in victim memory 218. A cache write may be a miss at a second address in the same set of addresses stored in victim memory 218. In this case, cache reads and cache writes can be performed in parallel without conflict. In yet another instance, a cache read may be a miss at a first address in a set of addresses stored in victim memory 218. A cache write may be a hit at a second address in the same set of addresses stored in victim memory 218. In this scenario, similar to the situation described above, cache reads can halt until a cache write to the location in victim memory 218 via the second data path is completed and the data is evicted to a higher-level cache or memory. Then, the cache read proceeds to read the set of addresses from the higher-level cache or memory into victim memory 218. In another scenario, a cache read could be a miss of the first address in the set of addresses stored in victim memory 218. A cache write could also be a miss of the second address in the same set of addresses stored in victim memory 218. In this case, cache reads and cache writes can proceed in parallel without conflict.

[0094] In another instance, a cache read may be received for victim memory 218 on a first data path, and a cache write may be received for victim memory 218 on a second data path. In some cases, a cache read may be a hit of an address stored in victim memory 218. A cache write may also be a hit of the same address stored in victim memory 218. In this case, the cache read may proceed first, and the cache write may be halted until after the cache read is complete. Alternatively, the order of cache writes and cache reads may be based on the data path from which the cache write and cache read are received, where a cache operation reaching a lower (or higher) numbered data path completes before another cache operation. In some cases, a cache read may be a miss of an address stored in victim memory 218. A cache write may also be a miss of the same address stored in victim memory 218. In this case, after a cache write operation completes to store data in victim memory 218, the cache write operation may be forwarded to a higher-level cache or memory, from which a cache read may then retrieve data.

[0095] In another example, a first cache read may be received for victim memory 218 on a first data path, and a second cache read may be received for victim memory 218 on a second data path. If the first cache read and the second cache read target different memory addresses, there is no conflict between a hit and a miss. In some cases, the first cache read may be a miss at a first address in a set of addresses. The second cache read may also be a miss at a second address in the same set of addresses. If the first cache read and the second cache read have different priorities, the higher-level cache or memory is accessed based on the higher priority. Otherwise, the higher-level cache or memory is accessed, and the set of memory addresses is obtained for storage in victim memory 218. Cases where the first cache read and the second cache read target the same address are handled in the same manner.

[0096] This document describes example methods, apparatuses, systems, and artifacts for facilitating write miss caches in L1 data caches. Other examples and combinations thereof include the following: Example 1 includes an apparatus comprising: a first cache store; a second cache store, wherein the second cache store includes a first portion and a second portion for storing a first set of data evicted from the first cache store; a cache controller coupled to the first cache store and the second cache store, and configured to receive a write operation, determine that the write operation results in a miss in the first cache store, and, in response to the miss in the first cache store, provide write miss information associated with the write operation to the second cache store for storage in the second portion.

[0097] Example 2 includes the device according to Example 1, wherein the cache controller is configured to compare a second portion of the second cache storage area with a threshold, and, based on the second portion exceeding the threshold, cause the write miss information to be transmitted to the second cache.

[0098] Example 3 includes the device according to Example 2, wherein the threshold corresponds to the interface bandwidth.

[0099] Example 4 includes the device according to Example 2, wherein the threshold corresponds to the size of the second portion.

[0100] Example 5 includes the device according to Example 1, wherein the write miss information is a first write miss information, and if the second cache storage contains a second write miss information corresponding to the memory address of the first write miss information, then the cache controller available for the second cache storage will not provide the first write miss information from the first cache storage to the second cache storage.

[0101] Example 6 includes the device according to Example 1, wherein the first cache storage area and the second cache storage area are connected in parallel to the central processing unit.

[0102] Example 7 includes the device according to Example 1, wherein the write miss information is a first write miss information, and the cache controller can be used to merge the first write miss information and the second write miss information when the first memory address of the first write miss information from the first cache storage area matches the second memory address of the second write miss information stored in the second portion.

[0103] Example 8 includes the device according to Example 7, wherein the cache controller merges the first write miss information with the second write miss information by at least one of the following: (a) retaining the first write information of the first write miss information, or (b) discarding the second write information of the second write miss information when the second write information corresponds to one or more bytes that are the same as the first write miss information.

[0104] Example 9 includes the device according to Example 1, wherein the second part includes a byte enable register in which the cache controller stores a value based on the write miss information.

[0105] Example 10 includes the device according to Example 9, wherein the value corresponds to an element of the write miss information to be written.

[0106] Example 11 includes a system comprising: a central processing unit for outputting a write command corresponding to a memory address; a first cache storage area for outputting write miss information from the first cache storage area to a second cache storage area when the first cache storage area does not store data at the memory address; and a second cache storage area, wherein the second cache storage area includes a first portion and a second portion for storing a first set of data evicted from the first cache storage area, the second cache storage area being used to store the write miss information in a dedicated segment of the second cache storage area, the dedicated segment being dedicated to the write miss information.

[0107] Example 12 includes the system according to Example 11, wherein when the dedicated segment has a write miss information greater than a threshold amount, the second cache storage area outputs the write miss information to the second cache.

[0108] Example 13 includes the system according to Example 12, wherein the threshold corresponds to the bandwidth of the interface to the second cache.

[0109] Example 14 includes the system according to Example 12, wherein the threshold corresponds to the size of the second portion.

[0110] Example 15 includes the system according to Example 11, wherein if the second cache storage contains a second write instruction corresponding to the same memory address as the write miss information from the central processing unit, the second cache storage will not store the write miss information from the first storage in the second portion.

[0111] Example 16 includes the system according to Example 11, wherein the first cache storage area and the second cache storage area are connected in parallel to the central processing unit.

[0112] Example 17 includes the system according to Example 11, wherein the write miss information is a first write miss information, and the system further includes a controller for merging the first write miss information and the second write miss information when a first memory address of the first write miss information from the first cache storage area matches a second memory address of the second write miss information stored in the second portion.

[0113] Example 18 includes the system according to Example 17, wherein the cache controller merges the first write miss information with the second write miss information by at least one of the following: (a) retaining the first write information of the first write miss information, or (b) discarding the second write information of the second write miss information when the second write information corresponds to one or more bytes that are the same as the first write miss information.

[0114] Example 19 includes a method comprising: receiving a write operation; determining that the write operation results in a miss in a first cache storage area; and in response to the miss in the first cache storage area, providing write miss information associated with the write operation to a second cache storage element having a first portion and a second portion for storage in the second portion, the first portion storing a first set of data evicted from the first cache storage area.

[0115] Example 20 includes the method according to Example 19, further comprising comparing the second portion of the second cache storage area with a threshold, and outputting the write miss information to the second cache based on the second portion exceeding the threshold.

[0116] Figure 4A yes Figure 2 An example circuit implementation of the main cache storage queue 212 with and / or 3. Figure 4AIn the main cache storage queue 212, there are instance latches 402a, 402b, 402c, 402d, 402e, instance merging circuits 403a-c, instance arithmetic component 404, instance atomic comparison component 406, instance read-modify-write merging component 408, instance selection multiplexer 410, instance ECC generator 412, instance arbitration manager 414, instance pending storage address data storage area 416, instance priority multiplexer 418, instance read port 424, and instance write port 426. Instance merging circuits 403a-d include instance comparator 420 and instance switch 422. Figure 4A The example illustrates a single pipeline for the main cache storage queue 212. However, the main storage element 214 can be arranged as more than one independent copy relative to different sets of supporting pipelines, as indicated by dashed box 400. Therefore, Figure 4A The pipelines can be regenerated multiple times for different groups, as described further below.

[0117] exist Figure 4A In this context, instance latches 402a, 402b, 402c, 402d, and 402e are electronic devices configured to store information (e.g., bytes, bits, etc.) obtained through the main cache storage queue 212. Instance latches 402a-c pass write data and information corresponding to whether the write data needs to be combined with read and correction data outside the ECC logic 310 in the arithmetic unit 404, atomic unit 406, and / or RMW merging component 408. Figure 4A In this example, latch 402a is communicatively coupled to cache controller 220 to receive read, write, and / or modify instructions. Such read, modify, and / or write instructions may originate from CPU 102 and be transmitted to latch 402a via cache controller 220. Latch 402a is coupled to latch 402b, tag RAM 208, arbitration manager 414, and pending memory address data storage area 416 to transmit such read, modify, and / or write instructions to latch 402b, tag RAM 208, arbitration manager 414, and pending memory address data storage area 416 in response to subsequent clock cycles of cache controller 220.

[0118] exist Figure 4A In this example, latch 402b is coupled to latch 402a, the data storage area 416 for the memory address to be processed, latch 402c, priority multiplexer 418, and comparator 420 to transmit the acquired read, modify, and / or write instructions in response to subsequent clock cycles of cache controller 220. In this manner, values ​​obtained from read, modify, and / or write instructions (e.g., byte values, bit values, etc.) are propagated through main cache queue 212.

[0119] Example latch 402c is coupled to latch 402b, priority multiplexer 418, arithmetic component 404, atomic comparison component 406, and read-modify-write merging component 408. This coupling enables latch 402c to transfer values ​​obtained from read, modify, and / or write instructions (e.g., byte values, bit values, etc.) to arithmetic component 404, atomic comparison component 406, and / or read-modify-write merging component 408 in response to subsequent clock cycles of cache controller 220. In some examples described herein, latch 402c may transfer values ​​obtained from read, modify, and / or write instructions (e.g., byte values, bit values, etc.) to one or more of arithmetic component 404, atomic comparison component 406, and / or read-modify-write merging component 408. For example, when cache controller 220 transmits an instruction to write bits into a currently stored word, latch 402c may transfer the value obtained from the read, modify, and / or write instruction (e.g., byte value, bit value, etc.) to read-modify-write merging component 408. In other instances described herein, although cache controller 220 may transmit instructions to write bits into a currently stored word, latch 402c may transfer the value obtained from the read, modify, and / or write instruction (e.g., byte value, bit value, etc.) to arithmetic component 404, atomic comparison component 406, and / or read-modify-write merging component 408.

[0120] Example latch 402d is coupled to first multiplexer 410, ECC generator 412 and latch 402e. This coupling enables latch 402d to transfer the value obtained from first multiplexer 410 to ECC generator 412 and / or merging circuit 403a in response to subsequent clock cycles of cache controller clock 220.

[0121] Example latch 402e is coupled to priority multiplexer 418 and MUX circuitry 314 of Figures 3 and / or 4. This coupling allows latch 402e to transfer the value obtained from priority multiplexer 418 to MUX circuitry 314 in response to a subsequent clock cycle of cache controller 220. For example, in a read operation of CPU 102 on an address that hits main memory element 214, a previous write to the same address may still be in flight (e.g., not fully written to main memory element 214). In this example, latch 402e collects the unwritten data bytes and provides them to MUX 314, which are eventually sent back to CPU 102.

[0122] Instance merging circuit 403a is coupled to latch 402d, merging circuit 403b, arithmetic component 404, atomic comparison component 406, and read-modify-write merging component 408. Instance merging circuit 403b is coupled to merging circuit 403a, priority multiplexer 418, and merging circuit 403c. Instance merging circuit 403c is coupled to merging circuit 403b and latch 402b. Instance merging circuits 403a-c facilitate comparisons of read operations in different segments of the main cache queue 212 to potentially reroute write operations to be merged with write operations corresponding to the same memory address location, as further described below. Although Figure 4A The example includes three merging circuits 403a-c, but additional merging circuits may exist to merge write operations from other segments of the main cache memory queue 212 (e.g., merging circuits that couple the output of latch 402d to the outputs of latch 402b and / or latch 402a, etc.). In some instances, merging circuits 403a-c are combined into a single circuit for comparing write operations from different latches 402b-d and rerouting based on matching memory addresses in any two or more of the different latches 402b-d.

[0123] exist Figure 4A In the example shown, arithmetic component 404 is coupled to latch 402c, first multiplexer 410, and ECC logic 310 to perform arithmetic operations (e.g., increment, decrement, etc.) on data from main memory 214. Furthermore, arithmetic component 404 performs histogram operations on the data stored in main memory 214. Figure 4A The example arithmetic component 404 shown is implemented by logic circuitry, such as a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of it, such as one or more analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable logic devices (FPLDs), digital signal processors (DSPs), etc. The operation of the example arithmetic component 404 is further described below.

[0124] exist Figure 4A In the example shown, atomic comparison component 406 is coupled to latch 402c, first multiplexer 410 and ECC logic 310 to compare data and a key at a memory address and replace the data if the data at the memory address matches the key. Figure 4AThe example atomic comparison component 406 shown is implemented by logic circuitry, such as a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of it, such as one or more analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable logic devices (FPLDs), digital signal processors (DSPs), etc. The operation of the example atomic comparison component 406 is further described below.

[0125] exist Figure 4A In the example shown, a read-modify-write merging component 408 is coupled to latch 402c, first multiplexer 410, and ECC logic 310 to facilitate read, modify, and / or write instructions sent by cache controller 220. For example, read-modify-write merging component 408 is coupled to ECC logic 310 to obtain the currently stored word that will be affected by the read, modify, and / or write instruction. In the example write operation, read-modify-write merging component 408 is configured to update the currently stored word obtained from ECC logic 310 with new bits, bytes, etc., obtained from latch 402c. Further description of read-modify-write merging component 408 is described below. Figure 4A The instance read-modify-write merging component 408 in the illustrated example is implemented by logic circuitry, such as a hardware processor. However, any other type of circuitry can be used alternatively or in lieu of such logic circuitry, such as one or more analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable logic devices (FPLDs), digital signal processors (DSPs), etc.

[0126] Example: The first multiplexer 410 is coupled to the arithmetic component 404, the atomic comparison component 406, and the read-modify-write merging component 408 to transfer the output of the arithmetic component 404, the atomic comparison component 406, or the read-modify-write merging component 408 to the latch 402d based on an instruction from the cache controller 220. For example, in the case where the cache controller 220 instructs the execution of a write function (e.g., the cache controller transmits a write request to the latch 402b), an instruction is sent by the cache controller 220 to the first multiplexer 410 to select the input connected to the read-modify-write merging component 408 to be transferred to the latch 402d. Figure 4A The example of the first multiplexer 410 shown is implemented by logic circuitry, for example, a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of such implementation, such as one or more analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable logic devices (FPLDs), digital signal processors (DSPs), etc.

[0127] exist Figure 4A In the example shown, ECC generator 412 is coupled to latch 402d and merging circuitry 403a to facilitate error detection and correction of values ​​(e.g., bytes, bits, etc.) stored in latch 402d. For example, ECC generator 412 is configured to regenerate ECC (e.g., generate error detection code) values ​​that will be stored with data (e.g., the merged word output from read-modify-write merging component 1108). The ECC values ​​are used by error detection and correction circuitry to determine whether an error has occurred during read and / or write operations, as further described above. Figure 4A The example ECC generator 412 shown is implemented by logic circuitry, such as a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of it, such as one or more analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable logic devices (FPLDs), digital signal processors (DSPs), etc.

[0128] exist Figure 4A In this configuration, instance arbitration manager 414 is coupled to latches 402a and 402b, the pending memory address data storage area 416, and main memory area 214 to facilitate read, modify, and / or write instructions received from cache controller 220. For example, in the case of receiving a write instruction from cache controller 220, arbitration manager 414 is configured to transfer the corresponding read instruction for the currently stored word to main memory area 214. Additionally, arbitration manager 414 is coupled to main memory area 214 to arbitrate conflicting accesses to main memory area 214. When multiple operations attempt to access main memory area 214 in the same cycle, arbitration manager 414 may select the operations permitted to access main memory area 214 according to a priority scheme. Suitable priority schemes are described in more detail below; however, in one instance, arbitration prioritizes read operations over write operations because write data in main cache storage queue 212 is available for subsequent operations, even before it is written to main memory area 214. Therefore, the performance impact is minimal when write data is allowed to wait in the main cache queue 212. However, when the main cache queue 214 is full of write data that has not yet been written back, the priority of write operations can be increased until they take precedence over competing read operations.

[0129] Figure 4AThe instance arbitration manager 414 in the illustrated example is implemented by logic circuitry, such as a hardware processor. However, any other type of circuit system may be used alternatively or in lieu of such implementation, such as one or more analog or digital circuits, logic circuits, programmable processors, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable logic devices (FPLDs), digital signal processors (DSPs), etc.

[0130] exist Figure 4A In this example, the pending memory address data storage area 416 is configured to store the addresses of read, modify, and / or write instructions obtained from the cache controller 220. In this manner, the pending memory address data storage area 416 maintains an address record associated with each value stored in any of the latches 402a, 402b, 402c, 402d, 402e and / or the merging circuits 403a, 403b, and / or 403c. Figure 4A The instance-to-be-processed memory address data storage area 416 in the illustrated example can be implemented by any device used for storing data, such as flash memory, magnetic media, optical media, etc. Furthermore, the data stored in the instance-to-be-processed memory address data storage area 416 can be in any data format, such as binary data, comma-separated data, tab-separated data, Structured Query Language (SQL) structures, etc.

[0131] Instance priority multiplexer 418 is coupled to latches 402b, 402c, 402d, and merging circuitry 403a to facilitate read operations when latches 402b, 402c, 402d, or merging circuitry 403a are storing values ​​corresponding to write instructions. For example, the cache controller may initiate four write instructions for a four-byte word with addresses A3, A2, A1, and A0: write address A0 with byte 0x11, write address A1 with byte 0x22, write address A3 with byte 0x23, and write address A0 with byte 0x44. In this example, when the cache controller 220 initiates a read instruction to read all four bytes, the priority multiplexer 418 is configured to obtain the byte value 0x11 stored in the merging circuit 403a, the byte value 0x22 stored in the latch 402d, the byte value 0x23 stored in the latch 402c, and the byte value 0x22 stored in the latch 402b. Furthermore, the address data storage area 416 to be processed transmits an instruction to the priority multiplexer 418 indicating which address value is associated with the byte value stored in the latches 402b, 402c, 402d, and merging circuit 403a. In this example, because the byte value stored in latch 402b is associated with address A0 and the byte value stored in merging circuit 403a is also associated with address A0, priority multiplexer 418 is configured to transmit a packet to latch 402e indicating that address A0 is 0x44 (e.g., a recent write instruction associated with address A0), address A1 is 0x22, and address A3 is 0x23.

[0132] In this way, the MUX circuit 314 is configured to update the value of the currently stored word with the byte value obtained from the priority multiplexer 418. This operation ensures that read instructions transmitted by the main cache queue 212 are likely to point to the correct word, even if write instructions may not have fully propagated through the main cache queue 212.

[0133] An instance read path (e.g., a read input to tag RAM 208) can operate in parallel with the main cache queue 212. Because read operations (e.g., read instructions) can reference data that may not yet be completed in write operations (e.g., write instructions), the main cache queue 212 may include write forwarding functionality, allowing the read path to obtain data from the main cache queue 212 that has not yet been written back to main memory 214. In this instance, the main cache queue 212 includes: a pending memory address data storage area 416 for recording the addresses of operations at each level of the main cache queue 212; a priority multiplexer 418 for selecting data for forwarding from a level (e.g., a latch) in the main cache queue 212; and a MUX circuit 314 that selects between the output of main memory 214 (via error detection and correction circuit 310) and the forwarded data from the main cache queue 212 from the data priority multiplexer 418.

[0134] Alternatively, because read operations (e.g., read instructions, read commands, etc.) may reference victim (e.g., evicted) data that may not yet be completed in write operations (e.g., write instructions, write commands, etc.), the main cache storage queue 212 includes a read invalidation function that forwards in-flight data (e.g., data in storage queue 212 that has not yet been stored in the main storage element 214) to the victim storage element 214 and / or L2 cache 212 and invalidates the remaining in-flight data in storage queue 212.

[0135] Instance read port 424 is coupled to the read path and data storage area 416. Read port 424 may be implemented by an interface that interfaces with the main cache controller 222 whenever a read miss occurs. For example, read port 424 is used to receive the victim address and a read invalidation command from the main cache controller 222. Read port 424 sends the victim address to data storage area 416 for comparison with the address to be processed stored in data storage area 416.

[0136] The instance write port 426 is coupled to the write path and latch 402a. Write port 426 may be implemented by an interface that interfaces with the main cache controller 222 (e.g., cache controller 220) to obtain write instructions. For example, write port 426 is used to receive an address and value from cache controller 220 for writing.

[0137] Figure 4A The elements are arranged in a way that represents a transaction flow. The time elements are represented by levels E1-E5. Each level represents a discrete time period, and in some instances, each level represents one clock cycle or an integer number of clock cycles.

[0138] An example flow of a read operation via main cache storage queue 212 will now be described. In the first cycle corresponding to level E1, L1 data cache 110 retrieves the record associated with the address of the read operation from tag RAM 208 to determine whether the data is stored in main memory 214. In the direct-mapped instance, L1 data cache 110 does not need to wait for tag RAM 208 comparison before requesting data from main memory 214, and therefore, the comparison between tag RAM 208 for the address of the read operation and the record at the cached address can be extended to the second or third clock cycle.

[0139] In the second cycle corresponding to level E2, if the arbitration manager 414 permits, the L1 data cache 110 may request data and ECC check bits from the main memory area 214. During this cycle, the L1 data cache 110 may also determine if newer data in the main cache queue 212 is available by comparing the read address with the pending memory address in the data storage area 416. If so, the priority multiplexer 418 is configured to forward the appropriate data from the main cache queue 212.

[0140] Data and ECC may be provided by the main cache memory 214 in the third cycle corresponding to level E3. However, this data may or may not correspond to the memory address specified in the read operation, because the L1 data cache 110 may allocate multiple extended memory addresses to the same entry in the main cache memory 214. Therefore, in the third cycle, the L1 data cache 110 determines whether the data and ECC provided from the main cache memory 214 correspond to the memory address in the read operation (e.g., a cache hit) based on a comparison recorded in the tag RAM 208. In the case of a cache hit, the data and ECC bits are received by the error detection and correction circuit 310, which corrects any errors in the data in the fourth cycle corresponding to level E4.

[0141] As described above, newer data that has not yet been written to main memory 214 may reside in main cache queue 212 and may be forwarded from main cache queue 212 via priority multiplexer 418. If so, MUX circuitry 314 selects the forwarded data instead of the corrected data from main memory 214.

[0142] Corrected data from main storage 214 or forwarded data from main cache queue 212 is provided to L1 data cache 110 in the fifth cycle corresponding to level E5. In this way, if there are cache hits in approximately 5 cycles, controller 220 can provide the data with a full ECC check and correction.

[0143] If the data and ECC bit are not present in main memory 214 (e.g., cache miss), main cache storage queue 212 may remain blocked until the data can be retrieved from extended memory 106 and / or victim memory 218, at which point the data can be written to main memory and tag RAM 208 can be updated.

[0144] Used to facilitate fully pipelined reads in Level 1 data caches using storage queues and data forwarding - Modified - Supported methods and devices for writing

[0145] In the example described herein, there are two cascaded cache systems (e.g., main memory 214 and victim cache memory 218). In the example described herein, main memory 214 is a directly mapped cache element and victim cache memory 218 is a fully associative cache memory. Both the directly mapped main memory 214 and the fully associative victim cache memory 218 are protected by error correction codes (ECC). Therefore, the example application involves reading lines from and / or moving lines from main memory 214. Consequently, the ECC logic will correct the cache lines and regenerate the ECC checksums before writing the lines to victim cache memory 218. This application can utilize two additional clock cycles of the CPU (e.g., one clock cycle for error correction performed by the ECC logic and another clock cycle for ECC checksum regeneration). To reduce this latency, the example described herein includes using the same parity block size between main memory 214 and victim cache memory 218. Therefore, both main memory 214 and victim cache memory 218 calculate and / or otherwise determine parity on the 32-bit boundaries. In this way, L1 cache 110 can move cache lines directly from main memory 214 to victim cache memory 218 with less latency.

[0146] In the examples described herein, the L1 data cache 110 supports multiple operations that read data from the cache and modify the data before rewriting it. For example, the L1 data cache 110 may support read-modify-write operations. A read-modify-write operation reads existing data and overwrites at least a portion of it. In ECC embodiments, the read-modify-write operation may be performed when writing less than the full group width (e.g., when writing a 32-bit 4-byte word). The reason for using the read-modify-write read functionality is that the portion of data in the group that will not be overwritten still contributes to the ECC check bits.

[0147] Read-modify-write operations can be divided into write operations and read operations, and the main cache queue 212 can be configured such that read operations in the read path are synchronized with write operations in the main cache queue 212. Read and write operations remain synchronized until the read-modify-write merging component 408 overwrites at least a portion of the read data with the write data, resulting in merged data. The merged data is provided to the ECC generator 412, which generates new ECC checksums for the merged data. The merged data and ECC checksums can then be provided to the arbitration manager 414 for storage in the main memory area 214.

[0148] In instance read-modify-write operations Figure 2 The cache controller 220 and / or 3 transmit a write request indicating a subset of bytes or the entire word (e.g., the first set of data) to be written. In this example, the write request transmitted via the cache controller 220 includes the address value of the byte to be written and the data to be written to the indicated byte. For example, Figure 2 The main memory area 214 of 214 and / or 3 may contain a four-byte word 0x12345678 associated with addresses A3, A2, A1, and A0. In this example, address A3 corresponds to byte 0x12 of the stored word, address A2 corresponds to byte 0x34, address A1 corresponds to byte 0x56, and address A0 corresponds to byte 0x78. In this example operation, the cache controller 220 may transmit the following write requests: replacing address A3 with byte 0x33 of the currently stored word 12345678, replacing address A1 with byte 0x22, and replacing address A0 with byte 0x11. In this example, a first write request that replaces the address A3 of the stored word with byte 0x33 will make the stored word 0x33345678, a second write request that replaces the address A1 of the stored word with byte 0x22 will make the stored word 0x33342278, and a third write request that replaces the address A0 of the stored word with byte 0x11 will make the stored word 0x33342211.

[0149] To handle such requests, L1 data cache 110 compares the address of the read operation with the record in tag RAM 208, and the L1 data cache requests data and ECC check bits from main memory 214 and / or main cache queue 212. Because read-modify-write operations modify data, in instances tracking the MESI (modified, exclusive, shared, and invalid) status of entries in main memory 214, a cache hit that is not in a modified or exclusive state can be considered a cache miss. Once data in the correct state is obtained and any errors are corrected, it is provided to read-modify-write merging component 408. In the same cycle, read-modify-write merging component 408 can overwrite at least a portion of the corrected data with the write data to produce merged data. ECC generator 412 generates new ECC check bits for the merged data.

[0150] In the example described herein, the ECC generator 412 operates at the word granularity. Therefore, the ECC generator 412 calculates the ECC checksum for the data block. In the example described herein, the data block may be four bytes (e.g., a word). The main cache storage queue 212 processes write instructions at the first instance cycle (e.g., completing the first write request to replace address A3 with byte 0x33), because the ECC generator 412 operates at the word granularity (e.g., 4-byte or 32-bit word), and the cache controller 220 initiates a read request for the currently stored word at address A3. In this example, the byte and address (e.g., 0x33 and A3) in the first write request are stored in latch 402b. Additionally, the cache controller 220 transmits the entire current storage word read request to main storage 214. Therefore, at the end of the first cycle, the entire current storage word read request is transmitted to main storage 214, and byte 0x33 is stored in the first latch 402b.

[0151] At the second cycle of the instance (e.g., completing a second write request to replace address A1 with byte 0x22), the byte from the first write request is transferred to latch 402c, the entire current storage word is transferred from main memory 214 to ECC logic 310, and the second write request (e.g., replacing address A1 with byte 0x22) is transferred via cache controller 220 to be stored in latch 402b. During the second cycle, read-modify-write merging component 408 obtains the byte stored in latch 402c, and the entire current storage word is transferred via ECC logic 310. In this way, read-modify-write merging component 408 identifies the address of the byte to be updated in the current storage word. Once the read-modify-write merging component 408 identifies and / or otherwise obtains: (a) the value (e.g., byte value, bit value, etc.) of the portion of the current storage word to be updated from latch 402c and (b) the current storage word from ECC logic 310, the read-modify-write merging component 408 writes a portion of the current storage word having the value obtained from latch 402c (e.g., replacing a portion of the current storage word with said value, merging a portion of the current storage word with said value, etc.). For example, the read-modify-write merging component 408 writes the value of a portion of a word to the address value corresponding to the portion of the word in the word. This instance of the written portion output by the read-modify-write merging component 408 may be referred to herein as a merged word. In some instances described herein, such a merged word is provided by the read-modify-write merging component 1108 for writing to the victim storage area 218.

[0152] In response, to initiate the write portion of the instance read-modify-write operation, selector multiplexer 410 transmits the merged word from read-modify-write merging component 408 for storage in latch 402d. In a subsequent clock cycle, ECC generator 412 obtains the merged word from latch 402d and generates the corresponding ECC checksum bit. In the same or subsequent clock cycles, ECC generator 412 transmits the merged word via merging circuits 403a, 403b, and 403c for processing by arbitration manager 414, thereby storing it in main memory 214.

[0153] However, in the example described above, because the cache controller 220 transmits three consecutive write instructions corresponding to the same stored word in main memory 214, the read-modify-write merging component 408 can merge these three write instructions into a single transaction when writing the three values ​​of the three write instructions to the current stored word. For example, before storing the merged word from the first write instruction in main memory 212, the main memory queue 212 feeds back (e.g., transmits) the merged word for use in a subsequent second write instruction.

[0154] Figure 4B It is a combination Figures 3A-4A An example circuit implementation of the instance data forwarding logic 460 implemented in the main cache storage queue 212. Although Figure 4B The instance data forwarding logic 460 is described as being implemented in conjunction with the main cache storage queue 212, but in other instances described herein, Figure 4B Any of the instances described can be implemented in conjunction with the victim cache storage queue 216.

[0155] exist Figure 4B In this instance, instance address line 462 (RD_ADDR) is coupled to cache controller 220 to obtain instance read instructions from CPU 102. Figure 4B In this instance, address line 462 receives a read instruction from main cache queue 212. In this way, main cache queue 212 can forward any data from in-flight write transactions while executing a read instruction from CPU 102. In main cache queue 212, instructions from CPU 102 (e.g., read instructions and / or other transactions, and / or write instructions and / or other transactions) contain an address, byte enable, and associated data. Figure 4B The topology includes an instance address storage area 464a (e.g., the unprocessed memory address data storage area 416 in Figure 4), an instance byten storage area 464b (e.g., a byte-enabled storage area), and an instance data storage area 464c (e.g., any one of latches 402a, 402b, 402c, etc.). Figure 4B In the address storage area 464a, address addr0 corresponds to the earliest read and / or write instruction in the main cache storage queue 212, and address addr3 corresponds to the latest read and / or write instruction in the main cache storage queue 212.

[0156] The address passed via address line 462 (e.g., a read instruction) is compared with all addresses (e.g., addr0, addr1, addr2, and addr3) in address memory 464a by instance comparison logic 466. In the example described herein, comparison logic 466 can compare the address of the read instruction with any number of entries, since addresses addr0, addr1, addr2, and addr3 can be completely or partially equivalent (e.g., identical). In this way, the instance output of comparison logic 466 is a 4-bit signal. This 4-bit signal is generated based on the corresponding byte enable signal in the byte memory 464b. This 4-bit signal can have any value (e.g., all zeros, all one, partially zeros, and partially one, etc.).

[0157] In the example operation, the four addresses of address storage area 464a may contain one or more valid bytes (e.g., logical high bytes). In the example described herein, main cache storage queue 212 is 64 bits (e.g., 8 bytes), and therefore main cache storage queue 212 can perform writes on any number of bytes, such as one to eight bytes.

[0158] In response to comparison logic 466 enabling the identification of the address of the included address memory 464a based on the byte in the byten memory 464b, instance output line 468 transmits the 8-bit result for each address in address memory 464a. In the instance described herein, there are four output lines 468 (e.g., dram_hit_DP0[0][7:0], dram_hit_dp0[1][7:0], dram_hit_dp0[2][7:0], and dram_hit_dp0[3][7:0]). In operation, a bit set to logic high (e.g., 1) in any output line 468 indicates that the corresponding byte at the corresponding address in address memory 464a has valid data to be forwarded. For example, if the first output line in output line 468 contains dram_hit_dp0[0], the byte value of the corresponding read instruction can be obtained from any address in address memory 464a.

[0159] Figure 4B The instance includes instance selection logic 470 and instance selection line 472. In the instance described herein, selection line 472 contains eight 2-byte outputs. Therefore, each corresponding byte in the byten memory area 464c enables one of the presence selection signals. In instance operation, when a read instruction indicates the reading of multiple addresses with multiple enabled bytes, instance selection logic 720 selects the most recent data. Such outputs of selection logic 470 (e.g., selection line 472) control instance multiplexers 474a-474h (multiplexers 474e-h are not shown). Figure 4B In this example, multiplexers 474a-h contain eight 1-byte input terminals. During operation, multiplexers 474a-h obtain their corresponding select lines in select line 472, indicating which byte of each of the data storage areas 464c should be forwarded. In this way, the main cache queue 212 can forward data from different in-flight storage areas (e.g., any one of the data storage areas 464c) based on the order of address comparisons (e.g., comparisons performed by comparator 466), the corresponding byte enable of the byten storage area 464b, and the order in which the main cache queue 212 issues write instructions (e.g., comparisons performed by select logic 470).

[0160] In the example described herein, any one of address line 462, address storage area 464a, byte storage area 464b, data storage area 464c, comparison logic 466, output line 468, selection logic 470, selection line 472, and / or multiplexers 474a-h may be implemented in the victim cache storage queue 216. Figure 4B In this configuration, the output terminals of multiplexers 474a-h are coupled to instance cache multiplexer 476. Figure 4B In this instance, cache multiplexer 476 is also coupled to a similar multiplexer implemented in this manner in association with victim cache storage queue 216. In operation, cache multiplexer 476 receives a selection signal from a cache controller (e.g., main cache controller 222 or victim cache controller 224) that has transmitted a read instruction. In this way, cache multiplexer 476 facilitates data forwarding to CPU 102.

[0161] In some instances, Figure 4B The topology can correspond to the instance write data forwarding component of the main cache storage queue 212, the write data forwarding component of the victim cache storage queue 216, and the MUX circuits 314, 316. In this example, the cache multiplexer 476 can be implemented by the instance MUX circuits 314, 316. Furthermore, in this example, any one of address line 462, address storage area 464a, byte storage area 464b, data storage area 464c, comparison logic 466, output line 468, selection logic 470, selection line 472, and / or multiplexers 474a-h can be implemented by an instance of the main cache storage queue 212 written into the data forwarding component. The address line 462, address storage area 464a, byte storage area 464b, data storage area 464c, comparison logic 466, output line 468, selection logic 470, selection line 472, and / or multiplexers 474a-h implemented in association with the victim storage area 216 can be implemented by an instance of the victim cache storage queue 216 written into the data forwarding component.

[0162] In some instances, Figure 4B The topology can correspond to the pending memory address data storage area 418 and the instance priority multiplexer 418. For example, address storage area 464a, byten storage area 464b, and / or data storage area 464c can be implemented by the instance pending memory address data storage area 416. In another instance, any one of address line 462, comparison logic 466, output line 468, selection logic 470, selection line 472, and / or multiplexers 474a-h can be implemented by the instance priority multiplexer 418.

[0163] In the examples described in this article, Figure 4BThe topology is used for each group of primary storage area 214 and victim storage area 218. For example, if primary storage area 214 has 8 groups, then Figure 4B The topology will be replicated 8 times, once for each group.

[0164] This document describes instance methods, devices, systems, and artifacts that facilitate fully pipelined read-modify-write support in Level 1 data caching using storage queues and data forwarding. Other instances and combinations thereof include the following:

[0165] Example 1 includes a device comprising a first storage area, a second storage area, and a storage queue coupled to the first storage area and the second storage area, the storage queue being configured to receive a first memory operation specifying a first set of data, process the first memory operation to store the first set of data in at least one of the first storage area and the second storage area, receive a second memory operation, and feed back the first set of data for use in the second memory operation before storing the first set of data in the at least one of the first storage area and the second storage area.

[0166] Example 2 includes the device according to Example 1, wherein the second memory operation is a read-modify write operation and specifies a second set of data, and the storage queue is available for merging the first set of data and the second set of data to produce a third set of data before storing the first set of data in at least one of the first storage area and the second storage area, and providing the third set of data for storage in at least one of the first storage area and the second storage area.

[0167] Example 3 includes the device according to Example 2, further including a third memory operation for receiving an instruction to read the third set of data.

[0168] Example 4 includes the device according to Example 1, wherein the second storage area is configured as a victim storage area of ​​the first storage area.

[0169] Example 5 includes the device according to Example 1, wherein the storage queue further includes a data storage area configured to store a first address value of the first set of data.

[0170] Example 6 includes the device according to Example 1, wherein the storage queue further includes an error code correction generator to generate error detection codes.

[0171] Example 7 includes the device according to Example 6, wherein the error code correction generator generates the error detection code in response to processing the first memory operation.

[0172] Example 8 includes a method comprising receiving a first memory operation specifying a first set of data, processing the first memory operation to store the first set of data in at least one of a first storage area and a second storage area, receiving a second memory operation, and transmitting the first set of data for use in the second memory operation before storing the first set of data in the at least one of the first storage area and the second storage area.

[0173] Example 9 includes the method according to Example 8, wherein the second memory operation is a read-modify-write operation that specifies a second set of data, and the method further includes merging the first set of data and the second set of data to produce a third set of data before storing the first set of data in at least one of the first storage area and the second storage area, and providing the third set of data to be stored in at least one of the first storage area and the second storage area.

[0174] Example 10 includes the method according to Example 9, further including a third memory operation that receives an instruction to read the third set of data.

[0175] Example 11 includes the method according to Example 8, wherein the second storage area is configured as a victim storage area of ​​the first storage area.

[0176] Example 12 includes the method according to Example 8, further including a first address value for storing the first set of data.

[0177] Example 13 includes the method according to Example 8, further including generating an error detection code.

[0178] Example 14 includes the method according to Example 13, further comprising generating the error detection code in response to processing the first memory operation.

[0179] Example 15 includes a system comprising: a central processing unit configured to transmit a first memory operation and a second memory operation; a first storage area coupled to the central processing unit; a second storage area coupled to the central processing unit; and a storage queue coupled to the first storage area, the second storage area, and the central processing unit, the storage queue being configured to receive the first memory operation specifying a first set of data, process the first memory operation to store the first set of data in at least one of the first storage area and the second storage area, receive the second memory operation, and, before storing the first set of data in at least one of the first storage area and the second storage area, feed back the first set of data for use in the second memory operation.

[0180] Example 16 includes the system according to Example 15, wherein the second memory operation is a read-modify-write operation and specifies a second set of data, and the storage queue is available for merging the first set of data and the second set of data to produce a third set of data before storing the first set of data in at least one of the first storage area and the second storage area, and providing the third set of data for storage in at least one of the first storage area and the second storage area.

[0181] Example 17 includes the system according to Example 16, further including a third memory operation that receives an instruction to read the third set of data.

[0182] Example 18 includes the system according to Example 15, wherein the second storage area is configured as a victim storage area of ​​the first storage area.

[0183] Example 19 includes the system according to Example 15, wherein the storage queue further includes a data storage area configured to store a first address value of the first set of data.

[0184] Example 20 includes the system according to Example 15, wherein the storage queue further includes an error code correction generator to generate an error detection code in response to processing the first memory operation.

[0185] Methods and devices for reducing read-modify-write cycles of misaligned writes.

[0186] When issuing write instructions to multiple memory banks, such write instructions can be transmitted along with corresponding read instructions, attempting to execute a complete read-modify-write cycle regardless of the size of the write instruction. For example, in such applications, the CPU might receive a write instruction instructing the writing of 128 bits starting at address A0 of the first memory bank across two 64-bit memory banks. In this example, although both instance memory banks are fully written, such applications maintain read instructions to read the data currently stored in said two instance memory banks. However, such methods are inefficient because they use twice the processing power (e.g., write and read instructions). Furthermore, such methods do not provide any control logic and / or processing circuitry to analyze the write instructions.

[0187] exist Figure 4AIn the example shown, main memory 214 and / or victim memory 218 can be multiple memory groups. For example, main memory 214 may contain sixteen memory groups (e.g., sixteen sub-RAMs), each 64 bits wide. In this example, when cache controller 220 transmits a write instruction to write all 64 bits of the first group to main memory 214 (e.g., write a 64-bit word starting from the first address of the first group), the write instruction can be executed without initiating a read instruction. For example, group processing logic 303 can detect that such a write to the entire group is about to be performed and thus instruct cache controller 220 to initiate a read-modify-write operation, rejecting the transmission of the read instruction.

[0188] Similarly, when cache controller 220 transmits write instructions to write all 128 bits of the first and second groups of main memory 214 to write port 426 (e.g., a write instruction indicating to write a 128-bit word starting at the first address of the first group and ending at the last address of the second group), the write instructions can be executed without initiating a read instruction. For example, group processing logic 303 can detect that such writes to all groups are about to be performed and thus instruct cache controller 220 to initiate a read-modify-write operation, rejecting the transmission of read instructions.

[0189] However, in some instances described herein, cache controller 220 may transmit a write instruction that writes 130 data bits (or any write instruction indicating a write to a subset of the memory bank). Of the 130 data bits, 64 data bits may be written to the first bank, 64 data bits may be written to the second bank, and 2 data bits may be written to the third bank of the main memory (e.g., a write instruction indicating a 130-bit word to be written starting at a first address in the first bank and ending at a second address in the third bank). In this instance, bank processing logic 303 detects that all addresses in the first and second banks of the main memory 214 will be fully written, and therefore instructs the cache controller to initiate a read-modify-write operation on the first and second banks of the main memory, rejecting the transmission of the read instruction. In this instance, bank processing logic 303 may detect (e.g., determine) that a subset of the memory bank of the main memory 214 (e.g., the third bank of the memory bank) will be partially written (e.g., two addresses out of 64 addresses will be written), and therefore instructs cache controller 220 to initiate a full read-modify-write operation on the third bank of the main memory 214. In the examples described herein, group processing logic 303 determines whether to allow a read operation (e.g., whether to initiate a full read-modify-write operation) in response to a write operation based on whether the number of addresses in a subset of the plurality of memory groups to be written meets a threshold. In the examples described herein, the threshold is not met when the number of addresses in the subset of the plurality of memory groups is greater than 0 and / or less than the number of addresses in the memory groups. In this example, group processing logic 303 generates a write instruction to CPU 102 as an indication to execute a write instruction as a full read-modify-write transaction. In the examples described herein, the threshold is met when the number of addresses in the subset of the plurality of memory groups is equal to the number of addresses in the memory groups. In this example, group processing logic 303 generates a write instruction to CPU 102 as an indication to execute a write instruction as a partial read-modify-write transaction (e.g., deny a read). Examples of read-modify-write operations are described above.

[0190] This document describes example methods, devices, systems, and artifacts for reducing read-modify-write cycles in misaligned writes. Other examples and combinations thereof include the following:

[0191] Example 1 includes a device comprising: a memory containing a plurality of memory groups; an interface configured to be coupled to a central processing unit for receiving write operations from the central processing unit, wherein the write operations are writes to a subset of the plurality of memory groups; and group processing logic coupled to the interface and the memory, the group processing logic being configured to determine, based on the write operations, the subset of the plurality of memory groups to be written to, and, in response to the write operations, determine whether to perform a read operation based on whether the number of addresses in the subset of the plurality of memory groups to be written to meets a threshold.

[0192] Example 2 includes the device according to Example 1, wherein the threshold is satisfied when all addresses of at least one of the plurality of memory groups are included in the write operation.

[0193] Example 3 includes the device according to Example 1, wherein the group processing logic generates a second instruction to the central processing unit when the number of addresses of at least one of the plurality of memory groups to be written does not meet the threshold, so as to perform the write operation to at least one of the plurality of memory groups that issued the read operation.

[0194] Example 4 includes the device according to Example 1, wherein the group processing logic determines the number of memory groups to be written based on the write operation by determining the total number of addresses contained in the write operation and determining the number of memory groups based on the addresses contained in the total number of addresses.

[0195] Example 5 includes the device according to Example 1, wherein the write operation indicates the number of the plurality of memory groups to be rewritten.

[0196] Example 6 includes the device according to Example 1, wherein the plurality of memory groups are sixteen memory groups.

[0197] Example 7 includes the device according to Example 1, wherein the memory is a victim storage area.

[0198] Example 8 includes a system comprising: a central processing unit configured to generate write operations indicative of writes to a subset of a plurality of memory groups; a victim memory area containing the plurality of memory groups; and group processing logic coupled to the central processing unit and the victim memory area, the group processing logic being configured to determine, based on the write operations, the subset of the plurality of memory groups to be written to, and, in response to the write operations, determine whether to perform a read operation based on whether the number of addresses in the subset of the plurality of memory groups to be written to meets a threshold.

[0199] Example 9 includes the system according to Example 8, wherein the threshold is satisfied when all addresses of at least one of the plurality of memory groups are included in the write operation.

[0200] Example 10 includes the system according to Example 8, wherein the group processing logic generates a second instruction to the central processing unit when the number of addresses of at least one of the plurality of memory groups to be written does not meet the threshold, to perform the write operation to at least one of the plurality of memory groups that issued the read operation.

[0201] Example 11 includes the system according to Example 10, wherein the central processing unit is further configured to generate read-modify-write operations in response to the second instruction for execution by at least one of the plurality of memory banks.

[0202] Example 12 includes the system according to Example 8, wherein the group processing logic determines the number of memory groups to be written based on the write operation by determining the total number of addresses contained in the write operation and determining the number of memory groups based on the addresses contained in the total number of addresses.

[0203] Example 13 includes a method comprising determining a subset of multiple memory groups to be written based on a write operation, and determining whether to perform a read operation in response to the write operation based on whether the number of addresses in the subset of the multiple memory groups to be written meets a threshold.

[0204] Example 14 includes the method according to Example 13, further comprising transmitting an indication to a central processing unit in response to the threshold being met.

[0205] Example 15 includes the method according to Example 13, wherein the threshold is satisfied when all addresses of at least one of the plurality of memory groups are included in the write operation.

[0206] Example 16 includes the method according to Example 13, further comprising generating a second instruction to perform the write operation to at least one of the plurality of memory groups that issued the read operation when the number of addresses of at least one of the plurality of memory groups to be written does not meet the threshold.

[0207] Example 17 includes the method according to Example 13, wherein determining the number of the plurality of memory groups to be written is performed by: determining the total number of addresses contained in the write operation, and determining the number of the plurality of memory groups based on the addresses contained in the total number of addresses.

[0208] Example 18 includes the method according to Example 13, wherein the write operation indicates the number of the plurality of memory groups to be rewritten.

[0209] Example 19 includes the method according to Example 14, further comprising obtaining the write operation from the central processing unit, the write operation indicating the number of the plurality of memory groups to be written.

[0210] Example 20 includes the method according to Example 14, wherein the memory is a victim storage area.

[0211] Aggressive write merging to reduce group pressure

[0212] exist Figure 4A In this example, instance main cache queue 212 stores several write operations at different sections of main cache queue 212 (e.g., at instance latches 402a-e). For example, when CPU 102 transmits three separate write operations in a row, the first write operation provided by CPU 102 is stored at first latch 402b, and moves to second latch 402c when a second operation is received at first latch 402b. Therefore, after receiving the three write operations, first latch 402b will store and / or output the last write operation in time (e.g., its last storage in main memory 214), second latch 402c will have the second write operation (e.g., its second storage in main memory 214), and third latch 402d will have the first write operation (e.g., its first storage in instance main memory 214). Whenever data in the main cache queue 212 is to be stored in the main memory 214, the instance arbitration manager 414 reserves a period for data to be written to the instance main memory 214. Therefore, during the reserved period, the main memory 214 may not be available for read operations. However, if two or more data operations stored in latches 402b, 402c, 402d correspond to the same memory address, the data can be merged so that the data is written to the memory address of the main memory 214 once, instead of twice or three times. For example, if a write operation stored in latch 402d corresponds to writing a byte to a memory address and a write operation stored in latch 402c corresponds to writing the same byte to a memory address, the second write will overwrite the first write.

[0213] The main cache queue 212 merges two writes into a single write, allowing only one cycle to be used to write the second transaction (e.g., eliminating the need to reserve a cycle for the first write), instead of reserving a cycle to write the first byte into main memory 214, which will be overwritten in a subsequent cycle. This aggressive merging reduces the number of cycles reserved for write operations. In this way, main memory 214 will have an extra cycle to perform read operations, thereby reducing overall system latency.

[0214] To aggressively merge write operations to the same memory address, the outputs of instance latches 402b-402d are coupled to instance merging circuits 403a-403c. For example, the output of the third latch 402d may be coupled to merging circuit 403a, the output of the second latch 402c may be coupled to merging circuit 403b, and the output of the first latch 402b may be coupled to merging circuit 403c. The output of merging circuit 403a may also be coupled to the output of the second latch 402c and merging circuit 403b, merging circuit 403b may be coupled to merging circuit 403c, and merging circuit 403c may be coupled to the input of the first latch 402b. Alternatively, additional comparator circuitry may be present for comparing the outputs of another set of latches (e.g., a comparator circuitry for comparing the output of latch 402b with the output of latch 402d). Instance merging circuits 403a-c include instance comparator 420 and instance switch 422.

[0215] Comparator 420 compares the memory address locations of each write operation stored in the respective latches 402b-402d to determine whether any write operation in the instance memory queue corresponds to the same memory address. Instance comparator 420 can be a single comparator comparing all write operations of latches 402b-402d, or a separate comparator 420 comparing two of latches 402b-d (e.g., a first comparator comparing the memory address of latch 402b with the memory address of latch 402c, a second comparator comparing the memory address of 402b to the memory address of latch 402d, etc.). Comparator 420 outputs the comparison result (e.g., using one or more signals corresponding to the one or more comparisons) to instance switch 422 and / or arbitration manager 414. If instance arbitration manager 414 receives a signal indicating a match, arbitration manager 414 will not retain the cycle used for the first write operation, and the first write operation is merged with the second write operation into the same memory location (e.g., releasing the cycle used for other cache operations).

[0216] Instance switch 422 reroutes write operations in instance latches 402b-402d based on comparison. For example, if the memory address of a write operation stored in instance latch 402d is the same as the memory address stored in latch 402c, instance switch 422 enables and / or disables rerouting the output of latch 402d to latch 402c instead of to instance arbitration manager 414. In this way, the two write operations are combined and written to main memory 214 as a single write operation in subsequent cycles instead of two write operations. Switch 422 can be an electrical switch, a transistor (e.g., MOSFET), a demultiplexer, and / or any other component that can reroute signals in the circuit.

[0217] When one of the MUXs in the merging circuits 403a-c receives a rerouted write operation, the MUX executes a merging protocol for the one or more rerouted write operations, prioritizing the latest write operation. For example, if comparator 420 determines that a write operation stored in instance latch 402c corresponds to the same memory address as a write operation stored in instance latch 402d, then the MUX of comparator 420 merges the data (such as combined) Figure 4D (Further description), and switch 422 reroutes the merged write operations stored in instance latch 402d to latch 402c. In this example, if a write operation in instance latch 402c corresponds to writing data to byte 0 and byte 2 of memory address and a write operation from latch 404d corresponds to writing data to byte 0 and byte 1, then instance merging circuit 403a merges the two write operations to retain the write data stored in latch 402c (e.g., writes to byte 0 and byte 2) and includes non-overlapping write data from latch 402d (e.g., byte 2). In this example, as part of the merging operation, merging circuit 403a discards the write data of byte 0 from latch 404d because the data to be written to byte 0 of latch 404d will be overwritten by the write instruction of latch 402c. Therefore, in the above example, the merged data corresponds to the write data of byte 0 from latch 402c, the write data of byte 1 from latch 404d, and the write data of byte 2 from latch 402c. When subsequent write operations are added to the main cache storage queue 212, the merged write data from latch 402c can be manipulated (e.g., via one of instance blocks 404, 406, 408) and / or pushed to the next latch 402d for storage in instance main memory 214 during subsequent cycles. An instance hardware implementation of the merging protocol is described below in conjunction with... Figure 4D Further description.

[0218] Figure 4D Show Figure 4A The merging circuit 402c and / or Figure 11A A hardware implementation of 1102c (e.g., for merging data from latch 402d into latch 402c). Similar hardware setups may be implemented to merge data between any two latches. Figure 4D The instance includes instance latches (e.g., memory areas) 402b-402d and is used for... Figure 4A The hardware components of comparator 420 and switch 422. Example comparator circuit 420 includes comparator and / or logic gates 480a-480f, and switch circuit 422 includes OR gate 482 and MUX 484. Although combined... Figure 4A Describe it, but if combined Figure 11A The description of the victim cache storage queue 216 allows for the use of... Figure 11A The latches 1102a-d, the instance comparator 1120, and the instance switch 322.

[0219] exist Figure 4D In one instance, instance latch 402d outputs the stored data to instance storage (e.g., via arbitration managers 414, 1114 to main storage 214 or victim storage 218), which locks its group during the first cycle. Figure 4D This illustrates how, when writing old data to a group of memory areas merged together, the old data is locked to the same address before another memory area / latch containing the newly written data. Although... Figure 4C The example illustrates the merging between instance latch 402d and instance latch 402c, but a similar structure can be used to merge data between any of latches 402a-402d. For example, if the data address at latch 402d matches the data address at latch 402b, latch 402 can merge its data with the data at latch 402b. Furthermore, if data at three or more latches corresponds to the same address, the data at those three or more latches can be merged into a single latch. As described above, if data at a particular latch is merged with data at a previous latch, the data at that particular latch is invalidated (e.g., by setting bits to correspond to invalidated values) or discarded, so that arbitration is not performed on the data to lock it into a set in memory.

[0220] In operation, instance comparator 480b compares the address of the data at latch 402d with the address of the data at latch 403c. The output of comparator 480b is only valid if both latches 402c and 402d contain bits set to valid. Therefore, instance comparator 480a compares the valid bits from latches 402c and 402d to ensure that all bits are valid. In this way, instance comparator 480d outputs a value (e.g., '1') only when the addresses at latches 402c and 402d are the same and the valid bits at both latches 402c and 402d are valid. Otherwise, instance comparator 480d outputs a second value ('0'). The output of comparator 480d is input to the select line of MUX 484 of switch 422. Therefore, if the addresses of latches 402c and 402d are the same, comparator 480d will control the MUX 484 output of switch 422 to merge the data (e.g., from OR gate 482 of switch 422).

[0221] The instance ADD gate 480c performs a logical AND function with the byte of latch 402d but not with the byte of latch 402c (e.g., using a NOT gate). The output of the instance ADD gate 480c ensures that if a byte is written through both latches 402c and 402d, latch 402c is held and latch 402d is ignored because latch 402c has the most recent memory address issued by CPU 102. Therefore, the instance comparator 480f only outputs the most recent memory address issued by CPU 102 for the address in the memory queue. The output of comparator 480f corresponds to dram_mrg_data_sel[7:0], which is used to select the last merged data between logic gates 402d and 402c byte by byte. Similar merging logic exists when merging the byte of latches 402c and 402d. The signal labeled (1) is used to select between store_byten or (store3_byten merged with store_4_byten), as described above.

[0222] This document describes example methods, apparatuses, systems, and articles of art for facilitating aggressive write merging to reduce group pressure. Other examples and combinations thereof include the following: Example 1 includes an apparatus comprising a first cache store, a second cache store, and a storage queue coupled to at least one of the first cache store and the second cache store and configured to receive a first memory operation, process the first memory operation to store a first set of data in at least one of the first cache store and the second cache store, receive a second memory operation, and merge the first memory operation and the second memory operation before storing the first set of data in at least one of the first cache store and the second cache store.

[0223] Example 2 includes the device according to Example 1, wherein the first memory operation specifies a first set of data, the second memory operation specifies a second set of data, and the storage queue is available for merging the first set of data and the second set of data to produce a third set of data before storing the first set of data in at least one of the first cache storage area and the second cache storage area, and providing the third set of data for storage in at least one of the first cache storage area and the second cache storage area.

[0224] Example 3 includes the device according to Example 2, wherein the storage queue is used to store the third set of data in at least one of the first cache storage area or the second cache storage area in a cycle.

[0225] Example 4 includes the device according to Example 1, wherein the storage queue can be used to merge the first memory operation and the second memory operation by canceling a portion of the first memory operation.

[0226] Example 5 includes the device according to Example 4, wherein the portion of the first memory operation is the byte to be written by the second memory operation.

[0227] Example 6 includes the device according to Example 4, wherein the portion is a first portion, and the storage queue can be used to merge the first memory operation and the second memory operation by holding a second portion of the first memory operation.

[0228] Example 7 includes the device according to Example 6, wherein the second portion of the first memory operation is bytes that are not written by the second memory operation.

[0229] Example 8 includes the device according to Example 1, wherein the first cache storage is a primary cache storage and the second cache storage is a victim cache storage.

[0230] Example 9 includes a system comprising: a central processing unit coupled in parallel to a first cache memory and a second cache memory; and a storage queue coupled to at least one of the first cache memory and the second cache memory, and configured to process a first memory operation from the central processing unit, the first memory operation being configured to store a first set of data in at least one of the first cache memory and the second cache memory, and configured to merge the first memory operation and the second memory operation corresponding to the same memory address before storing the first set of data in at least one of the first cache memory and the second cache memory.

[0231] Example 10 includes a system according to Example 9, wherein a first memory operation specifies a first set of data, a second memory operation specifies a second set of data, and the storage queue is available for merging the first set of data and the second set of data to produce a third set of data before storing the first set of data in at least one of the first cache storage area and the second cache storage area, and providing the third set of data for storage in at least one of the first cache storage area and the second cache storage area.

[0232] Example 11 includes the device according to Example 10, which further includes a storage queue for storing the third set of data in at least one of the first cache storage area or the second cache storage area in a cycle.

[0233] Example 12 includes the system according to Example 9, wherein the storage queue can be used to merge the first memory operation and the second memory operation by canceling a portion of the first memory operation.

[0234] Example 13 includes the system according to Example 12, wherein the portion of the first memory operation is the byte to be written by the second memory operation.

[0235] Example 14 includes the system according to Example 12, wherein the portion is a first portion, and the storage queue can be used to merge the first memory operation and the second memory operation by holding a second portion of the first memory operation.

[0236] Example 15 includes the system according to Example 14, wherein the second portion of the first memory operation is bytes not written by the second memory operation to...

[0237] Example 16 includes the system according to Example 9, wherein the first cache storage is a primary cache storage and the second cache storage is a victim cache storage.

[0238] Example 17 includes a method comprising obtaining a first memory operation, processing the first memory operation by executing instructions with a processor to store a first set of data in at least one of a first cache memory and a second cache memory, obtaining a second memory operation, and merging the first memory operation and the second memory operation by executing instructions with the processor before storing the first set of data in the at least one of the first cache memory and the second cache memory.

[0239] Example 18 includes the method according to Example 17, wherein the first memory operation corresponds to a first set of data and the second memory operation corresponds to a second set of data, the method further comprising, before storing the first set of data in at least one of the first cache storage area and the second cache storage area, merging the first set of data and the second set of data to produce a third set of data, and providing the third set of data to be stored in at least one of the first cache storage area and the second cache storage area.

[0240] Example 19 includes the method according to Example 18, further comprising storing the third set of data in at least one of the first cache storage area or the second cache storage area in a cycle.

[0241] Example 20 includes the method according to Example 17, further comprising merging the first memory operation and the second memory operation by canceling a portion of the first memory operation.

[0242] Optimized atomic operations and histogram operations in the L1 cache support

[0243] Atomic operations are other instances of multipart memory operations. For example, atomic compare and swap operations manipulate values ​​stored at memory locations based on comparisons of existing values ​​stored at those locations. For instance, if an existing value stored in L1 cache 110 matches a specific value, CPU 102 might want to replace the data stored in L1 cache 110 with the new value.

[0244] In some instance systems, when the CPU wants to perform an atomic operation, it sends a read operation to a memory address, manipulates the read data, and then performs a write operation to the same memory address to store the manipulated data. Furthermore, in such instance systems, the L1 cache suspends, rejects, blocks, and / or interrupts any transactions from other devices (e.g., other CPU cores, higher-level caches, extended memory, etc.) until the atomic operation is complete (e.g., to avoid manipulating the memory address corresponding to the atomic operation during the atomic operation). Therefore, such instance techniques require a significant amount of work to be done on behalf of the CPU and necessitate numerous retention cycles, which increases latency.

[0245] exist Figure 4A In this instance, the instance main cache queue 212 combines read-modify-write structures to process atomic operations. In this way, the instance CPU 102 can send a single atomic operation to the L1 cache 110, and the main cache queue 212 handles atomic data manipulation and write operations. Therefore, the CPU 102 uses a single cycle to execute atomic operations, and can use other cycles (e.g., for some instance atomic protocols) to perform other functions, thereby reducing the overall latency of the computing system 100.

[0246] In operation, when CPU 102 transmits atomic operations and / or atomic compare and swap operations to increment and / or swap data at a memory address, for example, an atomic instruction is received by latch 402a, and tag RAM 208 verifies whether the memory address is stored in instance main memory 214. If the memory address is stored in instance main memory 214, tag RAM 208 instructs instance main memory 214 to output the data at the memory address, while the atomic instruction is passed to instance latch 402b. When main memory 214 outputs data to latch 322a, instance latch 402b outputs the atomic operation to latch 402c. At this time, ECC logic 310 executes an error detection and / or correction protocol as described above, and data from the memory address location is forwarded to instance arithmetic component 404 (e.g., for atomic operations) or atomic compare component 406 (e.g., for atomic compare and swap operations). Arithmetic component 404 obtains atomic operations (e.g., data containing identification of how to manipulate data), and / or atomic compare and swap 406 obtains atomic compare and swap operations from latch 402c (e.g., containing a keyword and data to be written if the keyword matches the read data), and obtains data from the corresponding memory address from the output of ECC logic 310. Arithmetic component 404 performs data manipulation (e.g., incrementing the data by 1) and / or atomic compare component 406 performs swaps (substituting data if the read data matches the keyword, etc.) and outputs the incremented and / or swapped data (e.g., atomic result) to the corresponding memory address via instance MUX 410 to instance latch 402d (e.g., enabled via cache controller 220). Latch 402d outputs the new data corresponding to the memory address to ECC generator 412 to generate ECC bits, and arbitration manager 414, in conjunction with the ECC bits in instance main memory 214, writes the new data (e.g., atomic result and / or atomic compare and swap result) to the memory address. Alternatively, the correction value outside of EDD logic 412 is returned to CPU 102. Therefore, the atomic operation is executed using only one instruction from CPU 102.

[0247] Atomic comparison component 406 and / or arithmetic component 404 have several inputs. For example, atomic component 406 receives (e.g., obtains) the type of atomic operation to be performed (e.g., atomic comparison and swap or atomic swap), the new data to be swapped in, ECC correction data read from cache 310, and the size of the data manipulated during the atomic operation (e.g., 32 bits or 64 bits). Figure 4BIn the example circuit implementation 450, atomic comparison component 406 receives atomic comparison and swap operations, and arithmetic component 404 receives atomic operations. Atomic comparison component 406 compares a comparison value (e.g., a keyword) provided by CPU 102 with ECC data 310. Upon a match, new data replaces the old data (e.g., ECC data 310) and is swapped in and output to MUX 410. The size of the swapped-in new data is determined by the cas_acc_sz input (e.g., 32-bit or 64-bit). Figure 4C In the example circuit implementation 450, the atomic comparison component 406 can also receive atomic swap operations. The atomic comparison component 406 swaps in new data replacing the ECC data 310, regardless of the comparison result, and outputs the new value to the mux 410, whereby the old data from the address is read from main memory 214 and provided back to the CPU 102. The size of the swapped-in new data is determined by the cas_acc_sz input (e.g., 32-bit or 64-bit). Figure 4C In the example circuit implementation 450, the arithmetic component 404 may also receive atomic operations. The arithmetic component 404 manipulates the ECC data 310 and stores the manipulated data in the main storage element 214. The size of the new data swapped in is determined by the cas_acc_sz input (e.g., 32 bits or 64 bits). Although Figure 4C The example circuit 450 is described above in conjunction with the main storage queue, but circuit 450 can also be described in conjunction with the victim storage queue, as follows. Figure 11A Further description.

[0248] Figure 4C Show Figure 4A Part and / or of the main cache storage queue 212 Figure 11A Example circuit diagram of part of the victim cache storage queue 216. Figure 4C Detailed circuit diagrams of arithmetic units 404 and 1104 are shown.

[0249] Arithmetic unit 404 can be used for other types of memory transactions, such as histogram operations. Histogram operations retrieve values ​​from blocks stored in memory that represent histograms, and then modify the values ​​before storing them back at the same memory address or an alternative address. In an example, the first dataset contains the values ​​[0,0,2,0,0,3], and the second dataset contains blocks representing the number of occurrences of the corresponding values ​​within the first dataset. In some instance systems without arithmetic unit 404, to perform the histogram function, the CPU reads each value from the first dataset and increments the second dataset for each value. For example, to determine how many zeros are stored in a 10-byte dataset, the CPU might perform 10 reads. Then, to determine how many 1s are in the same dataset, the CPU would perform an additional 10 reads. Therefore, to perform histogram operations, such systems might require (N)(M) reads, where N is the size of the memory segment read (e.g., 10 bytes) and M is the number of values ​​that can be stored in each byte. Similar to atomic operations, L1 SRAM may need to block, pause, interrupt, discard, etc., all other read and / or write operations until the histogram operation is complete. In contrast, arithmetic unit 404 can be used to perform the same operation using a single transaction from the CPU.

[0250] Arithmetic units 404 and 1104 have several inputs, including the type of histogram (e.g., weighted or augmented, signed or unsigned), histogram size (e.g., byte, half-word, or word), histogram weights (e.g., signed weights to be added for each selected block group of a weighted histogram, or weights equal to one for a normal histogram), histogram sign (e.g., existing bits, signed or unsigned), and histogram saturation enabled.

[0251] Figure 4C Component 451 is for Figure 4CThe block group selection shown is read from ECC component 310. Component 452 selects weights to add to the block group from a weight vector provided by CPU 102. Cnt_value is the sum of the block group value from component 451 and the weights provided by CPU 102. Components 453, 454, and 458 serve as parts of the saturation circuit. Component 453 receives the histogram size (byte, half-word, or word) and a count value (the sum of the outputs of components 451 and 452) and determines whether the signed block group will saturate. Component 454 receives the histogram size (byte, half-word, or word) and a count value (the sum of the outputs of components 451 and 452) and determines whether the unsigned block group will saturate. The outputs of components 453 and 454 are sent to the MUX, which selects whether to use a signed saturation value or an unsigned saturation value based on the selected block group type (e.g., signed or unsigned). Component 458 receives the output of the MUX, histogram saturation enable, histogram type (e.g., signed or unsigned), sign bit of the block group, and sign bit of the weights, and outputs an updated cnt_value adjusted for the selected saturation type (e.g., based on Table 1 above). Components 455, 456, and 457 are used to position the resulting cnt_value and byte enable in the correct bit positions to write the new data group to the correct block group.

[0252] exist Figure 4A In this example, CPU 102 instructs main memory 214 to perform a histogram operation. This reduces the number of cycles CPU 102 must reserve for the operation from (N)(M) to 1. Furthermore, because the atomic operation protocol is already implemented in the memory queue, the histogram operation can be performed using arithmetic component 404 by performing N reads for the memory size N and incrementing the count for each value in the instance's main cache memory queue 212, thereby reducing the number of read operations from (N)(M) to N operations.

[0253] In operation, when CPU 102 transfers a histogram operation corresponding to a segment (e.g., an SRAM row) of main memory 214, the histogram operation is stored in instance latch 402a, while tag RAM 208 verifies whether the memory address corresponding to the histogram operation is available in main memory 214. Instance cache controller 220 facilitates read operations for each byte of the segment identified in the histogram operation (e.g., where the histogram block group is accessed in parallel by reading up to 128 bytes simultaneously). If available, tag RAM 208 instructs main memory 214 to output the data at the first byte of the segment of main memory 214, while the histogram operation is output from instance latch 402a to instance latch 402b. When instance main memory 214 outputs the data already read from the memory address to instance latch 322a, latch 402b outputs the histogram operation to instance latch 402c. After the ECC logic 310 performs error detection and correction, the data read at the byte is sent to the instance arithmetic component 404.

[0254] Upon receiving a read value from ECC logic 310 and a histogram instruction from latch 402c, arithmetic component 404 initiates data representing the histogram. For example, arithmetic component 404 may initiate a vector (e.g., representing the histogram) with an initial value (e.g., zero) for each possible value in a byte that can be stored in main memory. Arithmetic component 404 increments the value of the vector based on the output of ECC logic 310 (e.g., reading a byte). For example, if the read value of a byte is 0, arithmetic component 404 increments the vector by the value corresponding to 0.

[0255] Because each vector is incremented in parallel, the resulting vector corresponds to a histogram of values ​​that have been read in parallel from the corresponding segment of SRAM. Since the histogram values ​​are incremented bit-by-bit, the resulting vector is a histogram of values ​​stored in the segment of memory identified in the histogram operation from CPU 102. In some instances, the arithmetic component 404 may increment a weighted value (e.g., 1.5) in parallel. Upon completion, the instance histogram input to instance MUX 418 (e.g., controlled by instance pending memory address table 416) has been input to MUX 314 by instance latch 402e. Once the operation is complete, instance cache controller 220 controls MUX 314 to output the final histogram vector to instance CPU interface 202 via instance latch 322b, thereby ending the histogram operation.

[0256] In some instances, the L1 cache 110 supports the ability for histogram block groups to saturate after the histogram block group contains block group sizes (e.g., bytes, half-words, words, etc.) that exceed a threshold limit. Table 1 below shows examples of saturation values. Using this feature, the histogram block group values ​​will not scroll once they reach their maximum value.

[0257] Table 1 - Histogram Saturation Values

[0258]

[0259] This document describes example methods, apparatuses, systems, and artifacts for facilitating optimized atomic and histogram operations. Other examples and combinations thereof include the following: Example 1 includes a system comprising a cache store coupled to an arithmetic component and a cache controller coupled to the cache store, wherein the cache controller is configured to receive a specified set of data, retrieve the set of data from the cache store, determine a set of counts of corresponding values ​​in the set of data using the arithmetic component, generate a vector representing the set of counts, and provide the vector.

[0260] Example 2 includes the system described in Example 1, wherein the cache controller can be used to provide the vector for storage in the cache storage area.

[0261] Example 3 includes the system described in Example 1, wherein the cache controller can be used to provide the vector to the processor.

[0262] Example 4 includes the system according to Example 1, further including a storage queue coupled to the cache controller, the storage queue containing the arithmetic component.

[0263] Example 5 includes the system according to Example 1, wherein the cache storage is at least one of a primary cache storage or a victim cache storage.

[0264] Example 6 includes the system according to Example 1, wherein the arithmetic component will: (a) obtain the set of data from the cache storage via error detection and correction circuitry, and (b) obtain the memory operation from the central processing unit via a latch.

[0265] Example 7 includes the system according to Example 1, wherein the cache controller can be used to provide the vector to the central processing unit based on a single instruction from the central processing unit in a single cycle.

[0266] Example 8 includes a system comprising a cache storage area, and a cache controller and an arithmetic component coupled to the cache storage area, wherein the cache controller is configured to receive memory operations and arithmetic operations specifying a first set of data, retrieve the first set of data from the cache storage area, perform the arithmetic operations on the first set of data using the arithmetic component to produce a second set of data, and provide the second set of data.

[0267] Example 9 includes the system described in Example 8, wherein the cache controller can be used to provide the second set of data for storage in the cache storage area.

[0268] Example 10 includes the system described in Example 8, wherein the cache controller can be used to provide the second set of data to the processor.

[0269] Example 11 includes the system according to Example 8, further including a storage queue coupled to the cache controller, the storage queue including the arithmetic component.

[0270] Example 12 includes the system according to Example 8, wherein the cache storage is at least one of a primary cache storage or a victim cache storage.

[0271] Example 13 includes the system according to Example 8, wherein the arithmetic component will: (a) obtain the first set of data from the cache storage via error detection and correction circuitry, and (b) obtain the memory operation from the central processing unit via a latch.

[0272] Example 14 includes the system according to Example 8, wherein the cache controller can be used to provide the second set of data to the central processing unit based on a single instruction from the central processing unit in a single cycle.

[0273] Example 15 includes a method comprising: a memory operation to obtain a specified set of data, obtaining the set of data from a cache storage area, determining a set of counts of corresponding values ​​in the set of data, generating a vector representing the set of counts, and providing the vector.

[0274] Example 16 includes the method according to Example 15, wherein the vector is provided to the cache storage area.

[0275] Example 17 includes the method according to Example 15, wherein the vector is provided to the processor.

[0276] Example 18 includes the method according to Example 15, wherein the cache storage is at least one of a primary cache storage or a victim cache storage.

[0277] Example 19 includes the method according to Example 15, further comprising: (a) obtaining the set of data from the cache memory via error detection and correction circuitry, and (b) obtaining the memory operation from the central processing unit via a latch.

[0278] Example 20 includes the method according to Example 15, wherein providing the vector to the central processing unit is based on a single instruction from the central processing unit in a single cycle.

[0279] Atomic compares and swaps supported in the L1 cache of a consistency system

[0280] If data from a certain address is stored in L1 cache 110, data at the same address can also be cached in other caches (e.g., L2 cache 112 and / or L3 cache 114). Therefore, memory addresses need to be tracked and / or monitored to ensure that any changes to data in one cache are identified, tracked, and / or reflected in other caches (e.g., L2 cache 112 and L3 cache 114). (As mentioned above...) Figures 3A-3D As described, instance MESI RAM 300 tracks the state of data stored in main memory 214 to avoid data mismatches in different caches corresponding to the same memory address. For example, if CPU 102 performs a read operation, instance MESI RAM 300 changes the state of the memory address to shared because the data at that memory address will not be manipulated. If CPU 102 performs a write operation, instance MESI RAM 300 changes the state of the memory address to exclusive because the data at that memory address will be manipulated, and main memory 214 requires write access to that address. After the data at the memory address is written to main memory 214, MESI RAM 300 updates the state of the memory address to modified (e.g., indicating that the memory address has been modified).

[0281] As described above, during the atomic and / or histogram protocol, data from a memory address is read from main memory 214 and provided to main cache queue 212 for updates (e.g., additions) and written back to main memory 214. However, if the MESI RAM 300 has identified the state of the corresponding memory address as shared, write operations of the atomic protocol can cause problems with other levels of cache (e.g., because the write will cause data mismatch in different caches).

[0282] To avoid such data mismatches during atomic operations (e.g., those involving atomic compares and swaps), instance cache controller 220 marks cache hits corresponding to shared state as cache misses. In this way, cache controller 220 can instruct L2 interface 228 to send a cache miss to a higher-level cache using an exclusive state request. In this way, the higher-level cache can grant exclusive state to L1 cache 110, and L1 cache 110 can perform read and write operations as part of an atomic operation in response to receiving the granted exclusive state.

[0283] After a cache miss with an exclusive request is sent to a higher-level cache and the higher-level cache responds with a write data and an exclusive response, instance atomic operation logic 406 instructs MESI RAM 300 to mark the data as modified. Data received from L2 cache 112 is transferred to main cache storage queue 212 for storage in main memory 214. Because the operation is atomic (e.g., a regular atomic operation or atomic compare and swap) or a histogram protocol, the data from the higher-level cache is manipulated by instance arithmetic component 404 and / or instance atomic compare component 406 and stored in instance main memory 215 via instance ECC generator 412 and instance arbitration manager 414.

[0284] This document describes example methods, apparatuses, systems, and articles of art for facilitating atomic comparisons and swaps. Other examples and combinations thereof include the following: Example 1 includes a system comprising a cache memory, a cache controller coupled to the cache memory, wherein the cache controller is configured to receive a specified key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data with the key; store the first set of data at the memory address based on the second set of data corresponding to the key; and complete the memory operation without storing the first set of data at the memory address based on the second set of data not corresponding to the key.

[0285] Example 2 includes the system according to Example 1, further comprising a storage queue for the cache storage area, the storage queue comprising: a latch for interfacing with tag random access memory (RAM) to retrieve the second set of data from the cache storage area; an atomic comparison component, the cache controller causing the atomic comparison component to compare the second set of data with the key, and discarding the first set of data if the key does not match the second set of data; and an arbitration manager for storing the first set of data at the memory address in the cache storage area if the key matches the second set of data.

[0286] Example 3 includes the system according to Example 1, wherein the cache storage is at least one of a primary cache storage or a victim cache storage.

[0287] Example 4 includes the system according to Example 2, wherein the latch is a first latch, and the atomic comparison component is used to: (a) obtain the second set of data from the cache memory via an error detection and correction circuit, and (b) obtain the atomic comparison and swap command from the first latch via a second latch.

[0288] Example 5 includes the system according to Example 1, wherein the cache controller can be used to perform the memory operation based on a single instruction from the central processing unit in a single cycle.

[0289] Example 6 includes the system according to Example 1, further including a Modify Exclusive, Shared, Invalid (MESI) component for determining the state of the memory address of the memory operation, and the cache controller can be configured to provide a miss instruction to another cache if the memory address of the memory operation corresponds to a shared state, the miss instruction including an exclusive state request.

[0290] Example 7 includes the system according to Example 6, wherein the cache controller, after the exclusive state request from the other cache is granted, causes the arbitration manager to store the first set of data at the memory address in the cache storage area if the first data matches the keyword.

[0291] Example 8 includes the system according to Example 6, wherein the cache controller causes the tag RAM to retrieve the second set of data from the memory address of the cache storage area after the exclusive state request from the other cache is granted.

[0292] Example 9 includes a storage queue for a cache storage area, the storage queue comprising: a latch for retrieving a memory operation of a specified key, a memory address, and a first set of data, and retrieving a second set of data corresponding to the memory address; and an atomic comparison component for comparing the second set of data with the key, storing the first set of data at the memory address based on the second set of data corresponding to the key, and completing the memory operation without storing the first set of data at the memory address based on the second set of data not corresponding to the key.

[0293] Example 10 includes a storage queue as described in Example 9, wherein the cache storage is at least one of a primary cache storage or a victim cache storage.

[0294] Example 11 includes a storage queue according to Example 9, wherein the latch is a first latch, and the atomic comparison component is configured to: (a) obtain the second set of data from the cache storage via an error detection and correction circuit, and (b) obtain the atomic comparison and swap command from the first latch via a second latch.

[0295] Example 12 includes a storage queue according to Example 9, wherein if the first data matches the keyword, the storage queue executes the atomic comparison and swap command based on a single instruction from the central processing unit in a single cycle.

[0296] Example 13 includes a storage queue according to Example 9, further comprising: a Modify Exclusive, Shared, Invalid (MESI) component for determining the state of the memory address of the memory operation; and an interface for providing a miss instruction to another cache when the memory address of the memory operation corresponds to a shared state, the miss instruction containing an exclusive state request.

[0297] Example 14 includes a storage queue as described in Example 13, further including an arbitration manager for storing the first set of data at the memory address if the first data matches the keyword, after the exclusive state request from the other cache is granted.

[0298] Example 15 includes a storage queue as described in Example 13, wherein the latch will interface with the tag RAM to read the second set of data after the exclusive state request from the other cache is granted.

[0299] Example 16 includes a method comprising: receiving a specified keyword, a memory address, and a first set of data; retrieving a second set of data corresponding to the memory address; comparing the second set of data with the keyword; storing the first set of data at the memory address based on the second set of data corresponding to the keyword; and completing the memory operation without storing the first set of data at the memory address based on the second set of data not corresponding to the keyword.

[0300] Example 17 includes the method according to Example 16, further comprising: interfacing with tag random access memory (RAM) to retrieve the second set of data from a cache storage area, comparing the second set of data with the keyword, discarding the first set of data if the keyword does not match the second set of data, and storing the first set of data at the memory address in the cache storage area if the keyword matches the second set of data.

[0301] Example 18 includes the method according to Example 17, further comprising: (a) obtaining the second set of data via an error detection and correction circuit, and (b) obtaining the memory operation from the central processing unit.

[0302] Example 19 includes the method according to Example 16, wherein the memory operation is performed based on a single instruction from the central processing unit in a single cycle.

[0303] Example 20 includes the method according to Example 16, further comprising: determining the state of the memory address of the memory operation, and providing a miss instruction to another cache if the memory address of the memory operation corresponds to a shared state, the miss instruction including an exclusive state request.

[0304] Method and apparatus for forwarding and invalidating in-flight data pending writes in a storage queue.

[0305] In the examples described herein, when CPU 102 issues a read operation, tag RAM accesses 204, 206 determine whether the read operation hits or misses main memory element 214 and / or victim memory element 218. In the example where tag RAM accesses 204, 206 determine that the read command missed both main memory element 214 and victim memory element 218, cache controller 220 sends a victim creation operation to main memory element 214 (e.g., to determine the row to be evicted in main memory element 214). In some instances, problems can arise when main memory element 214 evicts a row corresponding to a pending write. For example, a row in main memory element 214 currently containing data to be written via storage queue 212 may have a pending write located in any of latches 402a-d. In some instances, an error can occur when a new address replaces a row that has been evicted from main memory element 214 while storage queue 212 is still attempting to write data from a previous write operation to the same row.

[0306] The example described herein includes issuing a read invalidation operation to storage queue 212 when cache controller 220 determines that a read operation is a read miss. When a victim is created in primary storage element 214, cache controller 220 sends a read invalidation operation to storage queue 212. The read invalidation operation instructs storage queue 212 to compare the victim's address with all addresses stored in latches 402a-d. If any address in latches 402a-d matches the victim's address, priority multiplexer 418 sends the data from the matching address to latch 402e to transfer the data to MUX circuitry 314. This type of operation can be referred to as data forwarding of data in flight. For example, when priority multiplexer 418 sends data corresponding to the victim to MUX circuitry 314 via latch 402e, MUX circuitry 314 forwards the victim's data to victim storage element 218 and / or L2 cache 112. Furthermore, the read invalidation operation invalidates the data stored in latches 402a-d when latches 402a-d contain the address corresponding to the victim. For example, each of latches 402a-d contains a valid tag. The valid tag indicates to latches 402a-d whether data will be stored in main memory element 214. When an invalid read operation invalidates the valid tag, latches 402a-d interrupt the writing of invalid data to main memory element 214.

[0307] In this instance operation, CPU 102 issues a write operation. In some instances, the write operation corresponds to address A. For example:

[0308] Write operation = write(address A): data1 / / Write data1 to the cache line corresponding to address A

[0309] Storage queue 212 receives a write operation and begins the process of writing data to address A of main storage element 214. In some instances, address A corresponds to cache line 1 in main storage element 214. Subsequently, CPU 102 issues a read operation. In some instances, the read operation corresponds to address B. For example:

[0310] Read operation = Read(Address B) / / Reads data corresponding to address B from the cache line. Example 2: Tag RAM accesses 204 and 206 check the addresses in tag RAM 208 and tag RAM 210, and determine that tag RAM 208 and 210 do not contain address B. The cache controller 220 obtains a read miss result from tag RAM accesses 204 and 206, and issues an allocation operation to determine the victim to be evicted from main memory element 214 to victim memory element 218 and / or L2 cache 112. When the cache controller 220 receives a response corresponding to the victim, the cache controller 220 issues a read invalidation operation to the memory queue 212.

[0311] The read port 424 of storage queue 212 receives a read invalidation operation and obtains the victim's address. Read port 424 sends the victim's address to data storage area 416 for comparison with all addresses stored in latches 402a-d. If data storage area 416 determines that any address stored in latches 402a-d matches the victim's address, data storage area 416 outputs an operation to priority multiplexer 418 to send the data corresponding to the victim's address to latch 402e. Latch 402e forwards the data to MUX circuitry 314 for delivery to victim storage element 218 and / or L2 cache 112.

[0312] Furthermore, in response to an address stored in latches 402a-d matching a victim address, latches 402a-d invalidate the data corresponding to the victim address. For example, the valid tag in latches 402a-d is updated to indicate that the data in the latch corresponding to the victim address is invalid. In this example, storage queue 212 will not attempt to write the data to the cache line corresponding to the previously evicted address.

[0313] This document describes example methods, apparatuses, systems, and artifacts for in-flight data forwarding and failure handling. Other examples and combinations thereof include the following:

[0314] Example 1 includes a device comprising a cache store and a cache controller, the cache controller being coupled to the cache store and configured to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache store, determine a victim address to be evicted in the cache store in response to the read miss, issue a read invalidation command specifying the victim address, compare the victim address with a set of addresses associated with a set of memory operations being processed by the cache controller, and provide data associated with the second memory operation in response to the victim address matching a first address in the set of addresses corresponding to a second memory operation in the set of memory operations.

[0315] Example 2 includes the device according to Example 1, wherein the cache controller issues the read invalid command when a read miss occurs in the tag random access memory.

[0316] Example 3 includes the device according to Example 1, wherein the cache controller determines the victim address to be evicted from the cache storage area to make room for data operating in a third memory.

[0317] Example 4 includes the device according to Example 1, wherein the cache controller can be used to interrupt the writing of data associated with the second memory operation in the cache storage area.

[0318] Example 5 includes the device according to Example 1, which further includes a first latch, a second latch, a third latch, and a fourth latch, wherein the first latch, the second latch, the third latch, or the fourth latch stores data of the victim's address.

[0319] Example 6 includes the device according to Example 5, wherein the first latch, the second latch, the third latch, and the fourth latch contain a valid tag that will be updated to invalid when the data of the victim's address is stored in any of the first latch, the second latch, the third latch, or the fourth latch.

[0320] Example 7 includes the device according to Example 1, further including a read port for initiating a comparison between the victim address and the set of addresses associated with the set of memory operations being processed by the cache controller when the read invalid command and the victim address are obtained at the read port.

[0321] Example 8 includes a method for invalidating a write operation, the method comprising: receiving a first memory operation; determining that the first memory operation corresponds to a read miss in a cache memory; determining a victim address to be evicted in the cache memory in response to the read miss; issuing a read invalidation command specifying the victim address; comparing the victim address with a set of addresses associated with a set of memory operations being processed by a cache controller; and providing data associated with the second memory operation in response to the victim address matching a first address in the set of addresses corresponding to a second memory operation in the set of memory operations.

[0322] Example 9 includes the method according to Example 8, further comprising issuing the read invalid command when a read miss occurs in the tag random access memory.

[0323] Example 10 includes the method according to Example 8, further comprising determining the victim address to be evicted from the cache storage area to make room for data operating in a third memory.

[0324] Example 11 includes the method according to Example 8, further comprising interrupting the writing of the data associated with the second memory operation into the cache storage area.

[0325] Example 12 includes the method according to Example 8, further comprising storing data of the victim's address in at least one of a first latch, a second latch, a third latch, and a fourth latch.

[0326] Example 13 includes the method according to Example 12, further comprising updating the valid tag of the first latch, the second latch, the third latch, or the first latch to invalid when any one of the first latch, the second latch, the third latch, and the fourth latch stores the data of the victim address.

[0327] Example 14 includes the method according to Example 8, further comprising, when the read port obtains the read invalid command and the victim address, initiating a comparison between the victim address and the set of addresses associated with the set of memory operations being processed by the cache controller.

[0328] Example 15 includes a system comprising a central processing unit for outputting a first memory operation, a cache coupled to the central processing unit, the cache including a cache memory area, and a cache controller coupled to the cache memory area and configured to receive the first memory operation, determine that the first memory operation corresponds to a read miss in the cache memory area, determine a victim address to be evicted in the cache memory area in response to the read miss, issue a read invalidation command specifying the victim address, compare the victim address with a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address in the set of addresses corresponding to a second memory operation in the set of memory operations, provide data associated with the second memory operation and invalidate the second memory operation.

[0329] Example 16 includes the system according to Example 15, wherein the cache is a first cache, and wherein the first cache can be used to retrieve data associated with the first memory operation from a second cache in response to the cache storage area not containing the data associated with the first memory operation.

[0330] Example 17 includes the system according to Example 15, wherein the cache includes a storage queue for storing write data of the second memory operation into the cache storage area in a plurality of clock cycles, wherein at least one portion of the data associated with the second memory operation is written into the cache storage area in each clock cycle.

[0331] Example 18 includes the system according to Example 17, wherein the cache is a first cache, and wherein the cache controller is configured to provide a portion of the remaining data in the storage queue to a second cache for storage when the second memory operation is invalid.

[0332] Example 19 includes the system according to Example 15, wherein the cache includes a storage queue for storing writes to be processed, and the second memory operation corresponds to the write to be processed.

[0333] Example 20 includes the system according to Example 15, wherein the central processing unit outputs the first memory operation after outputting the second memory operation. Figure 5 Show Figure 1 The L1 cache instance of 3 is based on the victim cache segment. Figure 5It includes tag RAM 210, victim storage area 218, MESI RAM 300, instance hit / miss comparison logic 306a, 306b, 306c, instance replacement policy 308 (e.g., replacement policy component 308), instance address encoder 326a, 326b, 326c, instance multiplexer (MUX) 330a, 330b, 330c, instance address read 332a, 332b, 332c, instance scalar interface 502, instance vector interface 504, instance listening address component 506, and instance response multiplexer 508. Figure 5 This illustrates a victim cache system that supports dual data paths and a consistency pipeline.

[0334] exist Figure 5 In the context of the instance scalar interface 502, the scalar interface 502 is used to... Figure 1 The L1 cache 110 of the data cache 108 is coupled to an interface of the instance processing core 104a. In some instances, the scalar interface 502 is an interface corresponding to the first data path (DP0) in a dual-data-path victim cache system. In some instances, the scalar interface 502 is an interface corresponding to the second data path (DP1) in a dual-data-path cache system. The instance scalar interface 502 is a 64-bit wide bidirectional and / or unidirectional interface. Alternatively, the instance scalar interface 502 may support different numbers of bits (e.g., 32 bits, 128 bits, etc.). In some instances, the scalar interface 502 receives and / or obtains data from the core 104a. In some instances, the scalar interface 502 sends data from the victim memory 218 to the core 104a. The instance scalar interface 502 is coupled to the instance tag RAM 210 and compare logic 306 to compare the address from the CPU 102 with the address in the tag RAM 210.

[0335] exist Figure 5 In the context of the instance vector interface 504, the 504 is... Figure 1The L1 cache 110 of the data cache 108 is coupled to an interface of the instance processing core 104a. In some instances, the vector interface 504 is an interface corresponding to the second data path (DP1) in a dual-data-path cache system. In some instances, the vector interface 504 is an interface corresponding to the first data path (DP0) in a dual-data-path cache system. The instance vector interface 504 is a 512-bit wide interface. Alternatively, the instance vector interface 504 may support different numbers of bits (e.g., 256 bits, 1024 bits, etc.). In some instances, the vector interface 504 receives and / or obtains data from the core 104a. In some instances, the vector interface 504 sends data from the victim memory 218 to the core 104a. The instance vector interface 504 is coupled to the instance tag RAM 210, the listen address component 506, and the comparison logic 306b to compare the address from the CPU 102 with the address from the tag RAM 210. In some instances, the scalar interface 502 and the vector interface 504 are connected by the CPU interface 202. Figure 2 ) Implementation. For example, scalar interface 502 and vector interface 504 may be included in CPU interface 202.

[0336] exist Figure 5 In this context, instance tag RAM 210 is connected to instance interfaces 502 and 504. However, in some instances, tag RAM 210 can be accessed via instance victim tag RAM 206. Figure 2 Coupled to interfaces 502 and 504. Instance tag RAM 210 is a dual-port fully associative tag RAM used to support dual data paths (e.g., a scalar data path and a vector data path). As used herein, fully associative tag RAM 210 permits access from main memory 214 ( Figure 2 The data is stored in any cache block, rather than forcing each memory address to a specific block. In some instances, because tag RAM 210 is fully associative, victim memory 218 is also fully associative.

[0337] exist Figure 5In this configuration, comparison logic 306a is connected to scalar interface 502, tag RAM 210, address encoder 326a, and alternative strategy component 308. Comparison logic 306b is connected to vector interface 504, tag RAM 210, address encoder 326b, and alternative strategy component 308. Comparison logics 306a and 306b support scalar and vector data paths. For example, comparison logic 306 can compare scalar data with data in tag RAM 210 and / or compare vector data with data in tag RAM 210. Comparison logic 306 provides hit or miss outputs to alternative strategy component 308 and address encoders 326a and 326b. In some instances, comparison logic 306 provides hit or miss outputs to multiplexers 330a and 330b.

[0338] exist Figure 5 In this context, instance replacement policy component 308 is coupled to comparison logic 306a, 306b. Instance replacement policy component 308 is control / decision generation logic. Instance replacement policy component 308 specifies entries (e.g., data) in instance victim storage area 218 based on multiple inputs. For example, replacement policy component 308 may determine the cache controller 220 ( Figure 2 The decision is whether to remove an entry from the victim store 218 or to add an entry to the victim store. The control logic of the alternative policy component 308 is configured to resolve address conflicts between the two addresses (e.g., scalar and vector) in a manner that maintains data consistency. Figure 6 The control logic of instance replacement strategy component 308 is shown.

[0339] exist Figure 5 In this example, address encoders 326a and 326b encode memory addresses into a form that can be decoded by the victim memory area 218. For example, the operation of address encoders 326a and 326b can be similar to... Figures 3A-3D Address encoder 326. Example address encoders 326a and 326b output encoded addresses to multiplexers 330a and 330b. For example, address encoder 326a can output encoded memory addresses to multiplexer 330a, and address encoder 326b can output encoded memory addresses to multiplexer 330b.

[0340] exist Figure 5In this configuration, multiplexers 330a and 330b select an address in response to the execution of comparison logic 306a and 306b. For example, multiplexer 330a may obtain an input corresponding to a hit from comparison logic 306a and thus select an encoded address from address encoder 326a. Alternatively and / or, multiplexer 330a may obtain an input corresponding to a miss from comparison logic 306a and thus select a memory address selected by alternative strategy component 308. Example multiplexers 330a and 330b are coupled to address reads 332a and 332b.

[0341] exist Figure 5 In this process, instance address reads 332a and 332b read the address value selected by the multiplexer into the victim storage area 218. For example, address reads 332a and 332b can identify addresses to be stored and / or removed from the victim storage area 218.

[0342] exist Figure 5 In this context, the victim store 218 is a fully associative cache. For example, the fully associative victim store 218 may place data in any unused block of the cache when data is retrieved from main memory 214 (e.g., victimized). The placement of data in the victim store 218 is based on the substitution policy component 308. For example, the substitution policy component 308 may determine when and where a row of data from main memory 214 should be placed in the victim store 218. In some instances, the victim store 218 outputs a response when address reads 332a, 332b read data into the victim store 218. In some instances, the victim store 218 generates DP0, DP1, and listener responses to transfer to the L2 data cache 112. In some instances, the response contains the data requested by CPU 102. For example, based on address reads 332a, 332b, if CPU 102 has requested such data, the victim store 218 may output the data from the memory address location. Additionally and / or alternatively, based on address reads 332a, 332b, if the substitution policy component 308 is substituted for data in the victim storage area 218, the victim storage area 218 may output the evicted data to the L2 cache 112.

[0343] exist Figure 5In this implementation, the instance listener address component 506 is implemented by the listener data path and / or otherwise by the interface. In addition to the two CPU data paths (e.g., DP0 and DP1), the L1 cache 110 includes a listener data path to add coherence to the L1 cache 110. The instance listener address component 506 is connected to the tag RAM 210 and the compare logic 306c. In some instances, the listener address component 506 receives the instance listener request address issued by a higher-level data cache (e.g., L2 data cache 112) that issues an address read to the tag RAM 210. For example, the listener address component 506 attempts to read a memory address from the tag RAM 210. The listener address component 506 then provides the address read to the compare logic 306c. The listener address component 506, and more generally the coherence pipeline, is used to store the MESI state of each cache line in the victim memory area 218 in the MESI RAM 300. By storing the MESI state of each cache line in the MESI RAM 300, the victim cache system supports coherence.

[0344] exist Figure 5 In this context, instance MESI RAM 300 is connected to comparison logic 306c. Instance MESI RAM 300 tracks the state of cache lines in main memory 214 and victim memory 218 by marking cache lines as modified, exclusive, shared, or invalid based on comparison logic 306c. For example, when the listener address component 506 issues a read request to tag RAM 210, tag RAM 210 may or may not return the correct memory address. Therefore, comparison logic 306c compares the memory address of the read request issued by the listener with the result from tag RAM 210 to determine the state of the cache line.

[0345] exist Figure 5 In the example topology shown, response multiplexer 508 is coupled to victim storage area 218 and victim cache storage queue 216. In this way, response multiplexer 508 is configured to select between data obtained through victim storage area 214 and / or data obtained through victim cache storage queue 216 to transfer the most recent data in the system. The instance operation of priority multiplexer 508 is described below.

[0346] Method and apparatus for multiple victim caches with dual data paths

[0347] In some victim caches, multiple architectures are not supported. For example, a victim cache may be a monolithic storage device that does not support multiple accesses by a processor (e.g., CPU) during the same clock cycle. For instance, a request to access data in a single victim cache can lock the entire victim cache. In such instances, there is a single register file capable of supporting access to one full victim cache line per clock cycle. In some such instances, the entire victim cache line associated with the single victim memory area can be locked to serve the request because the single register file is allocated to the victim memory data group receiving such a request.

[0348] The instances described in this article involve multiple sets of victim caches with dual data paths. In some of the described instances, Figure 2 The victim storage area 218 has multiple groups, and is therefore multi-grouped, or has multiple groups of data or memory structures. Advantageously, the multi-group structure of the victim storage area 218 enables support for two or more accesses per clock cycle (e.g., CPU accesses). Advantageously, the multi-group structure of the victim storage area 218 allows the servicing and / or implementation of said two or more accesses without performance overhead.

[0349] In some of the described instances, victim storage 218 has a dual-port fully associative tag RAM (e.g., Figure 2 (Label 210). In some of the described instances, both scalar and vector addresses support hit / miss comparisons. In such described instances, victim memory 218 is locked based on a hit / miss decision for each data path (e.g., scalar data path, vector data path, etc.). In instances where access to victim memory 218 is a hit, the location of the hit entry is selected. In instances where access to victim memory 218 is a miss, the allocation policy is checked for a specific set of victim memory 218s.

[0350] In some of the described instances, in a subsequent management level, the victim memory 218 for the selected group of two addresses is read, and the response is returned to the CPU. In some of the described instances, the selection logic is configured to resolve address conflicts between the two addresses (e.g., a scalar address and a vector address) in a manner that maintains data consistency. In some of the described instances, the control logic also resolves address conflicts.

[0351] In some of the described instances, group arbitration logic computes and / or otherwise determines the required group for each address and selects each group for reading. In some of the described instances, control logic resolves any group conflicts between the two addresses to serialize the two memory operations. In some of the described instances where both data paths access the same address, the control logic can prevent multiple allocation requests for the same address from being issued. Once data is read from victim memory 218, instance data multiplexing logic can fold the data into the correct data path before returning it to the CPU as a read response.

[0352] Figure 7A This is a schematic diagram of the first instance of the encapsulated data cache system 700. The first encapsulated data cache system 700 can be... Figure 1 L1 cache 110 or a portion thereof and / or more generally Figure 1 An example circuit implementation of the data cache 108 or a portion thereof. The first encapsulated data cache system 700 is encapsulated to provide a unified storage view to external systems (e.g., one or more CPUs, one or more processors, external hardware, etc.). For example, the first encapsulated data cache system 700 may use firmware, software, hardware logic, etc., and / or combinations thereof for encapsulation to encapsulate and / or otherwise abstract all complexities related to read-after-write (RAW) hazards, write-after-write (WAW) hazards, data forwarding, etc. Advantageously, in Figure 7A The unified architecture depicted in the example provides a separate port to external systems (e.g., CPU 102) to simplify access to data of interest in the latest version.

[0353] exist Figure 7A In the example, the first encapsulated data cache system 700 contains Figure 2 The victim cache storage queue 216 and Figure 2 Victim storage area 218. In Figure 7A In the context of the victim cache storage queue 216, multiple first instance independently addressable groups (e.g., data groups, storage area groups, data storage area groups, etc.) 702 are included. For example, the first independently addressable group 702 can be a group queue, a group sub-queue, etc. In such instances, the group queue, group sub-queue, etc., can contain multiple storage elements, as described below. Figure 7C and / or Figure 7E Described in the text. The first independently addressable group 702 is a victim cache storage queue group (e.g., a victim cache storage queue data group, a victim cache group queue, a victim cache group sub-queue, etc.). Figure 7AIn this context, victim cache storage queue 216 contains 16 victim cache storage queue groups 702. Alternatively, there may be fewer or more victim cache storage queue groups 702 than 16 instances.

[0354] exist Figure 7A In this context, the victim storage area 218 contains multiple second instance independently addressable groups (e.g., data groups, storage area groups, data storage area groups, etc.) 704. The second independently addressable group 704 is the victim storage area group (e.g., the victim storage area data group). Figure 7A In this context, victim storage area 218 contains 16 victim storage area groups 704. Alternatively, there may be fewer or more victim storage area groups 704 than 16 instances. For example, victim cache storage queue 216 may contain multiple group queues or group sub-queues, including a first group queue or a first group sub-queue (e.g., victim cache storage queue: group 1), and victim storage area 218 may contain multiple data groups, including a first data group (e.g., victim storage area: group 1).

[0355] In some instances, the victim cache storage queue 216 and the victim storage area 218 each have 256 rows, each with a line width of 1024 bits, and are divided into 16 groups, such as... Figure 7A As shown, each row in a given group is 64 bits. In some instances, victim cache storage queue 216 and victim storage area 218 each have 384 rows, each row having a line width of 1024 bits, and are divided into 16 groups, as shown. Figure 7A As shown, each line in a given set is 64 bits. Of course, the cache sizes described in the examples above are merely two instances, and the description is not limited to any particular cache line width, number of sets or lines, etc. Figure 7A As depicted, each of the first groups 702 corresponds to one of the second groups 704. For example, the first group (group 1) of the victim cache storage queue 216 forms a loop with the first group (group 1) having the victim storage area 218, and thus corresponds to the first group of the victim storage area 218.

[0356] Advantageously, the victim cache storage queue 216, the victim storage area 218, and / or more generally, the multi-set structure of the first encapsulated data cache system 700 can serve read and write operations sent to groups in parallel. In some instances, each group arbitrates its own process in response to read and / or write operations. By allowing each group of the first encapsulated data cache system 700 to operate independently, the operation of the first encapsulated data cache system 700 is more efficient because the entire cache line is not locked when a request is received. Instead, only the portion of the cache line allocated to the group receiving such a request is locked.

[0357] Figure 7C The instance victim cache has a multi-set structure of 720. In some instances, Figure 1 The L1 cache 110, L2 cache 112, and / or L3 cache 114 may have a victim cache set structure 720. In some instances, Figure 2 The victim cache storage queue 216 and / or Figure 2 The victim storage area 218 may have a victim cache multi-set structure 720. For example, the victim cache multi-set structure 720 may be an instance implementation of the victim cache storage queue 216 and / or the victim storage area 218.

[0358] The victim cache multi-set structure 720 is a data or memory structure containing 16 instance sets (sets 0-15) 722, where each set 722 has a data width of 64 bytes (e.g., bytes 0-7). Each set 722 contains 16 instance rows (rows 0-15) 724, where each row 724 has 128 bytes (e.g., 128 bytes = 8 bytes / set). The data width is 16 groups. Figure 7C In this context, each group of 722 can store 128 bytes (e.g., 128 bytes = 8 bytes / row). (16 lines). In Figure 7C In the middle, the victim cache has a multi-set structure of 720 that can store 2048 bytes (e.g., 2048 bytes = 128 bytes / set). (16 groups). The victim cache multi-group structure 720 can be independently addressed by group. For example, the first line in line 724 has a start line address 0 and an end line address 127, the second line in line 724 has a start line address 128 and an end line address 255, and so on.

[0359] In some instances, a cache line can be 128 bytes of data adapted to the width of a memory (e.g., DRAM) or a memory cell (e.g., main memory 214, victim memory 218, etc.). Figure 7C In this example, a cache line can occupy an entire row of the victim cache set structure 720. For instance, a cache line can use a row 724 of 16 sets, where each set is 8 bytes wide. Advantageously, the victim cache set structure 720 allows 16 different cache lines to access the data stored therein.

[0360] Figure 8A A schematic illustration shows the Instance Victim Cache Tag (VCT) Random Access Memory (RAM) 800. The VCT RAM 800 can be... Figure 2Example implementation of tag RAM 210. For example, VCT RAM 800 can be stored in Figure 2 The data addresses are stored in the victim cache storage queue 216, the victim storage area 218, etc. VCT RAM 800 is a multi-group VCT RAM. For example, VCT RAM 800 may contain multiple groups (e.g., data groups, memory groups, etc.), such as 16 groups, but VCT RAM 800 may have a different number of groups.

[0361] VCT RAM 800 includes instance allocation ports 802, 804, and 806, including a first instance allocation port (AP0) 802, a second instance allocation port (AP1) 804, and a third instance allocation port (AP2) 806. VCT RAM 800 includes instance read ports 808, 810, and 812, including a first instance read port (RP0) 808, a second instance read port (RP1) 810, and a third instance read port (RP2) 812. VCT RAM 800 includes an instance LRU read port 814. VCT RAM 800 includes instance output ports 816, 818, 820, and 822, including a first instance output port (OP0) 816, a second instance output port (OP1) 818, a third instance output port (OP2) 820, and a fourth instance output port (OP3) 822. Alternatively, VCT RAM 800 may have more than Figure 8A The description includes fewer or more allocation ports, read ports, LRU read ports, and / or output ports.

[0362] VCT RAM 800 includes allocation ports 802, 804, and 806 for filling victim memory 218. For example, allocation ports 802, 804, and 806 can be configured to receive requests from external hardware (e.g., CPU 102, main memory 214, etc.) to store data in victim memory 218. A first allocation port 802 is configured to receive first instance data 824. For example, the first allocation port 802 can receive first data 824 from a write state machine associated with a scalar data path (DP0). The first data 824 contains WRM_TAG_UPDATE0 data, which may represent data from... Figure 2Control signals generated by CPU interface 202 (e.g., scalar data path (DP0)). Control signals can be generated to notify VCT RAM 800 that CPU interface 202 has a cache line for moving from CPU interface 202 to victim memory 218, and therefore CPU interface 202 has an address for moving from CPU interface 202 to tag RAM 210. First data 824 contains VTAG_WR_TAG0 data, which may represent an address in VCT RAM 800 that corresponds to the address of data to be stored in victim cache 218 (e.g., tag address). First data 824 also contains VTAG_WR_SET0 data, which may represent the address in victim cache 218 where data (e.g., victim cache tag of DP0) is to be stored.

[0363] The second allocation port 804 is configured to receive second instance data 826. For example, the second allocation port 804 may receive second data 826 from a write state machine associated with the vector data path (DP1). The second data 826 contains WRM_TAG_UPDATE1 data, which may represent data from... Figure 2 Control signals generated by CPU interface 202 (e.g., vector data path (DP1)). Control signals can be generated to notify VCT RAM 800 that CPU interface 202 has a cache line for moving from CPU interface 202 to victim memory 218, and therefore CPU interface 202 has an address for moving from CPU interface 202 to tag RAM 210. Second data 826 contains VTAG_WR_TAG1 data, which may represent the address in VCT RAM 800 that corresponds to the address of data to be stored in victim cache 218 (e.g., tag address). Second data 826 contains VTAG_WR_SET1 data, which may represent the address in victim cache 218 where data (e.g., victim cache tag of DP1) is to be stored.

[0364] The third allocation port 806 is configured to receive third instance data 828. The third data 828 contains ARB_EVT_TAG_UPDATE data, which may represent a control signal generated from main memory 214. This control signal is an Arbitration (ARB) Eviction (EVT) Tag Update Control Signal, which may be generated to notify VCT RAM 800 that main memory 214 has a cache line moving from main memory 214 to victim memory 218, and therefore main memory 214 has an address moving from tag RAM 208 to tag RAM 210. The third data 828 contains ADP_EVT_WR_TAG data, which may represent an address in VCT RAM 800 that corresponds to the address of data to be stored in victim cache 218 (e.g., a tag address). The third data 828 contains ADP_EVT_WR_SET data, which may represent the address in victim cache 218 where data (e.g., a victim cache tag of a line moved from main cache to victim cache) is to be stored. For example, ADP_EVT_WR_TAG and ADP_EVT_WR_SET data can be referred to as Address Data Path (ADP) data. The first data 824, the second data 826, and / or the third data 828 can be one or more data packets, one or more signals based on a communication protocol (e.g., Inter-Integrated Circuit (I2C) protocol), etc.

[0365] VCT RAM 800 includes read ports 808, 810, and 812 to provide an interface for external hardware (e.g., CPU 102) to request reads and / or otherwise access data stored in victim memory 218. A first read port 808 is configured to receive fourth instance data 830. For example, the first read port 808 may receive fourth data 830 from scalar interface 502 of CPU 102. The fourth data 830 contains ADP_ADDR_E2_DP0 data, which may represent the address in victim memory 218 requested for access by scalar interface 502.

[0366] The second read port 810 is configured to receive fifth instance data 832. For example, the second read port 810 may receive the fifth data 832 from the vector interface 504 of the CPU 102. The fifth data 832 contains ADP_ADDR_E2_DP1 data, which may represent the address requested for access by the vector interface 504 in the victim memory area 218.

[0367] The third read port 812 is configured to receive data 834 from the sixth instance. For example, the third read port 812 can receive data from the sixth instance. Figure 5The listening address component 506 (e.g., a listening interface) receives the sixth data 834. The sixth data 834 contains SNP_ADDR_E2_DP0 data, which may represent the address requested for access by the listening address component 506 in the victim memory area 218.

[0368] LRU read port 814 is configured to receive seventh instance data 836. For example, LRU read port 814 can be used to receive data from the seventh instance. Figures 3A-3D The alternative policy component 308 receives seventh data 836. The seventh data 836 contains LRU_SET_DP0 and LRU_SET_DP1, which may represent the corresponding addresses associated with the least random use (LRU) cache lines of the victim memory 218. For example, LRU read port 814 may be a victim least random use (VLRU) read port configured to receive LRU data from the alternative policy component 308.

[0369] VCT RAM 800 includes output ports 816, 818, 820, and 822 for transmitting output to external hardware (e.g., CPU 102, main memory 214, etc.) in response to a read or write request (e.g., an allocation request) associated with victim memory 218. First output port 816 is configured to transmit first instance output data 838. For example, first output port 816 may transmit first output data 838 to scalar interface 502. First output data 838 includes VTAG_HIT_DP0 data, which may indicate that the data requested by scalar interface 502 is stored in victim memory 218. First output data 838 includes VTAG_MISS_DP0 data, which may indicate that the data requested by scalar interface 502 is not stored in victim memory 218. First output data 838 includes VTAG_SET_DP0 data, which may represent the address in victim memory 218 where the data requested by scalar interface 502 is stored.

[0370] The second output port 818 is configured to transmit second instance output data 840. For example, the second output port 818 can transmit the second output data 840 to the vector interface 504. The second output data 840 contains VTAG_HIT_DP1 data, which indicates that the data requested by the vector interface 504 is stored in the victim storage area 218. The second output data 840 contains VTAG_MISS_DP1 data, which indicates that the data requested by the vector interface 504 is not stored in the victim storage area 218. The second output data 840 contains VTAG_SET_DP1 data, which represents the address in the victim storage area 218 where the data requested by the vector interface 504 is stored.

[0371] The third output port 820 is configured to transmit third instance output data 842. For example, the third output port 820 may transmit the third output data 842 to the replacement policy component 308. The third output data 842 contains VTAG_ADDR_DP0 data, which may represent an address in the victim memory 218 associated with a request LRU_SET_DP0 received at the replacement policy component 308 at the LRU read port 814.

[0372] The fourth output port 822 is configured to transmit fourth instance output data 844. For example, the fourth output port 822 may transmit the fourth output data 844 to the replacement policy component 308. The fourth output data 844 contains VTAG_ADDR_DP1 data, which may represent the address in the victim memory 218 associated with the request LRU_SET_DP1 received at the replacement policy component 308 at the LRU read port 814.

[0373] Figure 8B Show Figure 8A Another schematic illustration of an example implementation of the VCT RAM 800. For example, Figure 8B Can correspond to Figure 5 The L1 cache 110 is a segment or portion thereof based on the victim cache.

[0374] Figure 8B Depicting Figure 8A Another example implementation of the VCT RAM 800. In Figure 8B In this context, VCT RAM 800 contains 16 instance sets 846. For example, set 846 contains a first set VCT_ADDR[0], a second set VCT_ADDR[1], and so on. Alternatively, VCT RAM 800 may contain fewer or more sets 846 than 16.

[0375] VCT RAM 800 is a victim cache tag storage area configured to store addresses (e.g., tag addresses) corresponding to set 846. Each set 846 is coupled to a corresponding entity in a first instance comparator 850 and a corresponding entity in a second instance comparator 852. The first comparator 850 may be an instance implementation of the comparison logic 306a of Figures 3 and / or 5. The second comparator 852 may be an instance implementation of the comparison logic 306b of Figures 3 and / or 5. The first set VCT_ADDR[0] is coupled to the first entity in the first comparator 850 and the first entity in the second comparator 852, the second set VCT_ADDR[1] is coupled to the second entity in the first comparator 850 and the second entity in the second comparator 852, and so on.

[0376] The first comparator 850 and the second comparator 852 are coupled to corresponding instance address encoder logic circuits 854 and 856, including the first instance address encoder logic circuit 854 and the second instance address encoder logic circuit 856. The first comparator 850 is coupled to the first address encoder logic circuit 854. The second comparator 852 is coupled to the second address encoder logic circuit 856.

[0377] Address encoder logic circuits 854 and 856 may be exemplary embodiments of address encoders 326a and 326b of Figures 3 and / or 5. For example, the first address encoder logic circuit 854 may be an exemplary embodiment of address encoder 326a. In other embodiments, the second address encoder logic circuit 856 may be an exemplary embodiment of address encoder 326b.

[0378] The first instance multiplexer 858A is coupled to the first address encoder logic circuit 854. The first address encoder logic circuit 854 includes a first instance decoder 860A, a first instance inverter (e.g., logic gate, inverting logic gate, etc.) 862A, a first instance AND gate (e.g., logic gate, AND logic gate, etc.) 864A, a first instance OR gate (e.g., logic gate, OR logic gate, etc.) 866A, a first instance encoder 868A, a third instance comparator 870A, and a fourth instance comparator 872A.

[0379] For clarity, Figure 8B Only one instance of each of the first AND gate 864A, the first OR gate 866A, the third comparator 870A, and the fourth comparator 872A is depicted. However, each of the first AND gate 864A, the first OR gate 866A, the third comparator 870A, and the fourth comparator 872A may represent 16 instances of the components. For example, the first AND gate 864A may represent and / or otherwise implement 16 instances of the first AND gate 864A, the first OR gate 866A may represent and / or otherwise implement 16 instances of the first OR gate 866A, and so on.

[0380] The first multiplexer 858A has a first input for receiving ADP_ADDR_E2_DP0, which indicates that the DP0 interface is sending data to... Figures 3A-3D The address of the E2 arbitration level request. The first multiplexer 858A has a second input for receiving SNP_ADDR_E2_DP0, which indicates that the listening interface is requesting... Figures 3A-3DThe listening address for the E2 arbitration level request. The first multiplexer 858A has a selection input for receiving SNP_ADDR_EN_DP0, which represents an enable signal from the listening interface, which, upon confirmation, can invoke the first multiplexer 858A to select a second input. The output of the first multiplexer 858A is coupled to the input of the first comparator 850. For example, each of the first comparators 850 can compare an address from the output of the first multiplexer 858A with a corresponding address in the set of VCT RAM 800. In such instances, the first of the first comparators 850 can compare an address contained in ADP_ADDR_E2_DP0 with an address stored in VCT_ADDR[0]. In some such instances, the first of the first comparators 850 can output and / or otherwise generate a logical one in response to an address from the first multiplexer 858A matching an address stored in VCT_ADDR[0].

[0381] The output of the first multiplexer 858A is coupled to the first input of the third comparator 870A. The output of instance DP0 read finite state machine (FSM) (READ_FSM_DP0) 873 and / or the output of instance DP0 write finite state machine (WRITE_FSM_DP0) 874 are coupled to the second input of the third comparator 870A. DP0 read finite state machine 873 and DP0 write finite state machine 874 are hardware-implemented finite state machines that respond to inputs from... Figure 5 The scalar interface 502 executes data logic. For example, DP0 read finite state machine 873 and / or DP0 write finite state machine 874 can transfer one or more of WRM_TAG_UPDATE0, VTAG_WR_TAG0, and VTAG_WR_SET0 to the third comparator 870A and / or the fourth comparator 872A. DP0 read finite state machine 873 and / or DP0 write finite state machine 874 can transfer VTAG_WR_TAG0 to the sixth instance comparator 872B contained in the second address encoder logic circuit 856. WRM_TAG_UPDATE0, VTAG_WR_TAG0, and VTAG_WR_SET0 are combined above. Figure 8A describe.

[0382] The first decoder 860A is a 4x16 decoder. The first decoder 860A has inputs for receiving VTAG_WR_SET0 data, which can represent an in-flight address from scalar interface 502 to victim memory 218. The first decoder 860A has outputs coupled to the inputs of a first inverter 862A. The first decoder 860A can convert the in-flight address into a bit vector, where each bit is inverted by one of the 16 instances of the first inverter 862A. The output of the first inverter 862A is coupled to the first input of a first AND gate 864A. The second input of the first AND gate 864A is coupled to the result bit of a comparison between a first comparator 850 and a tag of set 0 (e.g., VCT_ADDR[0]) and the output of a first multiplexer 858A. For example, the second input of the first AND gate 864A can be configured to receive HIT_DP0 data, which can represent a 16-bit vector, where each bit can correspond to whether the ADP_ADDR_E2_DP0 data is a hit (e.g., bit value 1) or a miss (e.g., bit value 0) in the victim memory area 218.

[0383] The output of the first AND gate 864A is coupled to the first input of the first OR gate 866A. The output of the third comparator 870A is coupled to the second input of the first OR gate 866A. The output of the fourth comparator 872A is coupled to the third input of the first OR gate 866A. The output of the first OR gate 866A is coupled to the input of the first encoder 868A. The first encoder 868A is a 16x4 encoder. For example, the first encoder 868A can generate HIT_ADDR0 data, which can represent... Figure 8A VTAG_SET_DP0. In such instances, HIT_ADDR0 may correspond to Figure 8A The first output data is 838.

[0384] The second address encoder logic circuit 856 includes a second instance decoder 860B, a second instance inverter (e.g., logic gate, inverting logic gate, etc.) 862B, a second instance AND gate (e.g., logic gate, AND logic gate, etc.) 864B, a second instance OR gate (e.g., logic gate, OR logic gate, etc.) 866B, a second instance encoder 868B, a fifth instance comparator 870B, and a sixth instance comparator 872B.

[0385] For clarity, Figure 8BOnly one instance of each of the second AND gate 864B, the second OR gate 866B, the fifth comparator 870B, and the sixth comparator 872B is depicted. However, each of the second AND gate 864B, the second OR gate 866B, the fifth comparator 870B, and the sixth comparator 872B may represent 16 instances of the aforementioned components. For example, the second AND gate 864B may represent and / or otherwise implement 16 instances of the second AND gate 864B, the second OR gate 866B may represent and / or otherwise implement 16 instances of the second OR gate 866B, and so on.

[0386] The second address encoder logic circuit 856 has a first input for receiving ADP_ADDR_E2_DP1, which indicates that the DP1 interface is connected to... Figures 3A-3D The address requested by the E2 arbitration level. ADP_ADDR_E2_DP1 is coupled to the input of the second comparator 852. For example, each of the second comparators 852 can compare the address contained in ADP_ADDR_E2_DP1 with its counterpart in the set of VCT RAM 800. In such instances, the first of the second comparators 852 can compare the address contained in ADP_ADDR_E2_DP1 with the address stored in VCT_ADDR[0]. In some such instances, the first of the second comparators 852 can output and / or otherwise generate a logical one in response to an address contained in ADP_ADDR_E2_DP1 matching an address stored in VCT_ADDR[0].

[0387] ADP_ADDR_E2_DP1 is coupled to the first input of the fifth comparator 870B. The output of instance DP1 read finite state machine (READ_FSM_DP1) 875 and / or the output of instance DP1 write finite state machine (WRITE_FSM_DP1) 876 are coupled to the second input of the fifth comparator 870B. DP1 read finite state machine 875 and DP1 write finite state machine 876 are hardware-implemented finite state machines that respond to inputs from... Figure 5 The data execution logic of the vector interface 504. For example, DP1 read finite state machine 875 and / or DP1 write finite state machine 876 can transfer one or more of WRM_TAG_UPDATE1, VTAG_WR_TAG1, and VTAG_WR_SET1 to the fifth comparator 870B and / or the sixth comparator 872B. DP1 read finite state machine 875 and / or DP1 write finite state machine 876 can transfer VTAG_WR_TAG1 to the fourth comparator 872A contained in the first address encoder logic circuit 854. WRM_TAG_UPDATE1, VTAG_WR_TAG1, and VTAG_WR_SET1 are combined above. Figure 8Adescribe.

[0388] The second decoder 860B is a 4x16 decoder. The second decoder 860B has inputs for receiving VTAG_WR_SET1 data, which can represent an in-flight address from vector interface 504 to victim memory 218. The second decoder 860B has outputs coupled to the inputs of the second inverter 862B. The second decoder 860B can convert the in-flight address into a bit vector, where each bit is inverted by one of the 16 instances of the second inverter 862B. The output of the second inverter 862B is coupled to the first input of the second AND gate 864B. The second input of the second AND gate 864B is coupled to the resulting bits of the comparison between the second comparator 852 and tags from set 0 (e.g., VCT_ADDR[0]) and ADP_ADDR_E2_DP1. For example, the second input of the second AND gate 864B can be configured to receive HIT_DP1 data, which can represent a 16-bit vector, where each bit can correspond to whether the ADP_ADDR_E2_DP1 data is a hit (e.g., bit value 1) or a miss (e.g., bit value 0) in the victim memory area 218.

[0389] The output of the second AND gate 864B is coupled to the first input of the second OR gate 866B. The output of the fifth comparator 870B is coupled to the second input of the second OR gate 866B. The output of the sixth comparator 872B is coupled to the third input of the second OR gate 866B. The output of the second OR gate 866B is coupled to the input of the second encoder 868B. The second encoder 868B is a 16x4 encoder. For example, the second encoder 868B can generate HIT_ADDR1 data, which can represent... Figure 8A VTAG_SET_DP1. In such instances, HIT_ADDR1 may correspond to Figure 8A The second output data is 840.

[0390] In the example operation conditions, the first address encoder logic circuit 854 can receive... Figure 1 The first read address of the memory instruction requested by CPU 102 (e.g., ADP_ADDR_E2_DP0), where the first read address is from... Figures 3A-3DThe E2 pipeline-level (arbitration) reception. In response to the first multiplexer 858A selecting a first input, the first multiplexer 858A can transmit a first read address to a first comparator 850. The first comparator 850 can compare the read address with a corresponding address in set 846. If the first comparator 850 determines that the read address matches the address stored at the corresponding address in set 846, the first comparator 850 can confirm and / or otherwise output logic one; otherwise, the first comparator 850 outputs logic zero. Therefore, the first comparator 850 can generate HIT_DP0 as a 16-bit vector on the 16-bit data bus in response to the comparison. For example, the 16-bit vector can be an embodiment of a signal string (e.g., a burst of pulses) representing a bit vector. The first comparator 850 can transmit HIT_DP0 to a first AND gate 864A.

[0391] A portion of the first address encoder logic circuit 854 and / or the second address encoder logic circuit 856 is cache hit-miss translation logic. For example, the first AND gate 864A, the third comparator 870A, and / or the fourth comparator 872A may be an example implementation of cache hit-miss translation logic. In such examples, the second AND gate 864B, the fifth comparator 870B, and / or the sixth comparator 872B may be an example implementation of cache hit-miss translation logic.

[0392] The first AND gate 864A is configured to determine whether to convert a hit (e.g., cache hit) to a miss (e.g., cache miss). For example, while the first read address is being processed during the E2 pipeline stage, the new address (VTAG_WR_SET0) can... Figures 3A-3D During the E3 pipeline stage, the address is written to the victim memory 218. In such an instance, the first decoder 860A can convert the new address into a 16-bit value, which can be inverted by the first inverter 862A. The first inverter 862A can pass the inverted 16-bit value to the first input of the first AND gate 864A. The first AND gate 864A can confirm a logic one in response to VTAG_WR_SET0 not matching the address in HIT_DP0, and therefore does not convert a cache hit to a cache miss. In other instances, the first AND gate 864A can output a logic zero in response to VTAG_WR_SET0 matching the address in HIT_DP0, and therefore convert a cache hit to a cache miss because the address requested in ADP_ADDR_E2_DP0 has been overwritten and is no longer available at that address.

[0393] In the instance operation conditions, the third comparator 870A and the fifth comparator 870B can be configured to convert a cache miss to a cache hit. For example, the third comparator 870A can determine that the first read address (ADP_ADDR_E2_DP0) in VCT RAM 800 requested during the E2 pipeline stage is written in the E3 pipeline stage, represented by VTAG_WR_TAG0. In such an instance, the third comparator 870A can confirm logic one in response to ADP_ADDR_E2_DP0 matching VTAG_WR_TAG0, and thus convert a cache miss to a cache hit, and HIT_ADDR0 can be updated using VTAG_WR_SET0 because the data would have been available when the ADP_ADDR_E2_DP0 address was read during the E3 pipeline stage.

[0394] In the instance operation conditions, the fourth comparator 872A and the sixth comparator 872B can be configured to convert a cache miss to a cache hit. For example, the fourth comparator 872A can determine that the first read address (ADP_ADDR_E2_DP0) in VCT RAM 800 requested during the E2 pipeline stage is written in the E3 pipeline stage via vector interface 504, represented by VTAG_WR_TAG1. In such an instance, the fourth comparator 872A can confirm logic one in response to ADP_ADDR_E2_DP0 matching VTAG_WR_TAG1, and thus convert the cache miss to a cache hit, and HIT_ADDR0 can be updated using VTAG_WR_SET1 because the data would have been available when the ADP_ADDR_E2_DP0 address was read during the E3 pipeline stage.

[0395] In the example operation conditions, the first OR gate 866A and the second OR gate 866B can be configured to generate a corresponding output to either the first encoder 868A or the second encoder 868B. For example, the first OR gate 866B can transmit a 16-bit vector representing a cache miss (e.g., a 16-bit value of 0) or a 16-bit vector representing a cache hit (e.g., a 16-bit value of the address of the cache hit). In such an example, the first encoder 868A can encode the 16-bit value from the first OR gate 866A into a 4-bit address, and thus generate HIT_ADDR0. Such example operation can be applied to the second OR gate 866B, the second encoder 868B, and / or more generally, to the second address encoder logic circuit 856.

[0396] This document describes instance methods, devices, systems, and artifacts for multiple sets of victim caches with dual data paths. Other instances and combinations thereof include the following:

[0397] Example 1 includes a cache system comprising a storage element comprising a group for storing data, a port for receiving memory operations in parallel, each of the memory operations having a corresponding address, and a plurality of comparators coupled such that each of the comparators is coupled to a corresponding port in the port and a corresponding group in the group, and is available for determining whether a corresponding address of a corresponding memory operation received by the corresponding port corresponds to the data stored in the corresponding group.

[0398] Example 2 includes the caching system according to Example 1, further including a victim cache containing victim cache data, and the data being tag data corresponding to the victim cache data.

[0399] Example 3 includes a caching system according to Example 1, wherein the memory operation includes a first memory operation, the caching system further includes a cache containing cache data, the data being tag data corresponding to the cache data, and a first comparator of the plurality of comparators generates a signal in response to detecting a cache hit based on the first data associated with the first memory operation corresponding to the data in the storage element.

[0400] Example 4 includes a cache system according to Example 1, wherein the plurality of comparators are a plurality of first comparators, and the cache system further includes address encoder logic circuitry comprising: a decoder having decoder inputs and decoder outputs, the decoder inputs being coupled to a first finite state machine associated with a scalar interface of a central processing unit; a plurality of inverters having respective inverter inputs and respective inverter outputs, the inverter inputs being coupled to the decoder outputs; a plurality of AND logic gates having respective first inputs and respective second inputs, the corresponding of the first inputs being coupled to the corresponding of the inverter outputs, the corresponding of the second inputs being coupled to the corresponding of the outputs of the plurality of first comparators; a plurality of second comparators being coupled to the corresponding of the outputs of the plurality of first comparators and the first finite state machine; and a plurality of third comparators being coupled to the respective outputs of the plurality of first comparators and a second finite state machine associated with a vector interface of the central processing unit.

[0401] Example 5 includes the caching system according to Example 4, wherein a first AND logic gate of the plurality of AND logic gates outputs a low logic signal that converts a cache hit to a cache miss in response to a first address associated with the scalar interface matching a second address associated with the cache hit.

[0402] Example 6 includes the caching system according to Example 4, wherein a first comparator of the plurality of second comparators outputs a logic high signal that converts a cache miss to a cache hit in response to a first address associated with the scalar interface matching a second address associated with the cache miss.

[0403] Example 7 includes the caching system according to Example 4, wherein a first comparator of the plurality of third comparators outputs a logic high signal that converts a cache miss into a cache hit in response to a first address associated with the vector interface matching a second address associated with the cache miss.

[0404] Example 8 includes a cache system according to Example 4, wherein the address encoder logic circuitry comprises: a plurality of OR logic gates having corresponding third inputs, corresponding fourth inputs, and corresponding fifth inputs, the third inputs being coupled to corresponding outputs of the plurality of AND logic gates, the fourth inputs being coupled to corresponding outputs of the plurality of second comparators, and the fifth inputs being coupled to corresponding outputs of the plurality of third comparators; and an encoder having encoder inputs and encoder outputs, the encoder inputs being coupled to the outputs of the plurality of OR logic gates, and the encoder outputs being coupled to the inputs of a multiplexer.

[0405] Example 9 includes a cache system according to Example 1, wherein the plurality of comparators are a plurality of first comparators, and the cache system further includes address encoder logic circuitry comprising: a decoder having decoder inputs and decoder outputs, the decoder inputs being coupled to a first finite state machine associated with a vector interface of a central processing unit; a plurality of inverters having respective inverter inputs and respective inverter outputs, the inverter inputs being coupled to the decoder outputs; a plurality of AND logic gates having respective first inputs and respective second inputs, the corresponding gate in the first inputs being coupled to the corresponding gate in the inverter outputs, the corresponding gate in the second inputs being coupled to the corresponding gate in the outputs of the plurality of first comparators; a plurality of second comparators being coupled to the corresponding gates in the outputs of the plurality of first comparators and the first finite state machine; and a plurality of third comparators being coupled to the respective outputs of the plurality of first comparators and a second finite state machine associated with the vector interface of the central processing unit.

[0406] Example 10 includes a victim caching system comprising a victim cache storage queue containing a first data set and a victim storage area coupled to the victim cache storage queue, the victim storage area containing a second data set different from the first data set.

[0407] Example 11 includes a victim caching system according to Example 10, wherein at least one of the first data group or the second data group contains 16 data groups.

[0408] Example 12 includes a victim caching system according to Example 10, wherein the first data group comprises a first data group having 8 addresses, each address having a data width of 1 byte, and the first data group is configured to store 64 bits.

[0409] Example 13 includes a victim caching system according to Example 10, wherein the second data group comprises a second data group having 8 addresses, each address having a data width of 1 byte, and the second data group is configured to store 64 bits.

[0410] Example 14 includes a victim caching system according to Example 10, wherein the responder in the first data group is coupled to the responder in the second data group.

[0411] Example 15 includes a method for identifying a cache hit in a victim cache, the method comprising: receiving a first read address from a first interface of a processor, receiving a second read address from a second interface of the processor, comparing the first read address and the second read address with data groups of a plurality of victim cache tag memories, identifying a cache hit in response to at least one of the first read address or the second read address being mapped to a first data group in the data groups, and outputting a cache hit address representing a victim cache address of cache data stored in the victim cache.

[0412] Example 16 includes the method according to Example 15, wherein the first interface is a scalar interface and the second interface is a vector interface.

[0413] Example 17 includes the method according to Example 15, further comprising, in response to identifying the cache hit, comparing the cache hit address with a first address received from a finite state machine associated with the first interface, the first address representing an address written into the victim cache in a previous pipeline stage, and in response to the cache hit address matching the first address, converting the cache hit to a cache miss.

[0414] Example 18 includes the method according to Example 15, further comprising, in response to identifying the cache hit, comparing the cache hit address with a first address received from a finite state machine associated with the second interface, the first address representing an address written into the victim cache in a previous pipeline stage, and in response to the cache hit address matching the first address, converting the cache hit to a cache miss.

[0415] Example 19 includes the method according to Example 15, further comprising identifying a cache miss in response to at least one of the first read address or the second read address not mapping to either of the data sets, comparing the first read address with a first address received from a finite state machine associated with the first interface, the first address representing an address written to the victim cache in a subsequent pipeline stage, and converting the cache miss to a cache hit in response to the first read address matching the first address.

[0416] Example 20 includes the method according to Example 15, further comprising identifying a cache miss in response to at least one of the first read address or the second read address not mapping to either of the data sets, comparing the second read address with a first address received from a finite state machine associated with the second interface, the first address representing an address written to the victim cache in a subsequent pipeline stage, and converting the cache miss to a cache hit in response to the second read address matching the first address.

[0417] Example 21 includes the method according to Example 15, wherein comparing the first read address and the second read address is performed substantially in parallel with the data groups of the plurality of victim cache tag memories.

[0418] Methods and apparatus for allocation in victim cache systems

[0419] The data cache architecture, including a victim cache system, allows the main cache (e.g., main memory 214) to allocate data to the victim cache (e.g., victim memory 218) when the main cache needs to create a victim. For example, when an incoming instruction is a read miss, the main cache needs to make room for the read-miss data. The main cache can be a direct-mapped cache, such that read misses are stored in only one location, indicated by the read-miss address. The main cache can allocate data at the read-miss location to move to the victim cache when the data is invalid, and evict the data from the read-miss location to a higher-level memory location when the data at that location is clean. For example, the main cache controller can select a modified (e.g., invalid) line in the main memory as the victim and select an unmodified (e.g., clean) line in the main memory for eviction. A line of invalid and / or modified data is data that has been updated by CPU 102. For example, a cache line in main memory 214 is invalidated and / or modified when it exists only in its current state and has been modified from a value in main memory (e.g., causing a data read via extended memory 106 to be flagged or permitted because it is not up-to-date or valid), and is therefore an allocation (e.g., victim) candidate. Instance MESI RAM 300 stores and / or tracks cache line states (e.g., clean, invalid, shared, exclusive, etc.), thereby allowing and / or enabling the identification of invalid lines in main memory 214.

[0420] The allocation policy of the main memory area can instruct the main cache controller to select to degrade modified lines because the data at the memory address is not located in a higher-level cache, or is located in a higher-level cache but is outdated. Such an allocation policy can instruct the main cache controller not to allocate / degrade clean and / or shared lines in the main memory area because the lines contain data at memory addresses that are already located in higher-level caches (e.g., L2 cache, L3 cache, extended memory, etc.).

[0421] However, this allocation strategy introduces latency when only invalid and / or modified lines in the L1 cache 110 are allocated (e.g., increasing the time required for the CPU to retrieve the requested data). The latency is due to the use of additional clock cycles to retrieve data from higher-level memory. For example, due to the parallel connection of main memory 214 and victim memory 218, retrieving data from higher-level memory takes longer than retrieving data from victim memory 218.

[0422] In the examples described herein, the allocation strategy reduces the latency of allocating cache lines from the primary cache (e.g., primary storage 214) to the victim cache (e.g., victim storage 218). For example, due to the architecture of the L1 cache 110 (e.g., the parallel connection between primary storage 214 and victim storage 218), the allocation strategy enables the primary cache controller 222 to allocate any cache line (e.g., clean and / or invalid) from primary storage 214 to victim storage 218. The parallel configuration of primary storage 214 and victim storage 218 allows victim storage 218 to act as an extension of primary storage 214. Therefore, in addition to providing a location for storing victim lines, victim storage 218 can also provide additional associativity to primary storage 214 by moving any cache line (e.g., clean and / or invalid) from primary storage 214 to victim storage 214. For example, because victim storage 218 and main storage 214 are accessed in parallel (e.g., simultaneously) via CPU 102, if a clean row is pending access and it is allocated to victim storage 218, the latency of accessing a clean row of data will not occur.

[0423] In a typical operation, the main cache controller 222 receives instructions (e.g., memory operations) from the CPU interface 202 (e.g., scalar interface 502 and / or vector interface 504). The main cache controller 222 obtains the result corresponding to the instruction from the main tag RAM access 204. For example, the main tag RAM access 204 determines whether the address in the instruction matches an address in tag RAM 208 and provides the result to the main cache controller 222. In some instances, the main cache controller 222 determines that the main memory area 214 will maliciously and / or allocate data to the victim memory area 218 based on the instruction and the result from the main tag RAM access 204. For example, the main cache controller 222 determines whether the instruction is a read operation and whether the read operation is a miss (e.g., determined based on the result of the main tag RAM access 204). If the read operation is a miss, the main cache controller 222 determines that the main memory area 214 needs to allocate data lines, paths, blocks, slots, etc., for allocation in the victim memory area 218.

[0424] In some instances, the main cache controller 222 allocates lines corresponding to the addresses of read-miss operations. For example, if a read operation wants to read data from address A but main memory 214 stores different data at that address location (e.g., address A'), the main cache controller 222 must remove the data at address A' because data at address A can only be stored at one location in main memory 214 (e.g., address A). The main cache controller 222 identifies the location in the direct-mapped cache (e.g., main memory 214) mapped to address A' and allocates the data at address A' to the victim memory 218. Therefore, the read operation can store the data at address A in main memory 214.

[0425] This document describes example methods, devices, systems, and artifacts for data distribution. Other examples and combinations thereof include the following:

[0426] Example 1 includes a device comprising a first cache storage area, a second cache storage area, and a cache controller, the cache controller being coupled to the first cache storage area and the second cache storage area and being configured to receive a memory operation at a specified address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage area, determines that the first set of data is unmodified relative to the extended memory, and stores the first set of data in the second cache storage area.

[0427] Example 2 includes the device according to Example 1, wherein the cache controller identifies a portion of the first cache storage area corresponding to the direct mapping location of the address.

[0428] Example 3 includes the device according to Example 1, wherein the cache controller allocates the first set of data to the second cache storage area to create space for data to operate on the second memory.

[0429] Example 4 includes the device according to Example 1, wherein the cache controller receives a second memory operation specifying a second address, determines, based on the second address, that the second memory operation evicts a second set of data from the first cache storage area, determines that the second set of data is modified relative to the extended memory, and stores the second set of data in the second cache storage area.

[0430] Example 5 includes the device according to Example 1, wherein the cache controller performs pending transactions in the storage queue on the first set of data during the eviction period.

[0431] Example 6 includes the device according to Example 1, wherein the second cache storage provides association to the first cache storage when the first set of data is stored in the second cache storage.

[0432] Example 7 includes the device according to Example 1, wherein the second cache storage is a victim cache storage.

[0433] Example 8 includes a method comprising: receiving a memory operation at a specified address, determining, based on the address, that the memory operation evicts a first set of data from a first cache storage area, determining that the first set of data is unmodified relative to the extended memory, and storing the first set of data in a second cache storage area.

[0434] Example 9 includes the method according to Example 8, further comprising identifying a portion of the first cache storage area corresponding to the direct mapping location of the address.

[0435] Example 10 includes the method according to Example 8, further comprising allocating the first set of data to the second cache storage area to create space for data to operate on the second memory.

[0436] Example 11 includes the method according to Example 8, further comprising receiving a second memory operation specifying a second address, determining, based on the second address, that the second memory operation evicts a second set of data from the first cache storage area, determining that the second set of data is modified relative to the extended memory, and storing the second set of data in the second cache storage area.

[0437] Example 12 includes the method according to Example 8, which further includes performing pending transactions of the storage queue on the first set of data during the eviction period.

[0438] Example 13 includes the method according to Example 8, wherein storing the first set of data allocated from the first cache storage includes providing association to the first cache storage.

[0439] Example 14 includes the method according to Example 8, wherein the second cache storage is a victim cache storage.

[0440] Example 15 includes a system comprising a central processing unit (CPU) for outputting memory operations at specified addresses and a cache coupled to the CPU, the cache being available for obtaining the memory operations from the CPU, the cache further comprising a first cache storage area, a second cache storage area, and a cache controller, the cache controller being configured to determine, based on the address of the memory operation, that the memory operation evicts a first set of data from the first cache storage area, determines that the first set of data is unmodified relative to extended memory, and stores the first set of data in the second cache storage area.

[0441] Example 16 includes the system according to Example 15, wherein the cache further includes a first tag random access memory coupled to the central processing unit, the first cache storage area and the cache controller, and a second tag random access memory coupled to the central processing unit, the second cache storage area and the cache controller.

[0442] Example 17 includes the system according to Example 15, wherein the cache controller determines, based on a second address of a second memory operation, that the second memory operation evicts a second set of data from the first cache storage area, determines that the second set of data is modified relative to the extended memory, and stores the second set of data in the second cache storage area.

[0443] Example 18 includes the system described in Example 15, wherein the cache controller performs pending transactions in the storage queue on the first set of data during the eviction period.

[0444] Example 19 includes the system according to Example 15, wherein the first cache storage area and the second cache storage area are connected in parallel to the central processing unit.

[0445] Example 20 includes the system according to Example 15, wherein the first cache storage is a direct-mapped cache and the second cache storage is a fully associative cache, the direct-mapped cache and the fully associative cache being coupled in parallel to the central processing unit.

[0446] Read-modify-write support in a consistency victim cache to facilitate parallel data paths. Methods and equipment

[0447] To facilitate memory systems that operate with memory consistency, and consequently, memory systems in which corresponding memory bits of each processing element contain the same stored data, some instance systems cannot include victim memory areas. The instance described herein overcomes this challenge by facilitating fully consistent memory systems, where victim memory areas (e.g., victim memory area 218) can operate with memory consistency in the system.

[0448] To provide consistency on data cache 108, instance scalar interface 502 (e.g., a 64-bit wide interface) and instance vector interface 504 (e.g., a 512-bit wide interface) are included in victim memory 218 of L1 cache 110. In this way, victim memory 218 of L1 cache 110 can serve two data paths of CPU 102.

[0449] In some of the examples described herein, the listener address component 506 is used to store the MESI state of each cache line in the victim memory area 218 in the MESI RAM 300. By storing the MESI state of each cache line in the MESI RAM 300, the victim cache system supports consistency.

[0450] Furthermore, the instance listener address component 506 obtains instance listener requests from a higher-level memory cache (e.g., L2 data cache 112) and transmits such listener requests to the tag RAM 210 and compare logic 306c. In some instances, the listener address component 506 triggers an address read instruction to the tag RAM 210. For example, if the L2 data cache 112 cannot recognize the data requested in a read request from the CPU 102, the L2 data cache 112 transmits the listener address component 506 to a lower level, namely the L1 data cache 110, to attempt to execute a read request for a memory address in the tag RAM 210. The listener address component 506 then provides the address read to the compare logic 306c. In the event of a miss being recognized (e.g., a read to the tag RAM 210 returns a miss), an appropriate listener response indicating unsuccessful read is generated and transmitted to the higher-level data cache (e.g., L2 data cache 112) that generated the listener address component 506.

[0451] Alternatively, if a hit is detected (e.g., a read response to tag RAM 210 returns a hit), the status of the corresponding row in MESI RAM 300 is read, and instance address encoder 326c generates an address value for victim memory 218 to obtain data. Therefore, an appropriate response indicating a successful read request is generated and transmitted as a listener response back to a higher-level data cache (e.g., L2 data cache 112) that generated the listener address component 506. In the example described herein, the listener response contains data in victim memory 218 corresponding to the address in tag RAM 210.

[0452] In instance operation, the corresponding storage queue (e.g., victim cache queue 216) can handle write instructions to addresses that are being read via the listening address. Therefore, while victim storage 218 is serving a listening request (e.g., when a listening request is being processed in response to a listening address component 506 receiving a listening request), victim cache queue 216 forwards data from victim cache queue 216 (e.g., data stored in latch 402e) to response multiplexer 508. In this way, any state changes obtained via vector interface 504 due to the listening address and any recently updated addresses obtained from victim cache queue 216 are forwarded to higher-level data caches (e.g., L2 data cache 112).

[0453] exist Figure 5 In the topology shown, the coherence pipeline is longer than the victim cache pipeline to provide sufficient time for the victim cache controller 224 to properly order such snoop responses and / or subsequent CPU 102 operations if they are issued to a higher-level memory controller.

[0454] In the example described herein, when a cache line is requested to be traced, the victim store 218 of the L1 data cache 110 can issue a tag update to a higher-level cache controller. In this way, the victim store 218 can facilitate the tracing of cache lines to distinguish between exclusive and modified cache elements.

[0455] In the example described herein, the victim storage area 218 of the L1 data cache 110 supports global consistency operations by allowing global consistency operations to be processed on a fully associative cache and iterated on the tag RAM 208 based on groups.

[0456] Although the above operations are described in conjunction with L1 data cache 110, any of the above operations and / or elements may be implemented on any of the additional levels of data caches in L2 data cache 112, L3 data cache 114 and / or data cache 108.

[0457] This document describes instance methods, devices, systems, and artifacts for facilitating read-modify-write support in consistency victim caches with parallel data paths. Other instances and combinations thereof include the following:

[0458] Example 1 includes a device comprising: a random access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random access memory being configured to receive a read request indicating a first address to be read via a listening interface; an address encoder coupled to the random access memory, the address encoder being configured to generate a second address corresponding to a victim cache based on the first address when the random access memory indicates a hit of the read request; and a multiplexer coupled to the victim cache to transmit a response containing data obtained from the second address of the victim cache.

[0459] Example 2 includes the device according to Example 1, wherein the read request is transmitted via a secondary data cache.

[0460] Example 3 includes the device according to Example 1, wherein the multiplexer is configured to be coupled to a victim cache store queue, the multiplexer being used to obtain input data from the victim cache store queue indicating a value to be written to the second address.

[0461] Example 4 includes the device according to Example 3, wherein the multiplexer is configured to transmit the response containing the input data from the victim cache storage queue.

[0462] Example 5 includes the device according to Example 1, wherein the random access memory is a tag random access memory.

[0463] Example 6 includes the device according to Example 1, wherein the victim cache is a plurality of memory sets.

[0464] Example 7 includes the device according to Example 1, wherein the first interface is a scalar interface and the second interface is a vector interface.

[0465] Example 8 includes the device according to Example 7, wherein the scalar interface is a 64-bit wide interface and the vector interface is a 512-bit wide interface.

[0466] Example 9 includes a system comprising a controller, a first memory, and a second memory configured to receive a listening request from the first memory, the second memory being configured to execute a read request of random access memory in response to the listening request, and generating an address corresponding to a victim cache when the random access memory indicates a hit of the read request, the address being used to read the victim cache, and transmitting a response to the second memory containing data obtained from the address of the victim cache.

[0467] Example 10 includes the system according to Example 9, wherein the first memory is a level 2 cache memory and the second memory is a level 1 cache memory.

[0468] Example 11 includes the system according to Example 9, wherein the second memory includes a multiplexer configured to be coupled to a victim cache memory queue, the multiplexer being used to obtain input data from the victim cache memory queue indicating a value of the address to be written to the victim cache in the second memory.

[0469] Example 12 includes the system according to Example 11, wherein the multiplexer is configured to transmit the response containing the input data from the victim cache storage queue.

[0470] Example 13 includes the system according to Example 9, wherein the second memory is coupled to the controller via a scalar interface and a vector interface, and the second memory is coupled to the first memory via a listening interface.

[0471] Example 14 includes the system described in Example 13, wherein the scalar interface is a 64-bit wide interface and the vector interface is a 512-bit wide interface.

[0472] Example 15 includes the system described in Example 13, wherein the controller is a central processing unit.

[0473] Example 16 includes a method comprising obtaining a read request indicating a first address to be read via a listening interface, generating a second address corresponding to a victim cache based on the first address when the read request is a hit, and generating a response containing data obtained from the second address in the victim cache.

[0474] Example 17 includes the method according to Example 16, further comprising transferring the read request from a secondary data cache.

[0475] Example 18 includes the method according to Example 16, further comprising obtaining input data from a victim cache storage queue indicating a value to be written to the second address.

[0476] Example 19 includes the method according to Example 18, further comprising transmitting the response containing the input data from the victim cache storage queue.

[0477] Example 20 includes the method according to Example 16, wherein the victim cache is a multi-set memory.

[0478] Method and apparatus for eviction in a dual-data-path victim cache system

[0479] In a victim cache system, when the primary cache (e.g., primary memory 214) needs to store new data, the primary cache sacrifices (e.g., allocates) a cache line to the victim cache (e.g., victim memory 218). When the primary cache creates a victim, a substitution policy (e.g., substitution policy component 308) determines where the victim can be stored in the victim cache (e.g., victim memory 218). In some instances, the victim cache is full, so data needs to be evicted to a higher-level cache memory (e.g., L2 cache 112, L3 cache 114, extended memory 106). When a write miss occurs, the victim cache (e.g., victim memory 218) also evicts data to a higher-level cache memory. For example, victim memory 218 contains a write miss buffer that buffers write miss data. The substitution policy can utilize fixed schemes to determine which data to evict from the victim cache. For example, eviction schemes such as First-In-First-Out (FIFO), random, and Least Recently Used (LRU) schemes. However, when there are two or more data paths, such eviction schemes are not configured to effectively manage data evicted from the victim's cache.

[0480] For example, a FIFO scheme evicts the data block that has been in the victim cache the longest (e.g., data in slot 0 if it's the first time eviction occurs). In a dual-data-path victim cache system (e.g., ...), ... Figure 5 In the victim cache segment shown, the FIFO scheme does not work when two incoming CPU accesses (e.g., instructions) both miss and / or both are allocating instructions. In such instances, additional stops occur if neither set from the victim cache is speculatively locked and read.

[0481] In different instances, main memory 214 stores address A and victim memory 218 stores address B. CPU 102 sends two requests: CPU 102 requests to read data from address A' using DP0 and CPU 102 requests to read data from address B using DP1. The data at address A' is mapped to the same location in main memory 214 as address A. Therefore, the first data path DP0 needs to allocate the data at address A to victim memory 218 (e.g., allocate the data at address A' to main memory 214). In a normal FIFO scheme, address A would be allocated to slot 0 of victim memory 218. However, slot 0 is occupied by address B, and CPU 102 requests access to address B in parallel with the request to allocate the data for the read instruction to address A'. Therefore, if data path DP0 evicts address B from slot 0, a stop (e.g., causing CPU 102 to stop waiting for memory access for one or more cycles) will occur so that the evicted data can be retrieved later from a higher-level cache.

[0482] The example described herein includes an eviction scheme for efficiently evicting data from victim memory 218 in a dual-data-path victim cache system. The instance eviction scheme is implemented by replacement policy component 308 of Figures 3 and 5. For example, replacement policy component 308 includes logic that analyzes input and produces output. For example, replacement policy component 308 receives input from hit-miss comparison logic 306a and 306b and determines which location in victim memory 218 will be replaced by data from main memory 214 and / or by data from a write-miss instruction. In the example described herein, replacement policy component 308 retains entries (e.g., paths, sets, cache lines, etc.) in victim memory 218 corresponding to the eviction locations. For example, replacement policy component 308 speculatively locks (e.g., retains) first and second victim cache lines (e.g., sets) specifically for eviction. First and second victim cache lines can be locked for specific data paths (e.g., a first victim cache line locked for DP0 and a second victim cache line locked for DP1). The following is in conjunction with... Figure 6 The eviction logic implemented by the alternative policy component 308 is described in more detail.

[0483] Turning Figure 6Instance First Table 602 and Instance Second Table 604 are depicted. Instance First Table 602 and Instance Second Table 604 describe the logic of Instance Replacement Policy Component 308. Instance Replacement Policy Component 308 utilizes LRU values. As used herein, an LRU value corresponds to a path that is the least recently used portion of the victim storage area 218. In some instances, an LRU value corresponds to a location in the victim storage element 218 that has not been accessed by the first or second data path recently. In a fully associative cache (e.g., victim storage area 218), addresses can be mapped to any “path” in the cache. Thus, a path is a block in the cache that stores data and contains a tag. In some LRU schemes, when the victim cache needs to evict data, the data in the location indicated by the LRU value (e.g., data in the least recently accessed portion of the victim storage area 218) is evicted. For example, in a 3-path cache, addresses A, B, and C occupy all three paths (e.g., blocks, slots, etc.). In this example, address A was recently accessed by CPU 102, address B was accessed before address A, and address C was accessed before address B. Therefore, address C is the least recently used address, and the portion of address C mapped to is equal to the LRU value.

[0484] Figure 6 The first table 602 of the instance contains a first data path scenario 606, a second data path scenario 608, and a third data path scenario 610. Instance data path scenarios 606, 608, and 610 correspond to... Figure 5 The validity of transactions (e.g., accesses) on DP0 and DP1. Transaction validity corresponds to whether CPU 102 sends a valid instruction to L1 cache 110. A valid instruction on the first data path DP0 and an invalid instruction on the second data path DP1 correspond to when the processing core sends an instruction on the first data path DP0 and leaves the second data path DP1 idle. In some instances, the first data path DP0 contains invalid instructions during a specific clock cycle. In some instances, the second data path DP1 contains invalid instructions during a specific clock cycle. Additionally and / or alternatively, both data paths DP0 and DP1 may contain valid instructions and / or may contain invalid instructions.

[0485] In instance table 602, the first data path scenario 606 corresponds to when Figure 5 When two data paths (DP0, DP1) contain valid transactions within the same clock cycle (DP0_valid = 1, DP1_valid = 1), in some instances, the alternative policy component 308 obtains results and / or instructions from both data paths DP0 and DP1.

[0486] In instance 1 table 602, second data path scenario 608 corresponds to a first data path (DP0) containing a valid transaction (DP0_valid = 1) and a second data path (DP1) containing an invalid transaction (DP1_valid = 0). In such instances, alternative policy component 308 determines that the transaction of DP1 contains an invalid instruction.

[0487] In instance table 602, the third data path scenario 610 corresponds to the first data path (DP0) containing an invalid transaction (DP0_valid = 0) and the second data path (DP1) containing a valid transaction (DP1_valid = 1). In some instances, the alternative policy component 308 determines that the transaction of DP0 contains an invalid instruction.

[0488] Instance First Data Path Scenario 606 in Instance First Table 602 includes Instance Hit-Hit Action 612, Instance Miss-Hit Action 614, Instance Hit-Miss Action 616, and Instance Miss-Miss Action 618. Instance Hit-Hit Action 612 indicates that an address on DP0 and an address on DP1 hit (e.g., match) an address in either tag RAM 208 or 210. In other words, Instance Hit-Hit Action 612 indicates that an address on DP0 and an address on DP1 hit main memory 214, victim memory 218, and / or write to a miss cache (combined with the above). Figures 3A-3DThe address in the description. Instance miss-hit action 614 indicates that the address on DP0 does not match the address in main memory 214, victim memory 218, and / or write-miss cache, and the address on DP1 matches the address in main memory 214, victim memory 218, and / or write-miss cache. In some instances, the miss portion of miss-hit action 614 indicates that DP0 will allocate a cache line from main memory 214 to victim memory 218, and thus evict data from victim memory 218 to free up cache lines in main memory 214. Instance hit-hit action 616 indicates that the address on DP0 matches the address in victim memory 218 and / or write-miss cache, and the address on DP1 does not match the address in victim memory 218 and / or write-miss cache. In some instances, the miss portion of the hit-miss action 616 indicates that DP1 will allocate a cache line from main memory 214 to victim memory 218, and thus evict data from victim memory 218 to free up space in the cache line of main memory 214. Instance miss-miss action 618 indicates that the addresses of DP0 and DP1 do not match in victim memory 218 and / or the write miss cache. In some instances, miss-miss action 618 indicates that both data paths DP0 and DP1 will allocate data from main memory 214 to victim memory 218. Additionally and / or alternatively, a miss indicating a write miss is writing data to the write miss buffer in victim memory 218.

[0489] Instance 2 data path scenario 608 in instance table 602 includes instance DP0 hit action 620 and instance DP0 miss action 622. In second data path scenario 608, first data path DP0 contains a valid transaction and second data path DP1 contains an invalid transaction. In some instances, alternative policy component 308 ignores second data path DP1 because second data path DP1 does not contain instructions.

[0490] Instance 3 data path scenario 610 in Instance 1 Table 602 includes Instance DP1 hit action 624 and Instance DP1 miss action 626. Instance DP1 hit action 624 corresponds to the action taken by the substitution policy component 308 when the address of the second data path DP1 matches the address in the victim storage area 218 and / or the write-miss cache. Instance DP1 miss action 624 corresponds to the action taken by the substitution policy component 308 when the address of the second data path DP1 does not match the address in the victim storage area 218 and / or the write-miss cache. Similar to Instance DP0 hit action 620 and DP0 miss action 622 under Instance 2 data path scenario 608, Instance substitution policy component 308 ignores the transaction of the first data path DP0 in Instance 3 data path scenario 610 because the transaction is invalid.

[0491] In Example 1 Table 602, the DP0 hit path indicates the victim memory area 218 that should be accessed by the first data path DP0 when an instruction is hit (e.g., read from the first data path, evicted from the first data path, written to the first data path, etc.) and / or written to a portion of the miss cache. In Example 1 Table 602, the DP1 hit path is the victim memory area 218 that should be accessed by the second data path DP1 when an instruction is hit and / or written to a portion of the miss cache.

[0492] In Instance 1 Table 602, the variable 'Y' is a variable indicating the location of the current path selected as LRU and indicating where the first data path DP0 should remove data from. In some instances, Y is assigned to the DP0 pointer. For example, when DP0 needs to evict a portion of the victim memory 218, the DP0 pointer points to location Y (e.g., the LRU path) for eviction. In some instances, the replacement policy component 308 stores indicators of the LRU paths of the victim memory 218 to be replaced by DP0. For example, the replacement policy component 308 maintains indicators accessible by the cache controller 220 that indicate a particular path that has not been recently accessed is available for eviction by the first data path DP0. As used herein, the terms "pointer" and "indicator" are used interchangeably.

[0493] In Instance 1 Table 602, the variable 'Y+1' indicates the location of the next LRU path from which data should be removed by the second data path DP1. In some instances, 'Y+1' is assigned to the DP1 pointer. For example, when the second data path DP1 needs to evict a portion of the victim memory 218, the DP1 pointer points to location Y+1 (e.g., the next LRU path) to perform the eviction. In some instances, the replacement policy component 308 stores indicators of the LRU paths of the victim memory 218 to be replaced by DP1. For example, the replacement policy component 308 maintains indicators accessible by the cache controller 220 that indicate a particular path that has not been recently accessed is available for eviction by the first data path DP0.

[0494] In the first instance operation of the substitution policy component 308, both data paths (DP0 and DP1) contain valid transactions (e.g., indicated in the first data path scenario 606) and both data paths (DP0 and DP1) contain addresses that match addresses in the instance victim storage element 218 (e.g., hit-hit action 612). For example, comparison logics 306a and 306b compare the addresses of DP0 and DP1 with addresses in the instance tag RAM 210 and provide the hit result to the substitution policy component 308. Since both data paths are valid and both data paths are hits, the DP0 hit path points to the portion of the victim storage area 218 containing the hit / match data corresponding to data path DP0 (e.g., a path), and the DP1 hit path points to the path containing the hit / match data corresponding to data path DP1. The victim storage area 218 responds with the requested data. The position of the LRU path does not increment and remains at position Y.

[0495] In a second instance operation of the substitution strategy component 308, both data paths (DP0 and DP1) contain valid transactions (e.g., indicated in the first data path scenario 606), the first data path DP0 is a miss, and the second data path DP1 hits the victim store 218 (e.g., miss-hit action 614). For example, the first comparison logic 306a returns a "miss" result to the substitution strategy component 308, and the second comparison logic 306b returns a "hit" result to the substitution strategy component 308. The DP1 hit path points to the portion (e.g., the path) in the victim store 218 containing the hit / matched data (e.g., the hit path). In some instances, the first data path DP0 will evict data from a portion (e.g., the path) in the victim store 218. Therefore, the DP0 pointer points to the location Y in the victim store 218 where data will be evicted.

[0496] Before eviction occurs, the substitution policy component 308 determines whether the DP1 hit path matches the address (e.g., position Y) of an LRU path. If the DP1 hit path does not have the same position as Y, the DP0 pointer points to the path with the same position as position Y (e.g., the LRU path). If the DP1 hit path does match the address of an LRU path, the DP0 pointer points to the position (Y+1) of the DP1 pointer, allowing DP0 to evict data without conflicting with the DP1 hit path.

[0497] In the second instance scenario 614, the LRU value and the next LRU value are incremented based on which position was evicted. For example, if DP0 evicts data from position Y+1 (e.g., DP1 hits a path that matches the position of the DP0 pointer), the LRU value is incremented twice and the next LRU value is incremented twice. Otherwise, if DP0 evicts data from position Y (e.g., DP1 hits a path that does not match the position of the DP0 pointer), the LRU value is incremented once and the next LRU value is incremented once.

[0498] In the third instance operation of the substitution strategy component 308, both data paths (DP0 and DP1) contain valid transactions (e.g., indicated in the first data path scenario 606), the first data path DP0 is a hit, and the second data path DP1 is a miss (e.g., hit-miss action 616). For example, the first comparison logic 306a returns a "hit" result to the substitution strategy component 308, and the second comparison logic 306b returns a "miss" result to the substitution strategy component 308. The DP0 hit path points to the path in the victim store 218 containing the hit / matched data. In some instances, the miss causes the second data path DP1 to be evicted from the path to free up space in the victim store 218. Therefore, the DP1 pointer points to the position Y+1 in the victim store 218 where it will be evicted.

[0499] Before eviction occurs, the substitution policy component 308 determines whether the DP0 hit path matches the address of the next LRU path (e.g., position Y+1). If the substitution policy component 308 determines that the DP0 hit path matches the address of the next LRU path (e.g., position Y+1), the DP1 pointer is moved to the position of the DP0 pointer (e.g., position Y), allowing DP1 to evict data without conflicting with the DP0 hit path. If the DP0 hit path does not match the address of the next LRU path, DP1 evicts data from position Y+1.

[0500] In the third instance scenario 616, the LRU value and the next LRU value are incremented based on which position was evicted. For example, if DP1 evicts data from position Y (e.g., DP0 hits a path that matches the position of the DP1 pointer), the LRU value is incremented once and the next LRU value is incremented once. Otherwise, if DP1 evicts data from position Y+1 (e.g., DP0 hits a path that does not match the position of the DP1 pointer), the LRU value is incremented twice and the next LRU value is incremented twice.

[0501] In the fourth instance operation of the substitution policy component 308, both data paths (DP0 and DP1) contain valid transactions (e.g., indicated in the first data path scenario 606) and both data paths are marked as misses (e.g., column 618). For example, when no address is found and / or does not match an address in tag RAMs 208, 210 in data paths DP0 and DP1, comparison logics 306a and 306b return a "miss" result to the substitution policy component 308. In the fourth operation, both data paths DP0 and DP1 are evicted from the path in victim memory 218. Therefore, the DP0 pointer points to position Y and the DP1 pointer points to position Y+1.

[0502] When both eviction operations are complete, the LRU value is incremented by two (e.g., Y+2) and the next LRU value is incremented by two (e.g., (Y+1)+2). In subsequent operations, if DP0 and DP1 are both missed, the DP0 path points to the new LRU value (e.g., Y+2) and the DP1 path points to the next LRU value (e.g., (Y+1)+2).

[0503] In the fifth instance operation of the substitution policy component 308, the first data path DP0 is a valid transaction and the second data path DP1 is an invalid transaction (e.g., indicated in the second data path scenario 608). In the fifth instance operation, the first data path DP0 is a hit (e.g., indicated in the DP0 hit action 620). For example, the comparison logic 306a returns a "hit" result to the substitution policy component 308. The DP0 hit path points to the path in the victim memory 218 containing the matching data. The LRU value (Y) remains unchanged because no data is to be evicted during the clock cycle.

[0504] In the sixth instance operation of the substitution policy component 308, the first data path DP0 is a valid transaction and the second data path DP1 is an invalid transaction (e.g., indicated in the second data path scenario 608). In the sixth instance operation, the first data path DP0 is a miss (e.g., indicated in the DP0 miss action 622). For example, comparison logic 306a returns a "miss" result to the substitution policy component 308. In this instance, the first data path DP0 evicts data from the victim store 218. The instance DP0 pointer points to position Y (e.g., LRU path). After evicting, the LRU value is incremented (e.g., Y+1).

[0505] In the seventh instance operation of the substitution policy component 308, the first data path DP0 is an invalid transaction and the second data path DP1 is a valid transaction (e.g., indicated in the third data path scenario 610). In the seventh instance operation, the second data path DP1 is a hit (e.g., indicated in the DP1 hit action 624). For example, the comparison logic 306b returns a "hit" result to the substitution policy component 308. The DP1 hit path points to the path in the victim memory 218 containing the matching data. The LRU value (Y) remains unchanged because no data is to be evicted during the clock cycle.

[0506] In the eighth instance operation of the substitution policy component 308, the first data path DP0 is an invalid transaction and the second data path DP1 is a valid transaction (e.g., indicated in the third data path scenario 610). In the eighth instance operation, the second data path DP1 is a miss (e.g., indicated in the DP1 miss action 626). For example, comparison logic 306b returns a "miss" result to the substitution policy component 308. In this instance, the second data path DP1 evicts data from the victim store 218. The DP1 pointer points to position Y (e.g., the LRU path). Due to the invalid transaction of DP0, the DP1 pointer does not point to position Y+1. Otherwise, when both transactions are valid, DP1 always points to Y+1 (e.g., unless it switches when the DP0 hit path matches Y+1). After the second data path DP1 evicts data from position Y, the LRU value is incremented (e.g., Y+1).

[0507] Turning to the second table 604, which shows the increase in the LRU value when the first data path DP0 and / or the second data path DP1 allocates data to the victim storage area 218. For example, when a read-miss occurs, the primary storage area 214 allocates a row of data to the victim storage area 218 using one of the data paths. The second table 604 contains a first valid column 626, a second valid column 628, a first allocation column 630, a second allocation column 632, a first LRU interference column 634, a second LRU interference column 636, and an LRU increment column 638.

[0508] In the second table 604, instance first valid column 626 corresponds to the validity of the second data path transaction. For example, zero (0) indicates that the DP1 transaction is invalid, and a - (1) indicates that the DP1 transaction is valid. Instance second valid column 628 corresponds to the validity of the first data path transaction. For example, zero (0) indicates that the DP0 transaction is invalid, and a - (1) indicates that the DP0 transaction is valid.

[0509] In the second table 604, instance first allocation column 630 indicates the allocation status of the second data path DP1. The allocation status corresponds to the data allocation from main memory 214 to victim memory 218 within a clock cycle. For example, zero (0) indicates that the second data path DP1 has not allocated data to victim memory 218, while a - (1) indicates that the second data path DP1 has allocated data to victim memory 218. Instance second allocation column 632 indicates the allocation status of the first data path DP0. For example, zero (0) indicates that the first data path DP0 has not allocated data to victim memory 218, while a - (1) indicates that the first data path DP0 has allocated data to victim memory 218. When a data path allocates data to victim memory 218, the data path evicts a path (e.g., slot, block, etc.) to make room for the allocated data. In some instances, data is allocated to victim memory 218 when a read-miss occurs in main memory 214.

[0510] In the second table 604, the first LRU interference column 634 indicates whether the first data path DP0 hits a location in the victim storage area 218 that is the same as the location of the second data path allocation pointer. For example, the address of the first data path DP0 is located at the least recently used location in the victim storage area 218. The first LRU interference column 634 includes a (1) to indicate that the hit location of the first data path DP1 is equal to the location of the second data path DP1 allocation pointer.

[0511] The second LRU scrambler column 636 indicates whether the second data path DP1 hits a location in the victim memory 218 that is the same as the location of the second data path allocation pointer. For example, the address of the second data path DP1 is located at the least recently used location in the victim memory 218. The second LRU scrambler column 636 includes a (1) to indicate that the hit location of the second data path DP1 is equal to the location of the first data path allocation pointer. As used herein, when DP0 is to be allocated, the first data path allocation pointer points to location Y (LRU value), and when DP1 is to be allocated, the second data path allocation pointer points to location Y+1 (next LRU value). In some instances, the pointers notify the cache controller 220 to evict a portion of the victim memory 218 to a higher-level cache (e.g., L2 112, L3 114, via extended memory 106). Instance replacement policy component 308 may initialize the first data path allocation pointer to point to location Y (LRU portion) and initialize the second data path allocation pointer to point to Y+1 (next LRU portion).

[0512] In the second table 604, the LRU increment column 628 indicates the increment of the LRU value Y. For example, the substitution strategy component 308 may increment the LRU value by one (e.g., Y+1), two (e.g., Y+2), or not at all (e.g., Y). In some instances, the increment of the LRU value depends on the state of data paths DP0 and DP1.

[0513] In instance operation, both the first data path DP0 and the second data path DP1 contain valid transactions. The instance replacement policy component 308 determines whether to allocate any data path. For example, when primary storage 214 needs to allocate data, the cache controller 220 sends a message to the replacement policy component 308.

[0514] If the first data path DP0 allocates data (e.g., moves data from main storage 214 to victim storage 218), then the first data path DP0 evicts the data from victim storage 214 (e.g., indicated by the first data path allocation pointer). To evict the data, the substitution policy component 308 determines whether the second data path DP1 is hit and where the hit occurs. For example, the substitution policy component 308 analyzes the location of the address of the second data path DP1 and determines whether said location matches the location of the first data path allocation pointer.

[0515] If the hit position of the second data path equals the position of the first data path allocation pointer (e.g., DP1 hit position = Y), the replacement policy component 308 updates the first data path allocation pointer to point to the next LRU value (Y+1) (e.g., notifying the cache controller 220 to evict the data of the next LRU value). In this way, the second data path DP1 reads / writes from the hit position Y and the first data path DP0 evicts data at LRU position Y+1. Through this operation, the first data path DP0 will not evict the read / write data of DP1. After the eviction occurs (e.g., data is evicted from Y+1 in the victim memory 218), the replacement policy component 308 increments the first data path allocation pointer by two and increments the second data path allocation pointer by two. For example, the replacement policy component 308 increments the LRU value (Y) by two and the next LRU value (Y+1) by two, because DP0 has just evicted at position Y+1, so the new LRU value will be Y+2. This operation is shown in line 640.

[0516] If the second data path hit location is not equal to the location of the first data path allocation pointer (e.g., DP1 hit location is not equal to Y), the replacement policy component ...

Claims

1. An apparatus comprising: Cache memory; as well as A cache controller, coupled to and configured to: A portion of the cache memory is allocated for write misses; Receive write operations; Determine whether the write operation is associated with a miss in the remaining portion of the cache memory; Based on the association of the write operation with the miss in the remaining portion of the cache memory, a set of write miss information is stored in the write miss cache; Receive the read operation associated with the write operation; as well as The read operation is serviced using the set of write miss information stored in the write miss cache.

2. The apparatus according to claim 1, wherein: The set of write miss information includes a set of data associated with the write operation; and Providing the service for the read operation includes providing the set of data from the write miss cache.

3. The apparatus according to claim 1, wherein: The cache memory is a first cache memory; The device further includes a second cache memory coupled to the cache controller and configured as a main cache; and The cache controller is further configured to: The remaining portion of the cache memory is allocated as a victim cache; as well as This causes the set of write miss information to be stored in the write miss cache, further based on the write operation associated with the miss in the main cache.

4. The apparatus according to claim 3, wherein: The main cache is a Level 1 L1 main cache; The victim cache is an L1 victim cache; and The cache controller is an L1 cache controller.

5. The apparatus of claim 4, wherein the cache controller is configured to: The utilization rate of the write-miss cache is compared with a threshold; and Based on the utilization rate exceeding the threshold, the set of write miss information is provided to the L2 cache subsystem.

6. The apparatus of claim 5, wherein the threshold corresponds to the bandwidth of the interface of the L2 cache subsystem.

7. The apparatus of claim 5, wherein the threshold corresponds to the size of the write miss cache.

8. The apparatus according to claim 1, wherein: The set of write miss messages is the first set of write miss messages; and The cache controller is configured to merge the first set of write miss information with the second set of write miss information when the first memory address of the first set of write miss information corresponds to the second memory address of the second set of write miss information stored in the write miss cache.

9. The apparatus of claim 1, wherein the write miss cache includes a byte enable register.

10. The apparatus of claim 9, wherein the byte enable register is configured to store the value of an element specifying the set of write miss information to be written.

11. An apparatus comprising: The processing core is configured to provide write operations; A cache controller, which is coupled to the processing core; A first cache memory, which is coupled to the processing core; as well as A second cache memory, coupled to the processing core, includes write-miss cache and remaining portions; The cache controller is configured to: Determine whether the write operation is associated with a miss in the first cache memory and a miss in the remaining portion of the second cache memory; Based on the association between the write operation and the miss in the first cache memory and the miss in the remaining portion of the second cache memory, a set of write miss information is stored in the write miss cache. Receive the read operation associated with the write operation; as well as The read operation is serviced using the set of write miss information stored in the write miss cache.

12. A method comprising: Allocate a portion of the cache memory for write misses; Receive write operations; Determine whether the write operation is associated with a miss in the remaining portion of the cache memory; Based on the association between the write operation and the miss in the remaining portion of the cache memory, a set of write miss information is stored in the write miss cache; Receive the read operation associated with the write operation; as well as The read operation is serviced using the set of write miss information stored in the write miss cache.

13. The method according to claim 12, wherein: The set of write miss information includes a set of data associated with the write operation; and Using the set of write miss information to provide the service for the read operation includes providing the set of data from the write miss cache.

14. The method according to claim 12, wherein: The cache memory is a first cache memory; and The method further includes: The remaining portion of the first cache memory is allocated as a victim cache; and The set of write miss information is stored in the write miss cache, further based on the write operation associated with a miss in the second cache memory.

15. The method of claim 14, wherein: The second cache memory is a Level 1 (L1) main cache; and The first cache memory is an L1 victim cache.

16. The method of claim 15, further comprising: The utilization rate of the write-miss cache is compared with a threshold; as well as Based on the utilization rate exceeding the threshold, the set of write miss information is provided to the L2 cache subsystem.

17. The method of claim 16, wherein the threshold corresponds to the bandwidth of the interface of the L2 cache subsystem.

18. The method of claim 16, wherein the threshold corresponds to the size of the write miss cache.

19. The method according to claim 12, wherein: The set of write miss messages is the first set of write miss messages; and The method further includes merging the first set of write miss information with the second set of write miss information when the first memory address of the first set of write miss information corresponds to the second memory address of the second set of write miss information stored in the write miss cache.

20. The method of claim 12, wherein: The write-miss cache includes a byte enable register; and The method further includes storing the values ​​of the set of write miss information elements to be written in the byte enable register.

21. An apparatus comprising: The first cache memory includes a first part and a second part; as well as A cache controller, coupled to and configured to: The write operation is determined to be associated with a miss in the first portion of the first cache memory; Since the write operation is associated with a miss in the first part, the write miss information is stored in the second part of the first cache memory; Receive the read operation associated with the write operation; as well as The write miss information stored in the second part of the first cache memory is used to service the read operation.

22. The apparatus according to claim 21, wherein: The write miss information includes data associated with the write operation; and In order to use the write miss information to service the read operation, the cache controller is configured to provide the data from the second portion of the first cache memory.

23. The apparatus of claim 21, wherein the cache controller is configured to: This causes data evicted from the second cache memory to be stored in the first cache memory.

24. The apparatus according to claim 23, wherein: The second cache memory is a Level 1 (L1) main cache memory; and The first cache memory is the L1 victim cache memory.

25. The apparatus of claim 24, wherein the cache controller is configured to: The utilization rate of the second portion of the first cache memory is compared with a threshold; and Based on the utilization rate exceeding the threshold, the write miss information is provided to the L2 cache memory.

26. The apparatus of claim 25, wherein the threshold corresponds to the bandwidth of the interface of the L2 cache memory.

27. The apparatus of claim 25, wherein the threshold corresponds to the size of the second portion of the first cache memory.

28. The apparatus according to claim 21, wherein: The write miss information is the first write miss information; and The cache controller is configured to: Based on the first memory address of the first write miss information corresponding to the second memory address of the second write miss information stored in the second part of the first cache memory, the first write miss information and the second write miss information are merged.

29. The apparatus of claim 21, wherein the second portion of the first cache memory includes a byte enable register.

30. The apparatus of claim 29, wherein the byte enable register is configured to store the value of an element specifying the write miss information to be written.

31. A method comprising: The cache controller receives write operations. Determine whether the write operation is associated with a miss in a first portion of a first cache memory, wherein the first cache memory includes the first portion and a second portion; Based on the association between the write operation and a miss in the first part of the first cache memory, write miss information is stored in the second part of the first cache memory; Receive the read operation associated with the write operation; as well as The write miss information stored in the second part of the first cache memory is used to service the read operation.

32. The method according to claim 31, wherein: The write miss information includes data associated with the write operation; and Using the write miss information to service the read operation includes providing the data from the second portion of the first cache memory.

33. The method of claim 31, further comprising: The data evicted from the second cache memory is stored in the first cache memory.

34. The method according to claim 33, wherein: The second cache memory is a Level 1 (L1) main cache; and The first cache memory is an L1 victim cache.

35. The method of claim 34, further comprising: The utilization rate of the second portion of the first cache memory is compared with a threshold. as well as Based on the utilization rate exceeding the threshold, the write miss information is provided to the L2 cache memory.

36. The method of claim 35, wherein the threshold corresponds to the bandwidth of the interface of the L2 cache memory.

37. The method of claim 35, wherein the threshold corresponds to the size of the second portion of the first cache memory.

38. The method according to claim 31, wherein: The write miss information is the first write miss information; and The method further includes: Based on the first memory address of the first write miss information corresponding to the second memory address of the second write miss information stored in the second part of the first cache memory, the first write miss information and the second write miss information are merged.

39. The method of claim 31, wherein the second portion of the first cache memory includes a byte enable register.

40. The method of claim 39, further comprising: The value of the element that specifies the write miss information to be written is stored in the byte enable register.

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