A method for data transmission based on a multi-core coprocessor system

Abstract

This invention relates to a method for data transmission based on a multi-core collaborative processing system. The method includes: a multi-core collaborative processing system comprising an application processor, a control processor, a DMA controller, and DDR memory; wherein the application processor, control processor, and DMA controller are each connected to the DDR memory; the control processor is connected to an external non-volatile storage medium and to the internal application processor and DMA controller; the DMA controller is connected to an external data acquisition unit; and the data acquisition unit interfaces with N types of single-modal data sources. The DMA controller supports direct register mode and SG mode. Based on this invention, real-time data transmission efficiency can be improved, application processor resources can be freed up, and priority transmission of critical data can be guaranteed through channel priority.

Description

Technical Field

[0001] This invention relates to the field of rail transit technology, and in particular to a method for data transmission based on a multi-core collaborative processing system. Background Technology

[0002] In the field of prognostics and health management (PHM) technology for rail transit, the accurate and efficient transmission and reception of PHM data is crucial to the system's performance and reliability. Traditional implementations typically use an application processor and a direct memory access (DMA) controller for data transmission. However, with the increase in the number of sensors and the improvement in sampling rate, existing solutions have gradually revealed a series of problems, such as high application-layer resource overhead and poor real-time data transmission. The main reasons for this are as follows: 1) In traditional solutions, the application processor needs to simultaneously respond to upper-layer application requests, DMA interrupts, data transfer operations, memory management, and other operations. When multiple channels of data are processed concurrently, frequent interrupts and memory operations can easily overload the processor, causing real-time problems such as data processing delays and data loss. 2) For DMA controllers that support scatter / gather (SG) modes, the application processor usually needs to handle a large number of buffer descriptor (BD) chain management tasks, increasing software overhead and error risk.

[0003] To address the aforementioned shortcomings, we propose an improvement: introducing a control processor (such as a Cortex-R5 series IP core) to exclusively manage the DMA controller, freeing up application processor resources so that it only needs to focus on the file storage portion of the data. This solution not only improves the real-time efficiency of data transmission but also frees up application processor resources and ensures priority transmission of critical data through channel prioritization. How to implement this improvement is the technical problem that this invention aims to solve. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by providing a method for data transmission based on a multi-core collaborative processing system. This invention comprises an application processor, a control processor, a DMA controller, and double data rate (DDR) memory, forming a multi-core collaborative processing system. The application processor, control processor, and DMA controller share the DDR memory. The control processor is also connected to an external non-volatile storage medium, and the DMA controller is connected to an external data acquisition unit implemented using a field-programmable gate array (FPGA). Upon system startup, the application processor is responsible for memory management and initializes the corresponding data file F for each channel on the non-volatile storage medium. i The DMA controller establishes a multi-channel connection with the data acquisition unit. The control processor sets the DMA operating mode of the DMA controller according to a two-choice operating mode (direct register mode or SG mode) and sets the priority registers of each channel on the DMA controller. When the system startup is complete, the control processor performs initial settings on the target address register + data length register (direct register mode) or CURDESC register (SG mode) on the DMA controller based on the channel linked list. After system startup, the data acquisition unit pushes the acquired data to the DMA controller. The DMA controller receives the corresponding channel data based on its local channel buffer and, in a predetermined operating mode, updates the data blocks in the corresponding queue buffers according to each channel buffer. During the update process, it sorts the transmission processes of multiple channels that simultaneously meet the update conditions based on channel priority, and sends a corresponding channel update interrupt to the control processor after each data block update is completed. The control processor updates the channel write pointer corresponding to the current interrupt upon receiving each channel update interrupt, and resets the target address register and data length register on the DMA controller based on the channel linked list corresponding to the current interrupt when the predetermined operating mode is direct register mode. The application processor confirms the queue update status based on the channel read and write pointers, and when any queue update status is updated, it reads the updated data from the queue buffer corresponding to the current channel, stores it in the corresponding data file, and refreshes the channel read pointer of the current channel. Based on this invention, not only can the real-time efficiency of data transmission be improved, but application processor resources can also be freed up, and priority transmission of critical data can be guaranteed through channel priority.

[0005] In view of this, embodiments of the present invention provide a method for data transmission based on a multi-core collaborative processing system, the method comprising: A multi-core collaborative processing system is composed of an application processor, a control processor, a DMA controller, and DDR memory. The application processor, control processor, and DMA controller are each connected to the DDR memory. The control processor is connected to an external non-volatile storage medium and to the application processor and DMA controller within the system. The DMA controller is connected to an external data acquisition unit. The data acquisition unit interfaces with N types of single-modal data sources, where the total number of modalities N is a preset positive integer. When the system starts up, the application processor performs N-channel logical storage planning on the DDR memory to obtain N-channel storage areas C. i And initialize a corresponding data file F for each channel on the non-volatile storage medium. i The DMA controller establishes N data connection channels with the data acquisition unit; the control processor sets the DMA working mode of the DMA controller according to a preset working mode, and stores the data in each channel's storage area C. i Channel priority y i The priority registers of each channel on the DMA controller are set; wherein, 1 ≤ channel index i ≤ N; the channel storage area C i The logical storage area includes the channel linked list B. i Queue buffer D i Channel write pointer w i Channel read pointer r i The channel priority y i The preset operating modes include direct register mode and SG mode. When the system startup is complete, the control processor is based on all the channel linked lists B. i The channel registers on the DMA controller corresponding to the preset working mode are initially configured; wherein, when the preset working mode is direct register mode, the channel registers are the target address register and data length register corresponding to each channel, and when the preset working mode is SG mode, the channel registers are the CURDESC register corresponding to each channel. After the system starts up, the data acquisition unit continuously samples each type of single-modal data source according to the sampling frequency corresponding to each type of single-modal data source and pushes the collected data to the DMA controller through each channel. The DMA controller sets up a corresponding channel buffer for each channel locally; receives the acquired data of the corresponding channel based on each channel buffer; and, based on the DMA operating mode and its corresponding channel register type, adjusts the queue buffer D corresponding to the current channel according to each channel buffer. iPerform data block update operations; and send a corresponding channel update interrupt to the control processor after each data block update is completed; wherein the buffer size of each channel buffer is greater than the preset buffer block size n. i Furthermore, all the aforementioned channel buffers are managed based on the first-in, first-out (FIFO) principle, and the buffer block size n i The value is the number of bytes; Each time the control processor receives a channel update interrupt, it writes the pointer w to the channel corresponding to the current interrupt. i Increment by 1; and confirm whether the preset working mode is direct register mode; if confirmed, then based on the channel linked list B corresponding to the current interrupt. i The target address register and the data length register on the DMA controller are reset; The application processor confirms the queue update status based on the read / write pointers of each channel; and when any of the queue update statuses are updated, it retrieves data from the queue buffer D corresponding to the current channel. i Read the updated data and store it into the corresponding data file F. i And refresh the channel read pointer corresponding to the current channel; the queue update status includes updated and not updated.

[0006] Preferably, the application processor includes a Cortex-A series processor; the control processor includes a Cortex-R5 series IP core; the DMA controller is an AXI DMA controller; and the data acquisition device is a multimodal data acquisition device implemented based on FPGA.

[0007] Preferably, the channel linked list B i Given a BD linked list, consisting of M linked list blocks b i,j 1 ≤ block index j ≤ M, and the total number of blocks M is a preset positive integer; The queue buffer area D i Includes M cache blocks d i,j Each of the aforementioned queue buffers D i All cache blocks are of equal size and are the corresponding cache block size n. i ; The channel linked list B i With the queue buffer D i One-to-one correspondence; The linked list block b i,j With the cache block d i,j One-to-one correspondence; The linked list block b i,j Including the following block address nxb i,j Cache block address da i,j ; When j < M, the address of the lower table block is nxb i,j For the (j+1)th linked list block b i,j+1 The starting address of the memory; When j=M, the address of the lower table block is nxb i,j For the first linked list block b i,1 The starting address of the memory; The cache block address da i,j For the corresponding cache block d i,j The starting address of the memory; The channel write pointer w i and the channel read pointer r i Each is an integer greater than or equal to 0, and is initially set to 0.

[0008] Preferably, the step is based on all the channel linked lists B i The initial settings for each channel register on the DMA controller corresponding to the preset operating mode are specifically included as follows: The control processor identifies the preset operating mode; If the preset operating mode is direct register mode, then the target address register and the data length register corresponding to each channel on the DMA controller are used as the current target address register and the current data length register; and the current target address register is set as the corresponding channel linked list B. i The first linked list block b i,j The cache block address da i,j And set the current data length register to the corresponding cache block size n. i ; If the preset operating mode is SG mode, then the CURDESC register corresponding to each channel on the DMA controller is used as the current CURDESC register; and the current CURDESC register is set to the corresponding channel linked list B. i The first linked list block b i,j The starting address of memory.

[0009] Preferably, based on the DMA operating mode and its corresponding channel register type, the queue buffer D corresponding to the current channel is configured according to each channel buffer. i Performing data block update operations specifically includes: The DMA controller identifies the DMA operating mode; If the DMA operating mode is direct register mode, then check whether the real-time cached data size of all the channel buffers has exceeded the corresponding cache block size n. iPerform identification; if the real-time cached data size of one or more of the channel buffers exceeds the corresponding cache block size n i If the size of all current real-time cached data exceeds the corresponding cache block size n, then according to the priority register of each channel,... i The channels are sorted, with higher priority channels appearing earlier in the list; and all sorted channels are traversed in order from front to back; during this traversal, the currently traversed channel is designated as the current channel; and the first n channels in the channel buffer of the current channel are selected. i The byte data forms the corresponding current data block, and the current data block is written to the target address pointed to by the target address register corresponding to the current channel. When the current data write operation is completed, the current data block is removed from the current channel buffer and the completion of a data block update is confirmed. If the DMA operating mode is SG mode, then check whether the real-time cached data size of all the channel buffers has exceeded the corresponding cache block size n. i Perform identification; if the real-time cached data size of one or more of the channel buffers exceeds the corresponding cache block size n i If the size of all current real-time cached data exceeds the corresponding cache block size n, then according to the priority register of each channel,... i The channels are sorted, with higher priority channels appearing earlier in the list; and all sorted channels are traversed in order from front to back; during this traversal, the currently traversed channel is designated as the current channel; and the first n channels in the channel buffer of the current channel are selected. i The byte data forms the corresponding current data block, and the CURDESC register corresponding to the current channel is used as the current register, and the linked list block b pointed to by the current register is... i,j As the current linked list block, the current data block is written to the cache block address da of the current linked list block. i,j The corresponding memory address, and based on the address nxb of the next list block of the current linked list block. i,j The current register is reset, and at the end of this register reset, the current data block is removed from the current channel buffer, and a data block update is confirmed to be completed.

[0010] Preferably, the channel linked list B corresponding to the current interruption... i Resetting the target address register and the data length register on the DMA controller specifically includes: The control processor uses the target address register and the data length register corresponding to the current interrupt on the DMA controller as the current target address register and the current data length register, respectively; and uses the corresponding address of the current target address register as the current target address; and uses the channel linked list B corresponding to the current interrupt as the current target address. i In the context, the cache block address da i,j The linked list block b that matches the current target address i,j As the current linked list block; and the next linked list block b of the current linked list block. i,j As the next linked list block; and set the current target address register to the cache block address da of the next linked list block. i,j Set the current data length register to the corresponding cache block size n. i .

[0011] Preferably, the step of confirming the queue update status based on the read / write pointers of each channel specifically includes: The application processor periodically checks all the channel storage areas C at a preset time frequency. i Perform one round of traversal; and during this round of traversal, store the channel C currently being traversed. i As the current storage area; and write pointer w to the channel of the current storage area. i and the channel read pointer r i The system identifies whether the queues are equal; if not, the corresponding queue update status is set to updated; if yes, the corresponding queue update status is set to not updated.

[0012] Preferably, when any of the queue update states is updated, the queue buffer D corresponding to the current channel is used. i Read the updated data and store it into the corresponding data file F. i And refresh the channel read pointer corresponding to the current channel, specifically including: When the application processor records any queue update state as "updated", it records the corresponding channel of the queue update state as the current channel; and stores the channel storage area C corresponding to the current channel. i As the current storage area; and set the queue cache area D of the current storage area as the current storage area. i As the current cache area; And write pointer w to the channel in the current storage area. i and the channel read pointer r i The difference is calculated as △wr=w i -r i ; and write pointer w to the channel in the current storage area. i and the channel read pointer ri Perform block index mapping to obtain the corresponding block index j w j r ; , ; 1≤j w j r ≤M, where mod is the modulo operator; And for block index j w j r Perform a comparison; If j w <j r If <M, then the j-th node of the current cache area will be... r +1 to the Mth cache block d i,j Extract the data, sort them sequentially to form the corresponding first data block, and then combine the first to jth data blocks from the current cache. w The cache block d i,j Extract the data, sort them sequentially to form the corresponding second data block, and then sort the first and second data blocks sequentially to form the corresponding current data block; If j w <j r =M, then the first to jth elements of the current cache area will be... w The cache block d i,j The extracted data are sorted sequentially to form the corresponding current data block; If j r <j w Then the j-th node of the current cache area will be... r +1 to the jth w The cache block d i,j The extracted data are sorted sequentially to form the corresponding current data block; If j r =j w If M < Δwr ≠ 0, then the j-th node of the current buffer will be... r +1 to the Mth cache block d i,j Extract the data, sort it sequentially to form the corresponding third data block, and then combine the first to jth data blocks from the current cache. r The cache block d i,j The extracted data are sorted sequentially to form the corresponding fourth data block, and the third and fourth data blocks are sorted sequentially to form the corresponding current data block; If j r =j w =M and △wr≠0, then the first to jth elements of the current cache area are... r The cache block d i,jThe extracted data are sorted sequentially to form the corresponding current data block; And the current data block is sent to the corresponding data file F i Add to; and at the end of this addition, reset the channel read pointer r of the current storage area. i Reset to the corresponding channel write pointer w i .

[0013] This invention provides a method for data transmission based on a multi-core collaborative processing system. As described above, this invention comprises an application processor, a control processor, a DMA controller, and DDR memory, forming a multi-core collaborative processing system. The application processor, control processor, and DMA controller share the DDR memory. The control processor is also connected to an external non-volatile storage medium, and the DMA controller is connected to an external data acquisition unit (implemented based on an FPGA). When the multi-core collaborative processing system starts, the application processor is responsible for memory management and initializes the corresponding data file F for each channel on the non-volatile storage medium. i The DMA controller establishes a multi-channel connection with the data acquisition unit. The control processor sets the DMA operating mode of the DMA controller according to a two-choice operating mode (direct register mode or SG mode) and sets the priority registers of each channel on the DMA controller. When the multi-core collaborative processing system completes startup, the control processor performs initial settings on the target address register + data length register (direct register mode) or CURDESC register (SG mode) on the DMA controller based on the channel linked list. After the multi-core collaborative processing system starts up, the data acquisition unit pushes the acquired data to the DMA controller. The DMA controller receives the corresponding channel data based on its local channel buffer and, in a predetermined operating mode, updates the data blocks in the corresponding queue buffers according to each channel buffer. During the update process, it sorts the transmission processes of multiple channels that simultaneously meet the update conditions based on channel priority, and sends a corresponding channel update interrupt to the control processor after each data block update is completed. The control processor updates the channel write pointer corresponding to the current interrupt upon receiving a channel update interrupt, and resets the target address register and data length register on the DMA controller based on the channel linked list corresponding to the current interrupt when the predetermined operating mode is direct register mode. The application processor confirms the queue update status according to the read and write pointers of each channel, and when any queue update status is updated, it reads the updated data from the queue buffer corresponding to the current channel, stores it in the corresponding data file, and refreshes the channel read pointer of the current channel. Based on the embodiments of the present invention, not only is the real-time efficiency of data transmission improved, but application processor resources are also freed up, and priority transmission of critical data is guaranteed through channel priority. Attached Figure Description

[0014] Figure 1 This is a schematic diagram illustrating a method for data transmission based on a multi-core collaborative processing system, as provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a multi-core collaborative processing system provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the channel linked list and queue buffer provided in an embodiment of the present invention. Detailed Implementation

[0015] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0016] Figure 1 This is a schematic diagram illustrating a method for data transmission based on a multi-core collaborative processing system, as provided in an embodiment of the present invention. Figure 1 As shown, this method includes the following steps: Step 1 consists of a multi-core collaborative processing system composed of an application processor, a control processor, a DMA controller, and DDR memory.

[0017] Here, as Figure 2 As shown in the schematic diagram of the multi-core collaborative processing system provided in this embodiment of the invention, the application processor, control processor, and DMA controller of this embodiment are respectively connected to DDR memory; the control processor is respectively connected to the non-volatile storage medium outside the system and the application processor and DMA controller inside the system; the DMA controller is connected to the data acquisition unit outside the system; the data acquisition unit is connected to N types of single-modal data sources, and the total number of modalities N is a preset positive integer.

[0018] The multi-core collaborative processing system of this invention is essentially a multi-processor system-on-a-chip (MPSoC). The method of this invention is essentially a data transmission scheme based on MPSoC, used to solve the problems of high application-layer resource overhead and poor real-time performance in data transmission inherent in the traditional application processor + DMA controller architecture.

[0019] The application processor in this embodiment of the invention includes a Cortex-A series processor, and the system running on the application processor is such as Linux or Windows. It is mainly responsible for the upper-level processing of PHM data, such as data file storage, compression, and analysis.

[0020] The control processor in this embodiment of the invention includes a Cortex-R5 series IP core. An embedded operating system (such as FreeRTOS, VxWorks, Zephyr, etc.) or a custom processing program runs on the control processor to perform exclusive control of the DMA controller, respond to DMA interrupts in real time, and communicate with the application processor via inter-core communication.

[0021] The DMA controller in this embodiment of the invention is an Advanced Dextensible Interface Direct Memory Access (AXI DMA) controller, which implements different processing flows through fixed hardware logic. This type of DMA controller supports two working modes: Direct Register mode and SG mode, provides multi-channel data transmission management, and provides a channel buffer for each channel to buffer data transmission and reception and manage it based on the First In First Out (FIFO) principle.

[0022] The data acquisition device in this embodiment of the invention is a multimodal data acquisition device implemented based on FPGA, used for continuous data acquisition operations from multiple types of single-modal data sources. The single-modal data sources in this embodiment of the invention can be any type of PHM data source in the field of rail transit fault prediction and health management technology, or any data source from other technical fields.

[0023] The non-volatile storage media in this invention include EPROM memory, EEPROM memory, Flash memory, hard disk, CD, etc.; the non-volatile storage media is used to store the data files collected by the data acquisition device.

[0024] Step 2: During system startup, the application processor performs N-channel logical storage planning on the DDR memory to obtain N-channel storage areas C. i And initialize a corresponding data file F for each channel on a non-volatile storage medium. i The DMA controller establishes N data connection channels with the data acquisition unit; the control processor sets the DMA operating mode of the DMA controller according to the preset operating mode, and sets the storage area C of each channel accordingly. i Channel priority y i Configure the priority registers for each channel on the DMA controller.

[0025] Here, the system mentioned in the method steps of this embodiment of the invention is a multi-core collaborative processing system. 1 ≤ channel index i ≤ N.

[0026] Channel storage area C in this embodiment of the invention i The logical storage area includes the channel linked list B.i Queue buffer D i Channel write pointer w i Channel read pointer r i Channel priority y i .in: Channel List B i Given a BD linked list, consisting of M linked list blocks b i,j 1 ≤ block index j ≤ M, and the total number of blocks M is a preset positive integer. Queue buffer D i Includes M cache blocks d i,j Each queue buffer D i All cache blocks are of equal size, and each is the corresponding cache block size n. i Channel linked list B i With queue buffer D i One-to-one correspondence. Linked list block b i,j With cache block d i,j One-to-one correspondence. Linked list block b i,j Including the following block address nxb i,j Cache block address da i,j .

[0027] The following table contains the block address nxb i,j The setting rule is: when j < M, the address of the lower table block is nxb. i,j For the (j+1)th linked list block b i,j+1 The starting address of memory; when j=M, the address of the next table block is nxb. i,j For the first linked list block b i,1 The starting address of memory.

[0028] Cache block address da i,j For the corresponding cache block d i,j The starting address of memory.

[0029] Channel write pointer w i and channel read pointer r i Each is an integer greater than or equal to 0, and is initially set to 0.

[0030] It should be noted that channel linked list B i With queue buffer D i The data structure can be referenced. Figure 3 The following is a schematic diagram of the channel linked list and queue buffer provided in the embodiments of the present invention for understanding.

[0031] The preset operating modes of this invention include direct register mode and SG mode.

[0032] Step 3: When the system startup is complete, the control processor, based on the linked list B of all channels... iPerform initial settings on the channel registers of the DMA controller corresponding to the preset operating mode.

[0033] Here, when the default operating mode is direct register mode, each channel register is the target address register and data length register corresponding to each channel; when the default operating mode is SG mode, each channel register is the corresponding CURDESC register for each channel.

[0034] The current step 3 specifically includes: Step 31: Control the processor to identify the preset working mode.

[0035] Step 32: If the preset operating mode is direct register mode, then the target address register and data length register corresponding to each channel on the DMA controller are used as the current target address register and current data length register; and the current target address register is set as the corresponding channel linked list B. i The first linked list block b i,j cache block address da i,j And set the current data length register to the corresponding cache block size n. i .

[0036] Step 33: If the preset operating mode is SG mode, then the CURDESC registers corresponding to each channel on the DMA controller are used as the current CURDESC registers; and the current CURDESC registers are set to the corresponding channel linked list B. i The first linked list block b i,j The starting address of memory.

[0037] Step 4: After the system starts up, the data acquisition unit continuously samples each type of data source according to the sampling frequency corresponding to each type of single-modal data source and pushes the collected data to the DMA controller through each channel.

[0038] Step 5: The DMA controller sets up corresponding channel buffers for each channel locally; receives the acquired data for the corresponding channel based on each channel buffer; and, based on the DMA operating mode and its corresponding channel register type, adjusts the queue buffer D corresponding to the current channel according to each channel buffer. i Perform data block update operations; and send a corresponding channel update interrupt to the control processor each time a data block update is completed.

[0039] Here, in this embodiment of the invention, the buffer size of each channel buffer is greater than the preset buffer block size n. i Furthermore, all channel buffers are managed based on the first-in, first-out (FIFO) principle, with a buffer block size of n. i The value n is used to identify the number of bytes, the cache block size. iThe specific value is a pre-set positive integer.

[0040] The current step 5 specifically includes: Step 51: The DMA controller sets up the corresponding channel buffer for each channel locally on the controller.

[0041] Step 52, and receive the acquisition data of the corresponding channel based on the buffer of each channel.

[0042] Step 53, and based on the DMA operating mode and its corresponding channel register type, according to the channel buffer, the queue buffer D corresponding to the current channel is configured. i Perform a data block update operation.

[0043] Specifically, it includes: Step 531: Identify the DMA working mode.

[0044] Step 532: If the DMA operating mode is direct register mode, check whether the real-time cached data size of all channel buffers has exceeded the corresponding cache block size n. i Perform identification; if the real-time cached data size of one or more channel buffers exceeds the corresponding cache block size n i If the size of all current real-time cached data exceeds the corresponding cache block size n, then the priority register of each channel will be used to prioritize the data. i The channels are sorted, with higher priority channels appearing earlier in the list. All sorted channels are then traversed in reverse order. During this traversal, the currently traversed channel is designated as the current channel, and the first n channels in the current channel's buffer are used to determine the order. i The byte data forms the corresponding current data block, and the current data block is written to the target address pointed to by the target address register corresponding to the current channel. When the data write operation is completed, the current data block is removed from the current channel buffer and the completion of a data block update is confirmed.

[0045] Step 533: If the DMA operating mode is SG mode, check whether the real-time cached data size of all channel buffers has exceeded the corresponding cache block size n. i Perform identification; if the real-time cached data size of one or more channel buffers exceeds the corresponding cache block size n i If the size of all current real-time cached data exceeds the corresponding cache block size n, then the priority register of each channel will be used to prioritize the data. i The channels are sorted, with higher priority channels appearing earlier in the list. All sorted channels are then traversed in reverse order. During this traversal, the currently traversed channel is designated as the current channel, and the first n channels in the current channel's buffer are used to determine the order. iThe bytes of data form the corresponding current data block, and the CURDESC register corresponding to the current channel is used as the current register, and the linked list block b pointed to by the current register is set. i,j As the current linked list block, write the current data block to the cache block address da of the current linked list block. i,j The corresponding memory address, and based on the address of the next block in the current linked list (nxb). i,j The current register is reset, and at the end of this register reset, the current data block is removed from the current channel buffer and the data block update is confirmed to be complete.

[0046] Step 54, and send a corresponding channel update interrupt to the control processor each time a data block update is completed.

[0047] Step 6: Whenever the processor receives a channel update interrupt, it writes pointer w to the channel corresponding to the current interrupt. i Increment by 1; and confirm whether the preset operating mode is direct register mode; if confirmed, then based on the channel linked list B corresponding to the current interrupt. i Reset the target address register and data length register on the DMA controller.

[0048] Specifically, it includes: Step 61: Whenever the processor receives a channel update interrupt, it writes pointer w to the channel corresponding to the current interrupt. i Add 1.

[0049] Step 62, and confirm whether the preset working mode is direct register mode.

[0050] Step 63: If confirmed, then based on the channel linked list B corresponding to the current interruption. i Reset the target address register and data length register on the DMA controller.

[0051] Specifically, this includes: using the target address register and data length register corresponding to the current interrupt on the DMA controller as the current target address register and the current data length register; using the address corresponding to the current target address register as the current target address; and setting the channel linked list B corresponding to the current interrupt as... i In the cache block address da i,j Linked list block b that matches the current target address i,j As the current linked list block; and set the next linked list block b of the current linked list block as the next linked list block of the current linked list block. i,j As the next linked list block; and set the current target address register to the cache block address da of the next linked list block. i,j Set the current data length register to the corresponding buffer block size n. i .

[0052] Step 7: The application processor confirms the queue update status based on the read / write pointers of each channel; and when any queue update status is updated, it retrieves data from the queue buffer D corresponding to the current channel. i Read updated data from the middle and store it into the corresponding data file F. i And refresh the channel read pointer corresponding to the current channel.

[0053] Here, the queue update status in this embodiment of the invention includes updated and not updated.

[0054] The current step 7 specifically includes: Step 71: Confirm the queue update status based on the read / write pointers of each channel.

[0055] Specifically, this includes: periodically updating all channel storage areas C according to a preset time frequency. i Perform one round of traversal; and during this round of traversal, store the channel C that is currently being traversed. i As the current storage area; and write pointer w to the channel of the current storage area. i and channel read pointer r i The system identifies whether the queues are equal; if not, the corresponding queue update status is set to updated; if yes, the corresponding queue update status is set to not updated.

[0056] Here, the preset time frequency in this embodiment of the invention is a pre-set time frequency parameter.

[0057] Step 72, and when any queue update status is updated, retrieve from the queue buffer D corresponding to the current channel. i Read updated data from the middle and store it into the corresponding data file F. i And refresh the channel read pointer corresponding to the current channel.

[0058] Specifically, it includes: Step 721: When any queue update state is "updated", the application processor records the corresponding channel of the queue update state as the current channel; and stores the channel storage area C corresponding to the current channel. i As the current storage area; and set the queue cache area D of the current storage area as the current storage area. i Used as the current cache area.

[0059] Step 722, and write pointer w to the channel in the current storage area. i and channel read pointer r i The difference is calculated as △wr=w i -r i And write pointer w to the channel in the current storage area. i and channel read pointer r i Perform block index mapping to obtain the corresponding block index j w jr .

[0060] Here, in this embodiment of the invention, block index j w j r The mapping method is as follows: , ; Where, 1≤j w j r ≤M, mod is the modulo operator.

[0061] Step 723, and for block index j w j r Compare them.

[0062] Step 724, if j w <j r If <M, then the j-th element in the current cache will be... r +1 to the Mth cache block d i,j Extract the data, sort them sequentially to form the corresponding first data block, and then use the first to jth data blocks from the current cache. w 1 cache block d i,j The extracted data are sorted sequentially to form the corresponding second data block, and the first and second data blocks are then sorted sequentially to form the corresponding current data block.

[0063] Step 725, if j w <j r =M, then the first to jth elements of the current cache will be... w 1 cache block d i,j The extracted data are sorted in order to form the corresponding current data block.

[0064] Step 726, if j r <j w Then the j-th node of the current cache will be... r +1 to the jth w 1 cache block d i,j The extracted data are sorted in order to form the corresponding current data block.

[0065] Step 727, if j r =j w If M < Δwr ≠ 0, then the j-th element in the current buffer will be... r +1 to the Mth cache block d i,j Extract the data, sort it sequentially to form the corresponding third data block, and then combine the first to jth data blocks from the current cache. r 1 cache block d i,j The extracted data are sorted sequentially to form the corresponding fourth data block, and the third and fourth data blocks are sorted sequentially to form the corresponding current data block.

[0066] Step 728, if j r =j w =M and △wr≠0, then the first to jth elements of the current buffer will be... r 1 cache block d i,j The extracted data are sorted in order to form the corresponding current data block.

[0067] Step 729, and then transfer the current data block to the corresponding data file F. i Add to; and at the end of this addition, reset the channel read pointer r of the current storage area. i Reset to the corresponding channel write pointer w i .

[0068] In summary, this invention provides a technical solution for data transmission based on a multi-core collaborative processing system. As described above, this invention comprises an application processor, a control processor, a DMA controller, and DDR memory, forming a multi-core collaborative processing system. The application processor, control processor, and DMA controller share the DDR memory. The control processor is also connected to an external non-volatile storage medium, and the DMA controller is connected to an external data acquisition unit (implemented based on an FPGA). When the multi-core collaborative processing system starts, the application processor is responsible for memory management and initializes the corresponding data file F for each channel on the non-volatile storage medium. iThe DMA controller establishes a multi-channel connection with the data acquisition unit. The control processor sets the DMA operating mode of the DMA controller according to a two-choice operating mode (direct register mode or SG mode) and sets the priority registers of each channel on the DMA controller. When the multi-core collaborative processing system completes startup, the control processor performs initial settings on the target address register + data length register (direct register mode) or CURDESC register (SG mode) on the DMA controller based on the channel linked list. After the multi-core collaborative processing system starts up, the data acquisition unit pushes the acquired data to the DMA controller. The DMA controller receives the corresponding channel data based on its local channel buffer and, in a predetermined operating mode, updates the data blocks in the corresponding queue buffers according to each channel buffer. During the update process, it sorts the transmission processes of multiple channels that simultaneously meet the update conditions based on channel priority, and sends a corresponding channel update interrupt to the control processor after each data block update is completed. The control processor updates the channel write pointer corresponding to the current interrupt upon receiving a channel update interrupt, and resets the target address register and data length register on the DMA controller based on the channel linked list corresponding to the current interrupt when the predetermined operating mode is direct register mode. The application processor confirms the queue update status according to the read and write pointers of each channel, and when any queue update status is updated, it reads the updated data from the queue buffer corresponding to the current channel, stores it in the corresponding data file, and refreshes the channel read pointer of the current channel. Based on the embodiments of the present invention, not only is the real-time efficiency of data transmission improved, but application processor resources are also freed up, and priority transmission of critical data is guaranteed through channel priority.

[0069] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0070] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for data transmission based on a multi-core collaborative processing system, characterized in that, The method includes: A multi-core collaborative processing system is composed of an application processor, a control processor, a DMA controller, and DDR memory. The application processor, control processor, and DMA controller are each connected to the DDR memory. The control processor is connected to both an external non-volatile storage medium and the internal application processor and DMA controller. The DMA controller is connected to an external data acquisition unit. The data acquisition unit interfaces with N types of single-modal data sources, where the total number of modalities N is a preset positive integer. When the system starts up, the application processor performs N-channel logical storage planning on the DDR memory to obtain N-channel storage areas C. i And initialize a corresponding data file F for each channel on the non-volatile storage medium. i The DMA controller establishes N data connection channels with the data acquisition unit; the control processor sets the DMA operating mode of the DMA controller according to a preset operating mode, and stores the data in each channel's storage area C. i Channel priority y i The priority registers of each channel on the DMA controller are set; wherein, 1 ≤ channel index i ≤ N; the channel storage area C i The logical storage area includes the channel linked list B. i Queue buffer D i Channel write pointer w i Channel read pointer r i The channel priority y i The preset operating modes include direct register mode and SG mode. When the system startup is complete, the control processor is based on all the channel linked lists B. i The channel registers on the DMA controller corresponding to the preset working mode are initially configured; wherein, when the preset working mode is direct register mode, the channel registers are the target address register and data length register corresponding to each channel, and when the preset working mode is SG mode, the channel registers are the CURDESC register corresponding to each channel. After the system starts up, the data acquisition unit continuously samples each type of single-modal data source according to the sampling frequency corresponding to each type of single-modal data source and pushes the collected data to the DMA controller through each channel. The DMA controller sets up a corresponding channel buffer for each channel locally; receives the acquired data of the corresponding channel based on each channel buffer; and, based on the DMA operating mode and its corresponding channel register type, adjusts the queue buffer D corresponding to the current channel according to each channel buffer. i Perform data block update operations; and send a corresponding channel update interrupt to the control processor after each data block update is completed; wherein the buffer size of each channel buffer is greater than the preset buffer block size n. i Furthermore, all the aforementioned channel buffers are managed based on the first-in, first-out (FIFO) principle, and the buffer block size n i The value is the number of bytes; Each time the control processor receives a channel update interrupt, it writes the pointer w to the channel corresponding to the current interrupt. i Increment by 1; and confirm whether the preset working mode is direct register mode; if confirmed, then based on the channel linked list B corresponding to the current interrupt. i The target address register and the data length register on the DMA controller are reset; The application processor confirms the queue update status based on the read / write pointers of each channel; and when any of the queue update statuses are updated, it retrieves data from the queue buffer D corresponding to the current channel. i Read the updated data and store it into the corresponding data file F. i And refresh the channel read pointer corresponding to the current channel; the queue update status includes updated and not updated.

2. The method for data transmission based on a multi-core collaborative processing system according to claim 1, characterized in that, The application processor includes a Cortex-A series processor; The control processor includes a Cortex-R5 series IP core; The DMA controller is an AXI DMA controller; The data acquisition device is a multimodal data acquisition device implemented based on FPGA.

3. The method for data transmission based on a multi-core collaborative processing system according to claim 1, characterized in that, The channel linked list B i Given a BD linked list, consisting of M linked list blocks b i,j 1 ≤ block index j ≤ M, and the total number of blocks M is a preset positive integer; The queue buffer area D i Includes M cache blocks d i,j Each of the aforementioned queue buffers D i All cache blocks are of equal size and are the corresponding cache block size n. i ; The channel linked list B i With the queue buffer D i One-to-one correspondence; The linked list block b i,j With the cache block d i,j One-to-one correspondence; The linked list block b i,j Including the following block address nxb i,j Cache block address da i,j ; When j < M, the address of the lower table block is nxb i,j For the (j+1)th linked list block b i,j+1 The starting address of the memory; When j=M, the address of the lower table block is nxb i,j For the first linked list block b i,1 The starting address of the memory; The cache block address da i,j For the corresponding cache block d i,j The starting address of the memory; The channel write pointer w i and the channel read pointer r i Each is an integer greater than or equal to 0, and is initially set to 0.

4. The method for data transmission based on a multi-core collaborative processing system according to claim 3, characterized in that, The basis is all the channel linked lists B i The initial settings for each channel register on the DMA controller corresponding to the preset operating mode are specifically included as follows: The control processor identifies the preset operating mode; If the preset operating mode is direct register mode, then the target address register and the data length register corresponding to each channel on the DMA controller are used as the current target address register and the current data length register; and the current target address register is set as the corresponding channel linked list B. i The first linked list block b i,j The cache block address da i,j And set the current data length register to the corresponding cache block size n. i ; If the preset operating mode is SG mode, then the CURDESC register corresponding to each channel on the DMA controller is used as the current CURDESC register; and the current CURDESC register is set to the corresponding channel linked list B. i The first linked list block b i,j The starting address of memory.

5. The method for data transmission based on a multi-core collaborative processing system according to claim 3, characterized in that, Based on the DMA operating mode and its corresponding channel register type, the queue buffer D corresponding to the current channel is configured according to each channel buffer. i Performing data block update operations specifically includes: The DMA controller identifies the DMA operating mode; If the DMA operating mode is direct register mode, then check whether the real-time cached data size of all the channel buffers has exceeded the corresponding cache block size n. i Perform identification; if the real-time cached data size of one or more of the channel buffers exceeds the corresponding cache block size n i If the size of all current real-time cached data exceeds the corresponding cache block size n, then according to the priority register of each channel,... i The channels are sorted, with higher priority channels appearing earlier in the list; and all sorted channels are traversed in order from front to back; during this traversal, the currently traversed channel is designated as the current channel; and the first n channels in the channel buffer of the current channel are selected. i The byte data forms the corresponding current data block, and the current data block is written to the target address pointed to by the target address register corresponding to the current channel. When the current data write operation is completed, the current data block is removed from the current channel buffer and the completion of a data block update is confirmed. If the DMA operating mode is SG mode, then check whether the real-time cached data size of all the channel buffers has exceeded the corresponding cache block size n. i Perform identification; if the real-time cached data size of one or more of the channel buffers exceeds the corresponding cache block size n i If the size of all current real-time cached data exceeds the corresponding cache block size n, then according to the priority register of each channel,... i The channels are sorted, with higher priority channels appearing earlier in the list; and all sorted channels are traversed in order from front to back; during this traversal, the currently traversed channel is designated as the current channel; and the first n channels in the channel buffer of the current channel are selected. i The byte data forms the corresponding current data block, and the CURDESC register corresponding to the current channel is used as the current register, and the linked list block b pointed to by the current register is... i,j As the current linked list block, the current data block is written to the cache block address da of the current linked list block. i,j The corresponding memory address, and based on the address nxb of the next list block of the current linked list block. i,j The current register is reset, and at the end of this register reset, the current data block is removed from the current channel buffer, and a data block update is confirmed to be completed.

6. The method for data transmission based on a multi-core collaborative processing system according to claim 3, characterized in that, The channel linked list B based on the current interruption i Resetting the target address register and the data length register on the DMA controller specifically includes: The control processor uses the target address register and the data length register corresponding to the current interrupt on the DMA controller as the current target address register and the current data length register, respectively; and uses the corresponding address of the current target address register as the current target address; and uses the channel linked list B corresponding to the current interrupt as the current target address. i In the context, the cache block address da i,j The linked list block b that matches the current target address i,j As the current linked list block; and the next linked list block b of the current linked list block. i,j As the next linked list block; and set the current target address register to the cache block address da of the next linked list block. i,j Set the current data length register to the corresponding cache block size n. i .

7. The method for data transmission based on a multi-core collaborative processing system according to claim 3, characterized in that, The process of confirming the queue update status based on the read / write pointers of each channel specifically includes: The application processor periodically checks all the channel storage areas C at a preset time frequency. i Perform one round of traversal; and during this round of traversal, store the channel C currently being traversed. i As the current storage area; and write pointer w to the channel of the current storage area. i and the channel read pointer r i The system identifies whether the queues are equal; if not, the corresponding queue update status is set to updated; if yes, the corresponding queue update status is set to not updated.

8. The method for data transmission based on a multi-core collaborative processing system according to claim 3, characterized in that, When any of the queue update states is updated, the queue buffer D corresponding to the current channel is used. i Read the updated data and store it into the corresponding data file F. i And refresh the channel read pointer corresponding to the current channel, specifically including: When the application processor records any queue update state as "updated", it records the corresponding channel of the queue update state as the current channel; and stores the channel storage area C corresponding to the current channel. i As the current storage area; and set the queue cache area D of the current storage area as the current storage area. i As the current cache area; And write pointer w to the channel in the current storage area. i and the channel read pointer r i The difference is calculated as △wr=w i -r i ; and write pointer w to the channel in the current storage area. i and the channel read pointer r i Perform block index mapping to obtain the corresponding block index j w j r ; , ； 1≤j w j r ≤M, where mod is the modulo operator; And for block index j w j r Perform a comparison; If j w <j r If <M, then the j-th node of the current cache area will be... r +1 to the Mth cache block d i,j Extract the data, sort it sequentially to form the corresponding first data block, and then combine the first to jth data blocks from the current cache. w The cache block d i,j Extract the data, sort them sequentially to form the corresponding second data block, and then sort the first and second data blocks sequentially to form the corresponding current data block; If j w <j r =M, then the first to jth elements of the current cache area will be... w The cache block d i,j The extracted data are sorted sequentially to form the corresponding current data block; If j r <j w Then the j-th node of the current cache area will be... r +1 to the jth w The cache block d i,j The extracted data are sorted sequentially to form the corresponding current data block; If j r =j w If M < Δwr ≠ 0, then the j-th node of the current cache area will be... r +1 to the Mth cache block d i,j Extract the data, sort it sequentially to form the corresponding third data block, and then combine the first to jth data blocks from the current cache. r The cache block d i,j The extracted data are sorted sequentially to form the corresponding fourth data block, and the third and fourth data blocks are sorted sequentially to form the corresponding current data block; If j r =j w =M and △wr≠0, then the first to jth elements of the current cache area are... r The cache block d i,j The extracted data are sorted sequentially to form the corresponding current data block; And the current data block is sent to the corresponding data file F i Add to; and at the end of this addition, reset the channel read pointer r of the current storage area. i Reset to the corresponding channel write pointer w i .

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