An atomic operation aggregation acceleration method and device based on a RISC-V architecture
By introducing aggregated execution mode and atomic operation aggregated coprocessors into the RISC-V architecture, the problems of cache coherency contention and memory access pressure in multi-core processors are solved, improving execution efficiency and reducing power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTHWEAT UNIV OF SCI & TECH
- Filing Date
- 2026-03-27
- Publication Date
- 2026-06-09
AI Technical Summary
In RISC-V architecture multi-core processors, when multiple processor cores execute atomic operations concurrently, there are problems such as severe cache coherency contention, high memory access pressure, and low execution efficiency.
By extending the execution semantics of RISC-V atomic operation instructions, an aggregated execution mode is introduced, and a RISC-V atomic operation aggregated coprocessor is introduced into the processor to centrally handle multiple concurrent atomic operation requests, reducing the number of atomic accesses to the target memory.
It significantly reduces cache consistency contention and memory access pressure, improves system execution efficiency, and reduces system power consumption.
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Figure CN122173293A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of computer architecture design and processor architecture, specifically to an atomic operation aggregation acceleration method and apparatus implemented on a RISC-V processor architecture, which is used to reduce memory system access pressure and improve overall execution efficiency in scenarios where multiple processor cores concurrently execute atomic operations. Background Technology
[0002] With the widespread use of multi-core processors and parallel programs, atomic operations are extensively used in scenarios such as shared counters, concurrent data structures, locking mechanisms, and memory allocation. Atomic operations typically have an indivisible "read-modify-write" execution semantic, and their purpose is to ensure the correctness of access to shared memory data in a concurrent environment.
[0003] In existing processor architectures, frequent atomic operations on the same memory address by multiple processor cores or threads can lead to severe performance bottlenecks. On the one hand, atomic operations require sequential processing through cache coherency protocols or memory arbitration mechanisms, causing the same cache line to migrate frequently between multiple processor cores, resulting in cache coherency contention. On the other hand, atomic operations typically require multiple atomic read-modify-write accesses to the target memory address, significantly increasing memory access latency and interconnect bandwidth usage, thereby limiting the overall throughput performance of the system and increasing power consumption.
[0004] In the RISC-V architecture, atomic operations are typically implemented using atomic memory operation instructions defined in the A extension, or through load-hold (LR) and conditional store (SC) instruction pairs. When multiple processor cores concurrently execute these atomic operations on the same memory address, hotspots inevitably form in the cache coherence system or memory subsystem, leading to a significant increase in the execution latency of atomic operations.
[0005] To alleviate these problems, academia and industry have proposed several software-based optimization methods, such as thread-local accumulation and software combining, which reduce contention by decreasing the number of atomic operations executed. However, these methods typically rely on software-level scheduling or dedicated threads, and suffer from implementation complexity, limited applicability, and additional software overhead.
[0006] Therefore, how to effectively optimize concurrent atomic operations at the processor architecture level, reduce the number of atomic accesses to the target memory, thereby reducing memory system pressure and improving system performance, remains a critical technical problem to be solved in RISC-V multi-core processor design. Summary of the Invention
[0007] To address the problems of severe cache coherency contention, high memory access pressure, and low execution efficiency in existing technologies when multiple processor cores concurrently execute atomic operations, this invention proposes an atomic operation aggregation acceleration method and device based on the RISC-V architecture.
[0008] This invention extends the execution semantics of RISC-V atomic operation instructions by introducing an aggregated execution mode for RISC-V atomic operations. This allows the processor, when executing RISC-V atomic operation instructions in aggregated execution mode, to no longer directly perform atomic read-modify-write operations on the target memory address. Instead, the atomic operation requests are delegated to a RISC-V atomic operation aggregation coprocessor for centralized processing. The atomic operation aggregation coprocessor receives RISC-V atomic operation requests from multiple processor cores, collects, determines the order of, and aggregates multiple RISC-V atomic operation requests targeting the same target memory address. When preset conditions are met, it submits the aggregated result to the target memory address as a single atomic operation.
[0009] By moving the linearization point of atomic operations from the memory system to the RISC-V atomic operation aggregation coprocessor, this invention can significantly reduce the number of atomic accesses to the target memory, reduce cache coherency contention and memory interconnect bandwidth usage, thereby improving the execution efficiency of multi-core processors in high-concurrency atomic operation scenarios and effectively reducing system power consumption. The specific steps are as follows: Step 1: Extend the execution semantics of RISC-V atomic operation instructions and introduce aggregate execution mode; Step 2: Introduce a RISC-V atomic operation aggregation coprocessor into the processor; Step 3: When the processor core executes RISC-V atomic operation instructions using aggregated execution mode, it sends the atomic operation request to the RISC-V atomic operation aggregated coprocessor. Step 4: The RISC-V atomic operation aggregation coprocessor receives RISC-V atomic operation requests from multiple concurrent execution contexts and associates the atomic operation requests with the corresponding aggregation processing units according to the target memory address. Step 5: The RISC-V atomic operation aggregation coprocessor internally accumulates the operands of the RISC-V atomic operation and maintains the status information of the current aggregation batch; Step 6: When the preset aggregate batch commit conditions are met, trigger an aggregate commit operation and perform a RISC-V atomic write-back operation on the target memory address. Step 7: After completing the aggregation submission, reset the current aggregation batch status and initialize the next aggregation batch; Furthermore, in step one, extending the execution semantics of RISC-V atomic operation instructions includes: introducing an aggregate execution flag for the atomic operation instructions to indicate that the corresponding atomic operation instructions adopt aggregate execution mode instead of direct memory execution mode.
[0010] Furthermore, in step two, the RISC-V atomic operation aggregation coprocessor introduced into the processor is an independent functional unit. The RISC-V atomic operation aggregation coprocessor is connected to the atomic operation execution path of the processor core and is used to centrally process RISC-V atomic operation requests in aggregation execution mode.
[0011] Furthermore, in step three, when the processor core executes a RISC-V atomic operation instruction in aggregated execution mode, it transfers the corresponding atomic operation request to the RISC-V atomic operation aggregated coprocessor through the atomic operation execution path, instead of directly accessing the cache coherence system or the target memory address.
[0012] Furthermore, in step four, the concurrent execution context includes multiple processor cores, hardware threads, or software threads. The RISC-V atomic operation aggregation coprocessor associates atomic operation requests from different concurrent execution contexts with the corresponding aggregation processing units based on the target memory address corresponding to the atomic operation request.
[0013] Furthermore, in step five, the aggregator performs cumulative aggregation on the operands of multiple RISC-V atomic operation requests and maintains status information related to the current aggregation batch. The status information includes at least the aggregation result, aggregation count information, and execution status identifier.
[0014] Furthermore, in step six, the preset batch submission conditions include at least one of the following: the number of atomic operation requests in the current batch reaches a preset threshold; the aggregation waiting time of the current batch reaches a preset time limit; or a control instruction related to memory synchronization or atomic operation semantics is received.
[0015] Furthermore, in step seven, after completing the aggregation submission operation, the RISC-V atomic operation aggregation coprocessor resets the state information of the current aggregation batch and initializes the next aggregation batch for subsequent processing; during the state reset and initialization process, newly arriving RISC-V atomic operation requests are cached or isolated and are associated with the next aggregation batch after the next aggregation batch is initialized.
[0016] The beneficial effects of this invention are as follows: (1) This invention introduces the aggregated execution mode of RISC-V atomic operations by extending the execution semantics of RISC-V atomic operation instructions, and centrally processes multiple concurrent atomic operation requests in the RISC-V aggregated coprocessor, thereby reducing frequent atomic read-modify-write access to the target memory address, significantly reducing cache consistency contention and memory access pressure, and improving the overall execution efficiency of the system.
[0017] (2) Under the premise of ensuring the semantic correctness of atomic operations, the present invention moves the linearization point of atomic operations to the inside of the RISC-V atomic operation aggregation coprocessor. By performing cumulative aggregation on multiple RISC-V atomic operation requests and submitting them to memory in a single atomic write-back manner, the equivalent execution of multiple RISC-V atomic operation requests is achieved, reducing the number of RISC-V atomic operations, reducing memory interconnect bandwidth usage and system power consumption.
[0018] (3) The present invention adopts an atomic operation aggregation mechanism compatible with the RISC-V architecture, which can be implemented on different RISC-V multi-core processor platforms. It has little dependence on specific processor core implementation and software running environment, and has good versatility and scalability. It is suitable for application scenarios such as high-concurrency parallel programs and shared data structures. Attached Figure Description
[0019] Figure 1 This is an overall flowchart of the atomic operation aggregation acceleration method based on the RISC-V architecture of this invention; Figure 2 This is a schematic diagram of the RISC-V atomic operation aggregation coprocessor structure of the present invention; Figure 3 This is a schematic diagram comparing the data flow of the present invention with that of traditional RISC-V atomic operations; Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0021] Figure 1 The figure illustrates a method for accelerating atomic operation aggregation based on a RISC-V architecture, as shown in the figure. The method includes the following steps: S101: Extends the execution semantics of RISC-V atomic operation instructions and introduces aggregate execution mode; S102: Introducing a RISC-V atomic operation aggregation coprocessor into the processor; S103: When the processor core executes RISC-V atomic operation instructions using aggregated execution mode, it sends the atomic operation request to the RISC-V atomic operation aggregated coprocessor. S104: The RISC-V atomic operation aggregation coprocessor receives RISC-V atomic operation requests from multiple concurrent execution contexts and associates the requests with the corresponding aggregators; S105: The RISC-V atomic operation aggregation coprocessor internally accumulates the operands of RISC-V atomic operations and maintains the status information of the current aggregation batch.
[0022] S106: When the preset aggregate batch commit conditions are met, trigger an aggregate commit operation and perform a RISC-V atomic write-back operation on the target memory address.
[0023] S107: After completing the aggregation commit, reset the current aggregation batch status and initialize the next aggregation batch.
[0024] Furthermore, in step S101, the execution semantics of RISC-V atomic operation instructions are extended by introducing an aggregate execution flag for the RISC-V atomic operation instructions, which is used to indicate that the corresponding atomic operation instructions adopt aggregate execution mode instead of direct memory execution mode.
[0025] Furthermore, in step S102, the RISC-V atomic operation aggregation coprocessor introduced into the processor is an independent functional unit. The RISC-V atomic operation aggregation coprocessor is connected to the RISC-V atomic operation execution path of the processor core and is used to centrally process atomic operation requests in aggregation execution mode.
[0026] Furthermore, in step S103, when the processor core executes an atomic operation instruction in aggregate execution mode, it transfers the corresponding RISC-V atomic operation request to the RISC-V atomic operation aggregate coprocessor through the atomic operation execution path, instead of directly accessing the cache coherence system or the target memory address.
[0027] Furthermore, in step S104, the RISC-V atomic operation aggregation coprocessor associates atomic operation requests from different concurrent execution contexts with the corresponding aggregation processing units based on the target memory address corresponding to the atomic operation request.
[0028] Furthermore, in step S105, the aggregator performs cumulative aggregation on the operands of multiple RISC-V atomic operation requests and maintains status information related to the current aggregation batch. The status information includes at least the aggregation result, aggregation count information, and execution status identifier.
[0029] Furthermore, in step S106, the preset batch submission conditions include at least one of the following: the number of RISC-V atomic operation requests in the current batch reaches a preset threshold; the aggregation waiting time of the current batch reaches a preset time limit; or a control instruction related to memory synchronization or atomic operation semantics is received.
[0030] Furthermore, in step S107, after completing the aggregation submission operation, the RISC-V atomic operation aggregation coprocessor resets the status information of the current aggregation batch and initializes the next aggregation batch for subsequent processing. Example
[0031] In a specific embodiment, the atomic operation aggregation acceleration method based on the RISC-V architecture described in this invention is applied to a RISC-V multi-core processor system containing four processor cores. The multiple processor cores access the same shared counter variable through shared memory to count the number of concurrent task completions. The shared counter variable is located at memory address A, and the multiple processor cores frequently perform fetch-and-add atomic operations on this shared counter variable during concurrent execution. In this embodiment, the atomic operation aggregation acceleration method based on the RISC-V architecture includes the following steps: Step 1: Extend the execution semantics of RISC-V atomic operation instructions and introduce aggregate execution mode.
[0032] In this embodiment, the RISC-V atomic addition instruction is extended by introducing an aggregate execution flag. When the atomic addition instruction carries the aggregate execution flag, it indicates that the atomic operation does not directly access the target memory address, but instead uses aggregate execution mode. For example, the processor core executes the following logical operation: performs an atomic increment operation on memory address A, and enables aggregate execution mode.
[0033] Step 2: Introduce a RISC-V atomic operation aggregation coprocessor into the processor.
[0034] An atomic operation aggregation coprocessor is set up inside the processor. The RISC-V atomic operation aggregation coprocessor is an independent functional unit connected to the RISC-V atomic operation execution path of the processor core, and is used to receive and process RISC-V atomic operation requests in aggregation execution mode.
[0035] Step 3: The processor core sends the RISC-V atomic operation request in aggregate execution mode to the RISC-V atomic operation aggregate coprocessor.
[0036] When each processor core executes the aforementioned atomic addition instruction, the processor core does not initiate an atomic read-modify-write access to memory address A. Instead, it sends a RISC-V atomic operation request to the atomic operation aggregation coprocessor. The atomic operation request includes at least: the target memory address A, the operation type (addition), and the operand (e.g., +1).
[0037] Step 4: The RISC-V atomic operation aggregation coprocessor receives and associates RISC-V atomic operation requests.
[0038] The atomic operation aggregation coprocessor receives atomic operation requests from multiple processor cores and categorizes the requests based on their corresponding target memory addresses. In this embodiment, since multiple atomic operation requests all point to memory address A, the requests are uniformly associated with the same aggregator.
[0039] Step 5: Perform cumulative aggregation of RISC-V atomic operation requests within the aggregator and maintain the aggregation batch status.
[0040] In this embodiment, it is assumed that 16 atomic operation requests arrive at the aggregator within one aggregation cycle, with each request having an operand count of +1. The aggregator internally sums the operand counts of the 16 atomic operation requests to obtain an aggregation result of +16, and records the number of requests in the current aggregation batch as 16.
[0041] Step 6: When the conditions for aggregate batch commit are met, execute the aggregate commit and perform a RISC-V atomic write-back.
[0042] When the number of RISC-V atomic operation requests in the aggregation batch reaches a preset threshold (e.g., 16), the RISC-V atomic operation aggregation coprocessor triggers an aggregation commit operation. In this embodiment, the RISC-V atomic operation aggregation coprocessor treats the aggregation result + 16 as an atomic addition operation and performs an atomic write-back on the target memory address A, thereby completing the processing that originally required 16 atomic operations in one RISC-V atomic operation on the memory side. During the execution of the above atomic write-back operation, if a new RISC-V atomic addition request arrives at the RISC-V atomic operation aggregation coprocessor, the request is not discarded, but is temporarily stored and associated with a new aggregation batch to avoid affecting the aggregation result being committed.
[0043] Step 7: After completing the aggregation commit, reset the aggregation batch status and initialize the next aggregation batch.
[0044] After completing the atomic write-back operation, the aggregator unit performs end processing on the current aggregation batch, including clearing the accumulated state and resetting the batch state information, and initializing the next aggregation batch to continue receiving new RISC-V atomic operation requests; during the state reset and initialization process, newly arrived RISC-V atomic operation requests are cached or isolated and associated with the next aggregation batch after the next aggregation batch is initialized.
[0045] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.
Claims
1. A method for accelerating atomic operation aggregation based on RISC-V architecture, comprising the following steps: Step 1: Extend the execution semantics of RISC-V atomic operation instructions and introduce aggregate execution mode. Step 2: Introduce a RISC-V atomic operation aggregation coprocessor into the processor. Step 3: When the processor core executes RISC-V atomic operation instructions using aggregated execution mode, it sends the atomic operation request to the RISC-V atomic operation aggregation coprocessor. Step 4: The RISC-V atomic operation aggregation coprocessor receives RISC-V atomic operation requests from multiple concurrent execution contexts, and associates the atomic operation requests with the corresponding aggregation processing units based on the target memory address. Step 5: The RISC-V atomic operation aggregation coprocessor internally accumulates the operands of the RISC-V atomic operations and maintains the status information of the current aggregation batch. Step Six: When the preset aggregate batch commit conditions are met, trigger an aggregate commit operation and perform a RISC-V atomic write-back operation on the target memory address. Step 7: After completing the aggregation submission, reset the current aggregation batch status and initialize the next aggregation batch.
2. The RISC-V-based atomic manipulation polymerization acceleration method as described in claim 1, characterized in that, Step one introduces an aggregate execution flag based on the original execution semantics of RISC-V atomic operation instructions. This flag indicates that the corresponding RISC-V atomic operation instructions should use aggregate execution mode instead of direct memory execution mode.
3. The RISC-V-based atomic manipulation polymerization acceleration method as described in claim 1, characterized in that, Step two introduces a RISC-V atomic operation aggregation coprocessor into the processor to receive RISC-V atomic operation requests from multiple processor cores and to collect and manage these requests to support subsequent RISC-V atomic operation aggregation processing.
4. The RISC-V-based atomic manipulation polymerization acceleration method as described in claim 1, characterized in that, In step three, when the processor core executes a RISC-V atomic operation instruction in aggregated execution mode, the corresponding atomic operation request is transferred to the RISC-V atomic operation aggregated coprocessor. The aggregated coprocessor receives and processes the atomic operation request, instead of directly performing a RISC-V atomic read-modify-write operation on the target memory address.
5. The RISC-V-based atomic manipulation polymerization acceleration method as described in claim 1, characterized in that, In step four, the RISC-V atomic operation aggregation coprocessor receives RISC-V atomic operation requests from multiple concurrent execution contexts and associates the atomic operation requests with the corresponding aggregation processing units according to the target memory address corresponding to the atomic operation requests, so as to be used for subsequent RISC-V atomic operation aggregation processing.
6. The RISC-V-based atomic manipulation polymerization acceleration method as described in claim 1, characterized in that, In step five, the RISC-V atomic operation aggregation coprocessor performs aggregation calculations on the operands of multiple associated RISC-V atomic operation requests within the corresponding aggregation processing unit, and maintains state information related to the current aggregation processing process for subsequent RISC-V atomic operation submission and management.
7. The RISC-V-based atomic manipulation polymerization acceleration method as described in claim 1, characterized in that, In step six, when the preset aggregation batch commit conditions are met, the RISC-V atomic operation aggregation coprocessor triggers an aggregation commit operation, writing the aggregation result in the current aggregation processing unit back to the corresponding target memory address in the form of a single RISC-V atomic operation. During the execution of the atomic write-back operation, newly arriving RISC-V atomic operation requests are cached or associated with a new aggregation batch to avoid affecting the ongoing aggregation commit operation.
8. The RISC-V-based atomic manipulation polymerization acceleration method as described in claim 1, characterized in that, In step seven, after completing the aggregation submission operation, the RISC-V atomic operation aggregation coprocessor resets the state information of the current aggregation processing unit and initializes the state of the next aggregation batch for subsequent RISC-V atomic operation request processing. During the state clearing and initialization process, newly arriving RISC-V atomic operation requests are cached or isolated and associated with the next aggregation batch after the initialization of the next aggregation batch is completed.