Simulation method, device, electronic device and storage medium

Abstract

The present disclosure provides a simulation method, device, electronic equipment and storage medium. The method comprises: allocating a plurality of to-be-simulated models to different simulation nodes, allocating a shared memory address for variables interacting between the to-be-simulated models in the same simulation node, allocating a reflection memory address for variables interacting between the to-be-simulated models in different simulation nodes, and generating an address allocation table; determining a model source file corresponding to the to-be-simulated model, generating variable address information in the model source file based on the address allocation table; parsing the model source file to obtain a model parsing file, the model parsing file including the variable address information; analyzing the model parsing file to establish a mapping between the variable address information and a monitoring queue; performing a simulation operation based on the model source file, and monitoring based on the mapping between the variable address information and the monitoring queue. The joint use of shared memory and reflection memory reduces the load of the reflection memory network and reduces the simulation timeout of the model.

Description

Technical Field

[0001] This disclosure relates to the field of simulation technology, and in particular to a simulation method, apparatus, electronic device and storage medium. Background Technology

[0002] This section is intended to provide background or context for the embodiments of this disclosure as set forth in the claims. The description herein is not intended to be a prior art simply because it is included in this section.

[0003] In the field of semi-physical simulation, the scenarios for full-machine-level, fully digital simulation are complex, and the amount of communication data in the network is large.

[0004] In the related technologies, the full-machine-level all-digital simulation scheme utilizes a reflective memory network to complete data communication for the entire network model.

[0005] However, as the number of nodes and the amount of data in the network increase, the read / write speed of single-node reflective memory decreases sharply, and the model on the simulator will experience a large number of serious timeouts. Summary of the Invention

[0006] In view of this, the purpose of this disclosure is to provide a simulation method, apparatus, electronic device and storage medium that at least partially solves one of the technical problems in the related art.

[0007] To achieve the above objectives, a first aspect of the exemplary embodiments of this disclosure provides a simulation method, comprising: Several simulation models are assigned to different simulation nodes, and shared memory addresses are assigned to variables that interact between the simulation models in the same simulation node. Reflection memory addresses are assigned to variables that interact between the simulation models in different simulation nodes, and an address allocation table is generated. Determine the model source file corresponding to the model to be simulated, and generate variable address information in the model source file based on the address allocation table; The model source file is analyzed to obtain a model analysis file, which includes the variable address information. The model profile file is parsed to establish a mapping between the variable address information and the monitoring queue; Simulation operations are performed based on the model source file, and monitoring is performed based on the mapping between the variable address information and the monitoring queue.

[0008] In some exemplary embodiments, the assignment of several models to be simulated to different simulation nodes includes: Determine the cross-linking relationships between the various simulation models; Based on the cross-linking relationships between the simulation models, the simulation models are grouped. The simulation models from different groups are assigned to different simulation nodes.

[0009] In some exemplary embodiments, before allocating shared memory addresses for variables interacting between the models to be simulated in the same simulation node, the method further includes: Determine the historical allocation information of the reflection memory address corresponding to the variable; Based on the historical allocation information of the reflected memory address, shared memory is configured in the simulation node, and the shared memory is used to provide the variable with the shared memory address to be allocated.

[0010] In some exemplary embodiments, determining the model source file corresponding to the model to be simulated, and generating variable address information in the model source file based on the address allocation table, includes: Based on the address allocation table, determine the variables corresponding to the model to be simulated; In response to determining that the variables corresponding to the model to be simulated are allocated the shared memory address, the variable address information corresponding to the shared memory address is generated in the model source file; And / or, In response to determining that the variable corresponding to the model to be simulated is assigned the reflection memory address, the variable address information corresponding to the reflection memory address is generated in the model source file.

[0011] In some exemplary embodiments, The step of analyzing the model source file to obtain a model analysis file includes: Analyze the function call relationships in the model source file to determine the coupling relationships between variables in the model source file; The coupling relationship is recorded in the model profile file.

[0012] In some exemplary embodiments, parsing the model profiling file and establishing the mapping between the variable address information and the monitoring queue includes: The model profile file is parsed to obtain the variable address information; Match the variable address information with the physical address; Establish a mapping between the physical address and the monitoring queue to obtain the mapping between the variable address information and the monitoring queue.

[0013] In some exemplary embodiments, the simulation operation based on the model source file and the monitoring based on the mapping between the variable address information and the monitoring queue include: The model source files are compiled to generate an executable program; The simulation operation is performed based on the executable program; During the simulation operation, data from the physical address is acquired asynchronously.

[0014] Based on the same inventive concept, a second aspect of the exemplary embodiments of this disclosure provides a simulation apparatus, including: The address allocation table determination module is configured to allocate several simulation models to different simulation nodes, allocate shared memory addresses for variables that interact between the simulation models in the same simulation node, allocate reflected memory addresses for variables that interact between the simulation models in different simulation nodes, and generate an address allocation table. The variable address information determination module is configured to determine the model source file corresponding to the model to be simulated, and generate variable address information in the model source file based on the address allocation table; The analysis module is configured to analyze the model source file to obtain a model analysis file, which includes the variable address information. The parsing module is configured to parse the model profile file and establish a mapping between the variable address information and the monitoring queue; The simulation and monitoring module is configured to perform simulation operations based on the model source file and to perform monitoring based on the mapping between the variable address information and the monitoring queue.

[0015] Based on the same inventive concept, a third aspect of the exemplary embodiments of this disclosure provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method as described in the first aspect.

[0016] Based on the same inventive concept, a fourth aspect of the exemplary embodiments of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method as described in the first aspect.

[0017] As can be seen from the above description, the simulation method, apparatus, electronic device, and storage medium provided in this disclosure include: allocating several models to be simulated to different simulation nodes, allocating shared memory addresses for variables interacting between the models to be simulated in the same simulation node, allocating reflected memory addresses for variables interacting between the models to be simulated in different simulation nodes, and generating an address allocation table; determining the model source file corresponding to the model to be simulated, and generating variable address information in the model source file based on the address allocation table; parsing the model source file to obtain a model profile file, the model profile file including the variable address information; parsing the model profile file to establish a mapping between the variable address information and a monitoring queue; performing simulation operations based on the model source file, and monitoring based on the mapping between the variable address information and the monitoring queue. This disclosure, through the combined use of shared memory and reflected memory, offloads the heavily loaded reflected memory network, reduces the load on the reflected memory network, and reduces model simulation timeouts. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a network structure for a simulation scheme based on a reflective memory network in related technologies; Figure 2 A schematic flowchart of a simulation method provided for an exemplary embodiment of this disclosure; Figure 3 A schematic diagram of a network structure for a simulation method provided as an exemplary embodiment of this disclosure; Figure 4 A schematic diagram of a simulation apparatus provided for an exemplary embodiment of this disclosure; Figure 5 A schematic diagram of the structure of an electronic device provided as an exemplary embodiment of the present disclosure. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the principles and spirit of this disclosure will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided merely to enable those skilled in the art to better understand and implement this disclosure, and are not intended to limit the scope of this disclosure in any way. Rather, these embodiments are provided to make this disclosure more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0021] It is important to understand in this article that any number of elements in the accompanying figures is for illustrative purposes and not for limitation, and that any naming is for distinction only and has no limiting meaning.

[0022] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. The article "a" or "an" preceding an element does not exclude the existence of multiple such elements.

[0023] The principles and spirit of this disclosure will be explained in detail below with reference to several representative embodiments.

[0024] As described in the background section, in the field of semi-physical simulation, the scenarios for full-machine-level all-digital simulation are complex, and the amount of communication data in the network is large.

[0025] In the related technologies, the full-machine-level all-digital simulation scheme utilizes a reflective memory network to complete data communication for the entire network model.

[0026] However, the inventors of this disclosure have discovered that as the number of nodes and the amount of data in the network increase, the read / write speed of the single-node reflective memory decreases sharply, and the model on the simulator will experience a large number of serious timeouts.

[0027] refer to Figure 1 This is a schematic diagram of a network structure for a simulation scheme based on a reflective memory network in related technologies.

[0028] This includes a host computer 101, a simulation node 102, and a switch 103.

[0029] The host computer 101 is the control center, management interface, and user interaction platform of the entire simulation system.

[0030] Simulation node 102 is the actual execution unit for simulation computation. In simulation schemes based on reflective memory networks in related technologies, one simulation node 102 is responsible for running a simulation model instance, executing the model's computational logic, and updating the model state within each simulation step.

[0031] Switch 103 is the high-speed data hub and network backbone for internal communication within the entire simulation system. It is responsible for the efficient and reliable transmission of data between the host computer 101, each simulation node 102, and between the simulation nodes 102 themselves.

[0032] The simulation nodes 102 and the host computer 101 of the entire reflective memory network are connected to form a ring network through the switch 103.

[0033] When simulation node 102 sends data, it sends an optical signal to the reflective memory network. Other simulation nodes 102 update their local register data after receiving the optical signal.

[0034] As an example, the optical signal will have a fixed delay of 750ns for each simulated node 102 it passes through. The more simulated nodes 102 there are in the network, the greater the delay will be.

[0035] When network bandwidth is low, a single simulation node 102 can guarantee good read and write performance. However, as the number of simulation nodes 102 and the amount of data in the network increase, the read and write rate of the reflected memory of a single simulation node 102 decreases sharply, and the model on the simulator will experience a large number of serious timeouts.

[0036] Specifically, the inventors of this disclosure have discovered that: In the simulation scheme based on reflective memory networks in related technologies, one simulation node 102 is responsible for running one simulation model instance. In this case, when there are many simulation models, the more simulation nodes 102 there are, the greater the latency will be.

[0037] Furthermore, the number of variables that need to be supported is quite large, and the overall expected amount of interactive data far exceeds the bandwidth that RFM network theory can support, and the ideal amount of communication data cannot be achieved in practical applications.

[0038] To address the aforementioned issues, this disclosure provides a simulation scheme, specifically comprising: assigning several models to be simulated to different simulation nodes, allocating shared memory addresses for variables interacting between the models to be simulated within the same simulation node, allocating reflected memory addresses for variables interacting between the models to be simulated in different simulation nodes, and generating an address allocation table; determining the model source file corresponding to each model to be simulated, and generating variable address information in the model source file based on the address allocation table; parsing the model source file to obtain a model profile file, the model profile file including the variable address information; parsing the model profile file to establish a mapping between the variable address information and a monitoring queue; performing simulation operations based on the model source file, and performing monitoring based on the mapping between the variable address information and the monitoring queue.

[0039] This disclosure reduces the load on the reflective memory network and decreases simulation timeouts by using shared memory and reflective memory in combination.

[0040] After introducing the basic principles of this disclosure, various non-limiting embodiments of this disclosure will be described in detail below.

[0041] refer to Figure 2 This is a flowchart illustrating a simulation method provided by an exemplary embodiment of the present disclosure.

[0042] The simulation method includes the following steps: Step S210: Assign several simulation models to different simulation nodes, allocate shared memory addresses for variables that interact between simulation models in the same simulation node, allocate reflection memory addresses for variables that interact between simulation models in different simulation nodes, and generate an address allocation table.

[0043] Below, we will first introduce the method of grouping several models to be simulated, specifically: In some exemplary embodiments, the assignment of several models to be simulated to different simulation nodes includes: Determine the cross-linking relationships between the various simulation models; Based on the cross-linking relationships between the simulation models, the simulation models are grouped. The simulation models from different groups are assigned to different simulation nodes.

[0044] In practical implementation, the cross-linking relationship between several models to be simulated refers to the interaction network formed between several models through physical connections, data flows, control logic, or functional dependencies.

[0045] Models with strong cross-linking relationships (e.g., cross-linking relationship values ​​greater than or equal to a preset cross-linking relationship threshold) are grouped together.

[0046] As an example, consider several simulation models applied to an aircraft, including flight control model, wing control model, flight dynamics model, aerodynamic model, propulsion system model, navigation system model, and environmental model.

[0047] Among them, the flight control model, wing control model, flight dynamics model, aerodynamic model and propulsion system model have strong interconnections and are classified into the same group.

[0048] The navigation system model and the environment model have a strong interconnected relationship and are grouped into the same group.

[0049] In comparison, for reference Figure 1 In related technologies, a simulation node is typically assigned to each model to be simulated; however, in this disclosure, reference is made to... Figure 3 Several simulation models 104 are grouped, and different groups of simulation models 104 are assigned to different simulation nodes 102. Compared with related technologies, this disclosure reduces the number of simulation nodes 102. By using shared memory and reflected memory in combination, the load on the heavily loaded reflected memory network is distributed, reducing the load on the reflected memory network and reducing model simulation timeouts.

[0050] In the above exemplary embodiment, a method for grouping several models to be simulated was introduced. The following will describe the communication method after grouping the several models to be simulated, specifically: Shared memory addresses are allocated for variables that interact between the simulation models in the same simulation node, and reflected memory addresses are allocated for variables that interact between the simulation models in different simulation nodes.

[0051] In practice, in order to enable communication between simulation models in the same group via shared memory, a shared memory area is configured in the simulation node.

[0052] In some exemplary embodiments, before allocating shared memory addresses for variables interacting between the models to be simulated in the same simulation node, the method further includes: Determine the historical allocation information of the reflection memory address corresponding to the variable; Based on the historical allocation information of the reflected memory address, shared memory is configured in the simulation node, and the shared memory is used to provide the variable with the shared memory address to be allocated.

[0053] As an example, assuming the range of reflection memory allocation addresses corresponding to the model to be simulated is 0x4000000-0x6000000 (67,108,864 - 100,663,296), then a shared memory area greater than 32M should be configured in the simulation node.

[0054] In practical implementation, if the simulation node itself only supports automatic allocation of shared memory addresses, this disclosure improves upon this by also supporting manual allocation of shared memory addresses. In this case, the simulation node is configured with shared memory addresses that support manual allocation.

[0055] As an example, if the range of automatically allocated shared memory addresses in the simulation node is (0-20,971,520), which is 20M space, then this disclosure configures manually allocated shared memory addresses in the portion of the space in the simulation node that is greater than 20M.

[0056] In the above exemplary embodiment, the communication method after grouping several models to be simulated was introduced. The generated address allocation table will be described below: In some exemplary embodiments, the address allocation table includes at least the following information: The variable's identifier and address information.

[0057] As an example, the identification information includes the variable's identifier.

[0058] As an example, address information includes the shared memory address or reflected memory address to which the variable is assigned.

[0059] In some exemplary embodiments, the address allocation table also includes the following information: Communication type information for variables.

[0060] As an example, communication type information includes reflected memory communication and shared memory communication.

[0061] Optionally, the address allocation table can be marked with either reflective memory communication or shared memory communication. For example, if reflective memory communication is marked, then unmarked addresses will default to shared memory communication.

[0062] Step S220: Determine the model source file corresponding to the model to be simulated, and generate variable address information in the model source file based on the address allocation table.

[0063] In some exemplary embodiments, determining the model source file corresponding to the model to be simulated, and generating variable address information in the model source file based on the address allocation table, includes: Based on the address allocation table, the variables corresponding to the model to be simulated are determined; In response to determining that the variables corresponding to the model to be simulated are allocated the shared memory address, the variable address information corresponding to the shared memory address is generated in the model source file; And / or, In response to determining that the variable corresponding to the model to be simulated is assigned the reflection memory address, the variable address information corresponding to the reflection memory address is generated in the model source file.

[0064] In specific implementation, the model source file corresponding to the model to be simulated is determined, including: The model source file corresponding to the model to be simulated is generated in real time. Alternatively, obtain the model source file corresponding to the pre-generated model to be simulated.

[0065] In specific implementation, based on the address allocation table, the variable address information in the model source file is generated, including: Based on the address allocation table, variable address information is written into the model source file.

[0066] In specific implementation, when the method for determining the model source file corresponding to the model to be simulated is to generate the model source file corresponding to the model to be simulated in real time, variable address information is written in the model source file in real time based on the address allocation table during the process of generating the model source file corresponding to the model to be simulated in real time. When the method for determining the model source file corresponding to the model to be simulated is to obtain the pre-generated model source file corresponding to the model to be simulated, the variable address information in the model source file is replaced based on the address allocation table.

[0067] In practical implementation, a C code generation tool is used to generate the model source file corresponding to the model to be simulated. Based on this, this disclosure provides the following interface for the C code generation tool to perform read and write operations in the shared memory area using variable address information: The write function is: setVarData; Function prototype: int setVarData(unsigned int offset, data, intlen); Function description: Sends variable data via variable offset.

[0068] Parameter description:

[0069] Function return value: 0 indicates successful execution, otherwise execution fails.

[0070] The function for reading data is: getVarData; Function prototype: void getVarData (unsigned int offset, data, intlen); Function description: Retrieves variable data at the corresponding offset address.

[0071] Parameter description:

[0072] Function return value: 0 indicates successful execution, otherwise execution fails.

[0073] As an example, C code generation tools can use variable address information to perform read and write operations in shared memory regions: setvarData(92274688,( )&CXE ATA76 TCQ Y.ATA7600 J1 SIN ANA V,8); setvarData(92274696,( )&CXE ATA76 TCQ Y.ATA7600 J1 COS ANA V,8); setvarData(92274704,( )&CXE ATA76 TCQ Y.ATA7600 J2 SIN ANA V,8); setVarData(92274712,( )&CXF ATA76 TCQ Y.ATA7600 J2 COS ANA V,8); Among them, "92274688", "92274696", "92274704", and "92274712" are variable address information.

[0074] In practical implementation, add the following comment information: variable address information, which will be used by subsequent analysis tools.

[0075] As an example: double ATA7600 J1 SIN ANA V; / / 92274688 double ATA7600 J1 COS ANA V; / / 92274696 double ATA7600 J2 SIN ANA V; / / 92274704 double ATA7600 J2 COS ANA V; / / 92274712 Among them, "92274688", "92274696", "92274704", and "92274712" are comment information: variable address information.

[0076] In practical implementation, considering that this disclosure is an improvement on a scheme based on a reflective memory network, the variables correspond to historical allocation information of reflective memory addresses. This disclosure effectively utilizes this historical allocation information of reflective memory addresses during read / write operations in the reflective memory region using the variable address information. Specifically: RFM uses DMA configuration.

[0077] RFM addresses use a merged address method: Direction of writing to reflected memory: Due to the address design, the addresses for writing to reflected memory are consecutive, so the overall write operations are merged.

[0078] The direction of reading reflected memory: determine the number of bytes within a preset number (e.g., 1000 bytes) and process them together to read reflected memory data into memory, then copy the data according to the offset memory.

[0079] Step S230: Analyze the model source file to obtain a model analysis file, which includes the variable address information.

[0080] In practice, when analyzing the model source file, the offset from the customer address allocation table is filled into the model variable parsing information and provided to the service for parsing.

[0081] In some exemplary embodiments, the step of parsing the model source file to obtain a model parsing file includes: Analyze the function call relationships in the model source file to determine the coupling relationships between variables in the model source file; The coupling relationship is recorded in the model profile file.

[0082] In practice, by analyzing the data flow or call chain of the model source file, the dependencies or coupling relationships between variables are automatically identified, revealing the internal logic of the simulation model and capturing key topology information that cannot be obtained from the address allocation table alone.

[0083] In some exemplary embodiments, the shared memory supports manual allocation; Then, the step of analyzing the model source file to obtain the model analysis file includes: The model source file is analyzed to identify whether the shared memory address of the variable in the model source file is manually allocated, and manual allocation identification information is obtained; The model analysis file includes the manually assigned identifier information.

[0084] In practice, when analyzing the model source file, a manual allocation flag is added to the variable information to indicate whether the model variable monitoring uses a manually allocated address to read data.

[0085] Step S240: Parse the model profile file and establish a mapping between the variable address information and the monitoring queue.

[0086] In some exemplary embodiments, parsing the model profiling file and establishing the mapping between the variable address information and the monitoring queue includes: The model profile file is parsed to obtain the variable address information; Match the variable address information with the physical address; Establish a mapping between the physical address and the monitoring queue to obtain the mapping between the variable address information and the monitoring queue.

[0087] In practical implementation, this disclosure modifies the service resolution function. When adding monitoring during the model initialization phase, the service matches the offset in the address allocation table with the actual offset allocated by the backend, establishing a mapping between the offset and the monitoring queue. Specifically: To achieve the above functionality, the following new API call has been added: Interface 1 is: getVarNameByOffset; Function prototype: int getVarNameByOffset(long offset, const varName, len); Function description: Retrieves the offset address and data length corresponding to a variable by its name.

[0088]

[0089] Function return value: 0 indicates successful execution, otherwise execution fails.

[0090] Interface 2 is: getCustomOffsetByName; Function prototype: int getCustomOffsetByName(const varName, offset, len); Function description: Retrieves the offset address and data length corresponding to a variable by its name.

[0091]

[0092] Function return value: 0 indicates successful execution, otherwise execution fails.

[0093] Step S250: Perform simulation operations based on the model source file, and perform monitoring based on the mapping between the variable address information and the monitoring queue.

[0094] In some exemplary embodiments, the simulation operation based on the model source file and the monitoring based on the mapping between the variable address information and the monitoring queue include: The model source files are compiled to generate an executable program; The simulation operation is performed based on the executable program; During the simulation operation, data from the physical address is acquired asynchronously.

[0095] As can be seen from the above, the simulation method provided in this disclosure includes: allocating several models to be simulated to different simulation nodes, allocating shared memory addresses for variables interacting between the models to be simulated in the same simulation node, allocating reflected memory addresses for variables interacting between the models to be simulated in different simulation nodes, and generating an address allocation table; determining the model source file corresponding to the model to be simulated, and generating variable address information in the model source file based on the address allocation table; parsing the model source file to obtain a model profile file, the model profile file including the variable address information; parsing the model profile file to establish a mapping between the variable address information and a monitoring queue; performing simulation operations based on the model source file, and performing monitoring based on the mapping between the variable address information and the monitoring queue.

[0096] This disclosure reduces the load on the reflective memory network and decreases simulation timeouts by using shared memory and reflective memory in combination.

[0097] Furthermore, the current simulation software toolchain is optimized by integrating the use of reflected memory address partitioning within the toolchain. This facilitates model monitoring on the simulation platform. The combined use of shared memory and reflected memory is an effective solution for full-machine-level, all-digital simulation, reducing node resource usage while meeting the requirements of high-load network data communication.

[0098] It should be noted that the method of this disclosure embodiment can be executed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method of this disclosure embodiment, and the multiple devices will interact with each other to complete the method described.

[0099] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0100] Based on the same inventive concept, corresponding to any of the above-described embodiments, this disclosure also provides a simulation device.

[0101] refer to Figure 4 This is a schematic diagram of a simulation device provided in an exemplary embodiment of the present disclosure.

[0102] The simulation device includes the following modules: The address allocation table determination module 910 is configured to allocate several simulation models to different simulation nodes, allocate shared memory addresses for variables that interact between the simulation models in the same simulation node, allocate reflection memory addresses for variables that interact between the simulation models in different simulation nodes, and generate an address allocation table. The variable address information determination module 920 is configured to determine the model source file corresponding to the model to be simulated, and generate variable address information in the model source file based on the address allocation table; The analysis module 930 is configured to analyze the model source file to obtain a model analysis file, which includes the variable address information. The parsing module 940 is configured to parse the model profile file and establish a mapping between the variable address information and the monitoring queue; The simulation and monitoring module 950 is configured to perform simulation operations based on the model source file and to perform monitoring based on the mapping between the variable address information and the monitoring queue.

[0103] In some exemplary embodiments, the address allocation table determination module 910 is specifically configured as follows: Determine the cross-linking relationships between the various simulation models; Based on the cross-linking relationships between the simulation models, the simulation models are grouped. The simulation models from different groups are assigned to different simulation nodes.

[0104] In some exemplary embodiments, the address allocation table determination module 910 is specifically configured as follows: Determine the historical allocation information of the reflection memory address corresponding to the variable; Based on the historical allocation information of the reflected memory address, shared memory is configured in the simulation node, and the shared memory is used to provide the variable with the shared memory address to be allocated.

[0105] In some exemplary embodiments, the variable address information determination module 920 is specifically configured as follows: Based on the address allocation table, the variables corresponding to the model to be simulated are determined; In response to determining that the variables corresponding to the model to be simulated are allocated the shared memory address, the variable address information corresponding to the shared memory address is generated in the model source file; And / or, In response to determining that the variable corresponding to the model to be simulated is assigned the reflection memory address, the variable address information corresponding to the reflection memory address is generated in the model source file.

[0106] In some exemplary embodiments, the profiling module 930 is specifically configured as follows: Analyze the function call relationships in the model source file to determine the coupling relationships between variables in the model source file; The coupling relationship is recorded in the model profile file.

[0107] In some exemplary embodiments, the parsing module 940 is specifically configured as follows: The model profile file is parsed to obtain the variable address information; Match the variable address information with the physical address; Establish a mapping between the physical address and the monitoring queue to obtain the mapping between the variable address information and the monitoring queue.

[0108] In some exemplary embodiments, the simulation and monitoring module 950 is specifically configured as follows: The model source files are compiled to generate an executable program; The simulation operation is performed based on the executable program; During the simulation operation, data from the physical address is acquired asynchronously.

[0109] For ease of description, the above apparatus is described in terms of its functions, divided into various modules. Of course, in implementing this disclosure, the functions of each module can be implemented in one or more software and / or hardware.

[0110] The apparatus of the above embodiments is used to implement the corresponding simulation method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0111] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the simulation method described in any of the above embodiments.

[0112] Figure 5 This embodiment illustrates a more specific hardware structure of an electronic device, which may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0113] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0114] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0115] The input / output interface 1030 is used to connect input / output modules to realize information input and output. The input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0116] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0117] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0118] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0119] The electronic devices described above are used to implement the corresponding simulation methods in any of the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0120] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this disclosure also provides a non-transitory computer-readable storage medium that stores computer instructions for causing the computer to execute the simulation method as described in any of the above embodiments.

[0121] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0122] The aforementioned non-transitory computer-readable storage media can be any available medium or data storage device that a computer can access, including but not limited to magnetic storage (e.g., floppy disks, hard disks, magnetic tapes, magneto-optical disks (MOs), etc.), optical storage (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND flash), solid-state drives (SSDs)).

[0123] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the simulation method as described in any of the embodiments in the exemplary method section above, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0124] Based on the same inventive concept, corresponding to the simulation method described in any of the above embodiments, this disclosure also provides a computer program product, which includes computer program instructions. In some embodiments, the computer program instructions can be executed by one or more processors of a computer to cause the computer and / or the processors to perform the simulation method. Corresponding to the execution entity for each step in each embodiment of the simulation method, the processor executing the corresponding step may belong to the corresponding execution entity.

[0125] The computer program products of the above embodiments are used to cause the computer and / or the processor to execute the simulation method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0126] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0127] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0128] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

[0129] While the spirit and principles of this disclosure have been described with reference to several specific embodiments, it should be understood that this disclosure is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for convenience of expression. This disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be interpreted in the broadest sense, thereby encompassing all such modifications and equivalent structures and functions.

Claims

1. A simulation method, characterized in that, include: Several simulation models are assigned to different simulation nodes, and shared memory addresses are assigned to variables that interact between the simulation models in the same simulation node. Reflection memory addresses are assigned to variables that interact between the simulation models in different simulation nodes, and an address allocation table is generated. Determine the model source file corresponding to the model to be simulated, and generate variable address information in the model source file based on the address allocation table; The model source file is analyzed to obtain a model analysis file, which includes the variable address information. The model profile file is parsed to establish a mapping between the variable address information and the monitoring queue; Simulation operations are performed based on the model source file, and monitoring is performed based on the mapping between the variable address information and the monitoring queue.

2. The method according to claim 1, characterized in that, The process of assigning several models to be simulated to different simulation nodes includes: Determine the cross-linking relationships between the various simulation models; Based on the cross-linking relationships between the simulation models, the simulation models are grouped. The simulation models from different groups are assigned to different simulation nodes.

3. The method according to claim 1, characterized in that, Before allocating shared memory addresses for variables interacting between the simulation models in the same simulation node, the method further includes: Determine the historical allocation information of the reflection memory address corresponding to the variable; Based on the historical allocation information of the reflected memory address, shared memory is configured in the simulation node, and the shared memory is used to provide the variable with the shared memory address to be allocated.

4. The method according to claim 1, characterized in that, The step of determining the model source file corresponding to the model to be simulated, and generating variable address information in the model source file based on the address allocation table, includes: Based on the address allocation table, determine the variables corresponding to the model to be simulated; In response to determining that the variables corresponding to the model to be simulated are allocated the shared memory address, the variable address information corresponding to the shared memory address is generated in the model source file; And / or, In response to determining that the variable corresponding to the model to be simulated is assigned the reflection memory address, the variable address information corresponding to the reflection memory address is generated in the model source file.

5. The method according to claim 1, characterized in that, The step of analyzing the model source file to obtain a model analysis file includes: Analyze the function call relationships in the model source file to determine the coupling relationships between variables in the model source file; The coupling relationship is recorded in the model profile file.

6. The method according to claim 1, characterized in that, The step of parsing the model profile file and establishing the mapping between the variable address information and the monitoring queue includes: The model profile file is parsed to obtain the variable address information; Match the variable address information with the physical address; Establish a mapping between the physical address and the monitoring queue to obtain the mapping between the variable address information and the monitoring queue.

7. The method according to claim 6, characterized in that, The simulation operation based on the model source file, and the monitoring based on the mapping between the variable address information and the monitoring queue, include: The model source files are compiled to generate an executable program; The simulation operation is performed based on the executable program; During the simulation operation, data from the physical address is acquired asynchronously.

8. A simulation device, characterized in that, include: The address allocation table determination module is configured to allocate several simulation models to different simulation nodes, allocate shared memory addresses for variables that interact between the simulation models in the same simulation node, allocate reflected memory addresses for variables that interact between the simulation models in different simulation nodes, and generate an address allocation table. The variable address information determination module is configured to determine the model source file corresponding to the model to be simulated, and generate variable address information in the model source file based on the address allocation table; The analysis module is configured to analyze the model source file to obtain a model analysis file, which includes the variable address information. The parsing module is configured to parse the model profile file and establish a mapping between the variable address information and the monitoring queue; The simulation and monitoring module is configured to perform simulation operations based on the model source file and to perform monitoring based on the mapping between the variable address information and the monitoring queue.

9. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions for causing the computer to perform the method of any one of claims 1 to 7.

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