A logic synthesis mapping method based on FPGA double-output lookup table
By optimizing the merging strategy using inverted indexes and resource cost functions, the problem of insufficient resource utilization in dual-output lookup tables in FPGA chips is solved, achieving more efficient resource utilization and area optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU DIANZI UNIV
- Filing Date
- 2026-06-01
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies do not fully utilize dual-output lookup table resources in FPGA chips, resulting in low resource utilization and a lack of a unified resource cost model, which affects engineering applications.
A candidate lookup table pair is generated using an inverted index mechanism, and the merging strategy is optimized through a resource cost function. Combined with structural and functional constraints, efficient splicing of dual-output lookup tables is achieved.
It significantly improves the utilization of dual-output lookup tables in FPGA chips, reduces the number of lookup tables and input pins, optimizes resource utilization, and is suitable for large-scale industrial netlists.
Smart Images
Figure CN122309814A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic design automation (EDA) technology, specifically relating to a logic synthesis mapping method based on FPGA dual-output lookup tables, and more particularly to an FPGA dual-output lookup table logic synthesis mapping method that performs post-processing and splicing on the existing single-output lookup table mapping results. Background Technology
[0002] The basic programmable logic unit of a Field-Programmable Gate Array (FPGA) typically employs a Look-Up Table (LUT) structure, where an n-input LUT can implement any n-input Boolean function. With advancements in technology and architecture, some FPGA chips have introduced dual-output LUT structures on top of single-output LUTs to further improve logic density and resource utilization without increasing the number of physical LUTs. Examples include LUT6D or equivalent dual-output LUT primitives. Internally, such a dual-output LUT can be equivalently understood as two 5-input LUTs sharing inputs I0–I4, and a 2-to-1 multiplexer using I5 as the selection signal. One output is the direct output of a 5-input LUT, while the other output is obtained by multiplexing the outputs of the two 5-input LUTs. Typically, a high input sharing on I0–I4 is required for the two outputs, and the logical expression corresponding to one output must be a subexpression or related function of the other output.
[0003] However, most existing mainstream synthesis tools (such as open-source workflows based on ABC) only explicitly perform cut selection and mapping optimization for single-output LUTs (such as 6-input single-output LUTs) during the technology mapping stage. For dual-output LUTs, the common practice is to first complete the mapping to single-output LUTs, and then perform simple "LUT merging" post-processing in subsequent process-related optimization stages, such as greedily merging LUT pairs based solely on "identical or highly similar input sets". This approach does not explicitly utilize the internal structure of dual-output LUTs, but only merges based on the similarity of input sets, resulting in a large number of functionally safe LUT pairs not being utilized, leading to low resource utilization of dual-output LUTs. In addition, this approach lacks a unified resource cost model, usually only considering the reduction in the number of LUTs, without simultaneously incorporating factors such as the number of input pins, routing complexity, and logic depth into a unified cost function. This can easily lead to situations where the reduction in the number of LUTs is limited or even the critical path order is lengthened, making it difficult to fully utilize the potential of dual-output LUTs and hindering engineering applications.
[0004] In summary, there is an urgent need for a dual-output LUT splicing method that can be executed in the form of post-processing during the process-related optimization stage, based on the existing single-output LUT mapping results. Summary of the Invention
[0005] The purpose of this invention is to overcome the problems in existing technologies, such as the use of only simple splicing strategies in the process-related post-processing stage, insufficient utilization of dual-output LUT structures, inadequate optimization of the number of LUTs and input pins, and low generation efficiency of candidate merging pairs. This invention proposes a logic synthesis mapping method based on FPGA dual-output LUTs. This method is typically executed as a post-processing splicing strategy after the existing single-output LUT mapping process. It can effectively reduce the number of LUTs and input pins while maintaining functional equivalence and a relatively unchanged critical path logic depth, thereby improving the utilization rate of FPGA dual-output LUTs.
[0006] In a first aspect, the present invention provides a logic synthesis method based on an FPGA dual-output LUT, the method comprising:
[0007] Read the target circuit netlist and preprocess it to obtain a single-output lookup table netlist containing multiple general lookup table units and special lookup table units;
[0008] The single-output lookup table netlist is subjected to primitive normalization to obtain a normalized lookup table netlist;
[0009] On the standardized lookup table network, an inverted index from the input signal to the lookup table unit is constructed using the actual input signal of each lookup table unit. Then, candidate lookup table pairs are generated, and structural constraint determination and functional constraint determination are performed on each candidate lookup table pair in sequence to determine the mergeable lookup table pairs that can be mapped to the same dual-output lookup table.
[0010] Construct a resource cost function, use the resource cost function to sort the mergeable lookup table pairs, perform merge mapping operations in sequence according to the sorting results, concatenate the selected lookup table pairs into a double-output lookup table with 6 inputs and 2 outputs, and generate the corresponding initialization parameters.
[0011] Furthermore, the preprocessing includes: reading the target circuit netlist and performing structural hashing; performing logic rewriting and redundancy elimination on Boolean logic and local fan-in structures; mapping logic nodes to single-output lookup tables with preset input widths through cutting construction and optimal cutting selection; and performing post-processing cleaning and multi-fan-out repair on the mapping results to obtain a single-output lookup table netlist.
[0012] Furthermore, the primitive standardization process includes:
[0013] Identify the general lookup table cell in the single-output lookup table netlist, and read the input width and initialization bit string of the general lookup table cell;
[0014] Match the type of native lookup table primitive in the target FPGA process library according to the input width, and write the initialization bit string into the initialization parameters of the native lookup table primitive;
[0015] Reconstruct the primitive input port connections according to the unified port naming rules, so that all lookup table primitives have a consistent input interface structure, and obtain a standardized lookup table netlist.
[0016] Furthermore, the actual input signal is the input signal of the lookup table unit participating in logical operations, and does not include constant input or unused input;
[0017] The key of the inverted index is the actual input signal, and the value is the set of lookup table cells containing that actual input signal.
[0018] Furthermore, the generation of candidate lookup table pairs is specifically as follows:
[0019] For each lookup table cell A, based on its actual input signal, query the inverted index for a set of lookup table cells that share at least one actual input signal; combine lookup table cell A with the queried lookup table cells respectively and remove duplicates to obtain a set of candidate lookup table pairs.
[0020] More preferably, the structural constraint determination is achieved by calculating the size of the union U of the true input signals and the size of the intersection C of the true input signals for any candidate lookup table pair (A, B), and then determining whether it satisfies the structural constraint conditions; specifically:
[0021]
[0022] The requirement is that |U| does not exceed the maximum number of input ports of the dual-output lookup table;
[0023]
[0024] The requirement is that |C| is not lower than the preset sharing threshold.
[0025] Candidate lookup table pairs are determined to pass the structural constraints only when both the union and intersection constraints mentioned above are satisfied. Subsequent functional constraint determinations are then performed on candidate lookup tables that pass the structural constraints.
[0026] The functional constraint determination adopts either the real selection signal method or the constant selection signal method;
[0027] The specific method of the real selection signal is as follows: select one real input signal from the union U as the selection signal sel, so that the Boolean function of one lookup table cell in the candidate lookup table pair is equivalent to the cofactor function of the other lookup table cell when the selection signal sel takes a fixed value.
[0028] The constant selection signal method is as follows: when there is no selection signal sel that satisfies the true selection signal method, the selection signal sel is set as a constant input, so that the two lookup table units are respectively mapped to the two five-input sub-table areas of the dual-output lookup table, and the Boolean functions of the two lookup table units are kept consistent with the original Boolean functions of the two lookup table units in their respective areas.
[0029] Candidate lookup table pairs determined by functional constraints are identified as mergeable lookup table pairs.
[0030] Furthermore, the resource cost function, taking into account both the number of input pins in the merged lookup table and the number of lookup tables required to implement the merge, is defined as follows:
[0031]
[0032] Where N is the number of lookup table entries and M is the number of lookup table input pins. As weight;
[0033] During the sorting process, the cost function difference is calculated for each mergeable lookup table pair (A, B). Sort according to the difference in cost function;
[0034] Cost function difference Defined as:
[0035]
[0036] in For the resource costs corresponding to the candidate lookup table pairs before the merger, This represents the resource cost corresponding to the merged dual-output lookup table.
[0037] Secondly, the present invention provides a logic synthesis mapping system based on an FPGA dual-output LUT, comprising:
[0038] The single-output lookup table acquisition module is used to read the target circuit netlist and preprocess it to obtain the single-output lookup table netlist.
[0039] The primitive standardization module is used to perform primitive standardization processing on the single-output lookup table netlist to obtain a standardized lookup table netlist.
[0040] The lookup table pair generation module is used to generate candidate lookup table pairs on the standardized lookup table network list through inverted index, and determine mergeable lookup table pairs that can be mapped to the same dual-output lookup table after constraint determination.
[0041] The lookup table merging module uses the resource cost function to sort the mergeable lookup table pairs, and performs merge mapping operations sequentially according to the sorting results to obtain a dual-output lookup table.
[0042] Thirdly, the present invention provides an electronic device including a processor and a memory, the memory storing machine-executable instructions executable by the processor, the processor executing the machine-executable instructions to implement the method.
[0043] Fourthly, the present invention provides a machine-readable storage medium, characterized in that the machine-readable storage medium stores machine-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the method.
[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0045] 1. This invention employs an inverted index mechanism that uses the real input signal as the key and the set of lookup table units as the value. This effectively avoids invalid traversal calculations and generates candidate pairs only between lookup tables that share the real input. This avoids pairwise enumeration at the O(N²) level and controls the candidate generation complexity to approximately O(N·k) (where N is the number of lookup tables and k is the average fan-in). This significantly reduces time and space overhead and is suitable for large-scale industrial netlists.
[0046] 2. This invention incorporates the number of lookup tables and the number of input pins into a resource cost function, using the cost difference before and after the merger. As the sorting basis and decision-making criteria, combined with non-conflict constraints and sensitivity verification, the merger scheme that maximizes resource benefits without increasing logic depth is selected first, thereby achieving a good balance between area, pins and performance.
[0047] 3. The preprocessing, primitive standardization, and merging stages of this invention can all be integrated as independent processing steps in existing synthesis tools, or they can be merged into a unified process-related optimization module as needed. This method is independent of a specific synthesis kernel, making it easy to promote and apply in different FPGA process libraries and EDA platforms. Attached Figure Description
[0048] To more clearly illustrate the technical solution of the present invention, the present invention will be further described below with reference to the accompanying drawings, in which:
[0049] Figure 1 This is a schematic diagram of the overall process of the logic synthesis and mapping method based on FPGA dual-output LUT of the present invention;
[0050] Figure 2 This is a flowchart illustrating the pre-optimization and single-output LUT mapping stage (step S1) of the present invention.
[0051] Figure 3 This is a flowchart illustrating the primitive standardization process (step S2) of the present invention.
[0052] Figure 4 This is a schematic diagram of the overall process of the LUT merging and mapping stage of the present invention, corresponding to steps S3 and S4;
[0053] Figure 5 This is a schematic diagram of the structural constraint determination process of the candidate lookup table in this invention;
[0054] Figure 6 This is a schematic diagram illustrating the functional constraint determination process and selection signal determination of the candidate lookup table in this invention.
[0055] Figure 7 This is a schematic diagram illustrating the construction of the dual-output LUT initialization parameter INIT64 and the netlist reconnection process of the present invention.
[0056] The accompanying drawings are for illustrative purposes only and are not drawn to scale. They do not constitute a limitation on the scope of protection of this invention. Detailed Implementation
[0057] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, only to facilitate and clearly illustrate the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different proportions may be used in different drawings to illustrate different aspects.
[0058] This invention provides a logic synthesis mapping method based on an FPGA dual-output LUT, the flowchart of which is shown below. Figure 1 As shown, the process begins by reading the input netlist, pre-optimizing it, and mapping it into a single-output LUT netlist. Next, primitive table transformation is performed, and port naming and INIT parameter formats are standardized to construct a standardized LUT netlist that facilitates bit-level computation and concatenation. Then, an inverted index is built on the standardized LUT netlist, and candidate LUT pairs are generated based on this. Structural and functional constraints are then executed sequentially to determine mergeable LUT pairs that can be mapped to the same dual-output LUT. Finally, the mergeable lookup table pairs are sorted and selected, and INIT64 construction and netlist back-connection are completed to achieve logical synthesis mapping of the dual-output LUT.
[0059] Specifically, this embodiment provides a logic synthesis mapping method based on FPGA dual-output LUTs, which effectively reduces the number of LUTs and input pins while maintaining the critical path logic depth essentially unchanged, improves the utilization rate of dual-output LUT units in the FPGA, and adapts to existing EDA design flows and process library constraints. The method includes:
[0060] S1: Perform pre-optimization on the logic netlist of the target circuit, reconstruct and map the combinational logic into a single-output lookup table netlist that satisfies the preset input width constraint, and control the logic depth while maintaining the functional equivalence of the circuit.
[0061] Specifically:
[0062] S101: Read the target circuit netlist and perform structural hashing;
[0063] S102: Perform logic rewriting and redundancy elimination on Boolean logic and local fan-in structures;
[0064] S103: Mapping logical nodes to single-output lookup tables with preset input widths through Cut construction and optimal Cut selection;
[0065] S104: Perform post-processing cleaning and multi-fanout repair on the mapping results to obtain the single-output lookup table netlist.
[0066] See appendix Figure 2 This example starts with the input circuit netlist, first performs structure hashing, then logic rewriting and redundancy elimination, then cut construction and optimal cut selection, and finally post-processing cleaning and multi-fanout repair. After processing, a single-output LUT netlist with a clear structure and an input width not exceeding a preset threshold is obtained, which serves as the basis for subsequent dual-output LUT splicing.
[0067] S2: Perform primitive standardization processing on the single-output lookup table netlist, convert the general lookup table unit into the native lookup table primitive of the target FPGA process library, and unify the input port naming and initialization parameter representation of the primitive to obtain a standardized lookup table netlist.
[0068] Specifically:
[0069] S201: Identify the general lookup table cell in the single-output lookup table netlist and read its input width and initialization bit string;
[0070] S202: Match the type of the native lookup table primitive in the target FPGA process library according to the input width, and write the initialization bit string into the initialization parameter of the native lookup table primitive;
[0071] S203: Rebuild primitive input port connections according to the unified port naming rules, so that all lookup table primitives have a consistent input interface structure, and obtain a standardized lookup table netlist.
[0072] S3: On the standardized lookup table network, construct an index structure from the input signal to the lookup table unit using the actual input signal of each lookup table unit. Generate candidate lookup table pairs based on the index structure, and perform structural constraint determination and functional constraint determination on the candidate lookup table pairs in sequence to determine the mergeable lookup table pairs that can be mapped to the same dual-output lookup table.
[0073] Specifically:
[0074] S301: For each lookup table cell A, query the set of lookup table cells that share at least one real input signal in the inverted index based on its real input signal;
[0075] S302: Combine the lookup table unit A with the lookup table unit obtained from the query and remove duplicates to obtain a set of candidate lookup table pairs.
[0076] S303: Perform structural constraint filtering on the obtained candidate lookup table pair set to obtain a candidate lookup table pair set that satisfies the structural constraints.
[0077] S304: The set of candidate lookup table pairs that satisfy the structural constraints is filtered by functional constraints to obtain mergeable lookup table pairs that can be mapped to the same double-output lookup table;
[0078] As an example, the structural constraint screening is as follows: Figure 5 As shown, its implementation process is as follows:
[0079] For any candidate lookup table pair (A, B), perform the following structural constraint check:
[0080] Calculate the union of the real input signals U:
[0081]
[0082] like If the number of inputs exceeds the maximum allowed number of inputs for the target dual-output LUT, the candidate pair is determined to be structurally unmergeable and is discarded directly.
[0083] Calculate the intersection C of the actual input signals:
[0084]
[0085] like If the input is less than the preset sharing threshold, it means that the two LUTs share too few inputs. It is difficult to utilize the shared 5-input sub-table within the dual-output LUT, so the merging benefit is limited and it should be discarded as well.
[0086] A candidate lookup table pair is determined to pass the structural constraints only if both the union and intersection constraints mentioned above are satisfied.
[0087] As an example, the functional constraint filtering is as follows: Figure 6 As shown, its implementation process is as follows:
[0088] First, try the real signal selection scheme, selecting one real input signal from the union U as the selection signal. This makes the Boolean function of one lookup table cell in a candidate lookup table pair equivalent to the Boolean function of another lookup table cell. The cofactor function when taking a fixed value;
[0089] If no condition is met. The signal will The signal is fixed as a constant signal 1, that is, the constant selection signal scheme is executed: the two lookup table units are respectively mapped to the two five-input sub-table areas of the dual-output lookup table, and remain consistent with the original function in their respective areas;
[0090] Candidate lookup table pairs determined by functional constraints are identified as mergeable lookup table pairs.
[0091] S4: Sort the mergeable lookup table pairs according to the cost function considering the number of lookup tables and the number of input pins, and select non-conflicting mergeable lookup table pairs in order of priority to perform merge mapping, merge the mergeable lookup table pairs into a dual-output lookup table with 6 inputs and 2 outputs and generate corresponding initialization parameters, thereby reducing the lookup table resource occupation and maintaining the stability of logic depth.
[0092] Specifically:
[0093] S401: Sort the mergeable lookup table pairs according to a resource cost function that considers the number of lookup tables and the number of input pins, and select non-conflicting mergeable lookup tables in order of priority.
[0094] The resource cost function is defined as follows:
[0095]
[0096] Where N is the number of lookup table entries and M is the number of lookup table input pins. As weight.
[0097] In an embodiment of the present invention, =10. This value is based on the priority setting of FPGA resource optimization: the number of LUTs is the core indicator of FPGA logic resource usage, and its influence weight is much higher than that of the number of input pins (in actual measurement, the resource consumption of 1 LUT is about equivalent to the wiring consumption of 10 input pins). Therefore, a weight ratio of 10:1 is adopted to ensure that the number of LUTs is reduced first.
[0098] During the sorting process, the cost function difference is calculated for each mergeable lookup table pair (A, B). Sort according to the difference in cost function;
[0099] Cost function difference Defined as:
[0100]
[0101] in For the resource costs corresponding to the candidate lookup table pairs before the merger, This represents the resource cost corresponding to the merged dual-output lookup table.
[0102] S402: Map the mergeable lookup table pair (A,B) to a dual-output lookup table primitive. Connect the corresponding input ports according to the actual inputs of the two lookup tables. One output is directly taken from the first five-input sub-table, and the other output is switched between the two five-input sub-tables by the selection signal.
[0103] like Figure 7 As shown, the initialization parameter INIT64 of the dual-output lookup table is constructed, and the truth tables of the two lookup tables are filled into the lower half and the upper half respectively. Missing inputs are filled with constants. After completing the construction of INIT, the output of the dual-output lookup table is reconnected to the original network, and the merged original lookup table cells are deleted.
[0104] S403: Perform equivalence and dependency checks on the merged structure. If the check fails, rollback is performed to maintain the correctness of the netlist. Finally, the final double-output LUT netlist is output.
[0105] In a preferred embodiment of the present invention, a shared true input sensitivity verification is further included before performing the merge mapping: the shared true input sensitivity verification is performed only when the two output pairs of the candidate lookup table pair (A,B) share at least one common sensitive input of the shared true input signal, so as to exclude candidate lookup table pairs that are nominally shared but functionally independent.
[0106] To verify the effectiveness of the method of the present invention, the method of the present invention was executed on the logic netlist of the circuit in the experimental environment shown in Table 1, and the results are shown in Table 2.
[0107] Table 1. Experimental environment of the logic synthesis mapping method based on FPGA dual-output lookup table proposed in this invention.
[0108] category Configuration operating system Linux CPU Intel(R) Xeon(R) Gold 6348 CPU @ 2.6GHz GPU NVIDIA GeForce RTX 4090 RAM 500GB Yosys 0.60
[0109] Table 2. Comparison of experimental results between the present invention and existing heuristic methods for area minimization in terms of LUT quantity and cost.
[0110] Design documents Original lookup table count Original resource consumption Number of lookup tables in this invention Resource consumption of this invention rate of change (%) design_1 5290 128795 2639 66283 48.53 design_3 25460 426980 20180 362340 15.14 design_9 1867 31989 1090 18840 41.11 design_15 51611 885847 24464 458865 48.2 design_18 1595 30609 782 15670 48.81 design_20 11299 205747 7378 141925 31.02 design_201 208620 4708051 119326 2757126 41.44 design_207 220602 3607063 127583 2217595 38.5
[0111] The present invention provides an electronic device including a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the method.
[0112] The memory configuration involved in this invention may include fast random access memory (RAM) and non-volatile storage media, such as disk storage devices like hard disks. The system establishes a communication connection with at least one external network element through at least one communication interface (which may be wired or wireless), supporting data exchange through various network environments such as the Internet, wide area network, local area network, or metropolitan area network.
[0113] The bus can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc.
[0114] The memory is used to store program code. When the processor receives instructions to execute these programs, it runs the programs stored in the memory. The method flows defined in any embodiment described in this invention can be integrated into the processor's operation or implemented by the processor itself. In short, after receiving an execution command, the processor executes the programs in the memory to implement the methods disclosed in this invention.
[0115] The processor can be an integrated circuit chip with signal processing capabilities. In implementing the method of this invention, each step can be implemented through the processor's internal hardware logic circuits or software instructions. The processor may be a general-purpose processor, such as a central processing unit (CPU) or a network processor (NP), or it may be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate and transistor logic devices, or discrete hardware components. These processors are capable of implementing or executing the various methods, steps, and logical flows disclosed in this invention.
[0116] The general-purpose processor can be a microprocessor or any standard processor. The method steps of this invention can be executed directly by a hardware decoding processor, or by a combination of hardware and software modules within the decoding processor. The software modules can be stored in established storage media such as random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), or electrically erasable programmable memory (EEPROM). These storage media reside within memory, from which the processor reads information and, in conjunction with its hardware, completes the steps of the method described above.
[0117] One embodiment of the present invention provides a computer program product stored in a readable storage medium and comprising a series of program codes. These codes contain instructions capable of implementing the processes described in the foregoing method embodiments. Specific implementation details have been described in detail in the previous method embodiments and will not be repeated here. In short, this computer program product enables a storage medium to be used to execute the methods disclosed in this invention.
[0118] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.
Claims
1. A logic synthesis method based on a dual-output lookup table in FPGA, characterized in that, The method includes: Read the target circuit netlist and preprocess it to obtain a single-output lookup table netlist; The single-output lookup table netlist is subjected to primitive normalization to obtain a normalized lookup table netlist; On the standardized lookup table network, an inverted index from the input signal to the lookup table unit is constructed using the actual input signal of each lookup table unit. Then, candidate lookup table pairs are generated, and structural constraint determination and functional constraint determination are performed on each candidate lookup table pair in sequence to determine the mergeable lookup table pairs that can be mapped to the same dual-output lookup table. Construct a resource cost function, use the resource cost function to sort the mergeable lookup table pairs, perform merge mapping operations in sequence according to the sorting results, concatenate the selected lookup table pairs into a double-output lookup table with 6 inputs and 2 outputs, and generate the corresponding initialization parameters.
2. The logic synthesis method according to claim 1, characterized in that, The preprocessing includes: reading the target circuit netlist and performing structural hashing; performing logic rewriting and redundancy elimination on Boolean logic and local fan-in structures; mapping logic nodes to single-output lookup tables with preset input widths through cutting construction and optimal cutting selection; and performing post-processing cleaning and multi-fan-out repair on the mapping results to obtain a single-output lookup table netlist.
3. The logic synthesis method according to claim 1, characterized in that, The primitive standardization process includes: Identify the general lookup table cell in the single-output lookup table netlist, and read the input width and initialization bit string of the general lookup table cell; Match the type of native lookup table primitive in the target FPGA process library according to the input width, and write the initialization bit string into the initialization parameters of the native lookup table primitive; Reconstruct the primitive input port connections according to the unified port naming rules, so that all lookup table primitives have a consistent input interface structure, and obtain a standardized lookup table netlist.
4. The logic synthesis method according to claim 1, characterized in that, The actual input signal is the input signal of the lookup table unit participating in the logical operation, and does not include constant input or unused input; The key of the inverted index is the actual input signal, and the value is the set of lookup table cells containing that actual input signal.
5. The logic synthesis method according to claim 1, characterized in that, The specific steps for generating candidate lookup table pairs are as follows: For each lookup table cell A, based on its actual input signal, query the inverted index for a set of lookup table cells that share at least one actual input signal; combine lookup table cell A with the queried lookup table cells respectively and remove duplicates to obtain a set of candidate lookup table pairs.
6. The logic synthesis method according to claim 1, characterized in that, The structural constraint determination is achieved by calculating the union size and intersection size of the true input signals of any candidate lookup table pair (A,B), and determining whether it satisfies the structural constraint conditions. If both the union size and the intersection size satisfy the constraint conditions, the candidate lookup table pair is determined to pass the structural constraint, and then its functional constraint is determined. The functional constraint determination adopts either the real selection signal method or the constant selection signal method; The specific method of the real selection signal is as follows: select one real input signal from the union U as the selection signal, so that the Boolean function of one lookup table cell in the candidate lookup table pair is equivalent to the cofactor function of the other lookup table cell when the selection signal sel takes a fixed value. The constant selection signal method is as follows: when there is no selection signal that satisfies the true selection signal method, the selection signal is set as a constant input, so that the two lookup table units are respectively mapped to the two five-input sub-table areas of the dual-output lookup table, and the Boolean function of the two lookup table units is kept consistent with the original Boolean function of the two lookup table units in their respective areas. If a candidate lookup table pair passes the functional constraint determination, it is determined to be a mergeable lookup table pair.
7. The logic synthesis method according to claim 1, characterized in that, The resource cost function takes into account both the number of input pins of the merged lookup table and the number of lookup tables required to achieve the merge, with the weight of the number of lookup tables being higher than that of the number of input pins. During the sorting process, for each mergeable lookup table pair (A,B), the cost function difference before and after merging is calculated, and the pairs are sorted according to the cost function difference.
8. A logic synthesis mapping system based on an FPGA dual-output lookup table that implements the method as described in any one of claims 1-7, characterized in that, include: The single-output lookup table acquisition module is used to read the target circuit netlist and preprocess it to obtain the single-output lookup table netlist. The primitive standardization module is used to perform primitive standardization processing on the single-output lookup table netlist to obtain a standardized lookup table netlist. The lookup table pair generation module is used to generate candidate lookup table pairs on the standardized lookup table network list through inverted index, and determine mergeable lookup table pairs that can be mapped to the same dual-output lookup table after constraint determination. The lookup table merging module uses the resource cost function to sort the mergeable lookup table pairs, and performs merge mapping operations sequentially according to the sorting results to obtain a dual-output lookup table.
9. An electronic device, characterized in that, It includes a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the method as described in any one of claims 1-7.
10. A machine-readable storage medium, characterized in that, The machine-readable storage medium stores machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the method as described in any one of claims 1-7.