Display panel and method for repairing

Abstract

This disclosure relates to a display panel and a method for repairing it. A display panel according to an example embodiment of this disclosure includes: a first driving voltage line and a second driving voltage line, the first driving voltage line and the second driving voltage line being spaced apart from each other and having a pixel between them; a plurality of driving voltage connection patterns configured to connect the first driving voltage line and the second driving voltage line; and a plurality of gate lines intersecting the first driving voltage line and the second driving voltage line, wherein the plurality of gate lines include at least one gate line including an open circuit portion, and wherein the plurality of driving voltage connection patterns include a repair pattern configured to connect the two ends of the at least one gate line that is disconnected by the open circuit portion.

Description

Technical Field

[0001] This disclosure relates to display panels and repair methods, and more specifically, to display panels and repair methods capable of repairing wiring defects. Background Technology

[0002] With the advent of the mature information age, the field of display devices that visually represent electrical information signals has made rapid progress.

[0003] Representative examples of display devices may include liquid crystal display (LCD) devices, organic light-emitting diode (OLED) display devices, quantum dot display devices, etc.

[0004] Typically, a display device includes a display panel and gating and source driving circuits electrically connected to the display panel and outputting gating signals and data signals. The display panel may include a display area comprising multiple pixels and a peripheral area, in which the gating and source driving circuits are disposed around the display area. Here, components such as various types of transistors, light-emitting elements, data lines, gating lines, driving voltage lines, reference voltage lines, and common voltage lines can be formed in the display area.

[0005] The descriptions provided in the discussion of the Related Art section should not be considered prior art merely because they are mentioned in or associated with that section. The discussion of the Related Art section may include information describing one or more aspects of the subject art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0006] The components in the display area can be formed on the substrate through multiple thin film deposition and etching processes. When defects occur during the etching process of the display panel, wiring defects such as open circuits in gate lines, data lines, and reference voltage lines may occur.

[0007] The display panel and repair method according to the example implementation can repair wiring defects by using lines other than the lines where the wiring defect has occurred.

[0008] The problems addressed in this disclosure are not limited to those described above, and additional problems not mentioned herein will become apparent to those skilled in the art from the following description.

[0009] According to an exemplary embodiment of this disclosure, a display panel may include: a first driving voltage line and a second driving voltage line, the first driving voltage line and the second driving voltage line being spaced apart from each other, and a pixel being present between the first driving voltage line and the second driving voltage line; a plurality of driving voltage connection patterns configured to connect the first driving voltage line and the second driving voltage line; and a plurality of gate lines intersecting the first driving voltage line and the second driving voltage line. Here, the plurality of gate lines may include at least one gate line including an open-circuit portion. The plurality of driving voltage connection patterns may include a repair pattern configured to connect the two ends of the at least one gate line that is disconnected by the open-circuit portion.

[0010] The repair method according to the example embodiment includes the following steps: a first operation, wherein the first operation forms a first driving voltage line and a second driving voltage line, and a plurality of driving voltage connection patterns configured to connect the first driving voltage line and the second driving voltage line, the first driving voltage line and the second driving voltage line being spaced apart from each other, and a pixel being present between the first driving voltage line and the second driving voltage line; a second operation, wherein the second operation forms a plurality of gate lines intersecting the first driving voltage line and the second driving voltage line, the plurality of gate lines including at least one gate line including an open circuit portion; and a third operation, wherein the third operation separates at least one of the plurality of driving voltage connection patterns from the first driving voltage line and the second driving voltage line, thereby forming a repair pattern configured to connect the two ends of the at least one gate line disconnected by the open circuit portion.

[0011] A display panel according to another exemplary embodiment of this disclosure may include: a first driving voltage line and a second driving voltage line, the first driving voltage line and the second driving voltage line being spaced apart from each other, with at least one pixel between the first driving voltage line and the second driving voltage line; a plurality of driving voltage connection patterns configured to connect the first driving voltage line and the second driving voltage line; and a plurality of gate lines intersecting the first driving voltage line and the second driving voltage line. Here, the number of gate lines disposed between every two adjacent driving voltage connection patterns in the plurality of driving voltage connection patterns may be two or less.

[0012] The display panel and repair method according to the exemplary embodiments of this disclosure can have the effect of easily repairing defects in various lines by using drive voltage lines in the form of a grid.

[0013] The effects of this disclosure are not limited to those described above. Other effects not mentioned will become clear to those skilled in the art from the following description. Attached Figure Description

[0014] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0015] Figure 1 This is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure;

[0016] Figure 2 This is a circuit diagram of a sub-pixel circuit according to an example implementation;

[0017] Figure 3 This is a plan view illustrating the normal wiring state of a display panel according to an exemplary embodiment of the present disclosure;

[0018] Figure 4 This is a circuit diagram illustrating the normal wiring state of a display panel according to an exemplary embodiment of the present disclosure;

[0019] Figure 5A This is an example Figure 3 An enlarged top view of the circuit section;

[0020] Figure 5B This is a plan view illustrating the drive voltage connection pattern according to an example embodiment;

[0021] Figure 6A This is a diagram illustrating defective wiring state 1 of the gate line according to an example implementation;

[0022] Figure 6B This is a diagram illustrating defective wiring state 2 of the gate line according to an example implementation;

[0023] Figure 7A This is a plan view of a display panel according to an exemplary embodiment of the present disclosure;

[0024] Figure 7B This is a plan view illustrating the signal path of the repaired gate line according to an example implementation;

[0025] Figures 8A to 8D This is a plan view illustrating the repair process according to an example implementation method;

[0026] Figures 9A to 9D This is a circuit diagram illustrating the repair process according to an example implementation method;

[0027] Figures 10A to 10C This is a cross-sectional view illustrating the repair process according to an example implementation method;

[0028] Figure 11 This is a plan view illustrating defective pixels according to an example implementation;

[0029] Figure 12 This is a circuit diagram illustrating a defective pixel according to an example implementation;

[0030] Figure 13 The diagram is an illustrative example of a pixel restoration method according to an exemplary implementation.

[0031] Figures 14A to 14C This is a plan view illustrating a pixel restoration process according to an example implementation method;

[0032] Figures 15A to 15C This is a circuit diagram illustrating a pixel restoration process according to an example implementation; and

[0033] Figures 16A to 16C This is a cross-sectional view illustrating a pixel restoration process according to an example implementation.

[0034] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals shall be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the dimensions, lengths, and thicknesses of layers, regions, and elements, and their depictions, may be exaggerated.

[0035] [List of reference numerals in the attached diagram]

[0036] VDDL: Drive voltage line

[0037] EVDD_1: Drive voltage connection pattern

[0038] GL1: First gate line

[0039] GL2: Second gate line

[0040] RPL: Pattern Repair

[0041] OP: Opening section

[0042] DVDDL(1): First Dummy Drive Voltage Line

[0043] DVDDL(2): Second Virtual Drive Voltage Line Detailed Implementation

[0044] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to that set forth herein, except that they must occur in a specific order, and can be varied as is known in the art. The names of the elements used in the following description may be chosen solely for ease of writing and may therefore differ from those used in actual products.

[0045] The advantages and features of this disclosure, as well as the methods for implementing them, will become apparent from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in a variety of different forms; rather, these embodiments are provided to complete the disclosure and enable those skilled in the art to fully understand its scope.

[0046] The shapes (e.g., dimensions, lengths, widths, heights, thicknesses, positions, radii, diameters, and areas), proportions, angles, numbers, etc., of the elements shown in the accompanying drawings to illustrate embodiments of the present disclosure are illustrative only and not intended to be limiting. Throughout the specification, the same reference numerals may denote the same parts. Furthermore, in describing the present disclosure, detailed descriptions of well-known technologies may be omitted or briefly given so as not to obscure the essence of the disclosure.

[0047] Terms such as “comprising,” “including,” “having,” “forming,” “constituting,” and “composed of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise specified, references to the components of a singular noun include the plural of that noun.

[0048] An aspect is an example aspect. "Implementation method," "example," "aspect," etc., should not be construed as superior to or better than other implementation methods. Unless otherwise stated, implementation method, example, exemplary implementation method, aspect, etc., may refer to one or more implementation methods, one or more examples, one or more example implementation methods, one or more aspects, etc. Furthermore, the term "may" encompasses all meanings of the term "may."

[0049] When describing components, they are interpreted as including tolerance ranges, even if not explicitly stated otherwise.

[0050] When describing positional relationships, for example, if the positional relationship between two parts is described as "above", "over", "below", "side", etc., then one or more other parts may be located between the two parts unless "directly" is used.

[0051] When a component or layer is disposed "on" another component or layer, the component is disposed directly on the other component or layer or disposed on the other component or layer, with another component in between.

[0052] Terms such as “below,” “lower,” “above,” and “upper” are used herein to describe the relationships between (multiple) elements or (multiple) articles as shown in the accompanying drawings. It should be understood that these terms are spatially relative and based on the orientation depicted in the drawings.

[0053] When describing temporal relationships, such as when describing temporal antecedents as "after", "following", "next", "before", etc., discontinuous cases may also be included unless "immediately" or "directly" is used.

[0054] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can be a second component within the technical spirit of this disclosure.

[0055] Throughout the specification, the same reference numerals generally denote the same elements.

[0056] The dimensions and thicknesses of each component illustrated in the accompanying drawings are shown for ease of description, and this disclosure is not necessarily limited to the dimensions and thicknesses of the illustrated components.

[0057] Features of the various embodiments of this disclosure can be combined or integrated with each other, either partially or completely. The example embodiments can be technically interoperable and performed in various ways, and can be performed independently or in conjunction with each other.

[0058] As used herein, “apparatus” can include display devices, such as liquid crystal modules (LCMs) or organic light-emitting diode (OLED) modules, which include a display panel and a driver for driving the display panel. It can also include assemblies of electronic devices or assemblies, such as laptop computers, televisions, computer monitors, vehicle or automotive devices, or equipment that includes another form of vehicle, as well as mobile electronic devices, such as smartphones or electronic boards, which are complete products or finished goods including LCMs, OLED modules, etc.

[0059] Therefore, the devices or apparatuses described herein may include display devices themselves, such as LCM or OLED modules, application products, and assemblies, including end-user devices comprising LCM or OLED modules.

[0060] Furthermore, in some embodiments, the LCM and OLED modules, consisting of a display panel and a driver, can be referred to as a "display device," and the electronic device can be referred to as a finished product including the LCM and OLED modules, which can be referred to as a "complete assembly." For example, the display device may include a liquid crystal display (LCD) panel or an organic light-emitting display (OLED) panel, and a source printed circuit board (PCB) as a control portion for driving the display panel. The complete assembly may also include a complete PCB, which is a complete control unit electrically connected to the source PCB to drive the entire complete assembly.

[0061] The display panel used in the embodiments of this disclosure can be any type of display panel, including but not limited to liquid crystal display panels, organic light-emitting diode (OLED) display panels, and electroluminescent display panels. The display panel suitable for the display device according to the embodiments of this disclosure is not limited to the shape or size of the display panel.

[0062] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, the terms “part” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the functions described herein that would be understood by one of ordinary skill in the art.

[0063] The various features of the various implementations described herein may be coupled or combined with each other in whole or in part, and may be technically interlocked and operated in various ways, and each of the example implementations may be performed independently or in combination with each other.

[0064] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The dimensions of the components shown in the drawings are drawn to scale for illustrative purposes only and are not drawn to scale with respect to the actual components shown in the drawings.

[0065] Figure 1 This is a plan view of the display panel of this disclosure according to an exemplary embodiment.

[0066] Reference Figure 1The horizontal direction X and vertical direction Y of the display panel 100 can be the length direction and width direction of the display panel 100, respectively. Furthermore, the horizontal direction X and vertical direction Y of the display panel 100 can also be represented by the row direction and column direction, respectively. The thickness direction Z can refer to the direction perpendicular to the plane defined by the horizontal direction X and vertical direction Y of the display panel 100. The display panel 100 can have a cross-section in the thickness direction Z.

[0067] Reference Figure 1 The display panel 100 according to an exemplary embodiment of the present disclosure may include a display panel driving circuit for writing pixel data to pixels, and a power supply 140 for generating the power required to drive the pixels and the display panel driving circuit.

[0068] The display area AA of the display panel 100 may include a pixel array for displaying an input image thereon. The pixel array may include multiple data lines DL, multiple gate lines GL intersecting the data lines DL, and pixels arranged in a matrix. The display panel 100 may include power lines commonly connected to the pixels. The power lines may be commonly connected to a constant voltage node of the pixel circuitry and supply the constant voltage required to drive the pixel PXL. The power lines may be implemented as strips or mesh wiring commonly connected to the pixels of the display panel 100.

[0069] Each pixel PXL may include multiple sub-pixels of different colors for implementing the color, such as a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The color settings of the sub-pixels can be changed. The first sub-pixel may be, but is not limited to, a blue (B) sub-pixel, the second sub-pixel may be a green (G) sub-pixel, the third sub-pixel may be a red (R) sub-pixel, and the fourth sub-pixel may be a white (W) sub-pixel. In an exemplary embodiment, each sub-pixel may display one of red, green, and blue. In another exemplary embodiment, each sub-pixel may display one of cyan, magenta, and yellow.

[0070] Each sub-pixel may include pixel circuitry for driving a light-emitting element. Each pixel circuit may be connected to data lines, gating lines, and power lines. Each sub-pixel may be divided into a circuit region and a light-emitting region. The pixel circuitry may be located within the circuit region. The light-emitting region may be the area where light is emitted by a light-emitting element electrically connected to the pixel circuitry.

[0071] The pixel array may include multiple pixel lines L1 to LN. Each pixel line L1 to LN may include a row of pixels arranged along the X-axis direction of the pixel array in the display panel 100. Pixels arranged in a pixel line may share a gating line GL. Subpixels arranged in the column direction (Y) along the data line direction may share the same data line DL. A horizontal period is the time obtained by dividing a frame period by the total number of pixel lines L1 to LN.

[0072] The power supply 140 outputs the voltage required to drive the pixels of the display panel 100 and the display panel driving circuitry by using a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc.

[0073] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image into the pixels of the display panel 100. The display panel driving circuit includes a data driver 110, a gating driver 120, and other circuit components.

[0074] The display panel driving circuit can use double rate drive (DRD) to drive pixels. In a DRD-driven display panel, data lines DL are connected to the left and right adjacent sub-pixels, reducing the number of channels and data lines DL in the data driver 110, which helps to ensure the pixel aperture ratio.

[0075] In one or more aspects, to further provide touch sensing and image display functions, the display panel driving circuit may further include at least one touch sensor and a touch sensing circuit, which is capable of detecting touch events from touch objects such as fingers or pens by sensing the touch sensor, or detecting the corresponding touch position (or touch coordinates). The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver can be integrated into a single source driver integrated circuit (IC), but are not limited to this.

[0076] Data driver 110 can receive pixel data of the input image as a digital signal from timing controller 130 and output a data voltage. Data driver 110 can output the data voltage by converting the pixel data of the input image into a gamma-compensated voltage in each frame period using a digital-to-analog converter (DAC). The data voltage can be output from each channel of data driver 110 through an output buffer.

[0077] The gating driver 120 may be formed in the display panel 100 together with the TFT array of the pixel array and the wiring. The gating driver 120 may be located on the non-display area NA of the display panel 100, or at least some of the gating drivers may be located in the display area AA in which the input image is reproduced.

[0078] In one or more aspects, the gate driver 120 may be connected to the display panel 100 via tape-on-board (TAB) technology, or to conductive pads, such as the pads of the display panel 100, via chip-on-glass (COG) technology or chip-on-panel (COP) technology, or to the display panel 100 via chip-on-film (COF) technology. In one or more aspects, the gate driver 120 may be disposed in the non-display area NA of the display panel 100 via gate-in-panel (GIP) technology, but is not limited thereto. Alternatively, the gate driver 120 may be disposed in the display area AA of the display panel 100.

[0079] The gating driver 120 may be located in the non-display areas NA on both sides of the display panel 100, with the display area AA of the display panel in between, and may supply gating pulses from both sides of the gating line GL in a dual-feed manner. In another embodiment, the gating driver 120 may be located in at least one of the left non-display area NA and the right non-display area NA of the display panel 100, and may supply the gating signal to the gating line GL in a single-feed manner. Under the control of the timing controller 130, the gating driver 120 sequentially outputs the pulses of the gating signal (hereinafter referred to as "gating pulses") to the gating line 103. The gating driver 120 may use shift registers to shift the gating pulses to sequentially supply the gating pulses to the gating line GL. The gating driver 120 may include one or more shift registers that output the pulses of the gating signal.

[0080] The timing controller 130 receives digital video data of the input image and timing signals synchronized with the digital video data from an external device such as the host system 200. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and a data enable signal. The vertical and horizontal periods can be determined by counting the data enable signals, thus the vertical and horizontal synchronization signals can be omitted. The data enable signal has a period of one horizontal period (1H). Based on the timing signals received from the host system 200, the timing controller 130 generates a data timing control signal for controlling the operating timing of the data driver 110 and a gating timing control signal for controlling the operating timing of the gating driver 120.

[0081] The timing controller 130 can add white data to the three primary colors of the pixel data RGB input from the host system and convert it into four sub-color data RGBW for transmission to the data driver 110. The three primary colors of the pixel data RGB can be converted into four sub-color data RGBW, including white data, using any known color conversion algorithm.

[0082] For example, the timing controller 130 can generate W data for the first pixel data based on the minimum grayscale value among the R, G, and B data of the first pixel data received as input image data, thereby converting the first pixel data into four sub-color data RGBW. Furthermore, the timing controller 130 can generate W data for the second pixel data based on the minimum grayscale value among the R, G, and B data of the second pixel data received as input image data, thereby converting the second pixel data into four sub-color data RGBW.

[0083] For each of the first and second pixel data, the grayscale values ​​of the R, G, and B data can be reduced using the W data. Here, R data is the data to be written to the red subpixel, G data is the data to be written to the green subpixel, B data is the data to be written to the blue subpixel, and W data is the data to be written to the white subpixel.

[0084] Level shifter 150 can receive gating timing control signals from timing controller 130 and generate start pulses and shift clocks to provide them to gating driver 120. The start pulse and shift clock output from level shifter 150 oscillate between gating high voltage and gating low voltage.

[0085] The host system 200 may include, but is not limited to, a motherboard from any of the following: a television system, a set-top box, a navigation system, a personal computer (PC), an in-vehicle system, a mobile terminal, or a wearable terminal. The host system may scale the image signal from the video source to match the resolution of the display panel 100 and may send it along with a timing signal to the timing controller 130.

[0086] Figure 2 This is a circuit diagram of a sub-pixel circuit according to an example implementation.

[0087] Reference Figure 2 The circuitry of each sub-pixel PXL (hereinafter referred to as the sub-pixel circuitry) can be connected to the data line DL of the data voltage Vdata to which pixel data is applied, the gating line GL of the gating pulse scan to which gating pulse is applied, the driving voltage line VDDL of the pixel driving voltage EVDD to which pixel driving voltage is applied, the low potential voltage line VSSL of the low potential voltage EVSS to which low potential voltage is applied, and the reference voltage line RL of the reference voltage Vref to which reference voltage is applied.

[0088] Each sub-pixel circuit may include a light-emitting element EL, multiple transistors DT, T1, and T2, and a capacitor C. However, the sub-pixel circuit configuration in the display panel described herein is not limited to this. For example, structures such as 4T1C, 5T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T1C, 7T2C, and 8T2C are also possible. Furthermore, it may include more or fewer transistors and capacitors.

[0089] The light-emitting element can be an organic light-emitting diode (OLED) or an inorganic light-emitting element, such as a micro LED. The light-emitting element EL can include, but is not limited to, red, green, and blue light-emitting elements. The anode electrode of the light-emitting element EL can be electrically connected to the driving element DT and is disposed in its corresponding light-emitting area within each pixel. When a current is generated from the driving element DT, the light-emitting element EL is driven and emits light, which is emitted to the outside of the display panel through the light-emitting area.

[0090] The driving element DT can generate current based on the gate-source voltage to drive the light-emitting element EL. The driving element DT includes a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. A capacitor C is connected between the first node N1 and the third node N3. The second node N2 is connected to the driving voltage line VDDL. The third node N3 is connected to the anode electrode of the light-emitting element EL. The cathode electrode of the light-emitting element EL is connected to the low-potential voltage line VSSL, to which a low-potential voltage EVSS is applied.

[0091] A first switching element T1 is connected between the data line DL and the first node N1. The first switching element T1 is turned on in response to a gating pulse scan. When the first switching element T1 is turned on, the data voltage Vdata of the pixel data is applied to the first node N1, thereby writing the pixel data to the sub-pixel. The first switching element T1 may include a gate electrode connected to the gating line GL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1.

[0092] A second switching element T2 is connected between the third node N3 and the reference voltage line RL. The second switching element T2 is turned on in response to a gating pulse scan. When the second switching element T2 is turned on, the third node N3 is connected to the reference voltage line RL. The second switching element T2 may include a gate electrode connected to the gating line GL, a first electrode connected to the third node N3, and a second electrode connected to the reference voltage line RL.

[0093] The first electrode can be one of the source electrode and the drain electrode, and the second electrode can be the other of the source electrode and the drain electrode. In this disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode can be used interchangeably. The source electrode can be the drain electrode, and the drain electrode can be the source electrode. Furthermore, the source electrode of any aspect of this disclosure can be the drain electrode of another aspect of this disclosure, and the drain electrode of any aspect of this disclosure can be the source electrode of another aspect of this disclosure.

[0094] The driving element DT should have uniform electrical characteristics across all sub-pixels; however, due to process variations and device characteristic variations, differences in electrical characteristics may exist between sub-pixels, and these differences may increase over time as the sub-pixel driving time increases. To compensate for these variations in the electrical characteristics of the driving element DT, an external compensation circuit can be applied to the display panel driving circuit.

[0095] Figure 3 This is a plan view illustrating the normal wiring state of a display panel according to an exemplary embodiment of the present disclosure. Figure 4 This is a circuit diagram illustrating the normal wiring state of a display panel according to an exemplary embodiment of the present disclosure. Figure 5A This is an example Figure 3 Enlarged plan view of the circuit section. Figure 5B This is a plan view illustrating the drive voltage connection pattern according to an example embodiment.

[0096] Reference Figure 3 and Figure 4 The display panel according to the example embodiment may include a plurality of pixels PXL1, PXL1', PXL2, and PXL2', and may include a driving voltage line MVDDL, a reference voltage line RL, data lines DL1, DL2, DL3, and DL4, and gate lines GL1 and GL2 configured to drive the plurality of pixels PXL1, PXL1', PXL2, and PXL2'. The horizontal direction X of the display panel 100 may be aligned with the gate lines GL1 and GL2, and its vertical direction Y may be aligned with the driving voltage line MVDDL, the reference voltage line RL, and the data lines DL1, DL2, DL3, and DL4.

[0097] Multiple pixels PXL (PXL1, PXL1', PXL2, and PXL2') may include a first pixel PXL1, a first dominant pixel PXL1', a second pixel PXL2, and a second dominant pixel PXL2'.

[0098] First pixel PXL1 and first main pixel PXL1', having the same structure, can be arranged in a repeating pattern along the vertical direction Y. Here, some circuit portions of the first pixel PXL1 and the first main pixel PXL1' can be aligned with each other in the horizontal direction X. For example, the first circuit portion CA1 and the second circuit portion CA2 of the first pixel PXL1 can be aligned with the third circuit portion CA3 and the fourth circuit portion CA4 of the first main pixel PXL1' in the horizontal direction X.

[0099] The second pixel PXL2 and the second main pixel PXL2', which have the same structure, can be arranged in a repeating pattern along the vertical direction Y. Here, some circuit portions of the second pixel PXL2 and the second main pixel PXL2' can be aligned with each other in the horizontal direction X. For example, the first main circuit portion CA1' and the second main circuit portion CA2' of the second pixel PXL2 can be aligned with the third main circuit portion CA3' and the fourth main circuit portion CA4' of the second main pixel PXL2' in the horizontal direction X.

[0100] The first pixel PXL1 and the second pixel PXL2 can be arranged in a repeating pattern along the horizontal direction X. Furthermore, the first main pixel PXL1' and the second main pixel PXL2' can also be arranged in a repeating pattern along the horizontal direction X. Hereinafter, taking the first pixel PXL1 and the second pixel PXL2 as examples, we will explain two pixels arranged in a repeating pattern along the horizontal direction X.

[0101] The first to fourth light-emitting components EA (EA1, EA2, EA3, EA4, EA1', EA2', EA3', and EA4') of the first pixel PXL1 and the second pixel PXL2 can be arranged sequentially in the horizontal direction X. For example, regarding the driving voltage line VDDL between the first pixel PXL1 and the second pixel PXL2, the first light-emitting component EA1 to the fourth light-emitting component EA4 of the first pixel PXL1 can be arranged sequentially from the left side to the left side, and the first light-emitting component EA1' to the fourth light-emitting component EA4' of the second pixel PXL2 can be arranged sequentially from the left side to the right side.

[0102] For example, the first light-emitting component EA1 to the fourth light-emitting component EA4 of the first pixel PXL1 can be located to the left of the driving voltage line VDDL, and the first main light-emitting component EA1' to the fourth main light-emitting component EA4' of the second pixel PXL2 can be located to the right of the driving voltage line VDDL, but is not limited thereto.

[0103] Conversely, the first to fourth circuit portions CA (CA1, CA2, CA3, CA4, CA1', CA2', CA3', and CA4') of the first pixel PXL1 and the second pixel PXL2 can be arranged symmetrically based on the vertical direction Y. Regarding the driving voltage line VDDL disposed between the first pixel PXL1 and the second pixel PXL2, the first circuit portions CA1 to CA4 of the first pixel PXL1 disposed on the left side can be symmetrical with the first main circuit portions CA1' to CA4' of the second pixel PXL2 disposed on the right side.

[0104] For example, the first circuit portion CA1 and the second circuit portion CA2 of the first pixel PXL1 can be respectively disposed above the corresponding first light-emitting components EA1 and EA2, and the third circuit portion CA3 and the fourth circuit portion CA4 of the first pixel PXL1 can be respectively disposed below the corresponding third light-emitting components EA3 and EA4. Similarly, the first main circuit portion CA1' and the second main circuit portion CA2' of the second pixel PXL2 can be respectively disposed below the corresponding first main light-emitting components EA1' and EA2', and the third main circuit portion CA3' and the fourth main circuit portion CA4' of the second pixel PXL2 can be respectively disposed above the corresponding third main light-emitting components EA3' and EA4'. However, the arrangement structure of multiple pixels is exemplary, and the embodiments of this disclosure are not limited thereto.

[0105] Each pixel in multiple pixels PXL1 and PXL2 may include one or more sub-pixels. For example, the first pixel PXL1 may include a first sub-pixel including a first light-emitting component EA1 and a first circuit portion CA1, a second sub-pixel including a second light-emitting component EA2 and a second circuit portion CA2, a third sub-pixel including a third light-emitting component EA3 and a third circuit portion CA3, and a fourth sub-pixel including a fourth light-emitting component EA4 and a fourth circuit portion CA4.

[0106] For example, the second pixel PXL2 may include: a first sub-pixel, the first sub-pixel including a first main light-emitting component EA1' and a first main circuit portion CA1'; a second sub-pixel, the second sub-pixel including a second main light-emitting component EA2' and a second main circuit portion CA2'; a third sub-pixel, the third sub-pixel including a third main light-emitting component EA3' and a third main circuit portion CA3'; and a fourth sub-pixel, the fourth sub-pixel including a fourth light-emitting component EA4' and a fourth main circuit portion CA4'.

[0107] Each pixel in multiple pixels PXL1 and PXL2 may include sub-pixels that emit different colors. For example, each pixel in multiple pixels PXL1 and PXL2 may include multiple sub-pixels, such as red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, but is not limited thereto. For example, the red sub-pixel may be the first sub-pixel, the green sub-pixel may be the second sub-pixel, the white sub-pixel may be the third sub-pixel, and the blue sub-pixel may be the fourth sub-pixel.

[0108] Combined with reference Figure 3 and Figure 4 The first light-emitting component EA1 and the first main light-emitting component EA1' can emit red light as a first sub-pixel, the second light-emitting component EA2 and the second main light-emitting component EA2' can emit green light as a second sub-pixel, the third light-emitting component EA3 and the third main light-emitting component EA3' can emit white light as a third sub-pixel, and the fourth light-emitting component EA4 and the fourth main light-emitting component EA4' can emit blue light as a fourth sub-pixel. However, the types of multiple sub-pixels are exemplary, and the embodiments of this disclosure are not limited thereto.

[0109] Each sub-pixel can be connected to the data line DL, the gating line GL, the driving voltage line MVDDL, and the reference voltage line RL.

[0110] Data lines DL1, DL2, DL3, and DL4 branch from their respective main data lines DL10, DL20, DL30, and DL40 to reach two adjacent pixels PXL1 and PXL2, and can be driven in DRD mode. For example, data lines DL1, DL2, DL3, and DL4 branch from their respective main data lines DL10, DL20, DL30, and DL40 to reach the corresponding sub-pixels of two adjacent pixels PXL1 and PXL2.

[0111] For example, the first main data line DL10 can branch to the first data line DL1 to be connected to the first sub-pixel of each of the first pixel PXL1 and the second pixel PXL2, the second main data line DL20 can branch to the second data line DL2 to be connected to the second sub-pixel of each of the first pixel PXL1 and the second pixel PXL2, the third main data line DL30 can branch to the third data line DL3 to be connected to the third sub-pixel of each of the first pixel PXL1 and the second pixel PXL2, and the fourth main data line DL40 can branch to the fourth data line DL4 to be connected to the fourth pixel PXL4.

[0112] Here, each of the first data lines DL1 to the fourth data line DL4 can form a branch line extending from it to the corresponding sub-pixel. Therefore, the first data lines DL1 to the fourth data lines DL4 can provide data signals to the corresponding sub-pixels through the branch lines.

[0113] Two data lines branching from a main data line can have branch lines positioned in different directions for two different circuit sections located in the same column. For example, when a single main data line branches into two data lines, one data line can have a branch line positioned on the upper side of a circuit section, while the other data line can have a branch line positioned on the lower side of another circuit section.

[0114] The gate lines GL (GL1 and GL2) may include a first gate line GL1 and a second gate line GL2. The first gate line and the second gate line may be arranged in a repeating pattern along the vertical direction Y. The first gate line GL1 and the second gate line GL2 that are adjacent to each other may be arranged above and below the circuit section CA, respectively, in the vertical direction Y.

[0115] For example, the first gate line GL1 can be positioned above the circuit section CA in the vertical direction Y, and the second gate line GL2 can be positioned below the circuit section CA in the vertical direction Y. The first gate line GL1 and the second gate line GL2 can each correspond to two data lines branching from the main data line. Therefore, although the main data line provides the same signal to both data lines, the two data lines can cross each other with different first and second gate lines.

[0116] For example, the first gate line GL1 can provide signals to the third circuit portion CA3 and the fourth circuit portion CA4 of the first pixel PXL1, and to the first main circuit portion CA1' and the second main circuit portion CA2' of the second pixel PXL2. Similarly, the second gate line GL2 can provide signals to the first circuit portion CA1 and the second circuit portion CA2 of the first pixel PXL1, and to the third main circuit portion CA3' and the fourth main circuit portion CA4' of the second pixel PXL2.

[0117] As an example, for the first pixel PXL1, the first and second sub-pixels can be formed at the intersection of the second gate line GL2 and the data line, and the third and fourth sub-pixels can be formed at the intersection of the first gate line GL1 and the data line. For the second pixel PXL2, the first and second sub-pixels can be formed at the intersection of the first gate line GL1 and the data line, and the third and fourth sub-pixels can be formed at the intersection of the second gate line GL2 and the data line, but are not limited to this.

[0118] In this case, for the first pixel PXL1, the first sub-pixel can be formed at the intersection of the second gate line GL2 and the first data line DL1, the second sub-pixel can be formed at the intersection of the second gate line GL2 and the second data line DL2, the third sub-pixel can be formed at the intersection of the first gate line GL1 and the third data line DL3, and the fourth sub-pixel can be formed at the intersection of the first gate line GL1 and the fourth data line DL4.

[0119] For the second pixel PXL2, the first sub-pixel can be formed at the intersection of the first gate line GL1 and the first data line DL1, the second sub-pixel can be formed at the intersection of the first gate line GL1 and the second data line DL2, the third sub-pixel can be formed at the intersection of the second gate line GL2 and the third data line DL3, and the fourth sub-pixel can be formed at the intersection of the second gate line GL2 and the fourth data line DL4.

[0120] In other words, in the DRD method, the first pixel PXL1 and the second pixel PXL2 are supplied with the same main data lines DL10, DL20, DL30 and DL40 signals, but can be driven separately by different gate lines GL1 and GL2.

[0121] For example, the first sub-pixel of the first pixel PXL1 can be driven by the second gate line GL2 and the first data line DL1 branching to the left from the first main data line DL10, and the first sub-pixel of the second pixel PXL2 can be driven by the first gate line GL1 and the first data line DL1 branching to the right from the first main data line DL10. Similarly, the second sub-pixel of the first pixel PXL1 can be driven by the second gate line GL2 and the second data line DL2 branching to the left from the second main data line DL20, and the second sub-pixel of the second pixel PXL2 can be driven by the first gate line GL1 and the second data line DL2 branching to the right from the second main data line DL20.

[0122] For example, the third sub-pixel of the first pixel PXL1 can be driven by the first gate line GL1 and the third data line DL3, which branches to the left from the third main data line DL30, and the third sub-pixel of the second pixel PXL2 can be driven by the second gate line GL2 and the third data line DL3, which branches to the right from the third main data line DL30. Similarly, the fourth sub-pixel of the first pixel PXL1 can be driven by the first gate line GL1 and the fourth data line DL4, which branches to the left from the fourth main data line DL40, and the fourth sub-pixel of the second pixel PXL2 can be driven by the second gate line GL2 and the fourth data line DL4, which branches to the right from the fourth main data line DL40.

[0123] Reference Figure 5BAccording to an exemplary embodiment of this disclosure, the driving voltage lines MVDDL may include a plurality of driving voltage lines VDDL disposed along the vertical direction Y and a plurality of driving voltage connection patterns EVDD_1 configured to connect the plurality of driving voltage lines VDDL. The driving voltage lines VDDL and the driving voltage connection patterns EVDD_1 may form a grid pattern by intersecting each other. However, the display panel of this disclosure is not limited thereto. For example, the driving voltage lines VDDL and the driving voltage connection patterns EVDD_1 may be integrally formed on the same layer. For example, refer to Figure 3 and Figure 5B The number of gate lines set between any two adjacent drive voltage connection patterns in the plurality of drive voltage connection patterns EVDD_1 can be less than 2, but is not limited thereto.

[0124] Each driving voltage line VDDL can be set between each pair of pixels PXL1 or PXL2. In other words, the driving voltage lines VDDL can be separated from each other between the first pixel PXL1 or the second pixel PXL2.

[0125] The driving voltage connection pattern EVDD_1 can connect to the driving voltage line VDDL. Each driving voltage connection pattern EVDD_1 is positioned between each pair of adjacent first gating lines GL1 and second gating lines GL2. Each driving voltage connection pattern EVDD_1 can be symmetrical about the driving voltage line VDDL positioned between the first pixel PXL1 and the second pixel PXL2.

[0126] Each drive voltage connection pattern EVDD_1 may include a connecting line EVDD_a and an overlapping portion EVDD_b. Each drive voltage connection pattern EVDD_1 may be configured such that the connecting line EVDD_a and the overlapping portion EVDD_b alternate. The connecting line EVDD_a and the overlapping portion EVDD_b may be integrally formed. The overlapping portion EVDD_b is the area that overlaps with and can contact the drive voltage line VDDL. For example, each overlapping portion EVDD_b and each drive voltage line VDDL may contact each other at the fifth contact portion CT5.

[0127] Each connecting line EVDD_a can be positioned between the overlapping portions EVDD_b by extending from them. For example, connecting lines EVDD_a can be positioned between each pair of drive voltage lines VDDL. Connecting lines EVDD_a may include a first connecting line EVDD_1a, a second connecting line EVDD_2a, and a third connecting line EVDD_3a positioned between the first connecting line EVDD_1a and the second connecting line EVDD_2a. For example, the first connecting line EVDD_1a, the second connecting line EVDD_2a, and the third connecting line EVDD_3a can be positioned between the overlapping portions EVDD_b.

[0128] The first connecting line EVDD_1a and the second connecting line EVDD_2a can extend from their respective overlapping portions EVDD_b toward the reference voltage line RL. For example, the first connecting line EVDD_1a and the second connecting line EVDD_2a can extend from their respective overlapping portions EVDD_b toward the third connecting line EVDD_3a. The first connecting line EVDD_1a and the second connecting line EVDD_2a can be arranged approximately along the horizontal direction X, excluding dependence on the light-shielding pattern. Figure 5A The curved part of the LS in the diagram.

[0129] The first connecting line EVDD_1a and the second connecting line EVDD_2a can be configured not to overlap with the corresponding branch lines of data lines DL1, DL2, DL3, and DL4, or the reference voltage line RL. Therefore, the first connecting line EVDD_1a and the second connecting line EVDD_2a can be positioned on different sides of the circuit section relative to the vertical direction Y.

[0130] For example, the first connecting line EVDD_1a can be disposed above the first circuit portion CA1 and the second circuit portion CA2 of the first pixel PXL1, while the second connecting line EVDD_2a can be disposed below the third circuit portion CA3 and the fourth circuit portion CA4 of the first main pixel PXL1' which is adjacent to the first pixel PXL1 relative to the reference voltage line RL.

[0131] In another example, the first connecting line EVDD_1a can be located above the third main circuit portion CA3' and the fourth main circuit portion CA4' of the second pixel PXL2, while the second connecting line EVDD_2a can be located below the first main circuit portion CA1' and the second main circuit portion CA2' of the second main pixel PXL2' that is adjacent to the second pixel PXL2 relative to the reference voltage line RL.

[0132] The third connecting line EVDD_3a can be bent from each of the first connecting line EVDD_1a and the second connecting line EVDD_2a, and can be positioned in the vertical Y direction. The third connecting line EVDD_3a can have an overlapping area along the length direction of the reference voltage line RL. For example, the third connecting line EVDD_3a can also overlap with the reference voltage line RL along its length direction. Here, the length direction of the reference voltage line RL refers to the orientation of the reference voltage line RL in the display panel.

[0133] A reference voltage line RL can be set between each pair of drive voltage lines VDDL. For example, the reference voltage line RL can be set between each pair of second data lines DL2 and third data lines DL3.

[0134] A reference voltage line RL can supply a reference voltage to each sub-pixel located on opposite sides in the horizontal direction X. For example, the reference voltage line RL can be connected to the corresponding sub-pixel via a branch line extending from the reference voltage line RL to the corresponding sub-pixel on the opposite side of the circuit.

[0135] Figure 5A Enlarged views of any two circuit sections, CA1 and CA2, are shown. Additionally, Figure 3 The first circuit portion CA1 to the fourth circuit portion CA4 of the first pixel PXL1 and the first main circuit portion CA1' to the fourth main circuit portion CA4' of the second pixel PXL2 can have the same as Figure 5A The circuit portion shown and described has the same structure.

[0136] Reference Figure 5A According to the example embodiment, the first circuit portion CA1 is connected to the branch line DL1_1 of the first data line DL1, the branch line RL_1 of the reference voltage line RL, and the drive voltage connection pattern EVDD_1, and may include a first switching element T1, a second switching element T2, a drive element DT, and a capacitor.

[0137] According to the example embodiment, the second circuit portion CA2 is connected to the branch line DL2_1 of the second data line DL2, the branch line RL_2 of the reference voltage line RL, and the drive voltage connection pattern EVDD_1, and may include a first switching element T1, a second switching element T2, a drive element DT, and a light-shielding layer LS. However, the structures of circuit portions CA1, CA2, CA3, CA4, CA1', CA2', CA3', and CA4' are exemplary, and the embodiments of this disclosure are not limited thereto. Hereinafter, the first switching element, the second switching element, the drive element, and the capacitor will be described based on the second circuit portion CA2.

[0138] The light-shielding layer LS is formed as any one of the electrodes of the capacitor and can have a light-shielding function to block light directed towards the active layers ACT1, ACT2 and ACT3.

[0139] The capacitor may include a light-shielding layer LS, a first active layer ACT1 of a first switching element T1, and an insulator between the light-shielding layer LS and the first active layer ACT1.

[0140] The first switching element T1 can be turned on in response to the gating pulse of the second gating line GL2.

[0141] The first switching element T1 may include a first active layer ACT1 and first-first contact portions CT1_1 and CT1_2 on opposite sides of the first active layer ACT1. The first switching element T1 can be connected to the second data line DL2 via the first-first contact portion CT1_1, and can be connected to the gate electrode GT of the driving element DT via the first-second contact portion CT1_2. Here, the first-first contact portion CT1_1 and the first-second contact portion CT1_2 may include corresponding electrodes for connecting to the second data line DL2 and the gate electrode GT.

[0142] The second switching element T2 can be turned on in response to the gating pulse of the second gating line GL2.

[0143] The second switching element T2 may include a second active layer ACT2 and a second-first contact portion CT2_1 and a second-second contact portion CT2_2 located on opposite sides of the second active layer ACT2. The second switching element T2 can be connected to a reference voltage line RL via the second-first contact portion CT2_1 and to a light-shielding layer LS via the second-second contact portion CT2_2. Here, the second-first contact portion CT2_1 and the second-second contact portion CT2_2 may include corresponding electrodes for connecting to the reference voltage line RL and the capacitor C.

[0144] When a signal is applied to the gate electrode GT, the drive element DT can be turned on.

[0145] The driving element DT may include a third active layer ACT3 and third-first contact portions CT3_1 and third-second contact portions CT3_2 on opposite sides of the third active layer ACT3. The gate electrode GL of the driving element DT may be connected to the first active layer ACT1 of the first switching element T1. The driving element DT may be connected to the driving voltage connection pattern EVDD_1 via the third-first contact portion CT3_1, and to the second active layer ACT2 of the second switching element T2 via the third-second contact portion CT3_2. Here, the third-first contact portion CT3_1 and the third-second contact portion CT3_2 may include corresponding electrodes for connecting to the driving voltage connection pattern EVDD_1 and the second active layer ACT2 of the second switching element T2.

[0146] Furthermore, the driving element DT can drive the light-emitting element by connecting it to the anode electrode of the light-emitting element via the third-second contact portion CT3_2. Here, the third-second contact portion CT3_2 may include an electrode for connecting to the anode electrode of the light-emitting element.

[0147] Furthermore, the first gate line GL1 can be formed to have multiple layers GL1_1 and GL1_2 in some regions. Additionally, the first gate line GL1 can branch at the points where it intersects with the drive voltage line VDDL, the first data line DL1, the second data line DL2, and the reference voltage line RL. The second gate line GL2 can have the same structure as the first gate line GL1, but is not limited thereto.

[0148] The first gate line GL1 may include a first layer GL1_1 and a second layer GL1_2. The first layer GL1_1 may be a gate line extending from a pad component. The second layer GL1_2 may be located in some areas where signal lines (e.g., DL1_1, DL2_1, RL_1, and RL_2) on a different layer than the first layer GL1_1 do not intersect. However, the structure of the first gate line GL1 and the second gate line GL2 is exemplary, and embodiments of this disclosure are not limited thereto.

[0149] Figure 6A This is a diagram illustrating defective wiring state 1 of the gate line according to an example implementation. Figure 6B This is a diagram illustrating defective wiring state 2 of the gate line according to an example implementation.

[0150] As described above, the first gate line GL1 may include a first layer GL1_1 and a second layer GL1_2. The gate line GL can be formed by thin film deposition and etching processes. During this process, if areas that should not be etched are etched (state 1) or if areas that should be etched are not etched (state 2), the gate line GL may become defective.

[0151] Figure 6A State 1 is illustrated, in which a defect occurs, thereby opening a portion of the first gate line GL1. For example, this portion of the first gate line GL1 is an area that should not be etched. A display panel according to an exemplary embodiment of this disclosure may include an open portion OP in any of the first gate lines GL1 having state 1. For example, state 1 may occur in a single-wire area, where the wiring is not configured as double-layered or the wiring has no branches. Therefore, the first gate line GL1 in state 1 may include an open portion OP in the first layer GL1_1. In particular, the open portion OP may be located in an area of ​​the first layer GL1_1 that does not overlap with the second layer GL1_2.

[0152] However, the state 1 described above is illustrative, and the embodiments of this disclosure are not limited thereto. For example, state 1 may appear in the second gate line GL2, and the open portion OP may appear anywhere in the gate line. In particular, the open portion OP may be located in the region of the second layer GL1_2 that does not overlap with the first layer GL1_1.

[0153] Figure 6B State 2 is illustrated, in which a defect occurs, causing a portion of the second gate line GL2 to be short-circuited to an adjacent signal line. A display panel according to an exemplary embodiment of this disclosure may include a short-circuited portion ST in either of the second gate lines GL2 when in state 2. For example, the second gate line GL2 in state 2 may include a short-circuited portion ST in the second layer GL2_2. For example, the short-circuited portion ST may be connected to a drive voltage line VDDL disposed adjacent to the second layer GL2_2 of the second gate line GL2. For example, the short-circuited portion ST may be connected to a reference voltage line RL disposed adjacent to the second layer GL2_2 of the second gate line GL2. However, state 2 described above is illustrative, and embodiments of this disclosure are not limited thereto.

[0154] Therefore, the display panel according to the example embodiment of this disclosure can perform repairs for states 1 and 2 as follows.

[0155] Here, when state 2 is repaired, a step of cutting the short-circuit portion ST can be added. With the short-circuit portion ST cut, an open-circuit portion OP can be formed in the second gate line GL2. Therefore, the repair process below will describe the repair of the open-circuit portion OP of the second gate line GL2.

[0156] Figure 7A This is a plan view of a display panel according to an exemplary embodiment of the present disclosure. Figure 7B This is a plan view illustrating the signal path of the repaired gate line according to an example implementation.

[0157] Reference Figure 7AThe display panel according to the example embodiment may include: a first driving voltage line VDDL (1) and a second driving voltage line VDDL (2) spaced apart from each other; pixels PXL (PXL1, PXL1', PXL2 and PXL2') between the first driving voltage line VDDL (1) and the second driving voltage line VDDL (2); a plurality of driving voltage connection patterns EVDD_1 configured to connect the first driving voltage line VDDL (1) and the second driving voltage line VDDL (1); and a plurality of gate lines GL (GL1 and GL2) intersecting the first driving voltage line VDDL (1) and the second driving voltage line VDDL (2). Here, the plurality of gate lines GL may include at least one gate line GL including an open circuit portion OP, and the plurality of driving voltage connection patterns EVDD_1 may include a repair pattern RPL separate from the first driving voltage line VDDL (1) and the second driving voltage line VDDL (2) to connect the two ends of at least one gate line disconnected by the open circuit portion OP.

[0158] Assuming that the display panel according to an exemplary embodiment of this disclosure includes an open-circuit portion OP in the second gate line GL2 of a plurality of gate lines GL1 and GL2, but is not limited thereto. For example, the open-circuit portion OP may overlap with a branch line DL3_3 of the third data line DL3 and a branch line RL_3 of the reference voltage line RL. Alternatively, the open-circuit portion OP may also be included in the first gate line GL1 of the plurality of gate lines GL1, GL2.

[0159] The repair method according to the example embodiment can be performed for each drive voltage connection pattern EVDD_1. A display panel according to the example embodiment of this disclosure can repair a defective second gate line GL2 such that the repair pattern RPL, separate from the first drive voltage line VDDL (1) and the second drive voltage line VDDL (2), connects the two ends of the second gate line GL2, which is disconnected by the open circuit portion OP. As a result, the repaired second gate line GL2 allows the gate pulse to flow normally through the repair pattern RPL.

[0160] Therefore, the display panel of this disclosure can form drive voltage lines MVDDL in a grid pattern, including multiple drive voltage lines VDDL and multiple drive voltage connection patterns EVDD_1. Even if the repair pattern RPL is used in some areas, the grid-form drive voltage lines MVDDL can provide drive voltage to the entire display area.

[0161] Multiple driving voltage lines VDDL may include a first driving voltage line VDDL (1) and a second driving voltage line VDDL (2) arranged adjacent to each other, with a pixel PXL between them.

[0162] The first driving voltage line VDDL (1) and the second driving voltage line VDDL (2) may each include a first dummy driving voltage line DVDDL (1) and a second dummy driving voltage line DVDDL (2) separated by cut portions C3, C4, C5 and C6, respectively. That is, the first dummy driving voltage line DVDDL (1) and the second dummy driving voltage line DVDDL (2) can be manufactured by forming cut portions C3, C4, C5 and C6 in the first driving voltage line VDDL (1) and the second driving voltage line VDDL (2). The first dummy driving voltage line DVDDL (1) may be the region between the third cut portion C3 and the fourth cut portion C4. The second dummy driving voltage line DVDDL (2) may be the region between the fifth cut portion C5 and the sixth cut portion C6. The first dummy driving voltage line DVDDL (1) and the second dummy driving voltage line DVDDL (2) that are not supplied with driving voltage can be used to electrically connect the repair pattern RPL and the repair gate lines GL2 (1) and GL2 (2).

[0163] The first driving voltage line VDDL (1) and the second driving voltage line VDDL (2) may include a third cut portion C3, a fourth cut portion C4, a fifth cut portion C5, and a sixth cut portion C6. Therefore, the driving voltage can be blocked in the circuit portion of the area being repaired.

[0164] The third cut portion C3 and the fourth cut portion C4 can be formed in the first driving voltage line VDDL (1). For example, the first driving voltage line VDDL (1) may include a first dummy driving voltage line DVDDL (1) located between the third cut portion C3 and the fourth cut portion C4. The fifth cut portion C5 and the sixth cut portion C6 can be formed in the second driving voltage line VDDL (2). For example, the second driving voltage line VDDL (2) may include a second dummy driving voltage line DVDDL (2) located between the fifth cut portion C5 and the sixth cut portion C6. The third cut portion C3 to the sixth cut portion C6 may be located between the branches of the first gate line GL1 and the second gate line GL2. Therefore, the display panel according to the exemplary embodiment of this disclosure uses the branches of the gate lines as reference points during the cutting process, thereby facilitating cutting.

[0165] The first dummy drive voltage line DVDDL (1) can contact the overlapping portion on one side of the repair pattern RPL through the fifth contact portion, and can contact the first repair gate line GL2 (1) through the first connection portion WD1. The second dummy drive voltage line DVDDL (2) can contact the overlapping portion on the other side of the repair pattern RPL through the fifth contact portion, and can contact the second repair gate line GL2 (2) through the second connection portion WD2.

[0166] Multiple drive voltage connection patterns EVDDL_1 may include a repair pattern RPL that connects the two ends of a defective second gate line GL2 that is disconnected by an open-circuit portion OP. The repair pattern RPL may be disconnected from two adjacent connection lines EVDD_a in the horizontal direction X by a first cut portion C1 and a second cut portion C2. In other words, the repair pattern RPL may be defined by the first cut portion CT1 and the second cut portion CT2. The repair pattern RPL may include two adjacent overlapping portions EVDD_b and the connection line EVDD_a between them.

[0167] Multiple gate lines GL1 and GL2 may include at least one second gate line GL2 including an open portion OP. The second gate line GL2 including the open portion OP may include a dummy gate line DGL, which is disposed between the cutting portions C7, C8, C9 and C10 and includes the open portion OP, a first repair gate line GL2 (1) connected to the repair pattern RPL through a first connecting portion WD1, and a second repair gate line GL2 (2) connected to the repair pattern RPL through a second connecting portion WD2.

[0168] The dummy gate line DGL is separate from the first repair gate line GL2 (1) and the second repair gate line GL2 (2), and may include an open section OP. The dummy gate line DGL may be determined by the seventh cutting section C7 to the tenth cutting section C10.

[0169] The first repair gate line GL2 (1) and the second repair gate line GL2 (2) may each have a first connection portion WD1 and a second connection portion WD2 in the regions that overlap with the two adjacent dummy drive voltage lines DVDDL (1) and DVDDL (2), respectively. The second gate line GL2 may be electrically connected to the repair pattern RPL through the first connection portion WD1 and the second connection portion WD2.

[0170] In the first connection portion WD1, the first repair gate line GL2 (1) and the first dummy drive voltage line DVDDL (1) disposed on different layers can contact each other. In the second connection portion WD2, the second repair gate line GL2 (2) and the second dummy drive voltage line DVDDL (2) disposed on different layers can contact each other. Each repair gate line GL2 (1) and GL2 (2) and a corresponding dummy drive voltage line among the dummy drive voltage lines DVDDL (1) and DVDDL (2) can be contacted by laser welding one of them. However, the method of contacting each repair gate line GL2 (1) and GL2 (2) with a corresponding dummy drive voltage line among the dummy drive voltage lines DVDDL (1) and DVDDL (2) is illustrative, and the display panel according to the exemplary embodiment of this disclosure is not limited thereto.

[0171] For example, the first connection portion WD1 may be located at the intersection of the first repair gate line GL2 (1) and the first dummy drive voltage line DVDDL (1), and the second connection portion WD2 may be located at the intersection of the second repair gate line GL2 (2) and the second dummy drive voltage line DVDDL (2), but is not limited thereto.

[0172] The circuit section in the area being repaired may malfunction because it is not being supplied with a drive voltage. To prevent this, the circuit section in the area being repaired may include a cut-out portion of the drive voltage line VDDL and the second strobe line GL2.

[0173] The second gate line GL2 may further include a seventh cutting portion C7, an eighth cutting portion C8, a ninth cutting portion C9, and a tenth cutting portion C10. Therefore, the gate pulse can be blocked in the circuit portion of the region being repaired.

[0174] At least in the repaired area, the seventh to tenth cut portions C7 to C10 can also be located outside the signal line of the circuit portion to which the signal of the second gate line GL2 is supplied. For example, the seventh to tenth cut portions C10 can be located outside the third main circuit portion CA3' and the fourth main circuit portion CA4' to which the signal of the second gate line GL2 is supplied. For example, for different drive voltage lines VDDL in which the repair pattern is provided, the seventh to tenth cut portions C10 can be formed in the region of the second gate line GL2 adjacent to one of the drive voltage lines VDDL and in the region of the second gate line GL2 adjacent to the other drive voltage line VDDL.

[0175] However, the number and position of the cut portions in the display panel according to the exemplary embodiments of this disclosure are not limited to those illustrated and described. For example, the seventh cut portion C7 and the eighth cut portion C8 or the ninth cut portion C9 and the tenth cut portion C10 formed in the second gate line GL2 can be formed as a single cut portion.

[0176] In addition, to prevent malfunctions of the circuit section caused by supplying various signals to the area being repaired, a cutting section may be further included. The cutting section is used to disconnect the branch lines DL1_1, DL2_1, DL3_1, DL4_1 of the first data line DL1 to the fourth data line DL4 and the branch lines RL_1, RL_2, RL_3, RL_4 of the reference voltage line RL connected to the circuit sections CA1, CA2, CA3, CA4.

[0177] Reference Figure 7B The repaired second gating line GL2 can supply gating pulses along the first signal path SS. The first signal path SS can proceed sequentially along the first repaired gating line GL2 (1), the first dummy drive voltage line DVDDL (1), the repaired pattern RPL, the second dummy drive voltage line DVDDL (2), and the second repaired gating line GL2 (2).

[0178] Figures 8A to 8D This is a plan view illustrating the repair process according to an example implementation. Figures 9A to 9D This is a circuit diagram illustrating the repair process according to an example implementation. Figures 10A to 10C This is a cross-sectional view illustrating the repair process according to an example implementation.

[0179] Figures 9A to 9D They correspond to respectively Figures 8A to 8D The circuit diagram. Additionally... Figure 8A , Figure 8B , Figure 8C and Figure 8D Examples of the same as Figure 9A , Figure 9B , Figure 9C and Figure 9D The processing steps shown are the same as those shown. Figures 10A to 10C This is an example in Figure 8C , Figure 9C The cross-sectional view of the process in which the connecting parts WD1 and WD2 are formed in the process shown.

[0180] also, Figure 8C and Figure 9C The welding process can be carried out in Figure 8B and Figure 9B It is executed before the cutting process in the process.

[0181] Reference Figure 8A and Figure 9A The second gate line GL2 may include an open-circuit portion OP. The open-circuit portion OP may be located in the second gate line GL2 adjacent to the third main circuit portion CA3'. For example, the open-circuit portion OP may overlap with at least one of the branch line DL3_1 of the third data line DL3 and the branch line RL_3 of the reference voltage line RL.

[0182] Reference Figure 8B and Figure 9BThe first cutting portions C1 to the tenth cutting portions C10 can be formed by a cutting process. The first cutting portions C1 to the tenth cutting portions C10 can also be located outside the area being repaired. The first cutting portions C1 to the tenth cutting portions C10 can be formed by laser cutting portions of the corresponding signal lines. Therefore, the first cutting portions C1 to the tenth cutting portions C10 can prevent circuit failures caused by supplying various signals to the area being repaired.

[0183] The first cut portion C1 and the second cut portion C2 can be formed in the driving voltage connection pattern EVDD_1. Here, the driving voltage connection pattern EVDD_1 between the first cut portion C1 and the second cut portion C2 can become the repair pattern RPL.

[0184] The third cut portion C3 to the sixth cut portion C6 can be formed in the drive voltage line VDDL. A first dummy drive voltage line DVDDL (1) can be formed between the third cut portion C3 and the fourth cut portion C4, and a second dummy drive voltage line DVDDL (2) can be formed between the fifth cut portion C5 and the sixth cut portion C6. As a result, the drive voltage can be blocked in the area where the repair is performed. For example, the first drive voltage line VDDL (1) may include the first dummy drive voltage line DVDDL (1) formed between the third cut portion C3 and the fourth cut portion C4, and the second drive voltage line VDDL (2) may include the second dummy drive voltage line DVDDL (2) formed between the fifth cut portion C5 and the sixth cut portion C6.

[0185] The seventh cut portion C7 to the tenth cut portion C10 can be formed in the second gate line GL2. A dummy gate line DGL including the open-circuit portion OP can be formed between the seventh cut portion C7 and the eighth cut portion C8 and the ninth cut portion C9 and the tenth cut portion C10. For example, the second gate line GL2 including the open-circuit portion OP can include a dummy gate line DGL formed between the seventh cut portion C7 and the eighth cut portion C8 and the ninth cut portion C9 and the tenth cut portion C10. A first repair gate line GL2(1) overlapping with the first dummy drive voltage line DVDDL(1) and a second repair gate line GL2(2) overlapping with the second dummy drive voltage line DVDDL(2) can be formed. As a result, in the repaired region, the gate pulse can be blocked.

[0186] However, the number and position of the cut portions in the display panel according to the exemplary embodiments of this disclosure are not limited to those illustrated and described.

[0187] Reference Figure 8C and Figure 9CConnection portions WD1 and WD2 can be formed in the area where the repair gate lines GL2 (1) and GL2 (2) overlap with the dummy drive voltage lines DVDDL (1) and DVDDL (2) by a soldering process. The first connection portion WD1 can be formed in the area where the first repair gate line GL2 (1) overlaps with the first dummy drive voltage line DVDDL (1), and the second connection portion WD2 can be formed in the area where the second repair gate line GL2 (2) overlaps with the second dummy drive voltage line DVDDL (2). The first connection portion WD1 and the second connection portion WD2 can electrically connect the repair gate lines GL2 (1) and GL2 (2) to the repair pattern RPL via the dummy drive voltage lines DVDDL (1) and DVDDL (2).

[0188] In each of the first connection portion WD1 and the second connection portion WD2, the respective repair gate lines GL2(1) and GL2(2) disposed on different layers and the corresponding respective dummy drive voltage lines DVDDL(1) and DVDDL(2) can be contacted by soldering one of them. However, the method of contacting the respective repair gate lines GL2(1) and GL2(2) with the corresponding dummy drive voltage line among the dummy drive voltage lines DVDDL(1) and DVDDL(2) is illustrative, and the display panel according to the exemplary embodiment of this disclosure is not limited thereto. See also Figures 10A to 10C The method of forming the first connecting part WD1 and the second connecting part WD2 will be explained.

[0189] Reference Figure 10A The display panel according to an exemplary embodiment of the present disclosure may include a substrate 10, a driving voltage line 11 disposed on the substrate 10, a first insulating layer 20 configured to cover the driving voltage line 11, a second insulating layer 21 disposed on the first insulating layer 20, a second gate line 23 disposed on the second insulating layer 21, a third insulating layer 30 configured to cover the second gate line 23, and a fourth insulating layer 40 disposed on the third insulating layer 30.

[0190] For example, the driving voltage line 11 may be disposed on a portion of the substrate 10, and the second gate line 23 may be disposed on a portion of the second insulating layer 21. The first insulating layer 20 may be configured to cover the driving voltage line 11 and the portion of the substrate 10 exposed by the driven voltage line 11, and the third insulating layer 30 may be configured to cover the second gate line 23 and the portion of the second insulating layer 21 exposed by the second gate line 23, but is not limited thereto.

[0191] Reference Figure 10B The laser process can be performed by emitting a laser from below the substrate 10. The driving voltage line 11 can be welded using the laser process.

[0192] Reference Figure 10C The welded driving voltage line 11a can contact the second gate line 23. For example, the upper surface of the welded driving voltage line 11a can contact the lower surface of the second gate line 23. Here, the laser processing can be terminated when the welded driving voltage line 11a and the second gate line 23 contact (CTa). Here, a gap 11b can also be formed between the welded driving voltage line 11a and the substrate 10.

[0193] Reference Figure 8D and Figure 9D This forms a first connecting portion WD1 and a second connecting portion WD2, thereby supplying a gating pulse to the second gating line GL2 via the repair pattern RPL. Therefore, the first signal path SS that supplies the gating pulse to the second gating line GL2 can proceed sequentially along the first repair gating line GL2 (1), the first dummy drive voltage line DVDDL (1), the repair pattern RPL, the second dummy drive voltage line DVDDL (2), and the second repair gating line GL2 (2).

[0194] Figure 11 This is a plan view illustrating defective pixels according to an example implementation. Figure 12 This is a circuit diagram illustrating a defective pixel according to an example implementation. Figure 11 and Figure 12 This shows the state after the above-mentioned repair process has been performed.

[0195] Reference Figure 11 and Figure 12 According to an exemplary embodiment of the present disclosure, the display panel may include an open-circuit portion OP in any one of a plurality of first gating lines GL1 and second gating lines GL2, and may include a repair pattern RPL configured to repair the open-circuit portion OP.

[0196] When performing the repair process for the second gate line GL2, the third main circuit portion CA3' and the fourth main circuit portion CA4' of the second pixel PXL2, as well as the first main circuit portion CA1' and the second main circuit portion CA2' of the second main pixel PXL2', may not be supplied with normal signals. For example, the third sub-pixel SP3 and the fourth sub-pixel SP4 of the second pixel PXL2, as well as the first main sub-pixel SP1' and the second main sub-pixel SP2' of the second main pixel PXL2', may be in a non-operating state D.

[0197] On the other hand, normal signals can be supplied to the first main circuit portion CA1' and the second main circuit portion CA2' of the second pixel PXL2, as well as the third main circuit portion CA3' and the fourth main circuit portion CA4' of the second main pixel PXL2'. For example, the first sub-pixel SP1 and the second sub-pixel SP2 of the second pixel PXL2, as well as the third main sub-pixel SP3' and the fourth main sub-pixel SP4' of the second main pixel PXL2', can be in a normal state N.

[0198] Figure 13 This is a diagram that schematically illustrates a method for repairing defective pixels by copying data according to an example implementation.

[0199] Reference Figure 13 The display panel according to an exemplary embodiment of the present disclosure may include an anode electrode corresponding to each sub-pixel and a pixel repair component RP_P disposed in the circuit portion of each sub-pixel.

[0200] According to an exemplary embodiment of this disclosure, the anode electrode can be configured to correspond to each of the plurality of sub-pixels SP1, SP2, SP3, SP4, SP1', SP2', SP3', and SP4'. For example, the anode electrode corresponding to the third main sub-pixel SP3' may include a first anode electrode portion AND_1 overlapping with the third light-emitting component EA3', a second anode electrode portion AND_2 overlapping with the third main circuit portion CA3', and a third anode electrode portion AND_3 extending from the first anode electrode portion AND_1 to the third sub-pixel SP3. Here, the third anode electrode portion AND_3 of the third main sub-pixel SP3' may partially overlap with the pixel restoration component RP_P disposed in the third main circuit portion CA3' of the third sub-pixel SP3.

[0201] Figures 14A to 14C This is a plan view illustrating a pixel restoration process according to an example implementation. Figures 15A to 15C This is a circuit diagram illustrating a pixel restoration process according to an example implementation. Figures 16A to 16C This is a cross-sectional view illustrating a pixel restoration process according to an example implementation. Figures 14A to 14C Examples of the same as Figures 15A to 15C The same processing steps.

[0202] Reference Figure 14A and Figure 15A The third anode electrode portion AND_3 corresponding to the third main sub-pixel SP3' can overlap with the light-shielding layer LS disposed in the third main circuit portion CA3' of the third sub-pixel SP3. Here, the light-shielding layer LS includes a pixel repair component RP_P, so the pixel repair component RP_P can overlap with the third anode electrode portion AND_3.

[0203] Reference Figure 14B and Figure 15B The third connection portion WD3 can be formed in the pixel repair component RP_P. In the third connection portion WD3, the third anode electrode portion AND_3 of the third main sub-pixel SP3' and the light-shielding layer LS of the third sub-pixel SP3 can contact each other. For example, the third anode electrode portion AND_3 of the third main sub-pixel SP3' or the light-shielding layer LS of the third sub-pixel SP3 can be welded using a laser process, thereby allowing the third anode electrode portion AND_3 and the light-shielding layer LS to contact each other. (See reference...) Figures 16A to 16C The method for forming the third connecting part WD3 will be explained.

[0204] Reference Figure 16A A display panel according to an exemplary embodiment of the present disclosure may include a substrate 10, a light-shielding layer 111 disposed on the substrate 10, a first insulating layer 20 configured to cover the light-shielding layer 111, a third insulating layer 30 disposed on the first insulating layer 20, a fifth insulating layer 50 disposed on the third insulating layer 30, a third anode electrode portion 81 disposed between the first insulating layer 20 and the fifth insulating layer 50, an intermediate layer 83 disposed on the third anode electrode portion 81, and a cathode electrode 85 disposed on the fifth insulating layer 50. For example, the third anode electrode portion 81 may be disposed on the first insulating layer 20 and the third insulating layer 30, and the fifth insulating layer 50 may be disposed on the intermediate layer 83.

[0205] Here, the third anode electrode section 81 and Figure 14B and Figure 15B The third anode electrode portion AND_3 of the third primary sub-pixel SP3' shown is the same, and the light-shielding layer 111 is the same as... Figure 14B and Figure 15B The third sub-pixel SP3 shown has the same light-shielding layer LS.

[0206] Reference Figure 16B When a laser is emitted from below the substrate 10, a laser process can be performed. The light-shielding layer 111 can be welded using the laser process.

[0207] Reference Figure 16C The welded light-shielding layer 111a can contact the third anode electrode portion AND_3. For example, the upper surface of the welded light-shielding layer 111a can contact the lower surface of the third anode electrode portion. Here, the laser process can be terminated when the welded light-shielding layer 111a and the third anode electrode portion AND_3 make contact (CTb). Here, a gap 111b can also be formed between the welded light-shielding layer 111a and the substrate 10.

[0208] Reference Figure 14C and Figure 15CThe pixel driving data of the third main sub-pixel SP3' can be sent to the light-shielding layer LS of the third sub-pixel SP3 through the third connection portion WD3. Here, the light-shielding layer LS of the third sub-pixel SP3 can be electrically connected to the driving element that drives the third main light-emitting component EA3' of the third sub-pixel SP3 to emit light, and the driving element can be electrically connected to the second anode electrode portion AND_2 of the third sub-pixel SP3.

[0209] Therefore, the driving data of the third main sub-pixel SP3' copied to the light-shielding layer LS of the third sub-pixel SP3 can be sequentially provided to the second anode electrode portion AND_2 and the first anode electrode portion AND_1 of the third sub-pixel SP3. For example, the second signal path DS of the pixel driving data provided in the normal state Nr after repair can proceed sequentially along the third anode electrode portion AND_3 of the third main sub-pixel SP3', the light-shielding layer LS of the third sub-pixel SP3, the driving element of the third sub-pixel SP3, the second anode electrode portion AND_2 of the third sub-pixel SP3, and the first anode electrode portion AND_1 of the third sub-pixel SP3.

[0210] The aforementioned pixel repair processing can be performed on the first principal sub-pixel SP1', the second principal sub-pixel SP2', the third principal sub-pixel SP3', and the fourth principal sub-pixel SP4', which are in non-operational state D. For example, pixel repair processing on the first principal sub-pixel SP1' can be performed using the first sub-pixel SP1, pixel repair processing on the second principal sub-pixel SP2' can be performed using the second sub-pixel SP2, pixel repair processing on the third sub-pixel SP3' can be performed using the third principal sub-pixel SP3, and pixel repair processing on the fourth sub-pixel SP4' can be performed using the fourth principal sub-pixel SP4.

[0211] Therefore, a display panel according to an example embodiment of this disclosure can normalize defective pixels by copying data from adjacent pixels through a gate repair process.

[0212] Although exemplary embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and various modifications can be made without departing from the technical spirit of the present disclosure.

[0213] Therefore, the exemplary embodiments disclosed herein are not intended to limit the technical ideas of this disclosure, but are for illustrative purposes, and the scope of the technical ideas of this disclosure is not limited by these embodiments.

[0214] Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and not restrictive.

[0215] In general, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents conferred by these claims. Therefore, the claims are not limited by this disclosure.

[0216] Cross-references to related applications

[0217] This application claims priority and benefit to Korean Patent Application No. 10-2024-0198423, filed on December 27, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display panel, the display panel comprising: A first driving voltage line and a second driving voltage line, the first driving voltage line and the second driving voltage line being spaced apart from each other, and a pixel being present between the first driving voltage line and the second driving voltage line; Multiple drive voltage connection patterns are configured to connect the first drive voltage line and the second drive voltage line; as well as Multiple gate lines, which intersect the first driving voltage line and the second driving voltage line. The plurality of gate lines includes at least one gate line that includes an open-circuit portion, and The plurality of drive voltage connection patterns include a repair pattern configured to connect the two ends of the at least one gate line that is disconnected by the open portion.

2. The display panel of claim 1, wherein, Each of the plurality of driving voltage connection patterns includes: The overlapping portions respectively contact the first driving voltage line and the second driving voltage line; and A connecting line, configured to connect the overlapping portions, and The repair pattern includes the overlapping portion and the connecting line.

3. The display panel of claim 2, wherein, The first driving voltage line includes: The first cut section; and The first dummy driving voltage line is separated from the first driving voltage line by the first cutting portion. The second driving voltage line includes: The second cut section; and The second dummy driving voltage line is electrically separated from the second driving voltage line by the second cut portion, and... The overlapping portions of the repair pattern respectively contact the first dummy driving voltage line and the second dummy driving voltage line.

4. The display panel according to claim 3, wherein, The at least one gate line includes a first repair gate line and a second repair gate line, the first repair gate line and the second repair gate line being separated from each other by the open portion, and The first repair gate line and the second repair gate line are electrically connected to the overlapping portion of the repair pattern, respectively.

5. The display panel according to claim 4, wherein, The at least one gate line further includes a dummy gate line, which is separate from the first repair gate line and the second repair gate line and includes the open portion.

6. The display panel according to claim 4, further comprising: The first connection part is located at the intersection of the first repair gating line and the first dummy driving voltage line; as well as The second connection part is located at the intersection of the second repair gating line and the second dummy drive voltage line. The first repair gate line and the second repair gate line contact the first dummy drive voltage line and the second dummy drive voltage line at the first connection portion and the second connection portion, respectively.

7. The display panel according to claim 2, further comprising: A reference voltage line is disposed between the first driving voltage line and the second driving voltage line. The connecting line partially overlaps with the reference voltage line along its length.

8. The display panel according to claim 7, wherein, The connecting lines include a first connecting line and a second connecting line extending from their respective overlapping portions toward the reference voltage line, and a third connecting line disposed between the first connecting line and the second connecting line.

9. The display panel according to claim 8, wherein, The first connecting line and the second connecting line are configured not to overlap with the reference voltage line, and The third connecting line partially overlaps with the reference voltage line along the length direction of the reference voltage line.

10. The display panel according to claim 1, wherein, The pixel includes multiple pixels, and the multiple pixels include a first pixel and a second pixel. Each of the plurality of pixels includes a circuit portion, a light-emitting component, and at least one anode electrode. The anode electrode includes: The first anode electrode portion overlaps with the light-emitting component; The second anode electrode portion overlaps with the circuit portion by extending from the first anode electrode portion; and The third anode electrode portion extends from the first anode electrode portion and overlaps with the circuit portion of an adjacent pixel. The third anode electrode portion of the first pixel contacts the circuit portion of the second pixel via a third connection portion.

11. The display panel according to claim 10, wherein, The third connection portion is formed in the pixel restoration component, and The pixel repair component overlaps with the third anode electrode portion.

12. The display panel according to claim 1, wherein, The pixel includes multiple pixels, and the multiple pixels include a first pixel and a second pixel. Each of the plurality of pixels includes a plurality of sub-pixels configured to emit light of different colors, and Subpixels in the first and second pixels that are configured to emit light of the same color are provided with the same data signal and different gating pulses.

13. The display panel according to claim 12, wherein, The first pixel includes: a first sub-pixel including a first circuit portion, a second sub-pixel including a second circuit portion, a third sub-pixel including a third circuit portion, and a fourth sub-pixel including a fourth circuit portion. The second pixel includes: a first sub-pixel including a first main circuit portion, a second sub-pixel including a second main circuit portion, a third sub-pixel including a third main circuit portion, and a fourth sub-pixel including a fourth main circuit portion. The plurality of gate lines include a first gate line and a second gate line, wherein the first gate line provides signals to the third circuit section and the fourth circuit section, the first main circuit section and the second main circuit section, and the second gate line provides signals to the first circuit section and the second circuit section, the third main circuit section and the fourth main circuit section.

14. The display panel according to claim 13, wherein, The first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, the third sub-pixel is a white sub-pixel, and the fourth sub-pixel is a blue sub-pixel.

15. A method for repairing a display panel, the method comprising the following steps: A first operation forms a first driving voltage line and a second driving voltage line, and a plurality of driving voltage connection patterns configured to connect the first driving voltage line and the second driving voltage line, wherein the first driving voltage line and the second driving voltage line are spaced apart from each other and there are pixels between the first driving voltage line and the second driving voltage line. A second operation is performed to form a plurality of gate lines that intersect the first drive voltage line and the second drive voltage line, the plurality of gate lines including at least one gate line that includes an open portion; as well as A third operation involves separating at least one of the plurality of drive voltage connection patterns from the first drive voltage line and the second drive voltage line, thereby forming a repair pattern configured to connect the two ends of the at least one gate line that is disconnected by the open portion.

16. The method of claim 15, wherein, The third operation includes a third-first operation, wherein the third-first operation forms a first cutting portion and a second cutting portion in the first driving voltage line and the second driving voltage line, respectively, and In the third-first operation, A first dummy driving voltage line is formed, separate from the first driving voltage line between the first cut portion, and A second dummy driving voltage line is formed, separate from the second driving voltage line between the second cut portion.

17. The method according to claim 16, wherein, The repair pattern contacts each of the first dummy driving voltage line and the second dummy driving voltage line. The at least one gate line overlaps with the first dummy drive voltage line and the second dummy drive voltage line on opposite sides, wherein the open-circuit portion is between the opposite sides, and The third operation includes a third-second operation, wherein the third-second operation forms a connection portion in the region where the at least one gate line overlaps with the first dummy drive voltage line and the second dummy drive voltage line.

18. The method of claim 17, wherein, In the third-second operation, the at least one gate line contacts the first dummy drive voltage line and the second dummy drive voltage line at the corresponding connection portion.

19. A display panel, the display panel comprising: A first driving voltage line and a second driving voltage line, the first driving voltage line and the second driving voltage line being spaced apart from each other, and at least one pixel being between the first driving voltage line and the second driving voltage line; Multiple driving voltage connection patterns are configured to connect the first driving voltage line and the second driving voltage line; as well as Multiple gate lines that intersect the first driving voltage line and the second driving voltage line, The number of gate lines between any two adjacent drive voltage connection patterns in the plurality of drive voltage connection patterns is 2 or less.

Images