Four-input differential comparator and signal loss detection apparatus

Abstract

This invention proposes a four-input differential comparator and a signal loss detection device, relating to the field of integrated circuit technology. The four-input differential comparator includes a load module and a multi-input differential pair circuit. The multi-input differential pair circuit includes a first differential pair and a second differential pair. Transistors in the first and second differential pairs are cross-coupled to form a first current superposition path and a second current superposition path. The bias currents of each transistor in the first and second differential pairs are the same. The load module then converts the first node current of the first current superposition path and the second node current of the second current superposition path into high / low level signals, thereby determining the magnitude between the input differential voltage corresponding to the input signal and the reference differential voltage corresponding to the reference signal. Based on this, this application can improve the technical problems of complex comparator circuit structure, high power consumption, and slow response speed in the prior art, and improve the accuracy of comparator decision-making.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a four-input differential comparator and a signal loss detection device. Background Technology

[0002] With the continuous evolution of integrated circuit technology, comparators, as a key fundamental module in analog and mixed-signal systems, are widely used in scenarios such as analog-to-digital converters (ADCs), phase-locked loops (PLLs), power management, sensor interfaces, and high-speed data sampling. In traditional designs, comparators often adopt a dual-input structure, that is, directly comparing a pair of differential input voltages (such as Vinp and Vinn), determining their relative magnitude, and outputting a logic level. This type of comparator has a mature structure, compact layout, controllable power consumption, and good matching and stability under process variations.

[0003] While this implementation architecture is clearly traceable in principle and can reuse mature operational amplifier libraries, making it feasible to some extent in discrete circuits or low-integration scenarios, in standard CMOS integrated circuit implementations, this approach relies on multiple high-precision matching resistors and multiple high-gain, wide-bandwidth operational amplifiers working together. This significantly increases the circuit size, quiescent current, layout area, and sensitivity to process mismatch, making it difficult to balance multiple constraints such as high integration, low power consumption, high-speed response, and high-precision decision-making in terms of overall performance. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a four-input differential comparator and a signal loss detection device, which can improve the technical problems of complex comparator circuit structure, high power consumption and slow response speed in the prior art, and improve the accuracy of comparator decision.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, the present invention provides a four-input differential comparator, the four-input differential comparator comprising: The load module and the multi-input differential pair circuit include a first differential pair and a second differential pair. The transistors under the first differential pair and the transistors under the second differential pair are cross-coupled to form a first current superposition path and a second current superposition path. The bias current of each transistor under the first differential pair and the transistors under the second differential pair is the same. The output terminals of the first current superposition path and the second current superposition path are also connected to the input terminal of the load module; the input terminal of the first differential pair is used to receive the first component of the input signal and the first component of the reference signal; the input terminal of the second differential pair is used to receive the second component of the input signal and the second component of the reference signal. The load module is used to convert the first node current of the first current superposition path and the second node current of the second current superposition path into high / low level signals to determine the magnitude between the input differential voltage corresponding to the input signal and the reference differential voltage corresponding to the reference signal.

[0006] Optionally, the first differential pair includes a first transistor group and a second transistor group; the second differential pair includes a third transistor group and a fourth transistor group; the control terminal of the first transistor group is used to connect to a positive input signal, the control terminal of the second transistor group is used to connect to a positive reference signal, the control terminal of the third transistor group is used to connect to a negative input signal, and the control terminal of the fourth transistor group is used to connect to a negative reference signal; the first terminal of the first transistor group is connected to the first terminal of the fourth transistor group; the first terminal of the second transistor group is connected to the first terminal of the third transistor group; the second terminal of the first transistor group is connected to the second terminal of the second transistor group; and the second terminal of the third transistor group is connected to the second terminal of the fourth transistor group. Among them, the first transistor group and the fourth transistor group form the first current superposition path; the second transistor group and the third transistor group form the second current superposition path; The number of transistors in the first transistor group is the same as the number of transistors in the third transistor group, and the number of transistors in the second transistor group is the same as the number of transistors in the fourth transistor group.

[0007] Optionally, the formula for calculating the first node current of the first current superposition path is expressed as:

[0008] The formula for calculating the second node current in the second current superposition path is as follows:

[0009] In the formula, This is the current at the first node; This refers to the current at the second node. This is the positive input current of the transistors in the first transistor group; This is the positive reference current for the transistors in the second transistor group; This is the negative input current of the transistors in the third transistor group; This is the negative reference current for the transistors in the fourth transistor group.

[0010] Optionally, when the first transistor group includes one transistor, the second transistor group includes multiple transistors, the third transistor group includes one transistor, and the fourth transistor group includes multiple transistors, all transistors in the second transistor group are connected in parallel, and all transistors in the fourth transistor group are connected in parallel; the control terminal of each transistor in the second transistor group receives a component of a positive reference signal; and the control terminal of each transistor in the fourth transistor group receives a component of a negative reference signal. The formula for calculating the current at the first node of the first current superposition path is as follows:

[0011] The formula for calculating the second node current in the second current superposition path is as follows:

[0012] In the formula, This is the current at the first node; This refers to the current at the second node. This is the positive input current of the transistors in the first transistor group; This is the positive reference current for the first transistor in the second transistor group; For the second transistor group N The positive reference current of each transistor; The negative input current of the third transistor group; This is the negative reference current for the first transistor in the fourth transistor group; For the fourth transistor group N The negative reference current of each transistor.

[0013] Optionally, the four-input differential comparator further includes a common-mode lock-in circuit, which includes a common-mode extraction module and a reference signal load module. The output of the common-mode extraction module is connected to the input of the reference signal load module, the output of the reference signal load module is connected to the input of the second differential pair, and the input of the reference signal load module is also used to receive the initial reference signal. The common-mode extraction module is used to receive AC input signals and extract real-time common-mode signals from the AC input signals; The reference signal load module is used to superimpose the real-time common-mode signal onto the initial reference signal to obtain the reference signal.

[0014] Optionally, the reference signal load module includes a first common-mode conversion unit, a current mirror, and a second common-mode conversion unit; the input terminal of the first common-mode conversion unit is connected to the output terminal of the common-mode extraction module, and the output terminal of the first common-mode conversion unit is connected to the input terminal of the current mirror; the output terminal of the current mirror is connected to the input terminal of the second common-mode conversion unit; the input terminal of the second common-mode conversion unit is also used to receive the initial reference signal. The first common-mode conversion unit is used to convert real-time common-mode signals into current signals; The current mirror is used to copy the current signal to the second common-mode conversion unit to generate a mirrored current signal; The second common-mode conversion unit is used to convert the mirror current signal into a reference common-mode level and superimpose the reference common-mode level onto the initial reference signal to obtain the reference signal.

[0015] Optionally, the common-mode extraction module includes a first resistor unit and a second resistor unit. The input terminal of the first resistor unit is used to receive the AC negative terminal signal; the input terminal of the second resistor unit is used to receive the AC positive terminal signal; and the output terminals of both the first resistor unit and the second resistor unit are connected to the input terminal of the reference signal load module.

[0016] Optionally, the four-input differential comparator further includes: a peak detection module, the output of which is connected to the input of the first differential pair; The peak detection module is used to receive AC input signals and obtain the upper peak value and lower peak value of the AC input signals, which are used as positive input signals and negative input signals, respectively.

[0017] Optionally, when the load module includes a current load structure, the load module includes a first transistor and a second transistor, the second terminal of the first transistor is connected to the second terminal of the second transistor, the control terminal of the first transistor is connected to the control terminal of the second transistor, the first terminal of the first transistor and the output terminal of the first current superposition path, and the first terminal of the second transistor is connected to the output terminal of the second current superposition path.

[0018] In a second aspect, the present invention also provides a signal loss detection device, comprising a four-input differential comparator according to any one of the first aspects described above.

[0019] The four-input differential comparator and signal loss detection device provided in this embodiment of the invention have the following beneficial effects: This four-input differential comparator includes a load module and a multi-input differential pair circuit. The multi-input differential pair circuit includes a first differential pair and a second differential pair. The transistors in the first differential pair and the second differential pair are cross-coupled to form a first current superposition path and a second current superposition path. The bias currents of each transistor in the first differential pair and the second differential pair are the same, so that the load module can quickly convert the first node current of the first current superposition path and the second node current of the second current superposition path into high / low level signals to determine the magnitude between the input differential voltage corresponding to the input signal and the reference differential voltage corresponding to the reference signal. This overcomes the obvious bottlenecks in the existing comparator implementation schemes, especially comparators based on cascaded discrete differential subtractors, in terms of integration, speed, power consumption, accuracy, and anti-interference.

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This shows one of the structural schematic diagrams of a four-input differential comparator provided in an embodiment of the present invention; Figure 2 A schematic diagram of the structure of the multi-input differential pair circuit provided in an embodiment of the present invention is shown; Figure 3 The circuit schematic of the multi-input differential pair circuit provided in the embodiment of the present invention is shown; Figure 4 This shows one of the circuit schematics of a four-input differential comparator provided in an embodiment of the present invention; Figure 5 The second circuit schematic diagram of the four-input differential comparator provided in this embodiment of the invention is shown. Figure 6 This is a second schematic diagram of the structure of a four-input differential comparator provided in an embodiment of the present invention; Figure 7 A schematic diagram of the common mode extraction module provided in an embodiment of the present invention is shown; Figure 8 A schematic diagram of the structure of the reference signal load module provided in an embodiment of the present invention is shown; Figure 9A circuit schematic diagram of a reference signal load module provided in an embodiment of the present invention is shown; Figure 10 The third schematic diagram of the structure of the four-input differential comparator provided in this embodiment of the invention is shown; Figure 11 The experimental results of the four-input differential comparator provided in the embodiment of the present invention are shown in the figure.

[0023] Icons: 10-Four-input differential comparator; 101-Load module; 102-Multi-input differential pair circuit; 103-Common-mode lockout circuit; 104-Peak detection module; 201-First differential pair; 202-Second differential pair; 203-Common-mode extraction module; 204-Reference signal load module; 301-First transistor group; 302-Second transistor group; 303-Third transistor group; 304-Fourth transistor group; 305-First resistor unit; 306-Second resistor unit; 307-First common-mode conversion unit; 308-Current mirror; 309-Second common-mode conversion unit; M1 M1 - First transistor; M2 - Second transistor; M3 - Third transistor; M4 - Fourth transistor; M5 - Fifth transistor; M6 - Sixth transistor; M7 - Seventh transistor; M8 - Eighth transistor; M9 - Ninth transistor; M10 - Tenth transistor; M11 - Eleventh transistor; M12 - Twelfth transistor; M13 - Thirteenth transistor; BUF - Buffer; OP - Operational amplifier; R1 - First resistor; R2 - Second resistor; Vinp - Positive input signal; Vinn - Negative input signal; Vrefp - Positive reference signal; Vrefn - Negative reference signal. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0026] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0027] According to the inventors' research, existing four-input comparators, especially those based on cascaded discrete differential subtractors, specifically employ an architecture of cascaded operational amplifiers and single-ended comparators (the outputs of the two operational amplifiers are connected to the two inputs of the single-ended comparator, respectively). The single-ended comparator then compares the voltage difference between the outputs of the two operational amplifiers. While the principle is clear, this approach suffers from significant bottlenecks in practical integrated circuit design and applications, particularly in terms of integration density, speed, power consumption, accuracy, and interference immunity.

[0028] Based on this, this application provides a comparator improvement scheme to overcome the above-mentioned technical problems.

[0029] Please refer to Figure 1 , Figure 1 A schematic diagram of a four-input differential comparator 10 provided in an embodiment of the present invention is shown. The four-input differential comparator 10 includes a load module 101 and a multi-input differential pair circuit 102. The multi-input differential pair circuit 102 includes a first differential pair 201 and a second differential pair 202. The transistors in the first differential pair 201 and the second differential pair 202 are cross-coupled to form a first current superposition path and a second current superposition path; and the bias current of each transistor in the first differential pair 201 and the second differential pair 202 is the same.

[0030] In this invention, the output terminals of the first current superposition path and the second current superposition path are also connected to the input terminal of the load module 101; the input terminal of the first differential pair 201 is used to receive the first component of the input signal and the first component of the reference signal; the input terminal of the second differential pair 202 is used to receive the second component of the input signal and the second component of the reference signal.

[0031] In one possible implementation, the first component of this embodiment corresponds to the positive terminal of the signal, and the second component corresponds to the negative terminal of the signal. Based on this, in this embodiment, the input terminal of the first differential pair 201 is connected to the positive terminal of the input signal (receiving the positive input signal described below) and the positive terminal of the reference signal (receiving the positive reference signal described below); the input terminal of the second differential pair 202 is connected to the negative terminal of the input signal (receiving the negative input signal described below) and the negative terminal of the reference signal (receiving the negative reference signal described below).

[0032] In this invention, the load module 101 is used to convert the first node current of the first current superposition path and the second node current of the second current superposition path into high / low level signals to determine the magnitude between the input differential voltage corresponding to the input signal and the reference differential voltage corresponding to the reference signal.

[0033] Based on this, in the multi-input differential pair circuit of this invention, the first differential pair and the second differential pair are cross-coupled to form two current superposition paths, so as to receive the current superposition value of each differential pair under the action of the input signal and the reference signal, that is, the first node current and the second node current mentioned above. Then, the load module is used to convert the first node current and the second node current into high / low level signals to determine the magnitude between the input differential voltage corresponding to the input signal and the reference differential voltage corresponding to the reference signal. Thus, while reducing the circuit structure, the bottlenecks in speed, power consumption, accuracy and anti-interference of the comparator implementation scheme in the prior art are overcome.

[0034] In this embodiment, the input differential voltage Vout1 corresponding to the input signal can be understood as the difference between the positive input signal Vinp and the negative input signal Vinn, that is, it is represented as: Vout1 = (Vinp - Vinn).

[0035] Similarly, the reference differential voltage Vout2 corresponding to the reference signal can be understood as the difference between the positive reference signal Vrefp and the negative reference signal Vrefn, that is, it is represented as: Vout2 = (Vrefp - Vrefn).

[0036] In this embodiment, the four-input differential comparator can map the unbalanced current of the input differential voltage Vout1 and the reference differential voltage Vout2 based on the output of the multi-input differential pair circuit in its cross-coupled state. Then, based on the load module, the balanced current is directly converted into a high-level signal or a low-level signal, thereby obtaining the decision result of the input differential voltage Vout1 and the reference differential voltage Vout2.

[0037] It should be noted that, in order to further improve the accuracy of the four-input differential comparator in this embodiment, in addition to ensuring that the bias current of each transistor in the first differential pair and the transistor in the second differential pair is the same, they can also be selected as transistors of the same specification, such as transistors of the same process and size. This makes the transconductance of each transistor the same under the same bias current, so that the accuracy of the four-input differential comparator does not depend on resistor matching, thus ensuring the high accuracy of the four-input differential comparator.

[0038] Therefore, in this embodiment, the four-input differential comparator uses differential inputs at both the input and reference terminals, and the common-mode noise in the current superposition path is synchronously canceled at the crossover point. Compared with the traditional single-ended structure, the four-input differential comparator in this embodiment has better noise immunity, especially in harsh noise environments.

[0039] This embodiment does not limit the structural composition of the differential pair in a multi-input differential pair circuit. For one possible implementation, please refer to... Figure 2 , Figure 2 The diagram shows a schematic of the structure of a multi-input differential pair circuit provided in an embodiment of the present invention. In this embodiment, the first differential pair includes a first transistor group 301 and a second transistor group 302; the second differential pair includes a third transistor group 303 and a fourth transistor group 304.

[0040] In this embodiment, the control terminal of the first transistor group 301 is used to connect to the positive input signal Vinp, the control terminal of the second transistor group 302 is used to connect to the positive reference signal Vrefp, the control terminal of the third transistor group 303 is used to connect to the negative input signal Vinn, and the control terminal of the fourth transistor group 304 is used to connect to the negative reference signal Vrefn. The first terminal of the first transistor group 301 is connected to the first terminal of the fourth transistor group 304; the first terminal of the second transistor group 302 is connected to the first terminal of the third transistor group 303; the second terminal of the first transistor group 301 is connected to the second terminal of the second transistor group 302; and the second terminal of the third transistor group 303 is connected to the second terminal of the fourth transistor group 304.

[0041] In this embodiment, when the first terminal of each transistor group is the drain, the second terminal is the source.

[0042] It should be noted that in this embodiment, the first transistor group 301 and the fourth transistor group 304 constitute a first current superposition path; the second transistor group 302 and the third transistor group 303 constitute a second current superposition path.

[0043] For details, please continue to refer to Figure 2In this embodiment, the first transistor group 301, the second transistor group 302, the third transistor group 303, and the fourth transistor group 304 are cross-connected. The first transistor group 301 and the fourth transistor group 304 are merged to the same current node. For example, the drain of the first transistor group is connected to the drain of the fourth transistor group to form a first current superposition path. Similarly, the second transistor group 302 and the third transistor group 303 are merged to the same current node. For example, the drain of the second transistor group is connected to the drain of the third transistor group to form a second current superposition path.

[0044] Based on this, the calculation formula for the first node current of the first current superposition path in this embodiment is expressed as:

[0045] In this embodiment, the formula for calculating the second node current of the second current superposition path is expressed as follows:

[0046] In the formula, This is the current at the first node; This refers to the current at the second node. This is the positive input current of the transistors in the first transistor group; This is the positive reference current for the transistors in the second transistor group; This is the negative input current of the transistors in the third transistor group; This is the negative reference current for the transistors in the fourth transistor group.

[0047] With the positive input current of the transistor in the first transistor group For example, this can be understood as the drain current of the transistor in the first transistor group in this embodiment. Combined with the basic condition mentioned above that "under the same bias current, the corresponding transconductance is the same", at this time, the forward input current... It can be characterized as: ≈ gm × (Vinp Vbias), where Vbias is the bias voltage.

[0048] Correspondingly, the negative reference current of the transistor in the fourth transistor group The calculation formula can be expressed as: ≈ gm × (Vrefn Vbias).

[0049] Based on this, by superimposing the two currents mentioned above, the first node current can be obtained. In this embodiment, the first node current... In essence, it is the positive terminal node voltage.

[0050] Similarly, the forward reference current of the transistors in the second transistor group This can be expressed as: ≈ gm × (Vrefp Vbias); negative input current of the transistors in the third transistor group. It can be represented as: ≈ gm × (Vinn Vbias), then the forward reference current of the transistors in the second transistor group can be used. and the negative input current of the transistor in the third transistor group By superimposing these values, the current at the second node can be obtained. The second node current in this embodiment In essence, it is the negative terminal node voltage.

[0051] The above derivation clearly shows that it is only necessary to determine the current at the first node. Second node current By understanding the relationship between the input differential voltage Vout1 and the reference differential voltage Vout2, the magnitudes can be directly determined.

[0052] Based on this, this embodiment can directly use the above-mentioned cross-coupling structure-physical structure without any adders, subtractors or multipliers. It directly skips the existing technology's method of "first use a resistor network to perform subtraction → operational amplifier amplification → comparison". On the basis of simplifying the processing structure, it speeds up the processing efficiency, avoids all traditional errors such as resistor mismatch, operational amplifier offset, common-mode drift, etc., and improves the calculation accuracy.

[0053] It should be noted that this embodiment does not limit the number of transistors in each transistor group. Figure 2 The structure of each transistor group is only illustrative. When any one or more transistor groups include multiple transistors, the transistors in the current transistor group are connected in parallel. Furthermore, the number of transistors in the first transistor group is the same as the number of transistors in the third transistor group, and the number of transistors in the second transistor group is the same as the number of transistors in the fourth transistor group.

[0054] In one possible implementation method, please refer to Figure 3 , Figure 3 The circuit schematic diagram of the multi-input differential pair circuit provided in the embodiment of the present invention is shown. When the first transistor group 301 includes one transistor, the second transistor group 302 includes multiple transistors, the third transistor group 303 includes one transistor, and the fourth transistor group 304 includes multiple transistors; the transistors in the second transistor group 302 are connected in parallel, and the transistors in the fourth transistor group 304 are all connected in parallel.

[0055] Since the control terminal of the second transistor group in this embodiment is used to connect to the positive reference signal Vrefp and the control terminal of the fourth transistor group is used to connect to the negative reference signal Vrefn, the control terminals of each transistor in the second transistor group 302 in this embodiment receive a component of the positive reference signal Vrefp respectively; and the control terminals of each transistor in the fourth transistor group 304 receive a component of the negative reference signal Vrefn respectively.

[0056] The formula for calculating the current at the first node of the first current superposition path is as follows:

[0057] The formula for calculating the second node current in the second current superposition path is as follows:

[0058] In the formula, This is the current at the first node; This refers to the current at the second node. This is the positive input current of the transistor in the first transistor group 301; This is the positive reference current for the first transistor in the second transistor group 302; For the second transistor group 302, the first N The positive reference current of each transistor; This is the negative input current of the third transistor group 303; This is the negative reference current for the first transistor in the fourth transistor group 304; For the fourth transistor group 304, the lower N The negative reference current of each transistor.

[0059] Please note that you should continue to refer to [the relevant documentation / reference]. Figure 3 Taking each transistor in the fourth transistor group 304 as an example, the control terminal of each transistor in the current fourth transistor group 304 is used to receive a component of the negative reference signal Vrefn, namely Vrefn-1, ..., Vrefn-N. Correspondingly, the negative reference current corresponding to each transistor in the fourth transistor group 304 in this embodiment can be understood as: the current of the component of the negative reference signal Vrefn corresponding to the current transistor.

[0060] Similarly, the control terminals of each transistor in the second transistor group 302 are used to receive a component of the positive reference signal Vrefp, namely Vrefp-1, ..., Vrefp-N. In this embodiment, the positive reference current corresponding to each transistor in the second transistor group 302 can be understood as the current of the component of the positive reference signal Vrefp corresponding to the current transistor.

[0061] Based on this, the first node current Second node current The formula for the difference can be simplified as follows: .

[0062] Meanwhile, since the bias currents of each transistor in the first differential pair and each transistor in the second differential pair are the same, that is, each transistor has the same transconductance.

[0063] Based on this, the aforementioned first node current Second node current The numerical relationship can be summarized as a comparison between the sum of the voltage differences of each transistor in the current second transistor group 302 and fourth transistor group 304 and the input differential voltage Vout1.

[0064] It should be noted that this embodiment does not limit the specific values ​​of the components corresponding to each transistor, nor does it limit the magnitudes of the positive reference signal Vrefp and / or the negative reference signal Vrefn and / or the negative input signal Vinn and / or the positive input signal Vinp. The first node current to be determined... Second node current Subsequently, in this embodiment, a high / low level can be directly output based on the load module.

[0065] In this embodiment, the load module is essentially a current-to-voltage conversion module, and its working principle can be understood as follows: due to the current at the first node in this embodiment... Second node current Essentially, it refers to the positive and negative node voltages. Based on the properties of the current-to-voltage conversion module, it can output corresponding level signals. When the first node current Ip is greater than the second node current In, the load module outputs a high level; otherwise, it outputs a low level.

[0066] It should be noted that, in one possible implementation, the load module in this embodiment may include a current load structure or a folded cascode load.

[0067] Please refer to Figure 4 , Figure 4 The circuit schematic of the four-input differential comparator provided in the embodiment of the present invention is shown. When the load module 101 includes a current load structure, the load module 101 includes a first transistor M1 and a second transistor M2. The second terminal of the first transistor M1 is connected to the second terminal of the second transistor M2. The control terminal of the first transistor M1 is connected to the control terminal of the second transistor M2, the first terminal of the first transistor M1, and the output terminal of the first current superposition path. The first terminal of the second transistor M2 is connected to the output terminal of the second current superposition path.

[0068] Please continue to refer to this. Figure 1 In this embodiment, the four-input differential comparator 10 further includes a third transistor M3 and a fourth transistor M4. The gates of the third transistor M3 and the fourth transistor M4 both receive a bias voltage Vbias. The sources of the third transistor M3 and the fourth transistor M4 are both grounded. The drain of the third transistor M3 is connected to the second terminals of the first transistor group 301 and the second transistor group 302. The drain of the fourth transistor M4 is connected to the second terminals of the third transistor group 303 and the fourth transistor group 304.

[0069] Please refer to Figure 5 , Figure 5 This diagram illustrates another circuit schematic of the four-input differential comparator provided in an embodiment of the present invention. When the load module 101 includes a folded cascode load, the load module 101 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a buffer BUF. Furthermore, the four-input differential comparator 10 also includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. The connection relationships between the fifth transistor M5 to the twelfth transistor M12 and the buffer BUF are not detailed here but can be directly referred to... Figure 5 Connection diagram.

[0070] Based on this, the present invention replaces the complex arithmetic unit with the input stage of a four-transistor-group comparator circuit, simplifying the structure and greatly saving area, while also freeing accuracy from the limitations of resistor matching. Furthermore, in this embodiment, the differential pairs use the same bias current, which significantly improves the common-mode rejection ratio and effectively reduces common-mode noise. Simultaneously, the four-input differential comparator in this embodiment can complete the comparison of two pairs of differences in a single stage, resulting in faster overall response speed and lower power consumption.

[0071] To further improve the output accuracy of the four-input differential comparator, please refer to... Figure 6 , Figure 6 This diagram illustrates another structural schematic of a four-input differential comparator provided in an embodiment of the present invention. The four-input differential comparator 10 further includes a common-mode lock-in circuit 103, which includes a common-mode extraction module 203 and a reference signal load module 204.

[0072] In this embodiment, the output terminal of the common mode extraction module 203 is connected to the input terminal of the reference signal load module 204, the output terminal of the reference signal load module 204 is connected to the input terminal of the second differential pair 202, and the input terminal of the reference signal load module 204 is also used to receive the initial reference signal.

[0073] Common mode extraction module 203 is used to receive AC input signals and extract real-time common mode signals from AC input signals; The reference signal load module 204 is also used to superimpose the real-time common-mode signal onto the initial reference signal to obtain the reference signal.

[0074] The common-mode lockout circuit 103 works as follows: the common-mode signal Vcm of the AC input signal is obtained through the common-mode extraction module 203, and then this common-mode signal Vcm is superimposed on the initial reference signals (Vrefp1 and Vrefn1) through the reference signal load module 204. When the common-mode of the input signal changes, the obtained common-mode point will also move accordingly, and thus the reference signal will also change.

[0075] This embodiment does not limit the specific structure of the common-mode extraction module 203. In one possible implementation, the common-mode extraction module 203 may include multiple resistors. For details, please refer to... Figure 7 , Figure 7 A schematic diagram of the common-mode extraction module provided in an embodiment of the present invention is shown. The common-mode extraction module 203 includes a first resistor unit 305 and a second resistor unit 306. The input terminal of the first resistor unit 305 is used to receive the AC positive terminal signal Vp; the input terminal of the second resistor unit 306 is used to receive the AC negative terminal signal Vn; the output terminals of the first resistor unit 305 and the second resistor unit 306 are both connected to the input terminal of the reference signal load module 204.

[0076] In one possible implementation, the first resistor unit 305 and the second resistor unit 306 in this embodiment may include resistor devices. When any resistor unit includes multiple resistor devices, the resistor devices are connected in series.

[0077] Furthermore, since the transistors at the comparator signal terminal and the sampling terminal are at the same bias point, the common-mode lockout circuit provided in this embodiment can greatly reduce the false trigger rate and improve the reliability and stability of detection.

[0078] This embodiment does not limit the specific structure of the common mode extraction module. For one possible implementation, please refer to [reference needed]. Figure 8 , Figure 8 A schematic diagram of the structure of a reference signal load module provided in an embodiment of the present invention is shown. In this embodiment, the reference signal load module 204 includes a first common-mode conversion unit 307, a current mirror 308, and a second common-mode conversion unit 309. The input terminal of the first common-mode conversion unit 307 is connected to the output terminal of the common-mode extraction module 203, and the output terminal of the first common-mode conversion unit 307 is connected to the input terminal of the current mirror 308. The output terminal of the current mirror 308 is connected to the input terminal of the second common-mode conversion unit 309. The input terminal of the second common-mode conversion unit 309 is also used to receive the initial reference signal.

[0079] In this embodiment, the first common-mode conversion unit 307 is used to convert the real-time common-mode signal into a current signal.

[0080] The current mirror 308 is used to copy the current signal to the second common-mode conversion unit to generate a mirrored current signal.

[0081] The second common-mode conversion unit 309 is used to convert the mirror current signal into a reference common-mode level and superimpose the reference common-mode level onto the initial reference signal to obtain the reference signal.

[0082] Please refer to Figure 9 , Figure 9 The circuit diagram of the reference signal load module provided in this embodiment of the invention is shown. In this embodiment, the first common-mode conversion unit 307 includes an operational amplifier OP, a first resistor R1, and a thirteenth transistor M13; the second common-mode conversion unit 309 includes a second resistor R2; wherein, the first input terminal of the operational amplifier OP is used to receive the common-mode voltage Vcm, the second input terminal of the operational amplifier OP is connected to the first terminal of the first resistor R1 and the source of the thirteenth transistor M13; the second terminal of the first resistor R1 is grounded; the output terminal of the operational amplifier OP is connected to the control terminal of the thirteenth transistor M13; the drain of the thirteenth transistor M13 is connected to the first terminal of the current mirror 308; the second terminal of the current mirror 308 is connected to the first terminal of the second resistor R2, and the second terminal of the current mirror 308 is also used to receive the initial reference signals (Vrefp1 and Vrefn1); the second terminal of the second resistor R2 is grounded.

[0083] To further improve the output accuracy of the four-input differential comparator, please refer to... Figure 10 , Figure 10 This diagram illustrates another structural schematic of the four-input differential comparator provided in an embodiment of the present invention. In this embodiment, the four-input differential comparator 10 further includes a peak detection module 104, the output of which is connected to the input of the first differential pair 201.

[0084] The peak detection module 104 is used to receive the AC input signal and obtain the upper peak value and lower peak value of the AC input signal to determine the positive input signal and the negative input signal respectively.

[0085] In this embodiment, the envelope of the AC input signal is extracted by the peak detection module 104, that is, the upper peak value and lower peak value are obtained from the AC positive terminal signal Vp and the AC negative terminal signal Vn respectively, so as to obtain the positive input signal Vinp and the negative input signal Vinn.

[0086] It should be noted that this embodiment does not limit the structure of the peak detection module described above, as long as it can extract the envelope from the AC input signal.

[0087] Following the same approach as the previous embodiment, the present invention also provides a signal loss detection device, including a four-input differential comparator of any of the first aspects described above. This signal loss detection device overcomes the obvious bottlenecks in the comparator implementation schemes of the prior art, especially the comparators based on cascaded discrete differential subtractors, in terms of integration, speed, power consumption, accuracy, and anti-interference.

[0088] In this embodiment, the four-input differential comparator integrates difference calculation and comparison functions into a single pole, resulting in a short signal path and low parasitic capacitance. For details, please refer to [reference needed]. Figure 11 , Figure 11 The experimental results of the four-input differential comparator provided in this embodiment of the invention are shown in the figure. The figure illustrates the experimental results of three sets of PVT processes. The first PVT process, FFLTLV, is used to characterize experimental conditions of Fast process angle, low temperature, and low voltage, for example, high switching speed, temperature of -40°C, and voltage below the rated voltage VDD (0.9VDD). The second PVT process, SSHTHV, is used to characterize experimental conditions of Low process angle, high temperature, and high voltage, for example, low switching speed, temperature of 127°C, and voltage above the rated voltage VDD (1.1VDD). The third PVT process, TYPICAL, is used to characterize basic experimental conditions, for example, balanced switching speed, temperature of 27°C, and rated voltage VDD. The corresponding input signals and reference signals can be found in the figure as trans_vin and trans_vref. The experimental results show that even under the worst PVT conditions, the response time of the four-input differential comparator 10 is less than 183 ns.

[0089] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0090] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0091] If the functionality is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0092] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A four-input differential comparator, characterized in that, The four-input differential comparator includes: The load module and the multi-input differential pair circuit include a first differential pair and a second differential pair. The transistors under the first differential pair and the transistors under the second differential pair are cross-coupled to form a first current superposition path and a second current superposition path. The bias current of each transistor under the first differential pair and each transistor under the second differential pair is the same. The output terminals of the first current superposition path and the second current superposition path are also connected to the input terminal of the load module; the input terminal of the first differential pair is used to receive the first component of the input signal and the first component of the reference signal; the input terminal of the second differential pair is used to receive the second component of the input signal and the second component of the reference signal. The load module is used to convert the first node current of the first current superposition path and the second node current of the second current superposition path into high / low level signals to determine the magnitude between the input differential voltage corresponding to the input signal and the reference differential voltage corresponding to the reference signal.

2. The four-input differential comparator according to claim 1, characterized in that, The first differential pair includes a first transistor group and a second transistor group; the second differential pair includes a third transistor group and a fourth transistor group; the control terminal of the first transistor group is used to connect to a positive input signal, the control terminal of the second transistor group is used to connect to a positive reference signal, the control terminal of the third transistor group is used to connect to a negative input signal, and the control terminal of the fourth transistor group is used to connect to a negative reference signal; the first terminal of the first transistor group is connected to the first terminal of the fourth transistor group; the first terminal of the second transistor group is connected to the first terminal of the third transistor group; the second terminal of the first transistor group is connected to the second terminal of the second transistor group; and the second terminal of the third transistor group is connected to the second terminal of the fourth transistor group. Wherein, the first transistor group and the fourth transistor group form a first current superposition path; the second transistor group and the third transistor group form a second current superposition path; The number of transistors in the first transistor group is the same as the number of transistors in the third transistor group, and the number of transistors in the second transistor group is the same as the number of transistors in the fourth transistor group.

3. The four-input differential comparator according to claim 2, characterized in that, The formula for calculating the current at the first node of the first current superposition path is as follows: The formula for calculating the second node current in the second current superposition path is as follows: In the formula, This is the current at the first node; This refers to the current at the second node. This is the positive input current of the transistors in the first transistor group; This is the positive reference current of the transistors in the second transistor group; The negative input current of the transistor in the third transistor group; This is the negative reference current for the transistors in the fourth transistor group.

4. The four-input differential comparator according to claim 2 or 3, characterized in that, When the first transistor group includes one transistor, the second transistor group includes multiple transistors, the third transistor group includes one transistor, and the fourth transistor group includes multiple transistors, all transistors in the second transistor group are connected in parallel, and all transistors in the fourth transistor group are connected in parallel; the control terminal of each transistor in the second transistor group receives a component of a positive reference signal; and the control terminal of each transistor in the fourth transistor group receives a component of a negative reference signal. The formula for calculating the current at the first node of the first current superposition path is as follows: The formula for calculating the second node current in the second current superposition path is as follows: In the formula, This is the current at the first node; This refers to the current at the second node. This is the positive input current of the transistors in the first transistor group; This is the positive reference current of the first transistor in the second transistor group; For the second transistor group N The positive reference current of each transistor; This is the negative input current of the third transistor group; The negative reference current of the first transistor in the fourth transistor group; The fourth transistor group is the first N The negative reference current of each transistor.

5. The four-input differential comparator according to claim 1 or 2, characterized in that, The four-input differential comparator further includes a common-mode lock-in circuit, which includes a common-mode extraction module and a reference signal load module. The output of the common-mode extraction module is connected to the input of the reference signal load module, and the output of the reference signal load module is connected to the input of the second differential pair. The input of the reference signal load module is also used to receive an initial reference signal. The common-mode extraction module is used to receive AC input signals and extract real-time common-mode signals from the AC input signals; The reference signal load module is used to superimpose the real-time common-mode signal onto the initial reference signal to obtain the reference signal.

6. The four-input differential comparator according to claim 5, characterized in that, The reference signal load module includes a first common-mode conversion unit, a current mirror, and a second common-mode conversion unit; the input terminal of the first common-mode conversion unit is connected to the output terminal of the common-mode extraction module, and the output terminal of the first common-mode conversion unit is connected to the input terminal of the current mirror; the output terminal of the current mirror is connected to the input terminal of the second common-mode conversion unit; the input terminal of the second common-mode conversion unit is also used to receive the initial reference signal. The first common-mode conversion unit is used to convert the real-time common-mode signal into a current signal; The current mirror is used to copy the current signal to the second common-mode conversion unit to generate a mirrored current signal; The second common-mode conversion unit is used to convert the mirrored current signal into a reference common-mode level and superimpose the reference common-mode level onto the initial reference signal to obtain the reference signal.

7. The four-input differential comparator according to claim 5, characterized in that, The common-mode extraction module includes a first resistor unit and a second resistor unit. The input terminal of the first resistor unit is used to receive the AC negative terminal signal; the input terminal of the second resistor unit is used to receive the AC positive terminal signal; the output terminals of the first resistor unit and the second resistor unit are both connected to the input terminal of the reference signal load module.

8. The four-input differential comparator according to claim 1 or 2, characterized in that, The four-input differential comparator further includes a peak detection module, the output of which is connected to the input of the first differential pair. The peak detection module is used to receive the AC input signal and obtain the upper peak value and lower peak value of the AC input signal to determine the positive input signal and the negative input signal, respectively.

9. The four-input differential comparator according to claim 1, characterized in that, When the load module includes a current load structure, the load module includes a first transistor and a second transistor. The second terminal of the first transistor is connected to the second terminal of the second transistor. The control terminal of the first transistor is connected to the control terminal of the second transistor, the first terminal of the first transistor, and the output terminal of the first current superposition path. The first terminal of the second transistor is connected to the output terminal of the second current superposition path.

10. A signal loss detection device, characterized in that, Includes the four-input differential comparator as described in any one of claims 1 to 9.

Images