PRE-CHARGING MECHANISM FOR MULTI-INPUT CHARGING DEVICE
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
- Filing Date
- 2014-11-17
- Publication Date
- 2026-07-02
Abstract
Description
TECHNICAL AREA
[0001] The present description generally concerns power supplies or power adapters, and in particular, but not exclusively, a pre-charging mechanism for multi-input switching charging devices. BACKGROUND
[0002] Switching chargers can be a critical component of many devices, such as communication devices like DSL modems and wireless portable devices including mobile phones, tablets, phablets, laptops, and the like. For example, a mobile communication device might have multiple power inputs that can be connected via an external adapter, power mat, universal serial bus (USB) cable, or wireless power dongle. Consequently, the switching chargers must support multiple inputs, only one of which can be active at a time. Existing switching chargers can suffer from a number of shortcomings, particularly reliability issues, startup power consumption, safety concerns, and / or low efficiency.These deficiencies can be caused by a current surge through the circuits connected to the inactive input paths. BRIEF DESCRIPTION OF THE DRAWING
[0003] Certain features of the technology in question are specified in the attached patent claims. However, for the purpose of description, several embodiments of the technology in question are shown in the figures below.
[0004] Fig. Figure 1A illustrates an example of a multi-input switching charging circuit according to one or more implementations.
[0005] Fig. Figure 1B illustrates an exemplary expression of a number of signal waveforms of the multi-input switching charging circuit according to Fig. 1A according to one or more implementations.
[0006] Fig. Figure 2A illustrates an example of a multi-input switching charging circuit that uses a pre-charge switch according to one or more implementations.
[0007] Fig. Figure 2B illustrates an exemplary expression of a number of signal waveforms of the multi-input switching charging circuit according to Fig. 2A according to one or more implementations.
[0008] Fig. 2C illustrates an example of an implementation of a pre-charge switch of a multi-input switching charging circuit according to one or more implementations.
[0009] Fig. Figure 3 illustrates an example of a multi-input switching charging circuit that uses bulk interconnect switches according to one or more implementations.
[0010] Fig. Figure 4 illustrates exemplary expressions of a number of signal waveforms of the multi-input switching charging circuit according to Fig. 2A according to one or more implementations.
[0011] Fig. Figure 5 illustrates an example of a method for providing a multi-input switching charging circuit according to one or more implementations.
[0012] Fig. Figure 6 illustrates an example of a wireless communication device according to one or more implementations. DETAILED DESCRIPTION
[0013] The detailed description given below is intended as a description of various configurations of the technology in question and is not meant to represent the only configurations in which the technology in question can be implemented in practice. The accompanying drawing is included herein and forms part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the technology in question. However, it is clear and evident to a person skilled in the art that the technology in question is not limited to the specific details given herein and can be implemented in practice using one or more implementations.In one or more examples, generally known structures and components are shown in a block diagram form to avoid obscuring the concepts of the technology in question.
[0014] The technology presented here provides a method and implementation for precharging the isolation nodes of inactive inputs of a multi-input switching charging device. This precharging can be performed before initiating charging from a higher supply voltage. Precharging can prevent unwanted high currents flowing from the active input supply to one or more inactive paths, as described in more detail herein. The technology presented here can offer a number of advantageous features, including layout advantages, circuit advantages, system advantages, and product advantages. Layout advantages include increased metallization reliability and a reduction in metal size requirements for shorter current paths. Regarding circuit advantages, the reliability of the output switching devices can be significantly improved.At the system level, this technology reduces start-up power consumption, improves the overall efficiency of the charging device, and increases system safety and lifespan. Product-level benefits include preventing a weak adapter from failing due to high start-up currents.
[0015] Fig. Figure 1A illustrates an example of a multi-input switching charging circuit. 100A according to one or more implementations of the technology in question. The multi-input switching charging circuit 100A can have multiple (for example, two or more) input supply nodes, such as IN1 and IN2 (additional supply nodes are not shown for simplicity), each of which can be connected to a power source, and a number of charge paths (for example, 110 and 120, where additional charging paths are not shown for simplicity). Examples of the power source can include an adapter, a power mat, a universal serial bus (USB), or a wireless power dongle. Each charging path (for example, 110 or 120 ) can have a central node (for example, MID1 or MID2) connected to a coupling switch, such as T2 or T4, for each of the charge paths 110 or 120 and a forward transistor, such as T1 or T3, each for the charge paths 110 or 120 The center nodes MID1 or MID2 can be coupled to a ground potential or earth potential, respectively, by large coupling capacitors C1 and C2 (e.g., 4.7 µF). The coupling switches T2 and T4 can be configured to provide a corresponding charge path (e.g., 110 or 120 ) to activate.
[0016] In some embodiments, examples of the forward transistors T1 and T3 and the coupling switches T2 and T4 may include NMOS transistors. Diodes D1 to D4, shown separately from transistors T1–T4, are body diodes that are structurally part of the respective transistors T1–T4, with the bulk or main body connected to the source node. For example, the anode of each diode (e.g., D3) is formed by the bulk of the respective transistor (e.g., T3), and the cathode of this diode is formed by the n-diffusion-drain node of the respective transistor. The charge path 110 or 120 can be activated by coupling a node CP1 or CP2 (for example, a gate electrode of transistors T2 or T4) to a suitable voltage.
[0017] In one or more embodiments, the forward transistor T1 of an activated charge path can 110be configured to have a switching voltage at the input of a charge undercut. 125 to provide a coil L1 and a capacitor C3. The forward transistor T1 can be connected to a switching circuit (in Fig. (1A not shown for simplicity) coupled, which is configured to control the forward transistor T1 of the activated charge path. 110 to control a switching voltage at an input of the charge circuit 125 to provide the coil L1 and the capacitor C3 of the charge circuit. 125 In conjunction with transistor T5, which is configured as a diode, the switching voltage can be converted into a DC voltage. The charge-limiting circuit 125 The DC voltage can be used, for example, for charging one or more batteries of a device or apparatus, such as a communication device or other devices, at an output of the charging circuit.125 provide.
[0018] When the path is activated 110 The voltage at MID1 rises to the high voltage value (for example, 20V) of the input supply at IN1 and, during the charging cutoff, 125 A current I1 (a switching regulator current) is provided, which can be used to charge one or more batteries. With a negligible voltage drop across the forward transistor T1, the same high voltage (e.g., 20V) can be applied to the anode of diode D3, with its cathode at ground potential (since the charging path 120 (is inactive). This high voltage forwards the diode D3 and causes a large unwanted current I2 to flow through this diode. This large unwanted current I2 can lead to a loss of efficiency and reliability of the charging circuit. 100A have as a consequence.
[0019] Fig. 1B illustrates an example expression 100B a number of signal waveforms 130 – 135 the multi-input switching charging circuit 100A according to Fig. 1A according to one or more implementations of the technology in question. The signal waveform 130 shows the voltage at the input supply node IN1 according to Fig. 1A, which increases during t1–t2 and reaches a constant value (e.g., 20V) at time t2. The signal waveform 131 The voltage VMID1 at the center node MID1 is shown according to Fig. 1A. The coupling switch T2 is closed at time t1, which allows the voltage VMID1 to follow the voltage at the input supply node IN1. The voltage at the input supply node IN2 according to Fig. 1A, which is determined by the signal waveform 132 As shown, at zero voltage, the charge path 120 according to Fig. 1A is inactive. The signal waveform 134 The voltage VMID2 at the middle node MID2 is shown according to Fig. 1A. The voltage VMID2 is zero until a time t5, which is the start of the switching of the forward transistor T1 according to Fig. 1A is, and increases when capacitor C2 is charged during each high cycle of the switching voltage at the input of the charge switch. 125 according to Fig. 1A charges, which is indicated by the signal waveform 135 The unwanted high current at node MID2, through diode D3, is shown. Fig. 1A flows during the cycles of the circuit voltage in which the voltage VMID2 has not reached the voltage VMID1.
[0020] In one or more implementations, a pre-charge switch can be connected to the center nodes of the charge paths. 110 and 120 be coupled, whereby it can be configured to be a middle node of an inactive path (for example) 120) to pre-charge to a high voltage. The high voltage can be a voltage (for example, 20V) at an input supply node (for example, IN1) connected to the activated path. 110 is connected, preventing diode D3 from conducting excessive current during startup. Consequently, no unwanted current (e.g., I2) can pass through diode D3.
[0021] Fig. Figure 2A illustrates an example of a multi-input switching charging circuit. 200A , which have a pre-charge switch 240 used according to one or more implementations of the technology in question. The multi-input switching charging circuit 200A is similar to the multi-input switching charging circuit 100A according to Fig. 1A with the exception of the addition of the pre-charge switch 240 The pre-charge switch 240can be used with the corresponding intermediate nodes MID1 and MID2 of the charging paths 110 and 120 (and other charging paths, which are not shown here for the sake of simplicity) are coupled by one or more coupling resistors (for example, R1 and R2). The pre-charge switch 240 can be for a predetermined time period before the switching voltage is provided (for example, t5 according to Fig. 1B) at the input of the charge circuit 125 be activated. As described above, the pre-charge switch can be 240 Once activated, MID2 couples to the voltage at MID1 (e.g., 20V), which prevents diode D3 from failing during the first few high cycles of the switching voltage (e.g., 135 according to Fig. 1B) conducts. This can be the multi-input switching charging circuit. 200A to facilitate working, reliably and with high efficiency.
[0022] Fig. 2B illustrates an example expression 200B a number of signal waveforms 130 – 133 , 234 and 135 the multi-input switching charging circuit 200A according to Fig. 2A according to one or more implementations. The descriptions of the signal waveforms 130 – 133 and 135 are the same as the above with reference to Fig. 1B discussed. The signal pattern 234 The voltage VMID2 at the middle node MID2 is shown according to Fig. 2A. The voltage VMID2 is zero at time t3, which is the start of conduction of the pre-charge switch. 240 according to Fig. 2A is, with the current increasing when capacitor C2 is changed according to... Fig. The device charges at 2A during the time period t3–t4, reaching a constant value approximately equal to the voltage at MID1 (e.g., VMID1). During the charging time period t3–t4, a well-controlled charging current can be applied via the pre-charge switch. 240 pass through. During the switching of the voltage at the input of the charge interruption. 125 However, no unwanted current passes through diode D3 according to Fig. 2A through.
[0023] Fig. 2C illustrates an example of the charge switch. 240 the multi-input switching charging circuit 200A according to Fig. 2A corresponding to one or more implementations of the technology in question. The charge switch 240 can be implemented, for example, using two PMOS transistors P1 and P2, connected via resistors R1 and R2 with center nodes MID1 and MID2 according to Fig. 2A can be coupled to voltages from VMID1 and VMID2. The gate nodes of the PMOS transistors P1 and P2 can be coupled together. The body and source nodes of the PMOS transistors P1 and P2 can be connected together and coupled to the gate nodes of the PMOS transistors P1 and P2 via a resistor R3. The gate nodes of P1 and P2 can then be coupled to a switch N1, which, when activated, connects to ground potential. In some implementations, the switch N1 is an NMOS transistor and can be activated by applying a pre-charge signal to a gate node of the NMOS transistor.
[0024] Fig. Figure 3 illustrates an example of a multi-input switching charging circuit. 300 , which uses the bulk connection switches S1 and S2 according to one or more implementations of the technology in question. As stated above with reference to the Fig. 1A and Fig. 2A is discussed, at the start of the switching voltage at the input of the charge circuit 125 a large unwanted current through the forward-operated diode D3 according to Fig. 2A passes through, which improves the reliability and efficiency of the multi-input switching charging circuit 200 which can adversely affect the diode. As stated above, diodes D3 and D4 can be formed by anodes that are the bulk of the respective NMOS transistors T3 and T4, and cathodes that can be formed by the n-diffusion-drain node of the respective NMOS transistors T3 and T4.
[0025] In one or more implementations, the direction of diodes D3 and D4 can be reversed by the bulk connection switches S1 and S2. For example, switch S2 can be configured to reverse the direction of diode D3 by connecting the bulk of NMOS transistor T3 to a drain node of NMOS transistor T3. Using this technique prevents a large, unwanted current from flowing through diode D3 when the voltage at the input of the charge circuit is high. 125 is increased to a high level (for example, the voltage of the input supply node IN1). Consequently, the current I1 can be drawn from the active charging path. 110 to the charge interruption 125 flow without any significant current passing through the inactive charge path 120 passes through, since diode D3 is operated in reverse bias by switch S2.
[0026] Fig. 4 illustrates exemplary expressions 410 , 420 and 430 a number of signal waveforms of the multi-input switching charging circuit 200A according to Fig. 2A corresponding to one or more implementations of the technology in question. The expression 410 shows signal patterns of currents 412 and 414 , which draws the current I1 from the active charging path 110 according to Fig. 2A and the useful current that flows through the coil of the charge circuit 125 according to Fig. Represent each instance where 2A passes through. The expression 420 shows a signal waveform of the unwanted current I2 according to Fig. 1A, which goes to capacitor C2 according to Fig. 1A flows. This current stops as soon as the voltage at MID2 drops to the voltage at MID1 according to Fig. 2A by closing the pre-charge switch 240 according to Fig. 2A is increased. The expression 430shows voltage level 432 and 434 the respective centers MID1 and MID2 according to Fig. 2A. If the switch 240 As it closes, the voltage level approaches 434 from MID2 the voltage level 432 from MID1 onwards.
[0027] Fig. 5 illustrates an example of a procedure 500 for providing a multi-input switching charging circuit according to one or more implementations of the technology in question. For the purpose of description, the exemplary method is 500 here with reference to the multiple-input switching charging circuits 100A and 200A according to the Fig. 1A and Fig. 2A is described, but it is not limited to this. Furthermore, for the purpose of description, the blocks of the exemplary procedure are shown. 500Here, they are described as occurring serially or linearly. Several blocks of the exemplary procedure. 500 However, they can happen in parallel. Additionally, the blocks of the exemplary procedure must be considered. 500 not be executed in the order shown and / or one or more of the blocks of the exemplary procedure 500 do not need to be executed.
[0028] Each of the multiple input feed nodes (for example, IN1 and IN2 according to the Fig. 1A and Fig. 2A) can be coupled to a power source ( 510 Each of the multiple charging paths (for example) 110 and 120 according to the Fig. 1A and Fig. 2A) can be connected by a respective coupling switch (for example, T2 and T4 according to Fig. 1A) can be coupled with one of the several input supply nodes ( 520 A middle node (for example, MID1 or MID2 according to the Fig. 1A and Fig. 2A) Each of the multiple charging paths can be connected to the respective coupling switch and a forward transistor (for example, T1 and T3 according to Fig. 1A) can be coupled ( 530 The respective coupling switch can be configured to activate a corresponding charging path from among the multiple charging paths. A pre-charge switch (for example) 240 according to Fig. 2A) can be coupled to a corresponding central node of each of the multiple charge paths ( 540 ). The forward transistor (for example, T1 according to Fig. 1A) of an activated (for example) 110 according to the Fig. 1A and Fig. 2A) the multitude of charging paths (for example 110 and 120 according to the Fig. 1A and Fig. 2A) can be configured to have a switching voltage (for example) 135 according to Fig. 1B) at an input of a charge circuit (for example) 125 according to the Fig. 1A and Fig. 2A) to provide ( 550 The pre-charge switch can be configured to have a central node (for example, MID2 according to Fig. 2A) of a non-activated path (for example) 120 according to Fig. 2A) to a high voltage (for example, the voltage of MID2 according to Fig. 2A) to precharge in order to prevent an unwanted high current (for example, I2 according to Fig. 1A), which is connected via a body diode (for example, D3 according to the Fig. 1A and Fig. 2A) of a corresponding forward transistor (for example, T3 according to the Fig. 1A and Fig. 2A) of the unactivated path, to prevent ( 560 ).
[0029] Fig. Figure 6 illustrates an exemplary wireless communication device according to one or more implementations of the technology in question. The wireless communication device 600 can a radio frequency (RF) antenna 610, a recipient 620 , a transmitter or transmission device 630 , a baseband processing module 640 , a storage 650 , a processing unit or processor 660 , a Local Oscillator Generator (LOGEN) 670 and a power supply or power adapter 680 include. In various embodiments of the technology in question, one or more of the blocks that are in Fig. The blocks shown in Figure 6 can be integrated into one or more semiconductor substrates. For example, the blocks can be... 620 – 670 can be implemented in a single chip or a single system on a chip, or in a multi-chip chipset.
[0030] The RF antenna 610It can be suitable for transmitting and / or receiving RF signals (e.g., wireless signals) over a wide range of frequencies. Although a single RF antenna 610 As illustrated, the technology in question is not limited to this.
[0031] The recipient 620 It may include a suitable logic circuit and / or code that can be operated to receive signals from the RF antenna. 610 to receive and process. The recipient 620 For example, it can be capable of amplifying and / or down-converting received wireless signals. In various embodiments of this technology, the receiver can 620 It must be capable of eliminating noise in received signals, and it can be linear over a wide range of frequencies. In this way, the receiver can 620It should be suitable for receiving signals according to a variety of wireless standards, including Wi-Fi, WiMAX, Bluetooth, and various cellular standards.
[0032] The broadcaster 630 It may include a suitable logic circuit and / or code that is capable of processing signals and receiving them from the RF antenna. 610 to transmit. The sender 630 For example, it can be capable of converting baseband signals to RF signals and amplifying RF signals. In various embodiments of this technology, the transmitter can 630 be capable of upconverting and amplifying baseband signals processed according to a variety of wireless standards. Examples of such standards include Wi-Fi, WiMAX, Bluetooth, and various cellular standards. In different embodiments of the technology in question, the transmitter can 630be operational, to provide signals for further amplification by one or more power amplifiers.
[0033] The duplexer 612 can provide isolation in the transmission band to prevent receiver saturation. 620 or damage to parts of the receiver 620 to avoid, and to meet one or more design requirements of the recipient 620 to simplify. Furthermore, the duplexer can 610 The duplexer attenuates the noise in the receiving band. It can operate in multiple frequency bands of different wireless standards.
[0034] The baseband processing module 640 The baseband processing module can include suitable logic, circuitry, interfaces, and / or code that can be operational to perform baseband signal processing. 640For example, it can analyze received signals and use control and / or regulation signals to configure various components of the wireless communication device. 600 , such as the recipient's 620 generate. The baseband processing module 640 can be operational, encoding, decoding, transcoding, modulating, demodulating, encrypting, decrypting, ciphering, decrypting and / or otherwise processing data according to one or more wireless standards.
[0035] The processing unit or processor 660 may include suitable logic, circuitry and / or code that processes data and / or controls operations of the wireless communication device. 600 This can enable the processor to do so. 660be able to send control signals to various other sections of the wireless communication device 600 to provide. The processor 660 This can also include the transmission of data between different sections of the wireless communication device. 600 control. Additionally, the processor can 660 enable the implementation of an operating system or otherwise execute code to operate the wireless communication device 600 to manage.
[0036] The storage 650 This can include suitable logic, circuitry, and / or code that enables the storage of various types of information, such as received data, generated data, code, and / or configuration information. The memory 650It can, for example, include RAM, ROM, flash memory, and / or magnetic storage. In various embodiments of the technology in question, information stored in the memory can be... 650 are stored for configuring the receiver 620 and / or the base tape processing module 640 be used.
[0037] The Local Oscillator Generator (LOGEN) 670 It may include suitable logic, circuitry, interfaces, and / or code that can be operational to generate one or more oscillating signals of one or more frequencies. The LOGEN 670 It can be operational, generating digital and / or analog signals. In this way, the LOGEN can 670It must be capable of generating one or more clock signals and / or sinusoidal signals. Characteristics of the oscillating signals, such as frequency and relative duty cycle, can be determined based on one or more control signals, for example, from the processor. 660 and / or the base tape processing module 640 be determined.
[0038] During operation, the processor can 660 the various components of the wireless communication device 600 Configure based on a wireless standard according to which signals are desired to be received. Wireless signals can be received via the RF antenna. 610 be received and by the recipient 620 amplified and downconverted. The baseband processing module 640It can perform noise estimation and / or noise cancellation, decoding and / or demodulation of the baseband signals. In this way, information in the received signal can be recovered and used appropriately. For example, the information can be audio and / or video data to be displayed to a user of the wireless communication device, data stored in the memory. 650 to be stored, and / or information that enables the operation of the wireless communication device 600 influence and / or enable the baseband processing module. 640 can transmit audio data, video data and / or control signals through the transmitter 630 The data to be transmitted must be modulated, encoded, and subjected to other processing according to various wireless standards. The power supply 680Can there be one regulated rail voltage or several regulated rail voltages (for example, V) DD ) for various circuits of the wireless communication device 600 provide. In one or more implementations of the technology in question, the power supply can be 680 a multi-input switching charging circuit (for example) 200A according to Fig. 2A), which has a pre-charge switch 240 used, or a multi-input switching charging circuit (for example) 300 according to Fig. 3) include the bulk connecting switches S1 and S2, as described above.
[0039] It would be apparent to a person skilled in the art that the various illustrative blocks, modules, elements, and methods described herein can be implemented as electronic hardware, computer software, or a combination of both. To illustrate this interchangeability of hardware and software, various illustrative blocks, modules, elements, components, and methods have been described above in general terms with regard to their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. A person skilled in the art can implement the described functionality in varying ways for each specific application.Different components and blocks can be arranged differently (for example, in a different order or divided in a different way) without leaving the scope of the technology in question.
[0040] As used here, the phrase "at least one of," preceding a series of elements, with the "and" or "or" separating any of the elements, modifies the list as a whole rather than each element of the list (i.e., each element individually). The phrase "at least one of" does not require a selection of at least one of each listed element; rather, the phrase allows a meaning that includes at least one of any one of the elements and / or at least one of any combination of the elements and / or at least one of each of the elements. For example, the phrases "at least one of A, B, and C" or "at least one of A, B, or C" refer, respectively, to only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.
[0041] An expression such as "an embodiment" does not imply that such an embodiment is essential to the technology in question, or that such an embodiment applies to all configurations of the technology in question. A disclosure relating to an embodiment may apply to all configurations, or to one configuration, or to several configurations. An embodiment may provide one example or several examples of the disclosure. An expression such as "an embodiment" may refer to one embodiment or several embodiments, and vice versa. An expression such as "an exemplary embodiment" does not imply that such an exemplary embodiment is essential to the technology in question, or that such an exemplary embodiment applies to all configurations of the technology in question.A disclosure relating to an embodiment may be applied to all embodiments, or to one embodiment, or to several embodiments. An embodiment may provide one example or several examples of the disclosure. A term such as "embodiment" may refer to one embodiment or several embodiments, and vice versa. A term such as "configuration" does not imply that such a configuration is essential to the technology in question, or that such a configuration applies to all configurations of the technology in question. A disclosure relating to a configuration may be applied to all configurations, or to one configuration, or to several configurations. A configuration may provide one example or several examples of the disclosure.A term such as "configuration" can refer to one configuration or to multiple configurations, and vice versa.
[0042] The word "exemplary" is used here to mean "serving as an example, case, or illustration." Any embodiment described herein as "exemplary" or as an "example" is not necessarily to be interpreted as preferred or advantageous over other embodiments. Furthermore, where the expression "include," "feature," or the like is used in the description or the claims, such expression shall be interpreted as inclusive in a manner similar to how the expression "comprise" is interpreted when used as a transitional word in a claim.
[0043] All structural and functional equivalents to the elements of the various embodiments described in this disclosure, which are known or subsequently become known to a person skilled in the art, are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be made public, regardless of whether such disclosure is explicitly cited in the claims. No claim element is to be interpreted in accordance with the provisions of 35 USC §112, sixth paragraph, unless the element is expressly cited using the phrase "equipment for" or, in the case of a method claim, the element is cited using the phrase "step for".
[0044] The preceding description is provided to enable a person skilled in the art to implement various embodiments described herein in practice. Various modifications of these embodiments will be readily apparent to the person skilled in the art, and the general principles defined herein can be applied to other embodiments. Thus, the patent claims are not intended to be limited to the embodiments shown herein, but are intended to have the full scope corresponding to the linguistic patent claims, whereby a reference to an element in the singular should not mean "one and only one" unless specifically stated as such, but rather "one or more". Unless specifically stated otherwise, the expression "some" refers to one or more.Masculine pronouns (for example, sein) include both feminine and neuter genders (for example, ihres and seinen) and vice versa. Headings and subheadings, where present, are used for simplicity only and do not limit the scope of the text.
[0045] A circuit for switching a charging device comprises several input supply nodes and a number of charging paths. Each input supply node is connectable to a power source. Each charging path can include a center node connected to a coupling switch and a forward transistor. The coupling switch can be configured to activate a corresponding charging path. A pre-charge switch can be coupled to a corresponding center node of each charging path. The forward transistor of an activated charging path can be configured to provide a switching voltage at the input of a charging circuit. The pre-charge switch can be configured to pre-charge a center node of a non-activated path to a high voltage to prevent an unwanted high current flowing through a body diode of a corresponding forward transistor of the non-activated path.
Claims
[1] Circuit for switching a charging device, the circuit comprising: a plurality of input supply nodes, each of which can be connected to a power source; a plurality of charge paths, each of the plurality of charge paths comprising a central node connected to a coupling switch and a forward transistor, the coupling switch being configured to activate a corresponding charge path of the plurality of charge paths; and a pre-charge switch coupled to a corresponding central node of each of the multitude of charge paths, wherein the forward transistor of an activated one of the plurality of charge paths is configured to provide a switching voltage at an input of a charge sub-circuit, and wherein the pre-charge switch is configurable to pre-charge a center node of an inactive path to a high voltage to prevent an unwanted high current passing through a body diode of a corresponding forward transistor of the inactive path. [2] Circuit according to claim 1, wherein forward transistors of the plurality of charge paths are coupled to a switching circuit configured to control the forward transistor of the activated plurality of charge paths to provide a switching voltage at an input of the charge circuit, wherein the charge circuit comprises an inductor and a capacitor. [3] Circuit according to claim 1, wherein the power source comprises an element consisting of an adapter, a power mat, a universal serial bus (USB) or a wireless power dongle. [4] Circuit according to claim 1, wherein the coupling switch comprises an NMOS transistor and wherein a source node of the NMOS transistor is coupled to an input supply node of a corresponding charge path of the plurality of charge paths. [5] Circuit according to claim 1, wherein the forward transistor comprises an NMOS transistor and wherein a drain node of the NMOS transistor is coupled to a center node of a corresponding charge path of the plurality of charge paths. [6] Circuit according to claim 5, wherein an anode of a body diode of the forward transistor comprises a bulk of the NMOS transistor and wherein a cathode of the body diode of the forward transistor comprises an n-diffusion source region connected to the center node of a respective charge path. [7] Circuit according to claim 6, further comprising a switch configured to reverse the direction of the body diode by connecting the bulk of the NMOS forward transistor to a drain node of the NMOS forward transistor. [8] Circuit according to claim 1, wherein the pre-charge switch is coupled to the corresponding central node of each of the plurality of charge paths by a coupling resistor or several coupling resistors, and is activated for a predetermined time period before the switching voltage is provided at the input of the charge circuit. [9] Circuit according to claim 1, wherein the high voltage comprises a voltage of an input supply node coupled to the activated one of the plurality of charge paths, wherein a pre-charging of the center node of the non-activated path simplifies reverse bias operation of a body diode of the corresponding forward transistor of the non-activated path, and wherein the activated one of the plurality of charge paths is conductively coupled to a corresponding input supply node. [10] Method for providing a multi-input switching charging device, the method comprising: Coupling each of a multitude of charge paths through a respective coupling switch to one of a multitude of input supply nodes configured to be coupled to a power source; Coupling a central node of each of the plurality of charge paths with the respective coupling switch and a forward transistor, wherein the respective coupling switch is configurable to activate a corresponding charge path of the plurality of charge paths; Coupling a pre-charge switch with a corresponding central node of each of the multitude of charge paths; Configuring the forward transistor of an activated multiplicity of charge paths to provide a switching voltage at an input of a charge circuit; and Configuring the pre-charge switch to pre-charge a center node of a non-activated path to a high voltage to prevent an unwanted high current passing through a body diode of a corresponding forward transistor of the non-activated path. [11] Method according to claim 10, further comprising coupling forward transistors of the plurality of charge paths with a switching circuit configured to control the forward transistor of the activated plurality of charge paths to provide a switching voltage at an input of the charge circuit, wherein the charge circuit comprises an inductor and a capacitor. [12] Method according to claim 10, wherein coupling each of the plurality of input supply nodes comprises coupling each of the plurality of input supply nodes to an element of an adapter, a powermat, a universal serial bus (USB) or a wireless power dongle. [13] Method according to claim 10, wherein the coupling switch comprises an NMOS transistor and wherein the method further comprises coupling a source node of the NMOS transistor to an input supply node of a corresponding charge path of the plurality of charge paths. [14] Method according to claim 10, wherein the forward transistor comprises an NMOS transistor and wherein the method further comprises coupling a drain node of the NMOS transistor to a center node of a corresponding charge path of the plurality of charge paths. [15] Method according to claim 14, wherein an anode of a body diode of the forward transistor comprises a bulk of the NMOS transistor, wherein a cathode of the body diode of the forward transistor comprises an n-diffusion source region and wherein the method further comprises connecting the cathode of the body diode of the forward transistor to the center node of a respective charge path. [16] Method according to claim 15, further comprising configuring a switch to reverse the direction of the body diode by connecting the bulk of the NMOS forward transistor to a drain node of the NMOS forward transistor. [17] Method according to claim 10, further comprising coupling the pre-charge switch to the corresponding central node of each of the plurality of charge paths by means of a coupling resistor or several coupling resistors and activating the pre-charge switch for a predetermined time period before providing the switching voltage at the input of the charge circuit. [18] Method according to claim 10, wherein the high voltage comprises a voltage of an input supply node coupled to the activated one of the plurality of charge paths, wherein precharging the center node of the non-activated path simplifies reverse bias operation of the body diode of the corresponding forward transistor of the non-activated path, and wherein the method further comprises conductively coupling the activated one of the plurality of charge paths to a corresponding input supply node. [19] Communication device with: a multi-input switching charging circuit, which includes: a plurality of input supply nodes, each of which can be connected to a power source; a plurality of charge paths, each of the plurality of charge paths comprising a central node connected to a coupling switch and a forward transistor, the coupling switch being configured to activate a corresponding charge path of the plurality of charge paths; and a pre-charge switch coupled to a corresponding central node of each of the multitude of charge paths, wherein the forward transistor of an activated one of the plurality of charge paths is configured to provide a switching voltage at an input of a charge sub-circuit, and wherein the pre-charge switch is configurable to pre-charge a center node of an inactive path to a high voltage to prevent an unwanted high current passing through a body diode of a corresponding forward transistor of the inactive path. [20] Communication device according to claim 19, wherein the coupling switch includes an NMOS transistor, a source node of the NMOS transistor is coupled to an input node of a corresponding charge path of the multitude of charge paths, a drain node of the NMOS transistor is coupled to a center node of a corresponding charge path of the plurality of charge paths, an anode of a body diode of the forward transistor comprises a bulk of the NMOS transistor, and a cathode of the body diode of the forward transistor comprises an n-diffusion source region connected to the center node of a respective charge path.