Clock generation circuit, chip, and electronic device

Abstract

This application discloses a clock generation circuit, chip, and electronic device. The clock generation circuit includes: a reference voltage generation module configured to generate a periodically changing reference voltage; a frequency-to-voltage conversion module configured to generate a feedback voltage based on a clock signal from the clock generation circuit; a comparison module configured to generate a control signal based on a comparison result between the feedback voltage and the reference voltage; and a voltage-controlled oscillator module configured to adjust and output the clock signal based on the control signal. The periodicity of the clock signal is the same as the periodicity of the reference voltage. Through this application, a closed-loop negative feedback mechanism can force the feedback voltage to track and lock onto the periodically changing reference voltage in real time, thereby driving the clock frequency to undergo synchronous periodic modulation and achieving precise spectrum expansion.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a clock generating circuit, chip, and electronic device. Background Technology

[0002] As electronic devices become more high-frequency and integrated, electromagnetic interference (EMI) has become a key bottleneck restricting the performance and reliability of electronic systems. In modules such as switching power supplies (e.g., DC / DC converters), the high-frequency switching action of their power switching devices generates strong clock harmonic noise. This noise interferes with the system itself and surrounding sensitive circuits through conduction and radiation, leading to decreased signal integrity, increased system bit error rate, and even functional failure.

[0003] To suppress such EMI problems, spread spectrum clocking (SSC) technology is widely used. The basic principle of this technology is to periodically modulate the switching frequency of the clock signal, dispersing the energy that was originally concentrated in a narrow frequency range to a wider frequency band, thereby reducing the noise peak intensity at specific frequency points and meeting the requirements of electromagnetic compatibility (EMC) specifications.

[0004] Currently, various implementation schemes for spread spectrum clocks exist in related technologies. One common scheme employs an open-loop modulation architecture, such as changing the clock period by directly modulating the charging and discharging current of the oscillator. However, the accuracy and stability of the output frequency of such schemes heavily depend on the absolute parameters of the components in the circuit (such as capacitance values ​​and current source matching). Under the influence of process deviations, power supply voltage fluctuations, and temperature changes, the parameters of key components will drift, causing core parameters such as the actual spread spectrum center frequency, modulation frequency, and modulation depth to deviate significantly from the design values. As a result, EMI suppression is difficult to predict and guarantee, especially in applications with stringent requirements for clock accuracy and long-term stability (such as high-precision power management).

[0005] Therefore, how to overcome the impact of process, voltage and temperature variations on the performance of spread spectrum clocks and improve their frequency accuracy and stability has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] In view of the above problems, embodiments of this application provide a clock generating circuit, chip, and electronic device to solve the above technical problems.

[0007] In a first aspect, embodiments of this application provide a clock generation circuit for outputting a clock signal, comprising: a reference voltage generation module configured to generate a periodically changing reference voltage; a frequency-to-voltage conversion module configured to generate a feedback voltage based on the clock signal from the clock generation circuit; a comparison module configured to generate a control signal based on a comparison result between the feedback voltage and the reference voltage; and a voltage-controlled oscillator module configured to adjust and output the clock signal based on the control signal. The periodic variation of the clock signal is the same as the periodic variation of the reference voltage, enabling the frequency of the output clock signal to be locked to the periodically changing reference voltage, thereby driving the clock frequency to undergo periodic modulation synchronously, achieving precise spectrum expansion, and solving the technical problems of poor output frequency accuracy, unstable spectrum expansion, and deteriorated electromagnetic interference suppression effect caused by circuit parameter drift and environmental changes in traditional open-loop spread spectrum clocks.

[0008] Secondly, embodiments of this application also provide a chip including the clock generation circuit described above.

[0009] Thirdly, embodiments of this application also provide an electronic device, including the aforementioned chip.

[0010] The clock generation circuit provided in this application constructs a closed-loop negative feedback loop consisting of a reference voltage generation module, a frequency-to-voltage conversion module, a comparison module, and a voltage-controlled oscillator module. It uses a periodically changing reference voltage as the tracking target for frequency modulation and utilizes closed-loop negative feedback to force the clock signal frequency to track the changes in the reference voltage in real time and accurately. This achieves programmed and precise control of the spectrum spreading process and monitors the frequency deviation of the output clock signal in real time, performing dynamic correction through feedback. This significantly improves the frequency accuracy and long-term stability of the output clock signal, solving the problems of traditional open-loop spread spectrum technology, which suffers from poor clock frequency performance due to environmental and parameter drift, inaccurate key spread spectrum parameters, and unstable electromagnetic interference suppression due to a lack of feedback adjustment. The circuit achieves the beneficial effects of high spread spectrum accuracy, good long-term stability, and strong anti-interference capability. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of the principle framework of the clock generation circuit provided in the embodiment of this application is shown; Figure 2This paper illustrates another schematic diagram of the clock generation circuit provided in an embodiment of this application. Figure 3 A circuit diagram of a reference voltage generation module provided in an embodiment of this application is shown; Figure 4 A schematic diagram of the principle framework of the periodic voltage generating unit provided in the embodiment of this application is shown; Figure 5 A circuit diagram of the periodic voltage generating unit provided in an embodiment of this application is shown; Figure 6 Another circuit diagram of the periodic voltage generating unit provided in an embodiment of this application is shown; Figure 7 This paper shows another circuit diagram of the periodic voltage generating unit provided in an embodiment of the present application; Figure 8 This paper shows another circuit diagram of the periodic voltage generating unit provided in an embodiment of this application; Figure 9 A schematic diagram of the principle framework of the periodic current generating unit provided in the embodiment of this application is shown; Figure 10 A circuit diagram of the periodic current generating unit provided in an embodiment of this application is shown; Figure 11 A circuit diagram of a frequency-to-voltage conversion module provided in an embodiment of this application is shown; Figure 12 A schematic diagram of the principle framework of the charging current generating unit provided in an embodiment of this application is shown; Figure 13 Another circuit diagram of the frequency-to-voltage conversion module provided in an embodiment of this application is shown; Figure 14 A circuit diagram of the charging current generating unit provided in an embodiment of this application is shown; Figure 15 A circuit diagram of the voltage-controlled oscillator module provided in an embodiment of this application is shown; Figure 16 A circuit diagram of the differential delay circuit provided in an embodiment of this application is shown; Figure 17 This diagram illustrates the change in output voltage and corresponding potential energy of the differential delay unit within one oscillation cycle of the clock generation circuit provided in this application embodiment. Figure 18 The diagram shows the output frequency waveform and corresponding spectrum obtained by the clock generation circuit according to an embodiment of this application; Figure 19 A schematic diagram of the principle framework of the chip provided in the embodiment of this application is shown; Figure 20A schematic diagram of the principle framework of the electronic device provided in the embodiments of this application is shown. Detailed Implementation

[0013] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0014] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0015] In the embodiments of this application, "at least one" refers to one or more; "multiple" refers to two or more. In the description of this application, the terms "first," "second," "third," etc., are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0016] References such as “one embodiment” or “some embodiments” as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the terms “comprising,” “including,” “having,” and variations thereof, as used in this specification, mean “including, but not limited to,” unless otherwise specifically emphasized.

[0017] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three kinds of relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0018] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0019] The clock generation circuit provided in this application can be used in various electronic devices that require suppression of electromagnetic interference (EMI), especially in systems containing switching power supply modules (such as DC / DC converters).

[0020] For example, the clock generation circuit is a spread spectrum clock generator, which can be integrated into the power management unit of an electronic device (such as a laptop, server, communication device, or portable electronic product). Specifically, the electronic device includes a DC / DC converter module, which typically includes: an input power port, at least one power switch (such as a MOSFET), an output filter composed of inductors and capacitors, and a power controller. The clock generation circuit is usually located inside the power controller or closely coupled to it.

[0021] In this application scenario, the clock generation circuit is configured to generate and output a spectrally spread clock signal. This clock signal serves as the driving clock for the power switching transistors, controlling their periodic switching operations. By distributing the spectral energy of the driving clock across a wider frequency band, the clock generation circuit effectively reduces the peak intensity of conducted and radiated interference (i.e., EMI noise) concentrated at specific frequency points caused by the high-speed switching of the power switching transistors. This helps ensure that the entire electronic device meets stringent electromagnetic compatibility (EMC) specifications and improves the operational stability and reliability of other sensitive circuits within the system, such as RF modules, sensors, and memory.

[0022] Please see Figure 1 This is a schematic diagram of the principle framework of a clock generation circuit provided in an embodiment of this application, as shown below. Figure 1 As shown, the clock generation circuit 10, used to output a clock signal, includes: a reference voltage generation module 11, a frequency-to-voltage conversion module 12, a comparison module 13, and a voltage-controlled oscillator module 14.

[0023] The reference voltage generation module 11 is configured to generate a reference voltage that varies periodically.

[0024] For example, the periodic change can take the form of a triangular wave, a sawtooth wave, etc. The reference voltage generation module 11 can be implemented in various ways, such as by including a triangular wave voltage generator and a voltage-to-current converter, to ultimately output a reference voltage with periodically varying amplitude. The specific circuit structure and implementation principle of the reference voltage generation module 11 will be described in detail below.

[0025] The frequency-to-voltage conversion module 12 is configured to generate a feedback voltage based on the clock signal from the clock generation circuit 10.

[0026] Specifically, the frequency-to-voltage conversion module 12 can be a switched-capacitor circuit. For example, the module may include a switch controlled by a clock signal and a capacitor. The capacitor is charged or discharged through the periodic operation of the switch, causing the average or peak voltage on the capacitor to be proportional to the frequency of the clock signal, thereby generating a feedback voltage. The specific circuit structure and working principle of this implementation will be described in detail below with reference to the accompanying drawings.

[0027] The comparison module 13 is configured to generate a control signal based on the comparison result between the feedback voltage and the reference voltage.

[0028] Specifically, the comparator module 13 is connected to the reference voltage generation module 11 and the frequency-to-voltage conversion module 12. A common implementation of the comparator module 13 is an operational amplifier (OPAMP) or an operational transconductance amplifier (OTA). For example, the non-inverting input of this operational amplifier receives the reference voltage, the inverting input receives the feedback voltage, and its output voltage is the control voltage.

[0029] The voltage-controlled oscillator module 14 is configured to adjust and output the clock signal according to the control signal. The periodic variation of the clock signal is the same as the periodic variation of the reference voltage.

[0030] The voltage-controlled oscillator module 14 can be a voltage-controlled oscillator (VCO). For example, the VCO can be a ring oscillator or an LC oscillator. Its oscillation frequency is controlled by the control voltage; when the control voltage increases, the output clock frequency increases; when the control voltage decreases, the output clock frequency decreases. Through this voltage-frequency conversion relationship, controlled frequency modulation is achieved.

[0031] Specifically, the frequency-to-voltage conversion module 12 is connected to the voltage-controlled oscillator module 14. The frequency-to-voltage conversion module 12 is connected to the voltage-controlled oscillator module 14 to receive the clock signal and generate a feedback voltage according to the frequency of the clock signal, thereby realizing a linear conversion from the frequency domain to the voltage domain. The output feedback voltage and the frequency of the clock signal both change periodically.

[0032] In this embodiment, the voltage-controlled oscillator module 14, the frequency-to-voltage conversion module 12, the comparison module 13, and the reference voltage generation module 11 together form a closed-loop negative feedback loop. The control signal output by the comparison module 13 drives the voltage-controlled oscillator module 14 to generate a clock signal. The frequency of this clock signal is linearly converted into a feedback voltage by the frequency-to-voltage conversion module 12. The feedback voltage is fed back to the comparison module 13 and compared with the periodic reference voltage, which serves as the modulation target. This negative feedback loop operates dynamically, enabling the feedback voltage to track the periodically changing reference voltage in real time. Since the feedback voltage and clock frequency have a fixed conversion relationship, the frequency of the clock signal is also forced to synchronously and accurately track the changing pattern of the reference voltage, thereby achieving periodic modulation of its frequency, and the periodic change of the clock signal is the same as the periodic change of the reference voltage.

[0033] The clock generation circuit provided in this embodiment, by constructing the aforementioned closed-loop negative feedback architecture, locks the clock frequency to a periodically changing reference voltage, thereby suppressing fluctuations in the parameters of components within the loop and significantly improving the accuracy and stability of the output frequency. Simultaneously, the changing waveform of the reference voltage forces the clock frequency to undergo continuous and smooth periodic changes according to a predetermined pattern, effectively spreading the narrowband spectrum of the clock signal into a wider frequency band. This effectively disperses the clock energy concentrated at a single frequency across a wider frequency band, significantly reducing the peak intensity of electromagnetic interference.

[0034] Please see Figure 2 This is a schematic diagram of another principle framework of the clock generation circuit provided in the embodiments of this application.

[0035] In some embodiments, the reference voltage generation module 11 includes a periodic voltage generation unit 110, a periodic current generation unit 111, a bias current unit 112, and a voltage divider unit 113. The periodic voltage generation unit 110 is configured to generate a periodically varying first voltage signal. The periodic current generation unit 111 is connected to the periodic voltage generation unit 110 and is configured to convert the first voltage signal into a periodically varying first current. The bias current unit 112 is configured to provide a bias current. The voltage divider unit 113 is connected to both the periodic current generation unit 111 and the bias current unit 112, and is configured to generate a reference voltage based on the first current and the bias current.

[0036] Please see Figure 3 This is a schematic diagram of the principle framework of the reference voltage generation module provided in the embodiments of this application.

[0037] In some specific embodiments, the periodic voltage generating unit 110 is a triangular wave voltage generating circuit, configured to generate a triangular wave voltage signal. The periodic current generating unit 111 is a triangular wave current generating circuit, connected to the triangular wave voltage generating circuit, configured to convert the triangular wave voltage signal into a corresponding triangular wave current signal (i.e., the first current I). GEN ).

[0038] In some embodiments, such as Figure 3 As shown, the voltage divider unit 113 includes a first resistor R1, a second resistor R2, and a second capacitor C2. The first resistor R1 and the second resistor R2 are connected in series between the output terminal of the periodic current generating unit 111 and ground, and the connection point of the first resistor R1 and the second resistor R2 forms a first common node. The first current I output by the periodic current generating unit 111... GEN The bias current I output by the bias current unit 112 BIAS After being superimposed, the current flows through the first resistor R1 and the second resistor R2, thereby generating a reference voltage V at the first common node. REF Optionally, one end of the second capacitor C2 is connected to the first common node, and the other end is grounded.

[0039] In some specific implementations, the comparison module 13 is a first operational amplifier OTA1, whose first input terminal (such as the in-phase input terminal) is connected to a first common node to receive a reference voltage V. REF The second input terminal (such as the inverting input terminal) receives the feedback voltage V. FB The comparison module 13 is configured to compare the feedback voltage V. FB and the periodically changing reference voltage V REF Compare and output the first control voltage V CTRL .

[0040] The control terminal of the voltage-controlled oscillator module 14 is connected to the comparator module 13 to receive the first control voltage V. CTRL And is configured to be based on the first control voltage V CTRL Adjust its output clock frequency Freq. The voltage-controlled oscillator module 14 has a first output terminal and a second output terminal, which respectively output a first clock signal CLK and a second clock signal CLKN that are inverses of each other.

[0041] Please see Figure 4 This is a schematic diagram of the principle framework of the periodic voltage generating unit provided in the embodiments of this application.

[0042] In some embodiments, the periodic voltage generation unit 110 includes a first bias current generation subunit 1100, a first current mirror subunit 1101, a first charge / discharge electron unit 1102, and a first comparison subunit 1103.

[0043] The first bias current generating subunit 1100 is configured to provide a first reference bias current.

[0044] The first reference bias current is a stable and precise constant current source, which can be generated by a bandgap reference circuit or a bias circuit independent of the power supply. Its amplitude determines the reference magnitude of the subsequent charge and discharge current. This first reference bias current does not drift significantly with changes in process, voltage, and temperature (PVT), providing a stable operating base for the voltage generation unit throughout the entire cycle.

[0045] The first current mirror subunit 1101 is connected to the first bias current generating subunit 1100 and is configured to generate a first mirror current and a second mirror current based on a first reference bias current.

[0046] Specifically, the first current mirror subunit 1101 adopts a current mirror structure. By replicating the first reference bias current and scaling it according to a preset scaling factor, it generates two independent but proportionally constant mirror currents. In a specific example, the second mirror current maintains a fixed proportional relationship with the first mirror current. This proportional relationship is achieved by adjusting the width-to-length ratio of the current mirror transistor, and once set, it remains fixed, ensuring the symmetry and repeatability of the charging and discharging process.

[0047] The first charge / discharge electronic unit 1102 is connected to the first current mirror subunit 1101. The first charge / discharge electronic unit 1102 includes a first capacitor. The first charge / discharge electronic unit 1102 is configured to charge the first capacitor based on a first mirror current and discharge the first capacitor based on a second mirror current according to a first control signal.

[0048] The first comparison subunit 1103 is connected to the first charge / discharge electronic unit 1102 and is configured to output a first control signal based on the comparison result of the voltage value of the first capacitor and the threshold voltage, so that the first capacitor generates a first voltage signal that changes periodically within the threshold voltage range.

[0049] Specifically, in the initial state, the voltage of the first capacitor is zero. The first charge / discharge electronic unit 1102, based on the initial state of the first control signal, begins charging the first capacitor using the first mirror current, causing the voltage VC1 of the first capacitor to rise linearly. When VC1 rises to the threshold voltage VTH, the first comparator subunit 1103 detects that VC1 ≥ VTH, flips its output state, and outputs the first control signal to the first charge / discharge electronic unit 1102. Responding to this first control signal, the first charge / discharge electronic unit 1102 switches to the discharge state, introducing the second mirror current into the first capacitor. Since the second mirror current is greater than the first mirror current and their directions are opposite, the first capacitor begins to discharge, and VC1 decreases linearly. When VC1 drops below the threshold voltage VTH, the first comparator subunit 1103 flips again, outputting the first control signal to switch back to the initial state, and the first charge / discharge electronic unit 1102 then switches back to the charging state, recharging the first capacitor C1 using the first mirror current.

[0050] The above process repeats cyclically, generating a first voltage signal on the first capacitor that varies periodically and linearly within a certain voltage range, with the threshold voltage VTH as a reference. The frequency of this first voltage signal is determined by the first mirror current, the second mirror current, the capacitance of the first capacitor, and the threshold voltage.

[0051] This embodiment achieves highly stable frequency and amplitude and good linearity of periodic voltage generation through closed-loop control composed of a constant ratio of charging and discharging current and a threshold comparison; it requires no external components, has excellent process-voltage-temperature (PVT) robustness, and the frequency can be linearly tuned by adjusting the reference bias current or the threshold voltage, providing a high-quality, high-precision on-chip periodic reference voltage source for the clock generation circuit.

[0052] Please see Figure 5 This is a circuit diagram of the periodic voltage generating unit provided in an embodiment of this application.

[0053] In some embodiments, such as Figure 5 As shown, the first charge / discharge electronic unit 1102 also includes a first switch SW1, and the first current mirror subunit 1101 includes a charging current mirror branch 11011 and a discharging current mirror branch 11012.

[0054] The first terminal of the first switch SW1 is connected to the first terminal of the first capacitor C1 and the charging current mirror branch 11011, the second terminal of the first switch SW1 is connected to the discharging current mirror branch 11012, and the second terminal of the first capacitor C1 is grounded.

[0055] In this process, the first switch SW1 responds to the first control signal GEN_CLK and controls the first capacitor C1 to be connected to the discharge current mirror branch 11012 for discharge.

[0056] The first comparison subunit 1103 has a preset threshold voltage range, which has a first threshold voltage and a second threshold voltage (the specific implementation of which can be found later). Figure 7 (See the illustrated embodiment and related description). The first comparison subunit 1103 is configured to compare the instantaneous voltage of the first capacitor C1 with the threshold voltage range, and output a first control signal GEN_CLK based on the comparison result.

[0057] The operation of this embodiment is as follows: During the charging phase, the first control signal GEN_CLK controls the first switch SW1 to turn off, and the first mirror current charges the first capacitor C1, causing its voltage to rise linearly. When the voltage of the first capacitor C1 rises to the second threshold voltage, the first comparator subunit 1103 outputs the first control signal to turn on the first switch SW1, and the second mirror current discharges the first capacitor C1, causing its voltage to drop linearly. When the voltage of the first capacitor C1 drops to the first threshold voltage, the first comparator subunit 1103 outputs the first control signal to turn off the first switch SW1, and the charging phase is restarted. This cycle repeats, causing the voltage of the first capacitor C1 to change periodically between the first threshold voltage and the second threshold voltage, generating a stable periodic first voltage signal.

[0058] This embodiment introduces a switch-controlled charging and discharging current path, which, together with the first control signal output by the first comparator subunit, causes the voltage of the first capacitor to change periodically and linearly between the first threshold voltage and the second threshold voltage, thereby generating a stable periodic voltage signal. This achieves precise timing control of the charging and discharging process, ensures the frequency stability of the output waveform, and provides a high-quality, high-precision on-chip periodic reference voltage source for the clock generation circuit.

[0059] In some embodiments, such as Figure 6 As shown, the periodic voltage generating unit 110 also includes a second switch SW2 and a third switch SW3; the second switch SW2 is connected between the first terminal of the first capacitor C1 and the charging current mirror branch 11011; the first terminal of the third switch SW3 is connected to the preset reference voltage terminal VREF_BG, and the second terminal is connected to the first terminal of the first capacitor C1.

[0060] The second switch SW1 and the third switch SW2 are controlled by a pair of complementary and overlapping enable signals SSC_EN_n and SSC_EN. When the third switch SW2 is closed, the second switch SW2 is open, and the first voltage signal GEN_CLK is a preset reference voltage. When the second switch SW2 is closed, the third switch SW3 is open, and the first voltage signal GEN_CLK changes periodically within the threshold voltage range.

[0061] It is understandable that the complementary and overlapping enable signals SSC_EN and SSC_EN_n can be directly generated by the digital control register or generated by the system power-on reset circuit with a delay, so as to ensure that the initial state of the first capacitor C1 is predictable when the spread spectrum function is enabled or disabled, thereby shortening the loop lock-in time.

[0062] Specifically, when the third switch SW3 is closed and the second switch SW2 is open, the first terminal of the first capacitor C1 is forcibly clamped to the preset reference voltage VREF_BG. At this time, the oscillation loop formed by the first charge / discharge electronic unit 1102 and the first comparator subunit 1103 is bypassed, and the first voltage signal GEN_CLK no longer exhibits periodic changes, but instead outputs a stable DC reference voltage. In this mode, the clock generation circuit operates in a normal non-spread spectrum state, outputting a clock signal of a fixed frequency. When the second switch SW2 is closed and the third switch SW3 is open, the charging current mirror branch 11011 is reconnected to the first capacitor C1, and the preset reference voltage VREF_BG is cut off. At this time, the first charge / discharge electronic unit 1102 and the first comparator subunit 1103 operate normally, and the first capacitor C1 is clamped to the preset reference voltage VREF_BG. CHARGE With the second mirror current I DISCHARGE Under the alternating action of linear charging and discharging, its voltage oscillates between a first threshold voltage and a second threshold voltage, thereby generating a periodic signal as the first voltage signal GEN_CLK output. In this mode, the clock generation circuit operates in spread spectrum mode, outputting a clock signal with a periodically modulated frequency.

[0063] This embodiment integrates a hardware-level enable / bypass capability for the periodic voltage generation unit 110 by adding a second switch SW2 and a third switch SW3 and configuring complementary and overlapping enable signals to control their on / off states. When the spread spectrum function is enabled, the circuit automatically switches to the oscillation mode to generate a periodic voltage to achieve clock frequency modulation. When the spread spectrum function is disabled, the circuit bypasses the oscillation loop and outputs a stable DC reference voltage, allowing the system to return to the normal non-spread spectrum operating state.

[0064] In some embodiments, such as Figure 7As shown, the first comparator unit 1103 includes a first comparator COMP1, a second comparator COMP2, and an RS flip-flop. Among them, the first input terminal of the first comparator COMP1 is connected to the first end of the first capacitor C5, and the second input terminal of the first comparator COMP1 is configured to receive a first threshold voltage VREF1; the first input terminal of the second comparator COMP1 is configured to receive a second threshold voltage VREF2, and the second input terminal of the second comparator COMP1 is connected to the first end of the first capacitor C5; the set terminal S of the flip-flop RS is connected to the output terminal of the first comparator COMP1, the reset terminal R is connected to the output terminal of the second comparator COMP2, and the output terminal of the flip-flop RS is connected to the control terminal of the first switch SW3.

[0065] Specifically, the first input terminal (such as the non-inverting input terminal) of the first comparator COMP1 is connected to the first end of the first capacitor C5 to obtain a voltage VGEN, and the second input terminal (such as the inverting input terminal) receives the first threshold voltage VREF1. The first input terminal (such as the non-inverting input terminal) of the second comparator COMP2 receives the second threshold voltage VREF2, and the second input terminal (such as the inverting input terminal) is connected to the first end of the first capacitor C5 to receive the voltage VGEN. The output terminal of the flip-flop RS outputs a first control signal GEN_CLK to control the first switch SW3.

[0066] In some specific embodiments, a preset reference voltage VREF_BG is between the first threshold voltage VREF1 and the second threshold voltage VREF2, that is, VREF1 > VREF_BG > VREF2. For example, VREF_BG = (VREF1 + VREF2) / 2.

[0067] When the enable signal SSC_EN is valid (for example, becomes high), the third switch SW3 is turned off, and the second switch SW2 is turned on, and the circuit enters the dynamic operating mode and starts to work. Initially, since VGEN = VREF_BG, and VREF2 < VGEN (= VREF_BG) < VREF1, the outputs of both the first comparator COMP1 and the second comparator COMP2 are logic low levels, and the RS flip-flop maintains its original state (for example, GEN_CLK is low), so as to keep the first switch SW1 off. At this time, the first mirror current I CHARGE charges the first capacitor C1 through the charging switch path, and VGEN starts to linearly rise from VREF_BG. When VGEN rises above the first threshold voltage VREF1, the output of the first comparator COMP1 flips to a logic high level, triggering the RS flip-flop to be set, making the first control signal GEN_CLK become high, and this high-level signal controls the first switch SW1 to close, thereby connecting the second mirror current I DISCHARGE to the charge and discharge path.

[0068] Because of I DISCHARGE >I CHARGE The first capacitor C1 discharges with a net discharge current (Ic). DISCHARGE - I CHARGE Discharge occurs, and VGEN decreases linearly from its peak. When VGEN drops below the second threshold voltage VREF2, the output of the second comparator COMP2 flips to a logic high level, triggering the RS flip-flop to reset, causing the first control signal GEN_CLK to return to a low level. The first switch SW1 opens again, and the second mirror current I... DISCHARGE The circuit was disconnected. The system re-entered the circuit via the first mirror current I. CHARGE The charging state of the first capacitor C1. VGEN rises linearly again from its trough. This cycle repeats, generating a voltage signal VREF_GEN (i.e., VGEN) that periodically varies between the first threshold voltage VREF1 and the second threshold voltage VREF2 on the first capacitor C1. According to the capacitor charging and discharging formula, the frequency of this voltage signal (i.e., the spread spectrum modulation frequency) is related to the first mirror current I. CHARGE Second mirror current I DISCHARGE It is directly proportional to the capacitance of the first capacitor C5, which is inversely proportional to the voltage swing (VREF1 to VREF2).

[0069] In some embodiments, the first mirror current I CHARGE The size and second mirror current I DISCHARGE The size is adjusted using digital modifier codes.

[0070] like Figure 8 As shown, the first current mirror subunit 1101 is also configured to receive a first set of digital trimming codes (e.g., GEN_TRIM<2:0> and GEN_TRIMN<2:0>), and synchronously adjust the first mirror current I according to the first set of digital trimming codes. CHARGE With the second mirror current I DISCHARGE The current value. It should be noted that during the adjustment process, the second mirror current I... DISCHARGE With the first mirror current I CHARGE They always maintain a fixed proportional relationship (e.g., I) DISCHARGE = 2 × I CHARGE This ensures the symmetry and frequency stability of the charging and discharging waveforms.

[0071] By adjusting the code value of the first set of digital trim codes, the charging and discharging rate of the first capacitor C1 can be linearly changed, thereby accurately calibrating the frequency (i.e., the spread spectrum modulation frequency) of the first voltage signal VGEN generated by the periodic voltage generation unit 110, so that it can remain stable near the preset target value under changes in process, voltage, and temperature. This first set of digital trim codes can be provided by the chip's internal power-on calibration circuit, register configuration, or external interface.

[0072] It is understood that the first current mirror subunit 1101 can be implemented using a digitally controlled current mirror network known in the art, for example, consisting of a main bias current source and multiple parallel selectable weighted current branches, with the switching of each branch controlled by a first set of digital adjustment codes, thereby realizing digital step adjustment of the output current. Such digital adjustment current mirrors are prior art, and their specific circuit configuration will not be described in detail here.

[0073] Please see Figure 9 This is a schematic diagram of the principle framework of the periodic current generating unit provided in the embodiments of this application.

[0074] In some embodiments, the periodic current generating unit 111 includes a second bias current generating subunit 1110 and a second current mirroring subunit 1111. The second bias current generating subunit 1110 is configured to generate a second reference bias current based on a first voltage signal. The second current mirroring subunit 1111 is connected to the second current mirroring subunit 1111 and is configured to mirror the second reference bias current to generate a first current I. GEN .

[0075] Specifically, the second bias current generating subunit 1110 is connected to the aforementioned periodic voltage generating unit 110 and receives a first voltage signal VGEN. Exemplarily, this first voltage signal is a triangular wave or approximately triangular wave voltage output by the periodic voltage generating unit 110, which varies periodically within a threshold voltage range. The second bias current generating subunit 1110 is configured to linearly generate a second reference bias current based on the instantaneous voltage value of the first voltage signal VGEN. The second bias current generating subunit 1110 may include a transconductance amplifier or a voltage-to-current conversion circuit, whose output current is proportional to the input voltage, thereby mapping the periodic voltage signal to a periodic current signal.

[0076] It is understood that the second bias current generating subunit 1110 can be implemented using voltage-to-current conversion circuits known in the art, such as feedback converters or transconductance amplifiers based on operational amplifiers. The specific circuit configuration is prior art and will not be described in detail here.

[0077] The second current mirroring subunit 1111 mirrors the second reference bias current to generate the first current I. GENThe first current I GEN It changes proportionally and periodically to the first voltage signal VGEN, thereby achieving precise replication and output of the modulated current.

[0078] It is understood that the second current mirror subunit 1111 can be implemented using current mirror structures known in the art, such as basic current mirror, common source cascode current mirror or programmable current mirror, etc., and its specific circuit configuration is also existing technology, which will not be described in detail here.

[0079] With the above structure, the periodic current generating unit 111 realizes the generation of periodic current from periodic voltage VGEN to periodic current I. GEN The linear transformation, and I GEN It changes proportionally and periodically to VGEN. This first current I... GEN It is then sent to subsequent circuits, where it is connected to the bias current I. BIAS Together they act on the impedance network to generate a periodically varying reference voltage VREF, providing a frequency modulation reference for the comparison module 13.

[0080] In some embodiments, the first current I GEN The size is adjusted using digital modifier codes.

[0081] like Figure 10 As shown, the second current mirror subunit 1111 is also configured to receive a second set of digital trimming codes (e.g., SSC_TRIM<2:0>) and adjust the first current I according to the second set of digital trimming codes. GEN The amplitude. Because the modulation amplitude of the reference voltage VREF is related to the first current I... GEN The change in amplitude is proportional to the frequency offset. By adjusting the second set of digital modulator codes, the spread spectrum modulation depth (i.e., the frequency offset range) can be linearly calibrated to precisely meet the design expectations.

[0082] It is understood that the second current mirror subunit 1111 can also be implemented using a digitally controlled current mirror network known in the art, and its specific circuit configuration will not be described in detail here.

[0083] In some embodiments, such as Figure 11 As shown, the frequency-to-voltage conversion module 12 includes a charging current generation unit 120 and a second charging / discharging unit 121. The charging current generation unit 120 is configured to provide a third current. The second charging / discharging unit 121 includes a second capacitor, which is configured to alternately charge and discharge based on the third current according to a clock signal to generate a feedback voltage.

[0084] In some embodiments, such as Figure 12As shown, the charging current generation unit 120 includes a third bias current generation subunit 1200 and a third current mirroring subunit 1201. The third bias current generation subunit 1200 is configured to generate a third reference bias current based on a preset reference voltage VREF_BG. The third current mirroring subunit 1201 is configured to mirror the third reference bias current to generate the third current.

[0085] It is understood that the third bias current generating subunit 1200 can be implemented using voltage-to-current conversion circuits known in the art, such as feedback converters based on operational amplifiers or transconductance amplifiers, and its specific circuit configuration is prior art. Similarly, the third current mirror subunit 1201 can be implemented using current mirror structures known in the art, such as basic current mirrors, cascode current mirrors, or programmable current mirrors, and its specific circuit configuration is also prior art, and will not be described in detail here.

[0086] With the above structure, the charging current generation unit 120 realizes the conversion current I from the preset reference voltage VREF_BG. FVC The linear transformation of (i.e., the third current), and the transformation current I FVC It is proportional to and highly stable with respect to the preset reference voltage VREF_BG. As mentioned earlier, in the stable state of the frequency-locked loop, the center frequency Freq_center of the output clock is proportional to the conversion current I. FVC Proportional to each other, therefore, by precisely setting the mirror ratio of VREF_BG and the third current mirror subunit 1201, a high-precision frequency reference current can be provided for subsequent circuits.

[0087] In some embodiments, such as Figure 13 As shown, the second charging / discharging unit 121 includes a fourth switch SW1, a fifth switch SW2, and a third capacitor C3. The first terminal of the third capacitor C3 is connected to the feedback node VFB of the comparator module 13, which receives the feedback voltage, and the second terminal of the third capacitor C3 is grounded. The first terminal of the fourth switch SW1 is connected to the charging current generating unit 120 and the feedback node, and the second terminal is connected to the first terminal of the second capacitor C4. The first terminal of the fifth switch SW2 is connected to the first terminal of the second capacitor C4, and the second terminals of the fifth switch SW2 and the second terminal of the second capacitor C4 are grounded.

[0088] Among them, the fourth switch SW1 and the fifth switch SW2 are controlled by the voltage-controlled oscillator module 14, which outputs a first clock signal CLK and a second clock signal CLKN that are inversely related to each other.

[0089] Specifically, the first terminal of the fourth switch SW1 is connected to the charging current generating unit 120, and its second terminal, together with the first terminal of the fifth switch SW2, is connected to the second common node N (i.e., the feedback node). The second capacitor C4 is connected between the second common node N and ground. The control terminals of the fourth switch SW1 and the fifth switch SW2 receive the first clock signal CLK and the second clock signal CLKN output by the voltage-controlled oscillator module 14, respectively, so that the two are alternately turned on by non-overlapping clock control. The second charging and discharging unit 121 periodically charges or discharges the second capacitor C4 by the alternating on and off of the fourth switch SW1 and the fifth switch SW2, so that the average voltage or peak voltage on the second capacitor C4 is proportional to the frequency of the output clock signal, thereby completing the linear conversion from frequency to voltage and generating a feedback voltage. The voltage on the second common node is this feedback voltage V. FB .

[0090] Furthermore, the third capacitor C3 is connected to the second input terminal of the first operational amplifier OTA1 (i.e., the feedback voltage V). FB Between the node and ground, used to stabilize the feedback voltage V FB .

[0091] In this embodiment, the clock generation circuit 10 achieves spread spectrum through closed-loop regulation. Specifically, its working principle is as follows: Reference voltage V... REF The voltage is a periodically changing triangular wave. Under the control of non-overlapping clocks CLK and CLKN, the equivalent impedance of the second charging / discharging unit 121 is as follows:

[0092] Where C4 is the capacitance value of the second capacitor C4, and Freq is the output clock frequency.

[0093] Therefore, the feedback voltage V FB as follows:

[0094] Comparison module 13 compares the feedback voltage V FB With reference voltage V REF Output control voltage V CTRL This drives the voltage-controlled oscillator module 14, forming a negative feedback loop. This loop forces the feedback voltage V... FB Dynamic tracking reference voltage V REF V FB ≈V REF Substituting into the above formula, we obtain the following output clock frequency:

[0095] In this embodiment, due to the reference voltage V REFThe frequency varies periodically, so the output clock frequency Freq also exhibits the same periodic variation, achieving spectrum spreading and modulation. This negative feedback mechanism can correct frequency deviations in real time, ensuring that the spectrum spreading process stably revolves around the target center frequency.

[0096] In some embodiments, the conversion current I FVC The amplitude is adjusted using digital tuning codes.

[0097] like Figure 14 As shown, the third current mirror subunit 1201 is also configured to receive a third set of digital trimming codes (e.g., FVC_TRIM<2:0>) and adjust the conversion current I according to the third set of digital trimming codes. FVC The amplitude. As mentioned earlier, the center frequency Freq_center of the output clock is related to the conversion current I. FVC Proportional to the frequency, by adjusting the third set of digital modifier codes, the spread spectrum center frequency can be calibrated with high precision, effectively compensating for the influence of passive device parameter drift on the center frequency.

[0098] It is understood that the third current mirror subunit 1201 can also be implemented using a digitally controlled current mirror network known in the art, and its specific circuit configuration will not be described in detail here.

[0099] Please see Figure 15 This is a circuit diagram of the voltage-controlled oscillation module provided in the embodiments of this application.

[0100] In some embodiments, the voltage-controlled oscillator module 14 includes a fourth bias current generating unit 140, an even number of cascaded differential delay units 141, and an output buffer unit 142.

[0101] The fourth bias current generating unit 140 is configured to generate a fourth reference bias current to provide quiescent current for the differential delay unit 141.

[0102] The differential output terminals (Y, YN) of the previous stage differential delay unit 141 are connected to the differential input terminals (INP, INN) of the next stage differential delay unit 141, and the output terminals (OUT, OUTN) of the last stage differential delay unit 141 are fed back to the input terminals (INP, INN) of the first stage differential delay unit 141, thus forming a closed-loop oscillation circuit.

[0103] Specifically, the number of differential delay units 141 is an even number, such as 4, 6 or 8, but the number is not limited to this. The specific number can be configured according to the oscillation frequency range and power consumption constraints required by the design.

[0104] The output buffer unit 142 is used to convert the differential signal output by the differential delay unit 141 into two single-ended complementary signals as clock signals.

[0105] The output buffer unit 142 is connected to the differential output terminal (OUT, OUTN) of the last stage differential delay unit 141.

[0106] Specifically, the fourth bias current generating unit 140 receives the first control signal V from the front-end comparison module 13. CTRL And according to the first control signal V CTRL An adjustable fourth reference bias current is generated. The fourth reference bias current provides the static operating current for the differential delay unit 141. By adjusting the magnitude of the fourth reference bias current, the delay time of the differential delay unit 141 is changed, thereby achieving voltage-controlled regulation of the oscillation frequency.

[0107] In some embodiments, such as Figure 16 As shown, the differential delay unit 141 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.

[0108] The control electrode of the first transistor M1 and the control electrode of the second transistor M2 are connected together to form the first input terminal INP of the differential delay unit 141. The first electrode of the first transistor M1 and the first electrode of the second transistor M2 are connected together to form the first output terminal YN of the differential delay unit 141. The second electrode of the first transistor M1 is grounded, and the second electrode of the second transistor M2 is connected to the power supply.

[0109] The control terminals of the third transistor M3 and the fourth transistor M4 are connected together to form the second input terminal INN of the differential delay unit 141. The first terminals of the third transistor M3 and the fourth transistor M4 are connected together to form the second differential output terminal Y of the differential delay unit 141. The second terminal of the third transistor M3 is grounded, and the second terminal of the fourth transistor M4 is connected to the power supply.

[0110] The control terminals of the fifth transistor M5 and the sixth transistor M6 are connected to the second output terminal Y. The first terminals of the fifth transistor M5 and the sixth transistor M6 are connected to the first differential output terminal YN. The second terminal of the fifth transistor M5 is grounded, and the second terminal of the sixth transistor M6 is connected to the power supply.

[0111] The control electrode of the seventh transistor M7 and the control electrode of the eighth transistor M8 are both connected to the first output terminal YN. The first electrode of the seventh transistor M7 and the first electrode of the eighth transistor M8 are both coupled to the second output terminal Y. The second electrode of the seventh transistor M7 is grounded, and the second electrode of the eighth transistor M8 is connected to the power supply.

[0112] The fifth transistor M6, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 form a cross-coupled positive feedback latch, which is configured to respond to the complementary level switching of the first input terminal INP and the second input terminal INN, and provide positive feedback to accelerate the switching when the voltages of the first output terminal YN and the second output terminal Y flip.

[0113] In one specific embodiment, the first transistor M1, the third transistor M3, the fifth transistor M5, and the seventh transistor M7 are NMOS transistors, and the second transistor M2, the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 are PMOS transistors. The control electrode of each transistor is the gate, the first electrode is the drain, and the second electrode is the source.

[0114] In this embodiment, the first input terminal INP and the second input terminal INN are configured to receive a pair of non-overlapping clock signals with opposite phases. This non-overlapping characteristic ensures that the two complementary switch pairs will not be in a high-impedance state simultaneously, guaranteeing reliable initiation of the state transition process and avoiding switch contention current.

[0115] The positive feedback acceleration principle of the differential delay unit is explained in detail below: When the first input signal switches from low to high and the second input signal switches from high to low, the rise in the first input signal increases the conduction of the first NMOS transistor M1, pulling down the potential of the first output terminal YN. The fall in the second input signal increases the conduction of the fourth PMOS transistor M4, pulling up the potential of the second output terminal Y. This rise in the potential of the second output terminal Y acts on the gates of the first latching transistors M5 and M6, causing a sharp increase in the conduction of the fifth NMOS transistor M5 and a decrease in the conduction of the sixth PMOS transistor M6, thus accelerating the decrease in the potential of the first output terminal YN with a larger pull-down current. Conversely, the decrease in the potential of the first output terminal YN acts on the gates of the second latching transistors M7 and M8, increasing the conduction of the eighth PMOS transistor M8 and decreasing the conduction of the seventh NMOS transistor M7, thus accelerating the increase in the potential of the second output terminal Y with a larger pull-up current.

[0116] Therefore, when the first input signal switches from low to high, it drives the first output terminal YN to decrease, and the decrease in YN accelerates the increase in the second output terminal Y through a positive feedback latch; when the second input signal switches from high to low, it drives the second output terminal Y to increase, and the increase in Y, in turn, accelerates the decrease in the first output terminal YN through a positive feedback latch. The driving direction of the input signals is consistent with the direction of the cross-coupling feedback, forming a self-reinforcing positive feedback loop, which makes the output state switching process exhibit an "avalanche" acceleration characteristic.

[0117] By employing complementary input switches to rapidly respond to input signals and initiate output switching, a cross-coupled positive feedback latch provides a strong regenerative drive current after the switching critical point, significantly compressing the rise / fall time of the output signal and resulting in a steep output waveform edge. Because the time window for the output signal to be at the noise-sensitive intermediate level is extremely short, and the positive feedback latch has high gain in steady state, it effectively resists voltage disturbances caused by power supply noise, substrate noise, and process fluctuations. Furthermore, the fast and deterministic switching reduces the random jitter of transistor switching delays, thereby significantly reducing the phase noise and period jitter of the voltage-controlled oscillator module. This differential delay unit is an ideal basic unit for fully differential ring voltage-controlled oscillators, especially suitable for spread spectrum clock generation circuits with high requirements for clock purity and modulation accuracy.

[0118] Please refer to the following: Figure 17 This example illustrates the change in output voltage (Y, YN) and corresponding potential energy of a differential delay unit during an oscillation cycle. During the oscillation process, when the output voltage is at a steady-state level (e.g., ...), ... Figure 17 When the M or K point is reached (corresponding to Y high / YN low or Y low / YN high respectively), the positive feedback latch formed by the cross-coupled first latching transistor pair (M5, M6) and the second latching transistor pair (M7, M8) exhibits high gain, effectively resisting external disturbances and maintaining the output voltage in the current steady state. This sustaining effect prolongs the flat portion of the output voltage waveform.

[0119] However, once the accumulated delay of the ring oscillation loop causes the complementary level switching between the first input terminal INP and the second input terminal INN to cause the internal node voltage to exceed a certain critical switching threshold (such as...), the internal node voltage will exceed a certain critical switching threshold. Figure 17 At the midpoint N), the positive feedback latch quickly enters the positive feedback phase. Specifically, the cross-coupling structure causes small changes in the output node on one side to be immediately amplified and fed back to the other side, thereby generating an acceleration effect that drives the circuit state to quickly complete the flipping of the output level, pushing the output voltage from the current steady-state point to another opposite steady-state point.

[0120] This embodiment uses a positive feedback latch composed of cross-coupled transistor pairs to shorten the time the signal is in the noise-sensitive level transition region, reduce the noise coupling window, and effectively reduce the phase noise and period jitter of the voltage-controlled oscillator module. Therefore, it improves the timing accuracy and long-term stability of the clock signal from the signal source, and ensures the accuracy and continuity of the spread spectrum modulation process.

[0121] Please see Figure 18 The diagram illustrates the output frequency waveform and its corresponding spectrum obtained by the clock generation circuit according to an embodiment of this application. Figure 18As shown in the waveform diagram above, the output clock frequency is periodically modulated in a triangular wave form around a center frequency fout, with a modulation depth of Δf. The spectrum diagram below compares the changes before and after enabling the spread spectrum function: before enabling, the clock signal energy is concentrated on a single narrow-band frequency point, which easily forms a high EMI peak; after enabling, through frequency modulation, the clock energy is effectively dispersed in a wider frequency band, the original single peak is significantly reduced, and the spectrum distribution is continuous and smooth, without obvious spurious peaks. This result verifies the excellent effect of the proposed solution in electromagnetic interference suppression.

[0122] This embodiment also provides a chip, such as Figure 19 As shown, the chip 20 includes the clock generation circuit 10 described in any of the above embodiments. By integrating the clock generation circuit 10, the chip 20 performs precise spectral expansion on the high-frequency clock signal generated or used within the system, dispersing the harmonic energy originally concentrated at a single frequency into a wider frequency band, thereby significantly reducing the electromagnetic interference peak caused by clock harmonics. The built-in parameter calibration mechanism of the chip 20 ensures the stability of its spread spectrum parameters under various operating conditions such as process, voltage, and temperature variations, while its fully differential voltage-controlled oscillator module effectively suppresses clock jitter introduced by power supply and ground noise, thereby improving the overall system performance and reliability.

[0123] This application also provides an electronic device, such as... Figure 20 As shown, the electronic device 30 includes a main body and a chip 20, as described above, disposed within the main body. By employing a chip 20 with an integrated clock generation circuit 10, the electronic device 30 can effectively suppress clock harmonic interference generated by high-frequency circuits (such as digital processors and switching power supplies) during operation, thereby improving the overall electromagnetic compatibility of the device. The stable, low-interference clock source provided by the clock generation circuit 10 helps ensure the accuracy and efficiency of signal processing, data conversion, or power management functions in the electronic device.

[0124] Electronic devices can be, but are not limited to, weighing scales, body fat scales, nutritional scales, infrared electronic thermometers, pulse oximeters, body composition analyzers, power banks, wireless chargers, fast chargers, car chargers, adapters, displays, USB (Universal Serial Bus) docking stations, styluses, true wireless earbuds, car infotainment screens, automobiles, smart wearable devices, mobile terminals, and smart home devices. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0125] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A clock generating circuit for outputting a clock signal, characterized in that, include: The reference voltage generation module is configured to generate a reference voltage that varies periodically. A frequency-to-voltage conversion module is configured to generate a feedback voltage based on the clock signal from the clock generation circuit; The comparison module is configured to generate a control signal based on the comparison result between the feedback voltage and the reference voltage; A voltage-controlled oscillator module is configured to adjust and output the clock signal according to the control signal; wherein the periodic variation of the clock signal is the same as the periodic variation of the reference voltage.

2. The clock generating circuit according to claim 1, characterized in that, The reference voltage generation module includes: The periodic voltage generation unit is configured to generate a first voltage signal that changes periodically; A periodic current generating unit is configured to convert the first voltage signal into a periodically changing first current; The bias current unit is configured to provide bias current; The voltage divider unit is configured to generate the reference voltage based on the first current and the bias current.

3. The clock generating circuit according to claim 2, characterized in that, The periodic voltage generating unit includes: The first bias current generating subunit is configured to provide a first reference bias current; The first current mirror subunit is configured to generate a first mirror current and a second mirror current based on the first reference bias current. A first charge-discharge electronic unit, comprising a first capacitor, is configured to charge the first capacitor based on a first mirror current and discharge the first capacitor based on a second mirror current according to a first control signal. The first comparison subunit is configured to output the first control signal based on the comparison result of the voltage value of the first capacitor and the threshold voltage, so that the first capacitor generates the first voltage signal that varies periodically within the threshold voltage range.

4. The clock generating circuit according to claim 3, characterized in that, The first charge-discharge electronic unit further includes a first switch, and the first current mirror subunit includes a charging current mirror branch and a discharging current mirror branch; The first terminal of the first switch is connected to the first terminal of the first capacitor and the charging current mirror branch, and the second terminal of the first switch is connected to the discharging current mirror branch. The second terminal of the first capacitor is grounded; The first switch receives the first control signal and controls the first capacitor to connect with the discharge current mirror branch to discharge.

5. The clock generating circuit according to claim 4, characterized in that, The periodic voltage generating unit further includes a second switch and a third switch; The second switch is connected between the first terminal of the first capacitor and the charging current mirror branch; The first end of the third switch is connected to a preset reference voltage terminal, and the second end is connected to the first end of the first capacitor. The second and third switches are controlled by a pair of non-overlapping enable signals. When the third switch is closed, the second switch is open, and the first voltage signal is the preset reference voltage. When the second switch is closed, the third switch is open, and the first voltage signal changes periodically within the threshold voltage range.

6. The clock generating circuit according to claim 3, characterized in that, The magnitudes of the first and second mirror currents are adjusted using digital modifier codes, and the ratio of the first mirror current to the second mirror current is a fixed value.

7. The clock generating circuit according to claim 2, characterized in that, The periodic current generating unit includes: The second bias current generating subunit is configured to generate a second reference bias current based on the first voltage signal; The second current mirror sub-unit is configured to mirror the second reference bias current to generate the first current.

8. The clock generating circuit according to claim 1, characterized in that, The frequency-to-voltage conversion module includes: The charging current generating unit is configured to generate a third current; and The second charge-discharge unit includes a second capacitor and is configured to alternately charge and discharge the second capacitor based on the third current according to the clock signal to generate the feedback voltage.

9. The clock generating circuit according to claim 8, characterized in that, The charging current generating unit includes: The third bias current generation subunit is configured to generate a third reference bias current based on a preset reference voltage; The third current mirror sub-unit is configured to mirror the third reference bias current to generate the third current.

10. The clock generating circuit according to claim 9, characterized in that, The second charging and discharging unit includes a fourth switch, a fifth switch, and a third capacitor; The first terminal of the third capacitor is connected to the feedback node of the comparison module that receives the feedback voltage, and the second terminal is grounded; The first end of the fourth switch is connected to the charging current generating unit and the feedback node, and the second end is connected to the first end of the second capacitor. The first terminal of the fifth switch is connected to the first terminal of the second capacitor, and the second terminal of the fifth switch is grounded. The fourth switch and the fifth switch are controlled by the voltage-controlled oscillator module, which outputs a first clock signal and a second clock signal that are in opposite phases.

11. The clock generating circuit according to claim 1, characterized in that, The voltage-controlled oscillator module includes a fourth bias current generation unit, an even number of cascaded differential delay units, and an output buffer unit. The fourth bias current generating unit is configured to generate a fourth reference bias current to provide a static current for the differential delay unit; The differential output of the previous stage differential delay unit is connected to the differential input of the next stage differential delay unit, and the output of the last stage differential delay unit is fed back to the input of the first stage differential delay unit. The output buffer unit is used to convert the differential signal output by the delay unit into two complementary single-ended signals, which are then output as the clock signal.

12. The clock generating circuit according to claim 11, characterized in that, The differential delay unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; In this configuration, the control electrodes of the first and second transistors are connected together as the first input terminal of the differential delay unit, and the first terminals of the first and second transistors are connected together as the first output terminal of the differential delay unit; the second terminal of the first transistor is grounded, and the second terminal of the second transistor is connected to a power supply; the control electrodes of the third and fourth transistors are connected together as the second input terminal of the differential delay unit, and the first terminals of the third and fourth transistors are connected together as the second output terminal; the second terminal of the third transistor is grounded, and the second terminal of the fourth transistor is connected to a power supply; the control electrodes of the fifth and sixth transistors are connected together to the second output terminal, and the first terminals of the fifth and sixth transistors are connected together to the first output terminal; the second terminal of the fifth transistor is grounded, and the second terminal of the sixth transistor is connected to a power supply; the control electrodes of the seventh and eighth transistors are connected together to the first output terminal, and the first terminals of the seventh and eighth transistors are connected together to the second output terminal; the second terminal of the seventh transistor is grounded, and the second terminal of the eighth transistor is connected to a power supply.

13. A chip, characterized in that, Includes a clock generation circuit as described in any one of claims 1 to 12.

14. An electronic device, characterized in that, Includes the chip as described in claim 13.

Images