Methods for forming semiconductor structures, semiconductor structures and electronic devices

Abstract

This application discloses a method for forming a semiconductor structure, a semiconductor structure, and an electronic device, relating to the field of resistive random access memory (RRAM) fabrication technology. The semiconductor structure, semiconductor structure, and electronic device provided in this application form one electrode and a resistive switching layer of an RRAM device through a self-aligned sidewall process. The other electrode is formed in a contact hole process module. To better form the contact between the contact hole electrode and the resistive switching layer, a filler material adjustment and re-etching step is proposed. The constructed RRAM device does not share a resistive switching material, effectively reducing crosstalk between devices. Furthermore, only one photomask is used to define the RRAM device, resulting in low process cost. In addition, since the RRAM cell is fabricated at the same level as the transistor, it is not limited by the thermal budget of subsequent processes, and the area of ​​the formed 1T1R memory device cell is close to the area of ​​the next smallest transistor at the used process node.

Description

Technical Field

[0001] This application relates to the field of resistive random access memory (RRAM) fabrication technology, specifically to a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. Background Technology

[0002] Resistive Random Access Memory (RRAM), as an emerging non-volatile memory, has become one of the important candidates for next-generation memory technology due to its advantages such as simple structure, high storage density, fast operation speed, low power consumption, and great potential for compatibility with standard CMOS processes. Its basic working principle is based on a metal-insulator-metal (MIM) structure. By applying a specific voltage pulse between the upper and lower electrodes, the resistance value of the intermediate resistive switching functional layer (usually a dielectric material) can be reversibly switched between a high resistance state (HRS) and a low resistance state (LRS), thereby realizing the storage of data "0" and "1".

[0003] In existing technologies, to integrate with mainstream logic processes, RRAM device cells are typically fabricated in the back-end interconnect (BEOL) process of integrated circuits, i.e., located above active devices such as transistors and between multiple layers of metal interconnects. For example, a typical method of integrating RRAM in the back-end process requires additional photomask steps, independent of the standard logic interconnect process, to define the top and bottom electrodes and the resistive switching functional layer region of the RRAM. While this approach of integrating RRAM as a separate layer in the back-end achieves separation from the front-end transistors, it typically requires at least two additional photomasks (e.g., for patterning the bottom electrode and resistive switching material stack), increasing process complexity and manufacturing costs.

[0004] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0005] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a method for forming a semiconductor structure, a semiconductor structure, and an electronic device.

[0006] This application provides a method for forming a semiconductor structure, including the following steps: S1. A substrate having completed gate fabrication and source / drain ion implantation for at least two transistors, wherein the at least two transistors have a common source / drain region. S2. Sequentially deposit the etch stop layer and the first interlayer dielectric layer, and planarize the first interlayer dielectric layer; S3. Patterning is performed using a single photomask to form openings in the first interlayer dielectric layer and the etch stop layer above the common source / drain region to expose the common source / drain region; S4. Sequentially deposit the first electrode material and the resistive switching functional layer material; S5. Using the gate sidewall of the transistor as a self-aligned mask, perform anisotropic dry etching to remove the first electrode material and resistive switching functional layer material outside the gate sidewall, thereby forming a resistive switching memory stack on the sidewall surface of the two gate sidewalls above the common source and drain region. S6. Deposit a filler material layer, and then planarize the filler material layer; S7. Deposit the second interlayer dielectric layer and perform contact hole etching. Simultaneously, etch out the first contact hole connecting the source / drain region of the transistor and the second contact hole connecting the top of the resistive switching functional layer in the resistive switching memory stack, wherein the bottom of the second contact hole remains within the filling material layer. S8. Selectively etch back the filling material layer to expose a portion of the surface above the resistive switching functional layer; and S9. Fill the first contact hole and the second contact hole with conductive material to form contact plugs that are electrically connected to the transistor and the resistive switching functional layer, respectively, wherein the conductive material filled in the second contact hole constitutes the second electrode of the resistive switching memory.

[0007] In some embodiments, after step S1 and before step S2, the method further includes: Metal silicide layers are formed on the surface of the source and drain regions of the transistor.

[0008] In some embodiments, step S3 specifically includes: Deposit hard mask layer; The hard mask layer is patterned using the single photomask; Using a patterned hard mask layer as a mask, the first interlayer dielectric layer and the etch stop layer are etched sequentially to form the opening; Remove the hard mask layer.

[0009] In some embodiments, the material of the hard mask layer includes titanium nitride or silicon oxynitride.

[0010] In some embodiments, the materials of the first interlayer dielectric layer and the second interlayer dielectric layer are low dielectric constant materials.

[0011] In some embodiments, the material of the first interlayer dielectric layer / second interlayer dielectric layer includes ULK material or BD material.

[0012] In some embodiments, the etching rate of the filling material layer in the contact hole etching process is greater than the etching rate of the etch stop layer material, and less than the etching rates of the first interlayer dielectric layer and the second interlayer dielectric layer.

[0013] In some embodiments, the material of the filling material layer is silicon dioxide or silicon carbide.

[0014] In some embodiments, in step S9, the conductive material includes a barrier layer / adhesion layer and a contact hole metal material; The step of filling the first contact hole and the second contact hole with conductive material includes: A diffusion barrier layer / adhesion layer and contact hole metal material are sequentially deposited in the first contact hole, the second contact hole and the third contact hole.

[0015] This application also provides a semiconductor structure, including: Substrate; At least two transistors are formed on the substrate, and the at least two transistors have a common source-drain region between them; A resistive switching memory stack is formed above the common source-drain region and on the sidewall surface opposite to the gate sidewall of two adjacent transistors. The resistive switching memory stack includes a first electrode and a resistive switching functional layer stacked sequentially from the inside to the outside along the sidewall surface. A layer of filling material is placed between two opposing resistive switching memory stacks above the shared source / drain region; The second electrode is formed above the filler material layer and is in electrical contact with the resistive switching functional layer.

[0016] In some embodiments, the material of the first electrode includes at least one of metals Ti / Ta / W / Ru and their nitrides; The material of the resistive switching functional layer includes metal oxides.

[0017] In some embodiments, the material of the filling material layer is silicon dioxide or silicon carbide.

[0018] This application also provides an electronic device, including the semiconductor structure described in any of the above embodiments.

[0019] The semiconductor structure formation method, semiconductor structure, and electronic device proposed in this application form one electrode and resistive switching layer of an RRAM device through a self-aligned sidewall process. The other electrode is formed in a contact hole process module. To better form the contact between the contact hole electrode and the resistive switching layer, a filler material adjustment and re-etching step is proposed. The constructed RRAM device does not share resistive switching material, effectively reducing crosstalk between devices. Moreover, only one photomask is used to define the RRAM device, resulting in lower process costs than existing back-end based process solutions. In addition, since the RRAM cell is fabricated at the same level as the transistor, it is not subject to the thermal budget limitations of the back-end process. The device performance can be optimized and improved by introducing additional thermal treatment processes. The area of ​​the formed 1T1R memory device cell is close to the area of ​​the next smallest transistor in the process node used, and theoretically, an area efficiency of 4F^2 can be achieved. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure provided in this application.

[0021] Figure 2 This is a partial flowchart illustrating a method for forming a semiconductor structure provided in this application.

[0022] Figures 3 to 14 This is a schematic diagram of the semiconductor structure formed by each key process step in a semiconductor structure formation method provided in this application embodiment.

[0023] Figure 15 yes Figure 14 The equivalent circuit diagram of the semiconductor structure shown is illustrated. Detailed Implementation

[0024] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0025] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0026] To better understand this application, the research background of this application will be explained in detail below.

[0027] To further simplify processes, reduce costs, and increase integration density, the industry has begun exploring solutions for integrating RRAM devices with front-end transistors on the same or adjacent process layers. For example, one method for forming RRAM devices on the same layer as transistor devices aims to reduce process steps and the number of photomasks, and to build RRAM cells by sharing or adjusting the front-end process, thereby potentially achieving a more compact layout and lower manufacturing costs.

[0028] However, the aforementioned in-layer integration scheme still faces some challenges. For example, how to achieve seamless compatibility and high reliability with transistor processes while ensuring the performance of RRAM devices (such as switching uniformity and durability) is a key issue. Furthermore, in the above integration scheme, multiple RRAM cells share a continuous resistive switching material layer, which can easily lead to electrical crosstalk between cells in high-density arrays. That is, operations on one cell (such as reset or set) may interfere with the resistance state of neighboring cells through the shared resistive switching material layer, thereby affecting the reliability of stored data and the accuracy of read operations.

[0029] In summary, existing RRAM technologies, whether back-end independent integration or front-end co-layer integration, all have room for further optimization in terms of process cost, integration complexity, or electrical isolation performance between devices. Therefore, a new RRAM device structure and manufacturing method is needed that can achieve lower manufacturing costs, better process scalability, and effectively suppress inter-cell crosstalk in high-density arrays while maintaining good compatibility with standard processes.

[0030] Based on this, embodiments of this application provide a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. Through improved device structure and process methods, the technical problems of high process cost, limited process scalability, and significant inter-cell crosstalk in high-density arrays in the prior art are solved.

[0031] Figure 1 This is a schematic flowchart illustrating a method for forming a semiconductor structure provided in this application. Figure 1 As shown, this application provides a method for forming a semiconductor structure, including the following steps: S1. A substrate 1 is provided in which the gate 25 of at least two transistors has been fabricated and source / drain ion implanted, and the at least two transistors have a common source / drain region 23 between them; In step S1, for example, see Figure 3 The substrate 1, in which the transistor gate 25 has been fabricated and source / drain ion implanted, each of the gate 25 structures has a gate sidewall 21, and a common source / drain region 23 (which may be a Silicide or SiGe structure) is defined in the substrate 1 between at least two gate 25 structures.

[0032] In some embodiments, after step S1 and before step S2, the method may further include: forming a metal silicide layer 3 on the surface of the source and drain regions (including source / drain region 22 and common source / drain region 23) of the transistor. For example, see... Figure 3 The silicide formation step includes forming a metal silicide layer 3 on the surface of the source / drain region 22 and the common source / drain region 23 of the transistor to reduce the contact resistance of these regions.

[0033] S2. Sequentially deposit the etch stop layer 4 and the first interlayer dielectric layer 5, and planarize the first interlayer dielectric layer 5. In step S2, for example, such as Figure 4 As shown, Etch Stop Layer Deposition: An etch stop layer 4 is deposited across the entire wafer surface. This etch stop layer 4 can be formed from materials such as silicon nitride or silicon carbonitride, and serves to stop the etching process and protect the underlying structure during subsequent dielectric layer etching.

[0034] The material of the first interlayer dielectric layer 5 can be a low-dielectric-constant material (low-k material). Low-k materials refer to insulating materials with a dielectric constant lower than that of traditional silicon dioxide (SiO2, k≈3.9-4.2). For example, such as... Figure 5As shown, low-k deposition and chemical mechanical planarization (CMP) involves depositing a layer of low-dielectric-constant material (e.g., ULK (Ultra-Low-k, dielectric constant k ≤ 2.7), BD (Black Diamond, a low-dielectric-constant material, composed of Si, C, H, and O elements) as the interlayer medium, and then using a chemical mechanical planarization process to planarize its surface, preparing a smooth surface for subsequent photolithography and patterning steps.

[0035] S3. Patterning is performed using a single photomask to form an opening W in the first interlayer dielectric layer 5 and the etch stop layer 4 above the common source / drain region 23 to expose the common source / drain region 23. like Figure 2 As shown, step S3 may specifically include: S31, Deposit hard mask layer M; S32. The hard mask layer M is patterned using the single photomask; S33. Using the patterned hard mask layer M as a mask, the first interlayer dielectric layer 5 and the etch stop layer 4 are etched sequentially to form the opening W; S34. Remove the hard mask layer M.

[0036] Specifically, such as Figure 6 As shown, the RRAM region open is created by using photolithography (using a single photomask) and etching processes to open a window (opening W) above the common source / drain region 23 of the RRAM device. A hard mask layer M (such as TiN, SiON, etc.) is then used to cover the other areas. Figure 7 As shown, the next step is to remove the ESL (RRAM region) etch stop layer: remove the ESL etch stop layer 4 material at the bottom of the opened window (opening W) to expose the underlying silicide surface. Figures 7 to 8 As shown, the next step is hard mask removal: the hard mask layer M used to define the opening pattern of the RRAM region is removed, exposing the ESL etch stop layer 4 underneath.

[0037] S4. Sequentially deposit the first electrode material 6 and the resistive switching functional layer material 7; In step S4, for example, see Figure 9Electrode and resistive layer deposition is performed: the first electrode material 6 (which can be metal Ti / Ta / W / Ru and its nitrides) and the resistive switching functional layer material 7 (which can be H) constituting the RRAM device are sequentially deposited on the entire wafer surface. f Metal oxide materials such as O2 and Ta2O5).

[0038] S5. Using the gate sidewall 21 of the transistor as a self-aligned mask, perform anisotropic dry etching to remove the first electrode material 6 and the resistive switching functional layer material 7 on the outside of the gate sidewall 21, thereby forming a resistive switching memory stack r on the sidewall surface of the two gate sidewalls 21 above the common source-drain region 23. In step S5, for example, such as Figures 9 to 10 As shown, self-aligned etching: using the existing gate sidewall 21 structure of the transistor as a self-aligned mask, anisotropic dry etching is performed. This step etches away the first electrode material 6 and the resistive switching functional layer material 7 outside the gate sidewall 21, leaving only the resistive switching memory stack r above the common source / drain region 23, in the area blocked by the two gate sidewalls 21. This is a key step in achieving patterning without additional photomasks and device miniaturization.

[0039] S6. Deposit the filling material layer 9, and then planarize the filling material layer 9; In step S6, for example, see Figures 10 to 11 Filler deposition and planarization (CMP): A filler material layer 9 (filler) is deposited. The filler material is required to have an etching selectivity between Low-k and ESL materials in the contact hole etching process. Specifically, Low-k materials have the fastest etching rate, followed by filler materials, and ESL materials have the slowest etching rate. The filler material can be SiO2 or SiC, etc. After filler material filling, chemical mechanical planarization is performed again to restore the surface to flatness, while embedding and isolating the RRAM stack structure.

[0040] S7. Deposit the second interlayer dielectric layer 10 and perform contact hole etching. Simultaneously, etch out the first contact hole 11A connecting the source / drain region 22 of the transistor and the second contact hole 11C connecting the top of the resistive switching functional layer 7a in the resistive switching memory stack r. The bottom of the second contact hole 11C remains in the filling material layer 9. In step S7, the material of the second interlayer dielectric layer 10 can be a low dielectric constant material. For example, see... Figure 12Low-k dielectric redeposition and contact etch: A low-k dielectric layer is deposited again. Subsequently, using standard contact etch and etching processes, the first contact hole 11A connecting the source / drain regions of the transistor and the second contact hole 11C connecting the top of the resistive switching functional layer 7a in the resistive switching memory stack r are simultaneously etched. In addition, the third contact hole 11B connecting the gate 25 structure is also simultaneously etched. Due to the choice of the critical filler material, the second contact hole 11C in the RRAM device region stops above the filler, leaving a certain safe distance from the metal silicide layer 3.

[0041] S8. Perform selective back etching on the filling material layer 9 to expose part of the surface of the upper part of the resistive switching functional layer 7a; In step S8, for example, see Figures 12 to 13 Filler recess: After the contact hole etching, the filler filling medium formed in step S6 is selectively and with a controllable depth etched back. Step S8 aims to control the exposed area of ​​the top of the sidewall resistive switching functional layer 7a, removing the filler material covering it to prepare for the subsequent formation of a good and area-controllable interface between the contact hole metal material and the resistive switching layer. Step S8 is crucial for optimizing contact and device performance.

[0042] S9. Fill the first contact hole 11A and the second contact hole 11C with conductive material to form contact plugs that are electrically connected to the transistor and the resistive switching functional layer 7a, respectively, wherein the conductive material filled in the second contact hole 11C constitutes the second electrode E of the resistive switching memory R1 and R2.

[0043] In step S9, for example, see Figures 13 to 14 Contact formation: In the etched contact holes 11A, 11B, and 11C, a diffusion barrier layer / adhesion layer 12 and a contact hole metal material 13 are sequentially deposited, and contact plugs are formed through filling and planarization processes. The diffusion barrier layer / adhesion layer 12 and the contact hole metal material 13 in contact hole 11C, which are directly connected to the RRAM resistive switching functional layer 7a, constitute the second electrode E of the RRAM.

[0044] Finally, the resistive random access memory (RRAM) R1 and R2 were fabricated on the common source / drain region 23 of the transistor, and integrated with the transistor source / drain contacts. The entire process requires only one additional photomask, and the RRAM cells are naturally isolated with low crosstalk. Figure 15 yes Figure 14 The equivalent circuit diagram of the semiconductor structure shown is illustrated.

[0045] The semiconductor structure formation method provided in this application forms one electrode and a resistive switching layer of an RRAM device through a self-aligned sidewall process, while the other electrode is formed in a contact hole process module. To better form the contact between the contact hole electrode and the resistive switching layer, a filler material adjustment and re-etching step is proposed. The constructed RRAM device does not share a resistive switching material, effectively reducing crosstalk between devices. Moreover, only one photomask is used to define the RRAM device, resulting in lower process costs than existing back-end based process solutions. Furthermore, since the RRAM cell is fabricated at the same level as the transistor, it is not subject to the thermal budget limitations of the back-end process. The device performance can be optimized and improved by introducing additional thermal treatment processes. The area of ​​the formed 1T1R memory cell (1T1R cell0, 1T1R cell1) is close to the area of ​​the next smallest transistor in the process node used, and theoretically, an area efficiency of 4F^2 can be achieved.

[0046] Furthermore, since RRAM devices use a contact hole structure, there are no restrictions on transistor devices on the same layer. The transistors can be polysilicon transistor structures with nodes of 40nm and above, or planar High-kMetal Gate structures with nodes of 28nm, or FinFET structures with more advanced process nodes.

[0047] Based on the same inventive concept, embodiments of this application also provide a semiconductor structure. For example... Figure 14 As shown, an embodiment of this application provides a semiconductor structure 100, comprising: Substrate 1; At least two transistors are formed on the substrate 1, and the at least two transistors have a common source-drain region 23 between them; A resistive switching memory stack r is formed above the common source-drain region 23 and located on the opposite sidewall surfaces of two adjacent transistor gate sidewalls 21. The resistive switching memory stack r includes a first electrode 6a and a resistive switching functional layer 7a stacked sequentially from the inside to the outside along the sidewall surfaces. A layer of filling material 9 is filled between two opposing resistive switching memory stacks r above the common source / drain region 23; The second electrode E is formed above the filling material layer 9 and is in electrical contact with the resistive switching functional layer 7a.

[0048] In some embodiments, the material of the first electrode 6a includes at least one of metals Ti / Ta / W / Ru and their nitrides; the material of the resistive switching functional layer 7a includes metal oxides.

[0049] In some embodiments, the material of the filling material layer 9 is silicon dioxide or silicon carbide.

[0050] Since the semiconductor structure provided in this embodiment can be formed based on any of the methods described in the foregoing embodiments, it has the same technical effects as the semiconductor structure formed in the above method embodiments, and will not be described again here.

[0051] Based on the same inventive concept, embodiments of this application also provide an electronic device, including the semiconductor structure described in any of the above embodiments.

[0052] Since the electronic device provided in this embodiment includes the semiconductor structure, it can achieve the same technical effects as the semiconductor structure provided in the above embodiments, and will not be described again here.

[0053] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0054] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, Includes the following steps: S1. A substrate having completed gate fabrication and source / drain ion implantation for at least two transistors, wherein the at least two transistors have a common source / drain region. S2. Sequentially deposit the etch stop layer and the first interlayer dielectric layer, and planarize the first interlayer dielectric layer; S3. Patterning is performed using a single photomask to form openings in the first interlayer dielectric layer and the etch stop layer above the common source / drain region to expose the common source / drain region; S4. Sequentially deposit the first electrode material and the resistive switching functional layer material; S5. Using the gate sidewall of the transistor as a self-aligned mask, perform anisotropic dry etching to remove the first electrode material and resistive switching functional layer material outside the gate sidewall, thereby forming a resistive switching memory stack on the sidewall surface of the two gate sidewalls above the common source and drain region. S6. Deposit a filler material layer, and then planarize the filler material layer; S7. Deposit the second interlayer dielectric layer and perform contact hole etching. Simultaneously, etch out the first contact hole connecting the source / drain region of the transistor and the second contact hole connecting the top of the resistive switching functional layer in the resistive switching memory stack, wherein the bottom of the second contact hole remains within the filling material layer. S8. Selectively etch back the filling material layer to expose part of the surface of the upper part of the resistive switching functional layer; S9. Fill the first contact hole and the second contact hole with conductive material to form contact plugs that are electrically connected to the transistor and the resistive switching functional layer, respectively, wherein the conductive material filled in the second contact hole constitutes the second electrode of the resistive switching memory.

2. The method according to claim 1, characterized in that, After step S1 and before step S2, the method further includes: Metal silicide layers are formed on the surface of the source and drain regions of the transistor.

3. The method according to claim 1, characterized in that, Step S3 specifically includes: Deposit hard mask layer; The hard mask layer is patterned using the single photomask; Using a patterned hard mask layer as a mask, the first interlayer dielectric layer and the etch stop layer are etched sequentially to form the opening; Remove the hard mask layer.

4. The method according to claim 3, characterized in that, The material of the hard mask layer includes titanium nitride or silicon oxynitride.

5. The method according to claim 1, characterized in that, The materials of the first interlayer dielectric layer and the second interlayer dielectric layer are low dielectric constant materials.

6. The method according to claim 1 or 5, characterized in that, The material of the first interlayer dielectric layer / second interlayer dielectric layer includes ULK material or BD material.

7. The method according to claim 1, characterized in that, The etching rate of the filling material layer in the contact hole etching process is greater than the etching rate of the etch stop layer material, but less than the etching rates of the first interlayer dielectric layer and the second interlayer dielectric layer.

8. The method according to claim 1 or 7, characterized in that, The filling material layer is made of silicon dioxide or silicon carbide.

9. The method according to claim 1, characterized in that, In step S9, the conductive material includes a barrier layer / adhesive layer and a contact hole metal material; The step of filling the first contact hole and the second contact hole with conductive material includes: A diffusion barrier layer / adhesion layer and contact hole metal material are sequentially deposited in the first contact hole, the second contact hole and the third contact hole.

10. A semiconductor structure, characterized in that, include: Substrate; At least two transistors are formed on the substrate, and the at least two transistors have a common source-drain region between them; A resistive switching memory stack is formed above the common source-drain region and on the sidewall surface opposite to the gate sidewall of two adjacent transistors. The resistive switching memory stack includes a first electrode and a resistive switching functional layer stacked sequentially from the inside to the outside along the sidewall surface. A layer of filling material is placed between two opposing resistive switching memory stacks above the shared source / drain region; The second electrode is formed above the filler material layer and is in electrical contact with the resistive switching functional layer.

11. The semiconductor structure according to claim 10, characterized in that, The material of the first electrode includes at least one of the following: metals Ti / Ta / W / Ru and their nitrides; The material of the resistive switching functional layer includes metal oxides.

12. The semiconductor structure according to claim 10, characterized in that, The filling material layer is made of silicon dioxide or silicon carbide.

13. An electronic device, characterized in that, Includes the semiconductor structure described in any one of claims 10 to 12.

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