Time window test comparison method, system and signal detection circuit

Abstract

This application provides a time window test comparison method, system, and signal detection circuit. It includes acquiring edge transition information of the signal under test (DUT) output by the device under test (DUT) within a time window, and collecting sampled values ​​of the DUT at test moments within the time window. Then, based on the sampled values, the expected value corresponding to the time window, and the edge transition information, the test result of the DUT is determined. By acquiring transition information that reflects the edge transitions of the DUT within the time window, and combining this with the sampled values ​​and expected values ​​at test moments for comprehensive judgment, the signal transitions occurring in the DUT throughout the entire time window can be effectively identified. This overcomes the omission of signal transitions occurring at other moments within the time window caused by relying solely on single-point sampling at the test moment. Therefore, it achieves a true and comprehensive reflection of the stability of the DUT within the time window, significantly improving the accuracy and reliability of chip testing.

Description

Technical Field

[0001] This application relates to chip testing technology, and in particular to a time window test comparison method, system, and signal detection circuit. Background Technology

[0002] The stability of a chip's output signal is a key indicator of its performance; therefore, detecting the stability of the chip's output signal is an important part of chip testing. Related technologies typically employ a single-point sampling method, where the chip's output signal is sampled at a fixed sampling time within each test cycle, and the sampled value is compared with a preset expected value to determine whether the chip's output signal is stable, thereby confirming whether the chip is functioning correctly.

[0003] However, single-point sampling can only reflect the signal state at the moment of sampling and cannot detect signal transitions that occur outside the single-point sampling moment during the test cycle. For example, if a brief level transition occurs in the signal during the test cycle but the transition does not fall within the sampling moment, single-point sampling cannot identify this transition. This results in the test results not accurately reflecting the stability of the chip's output signal, thus affecting the accuracy of chip testing. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of this application provide a time window test comparison method, system, and signal detection circuit.

[0005] One aspect of this application provides a time window test comparison method, comprising: acquiring edge transition information of a signal under test output by a device under test within a time window; collecting sampled values ​​of the signal under test at test times within the time window; and determining the test result of the device under test within the time window based on the sampled values, the expected value corresponding to the time window, and the edge transition information.

[0006] Another aspect of this application provides a signal detection circuit, comprising: a frequency division module for receiving a test signal output by a device under test (DUT) within a time window, performing N-level frequency division processing on the test signal, and outputting a frequency-divided signal; a system clock module for outputting a master clock; a frequency division sampling module for acquiring and storing signal output values ​​of at least one level of frequency division based on edge information of the frequency-divided signal and edge information of the master clock, determining the number of toggles of the test signal based on the edge information of the frequency-divided signal, and constructing edge transition information of the test signal based on the signal output value and the number of toggles; and a signal sampling module for acquiring sampled values ​​of the test signal at test times within the time window.

[0007] In another aspect of this application, a time window comparison system is provided, comprising: a vector generator, configured to output a time window and a corresponding expected value stored in a storage device to a timing generator; the timing generator, configured to, when receiving a test signal output by a device under test (DUT), detect edge transition information of the test signal within the time window, and collect sampled values ​​of the test signal at test times within the time window; and determine the test result of the DUT within the time window based on the sampled values, the expected value, and the edge transition information.

[0008] The time window test comparison method, system, and signal detection circuit in this application embodiment include: acquiring edge transition information of the signal under test (DUT) output by the device under test (DUT) within a time window; collecting sampled values ​​of the DUT at test moments within the time window; and then determining the test result of the DUT based on the sampled values, the expected value corresponding to the time window, and the edge transition information. Therefore, by acquiring transition information that reflects the edge transitions of the DUT within the time window and combining it with the sampled values ​​and expected values ​​at test moments for comprehensive judgment, the signal transitions of the DUT within the entire time window can be effectively identified. This overcomes the omission of signal transitions occurring at other moments within the time window caused by relying solely on single-point sampling at the test moment, thus achieving a true and comprehensive reflection of the stability of the DUT within the time window and significantly improving the accuracy and reliability of chip testing.

[0009] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0010] The accompanying drawings, which form part of this specification, illustrate embodiments of this application and, together with the description, serve to explain the principles of this application.

[0011] This application can be more clearly understood with reference to the accompanying drawings and the following detailed description, wherein: Figure 1 This is a flowchart illustrating a time window test comparison method provided in an exemplary embodiment of this application.

[0012] Figure 2 This is a flowchart illustrating step S100 provided in an exemplary embodiment of this application.

[0013] Figure 3 This is a flowchart illustrating step S101 provided in an exemplary embodiment of this application.

[0014] Figure 4 This is a schematic diagram of the structure of a signal detection circuit provided in an exemplary embodiment of this application.

[0015] Figure 5This is a schematic diagram of the structure of a frequency divider module provided in an exemplary embodiment of this application.

[0016] Figure 6 This is a schematic diagram of the structure of a high-level sampling chain provided in an exemplary embodiment of this application.

[0017] Figure 7 This is a schematic diagram of the structure of the first frequency divider unit provided in an exemplary embodiment of this application.

[0018] Figure 8 This is a schematic diagram of the structure of a low-level sampling chain provided in an exemplary embodiment of this application.

[0019] Figure 9 This is a schematic diagram of the signal detection circuit provided in an application example of this application.

[0020] Figure 10 This is a schematic diagram of the high-level sampling chain provided in an application example of this application.

[0021] Figure 11 This is a schematic diagram of another high-level sampling chain provided in an application example of this application.

[0022] Figure 12 This is a schematic diagram of the waveform of the signal under test provided in an exemplary embodiment of this application.

[0023] Figure 13 This is a schematic diagram of the FPGA structure provided in an application example of this application.

[0024] Figure 14 This is a schematic diagram of the time window test comparison method provided in an application example of this application.

[0025] Figure 15 This is a schematic diagram of the structure of a time window comparison system provided in an exemplary embodiment of this application.

[0026] Figure 16 This is a schematic diagram of the structure of an application embodiment of the electronic device of this application. Detailed Implementation

[0027] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present application.

[0028] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this application are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0029] It should also be understood that in the embodiments of this application, "multiple" can refer to two or more, and "at least one" can refer to one, two or more.

[0030] It should also be understood that any component, data or structure mentioned in the embodiments of this application can generally be understood as one or more unless explicitly defined or given contrary guidance in the context.

[0031] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects have an "or" relationship.

[0032] It should also be understood that the description of the various embodiments in this application emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0033] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0034] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this application and its application or use.

[0035] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0036] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0037] In the process of developing this application, it was discovered that single-point sampling can only reflect the signal state at the sampling moment and cannot detect signal transitions occurring at other times within the test cycle. For example, when testing whether the chip output signal is high within a 5ns test cycle, if the sampling moment is set at 2ns and the sampled value is high, but the chip output signal is briefly low between 1ns and 1.6ns, and the duration of this brief low level (0.6ns) is less than the test cycle, the single-point sampling method cannot capture this transition and will still determine the test result as passed. This leads to the missed detection of signal stability issues, affecting the accuracy of chip testing.

[0038] Figure 1This is a schematic flowchart of a time window test comparison method provided in an exemplary embodiment of this application. This embodiment can be applied to electronic devices, such as... Figure 1 As shown, this time window test comparison method may include the following steps: Step S100: Obtain the edge transition information of the signal under test output by the device under test within the time window.

[0039] The device under test (DUT) can include, for example, a chip, wafer, or integrated circuit. The signal under test (SUT) is an electrical signal output by the DUT that needs to be captured and analyzed. For example, the SUT can be a clock signal, data signal, control signal, address signal, or status indication signal. The time window is a preset continuous time period with an initial and an end time. The time window can be, for example, a single test cycle (pattern cycle), any time interval within a test cycle, or an integer multiple of the master clock cycle. The master clock is generated by the system clock (Local clock) and is used to provide a timing reference for signal acquisition during the testing process of the DUT. Edge transition information indicates the changes in the logic level edges of the SUT within the time window. For example, edge transition information can include whether an edge transition occurred in the SUT within the time window and / or the number of edge transitions.

[0040] The device under test (DUT) can be connected to a pin electronic (PE) chip. Before acquiring the edge transition information of the DUT signal, the PE chip can preprocess the DUT signal. For example, the PE chip can adjust the voltage and / or current parameters of the DUT signal to eliminate distortion or glitches, making the DUT signal waveform smoother and more stable, thereby improving the accuracy of the subsequently determined edge transition information. Any edge transition detection method can be used to acquire the edge transition information of the DUT signal within a time window. For example, a high-speed synchronous sampling method can be used to acquire the edge transition information of the DUT signal. This involves continuously sampling the signal based on a sampling clock frequency higher than the highest frequency of the DUT signal (e.g., 5 to 10 times higher), obtaining a sequence of signal values ​​representing the change of the DUT signal level over time. Then, by analyzing the logical changes of adjacent signal values, the total number of edge transitions within the time window is counted as the edge transition information.

[0041] In one implementation, the time window test comparison method of this embodiment can be applied to a chip testing device. Chip testing devices are used to test the functionality and performance of chips, wafers, or integrated circuits. For example, a chip testing device can be an Automatic Test Equipment (ATE).

[0042] Step S110: Collect the sampled value of the signal under test at the test time within the time window.

[0043] Here, the sampled value refers to the instantaneous level value of the signal under test at the test moment, which is a specified moment within a time window. Specifically, the signal under test can be sampled based on the master clock to obtain the sampled value. For example, the current level value of the signal under test can be acquired at the effective edge (rising edge or falling edge) of the master clock and output and stored as the sampled value.

[0044] Step S120: Based on the sampled value, the expected value corresponding to the time window, and the edge transition information, determine the test result of the device under test within the time window.

[0045] In one implementation, the expected value (expected level value) corresponding to a time window can be obtained from the test vector (pattern) applied to the chip under test. The test result may include whether the chip under test passes or fails the test.

[0046] Signal stability judgment rules can be preset, and the test result can be determined based on the sampled value, expected value, and edge transition information using these rules. For example, if the sampled value is consistent with the expected value, and the edge transition information indicates that no edge transition occurred in the signal under test within the time window, the test result of the chip under test is determined to be a pass. Otherwise, if the sampled value is inconsistent with the expected value, and / or the edge transition information indicates that an edge transition exists, the chip under test is determined to be a fail.

[0047] In this embodiment, by acquiring transition information that reflects the edge transition of the signal under test within a time window, and combining the sampled value and expected value at the test moment for comprehensive judgment, the signal transition of the signal under test within the entire time window can be effectively identified. This overcomes the omission of signal transitions occurring at other times within the time window caused by relying solely on single-point sampling at the test moment, thereby achieving a true and comprehensive reflection of the stability of the signal under test within the time window and significantly improving the accuracy and reliability of chip testing.

[0048] Figure 2 This is a flowchart illustrating step S100 provided in an exemplary embodiment of this application. In some alternative embodiments, such as Figure 2 As shown, step S100 may include the following steps: Step S101: Perform N-level frequency division processing on the signal under test to obtain at least one level of frequency division signal output value and the number of flips of the signal under test.

[0049] Where N is a positive integer greater than or equal to 1. Each level of frequency division divides the input signal by 2 and outputs the corresponding divided signal. By performing N levels of frequency division on the signal under test, the frequency of the signal under test can be divided to the power of 2.

[0050] For example, N series-connected frequency divider circuits can be used to perform N-level frequency division on the signal under test. Specifically, the first-level frequency division process takes the signal under test as input, divides it by two using the frequency divider circuit, and outputs the first-level divided signal. The second-level frequency division process takes the divided signal corresponding to the first-level frequency division as clock input, divides it by two using the frequency divider circuit, and outputs the second-level divided signal, and so on, with the Nth-level frequency division process outputting the Nth-level divided signal. The signal output value of each level of frequency division can be obtained by detecting the edge change (rising edge or falling edge) of the frequency division signal at that level. Specifically, at each valid edge (rising edge or falling edge) of the frequency division signal, the instantaneous level value of the frequency division signal at the corresponding moment is collected as the signal output value of that level of frequency division. At each valid edge of the master clock, the instantaneous level value of each level of frequency division signal is synchronously collected as the signal output value. Both are signal output values.

[0051] The number of transitions of the signal under test refers to the number of times the signal under test changes level within a time window. Each transition of the signal under test from high level to low level (falling edge) or from low level to high level (rising edge) is counted as one transition.

[0052] Step S102: Construct edge transition information based on the signal output value of at least one level of frequency division and the number of toggles.

[0053] The edge transition information includes the signal output value of at least one level of frequency division and the number of transitions of the signal under test.

[0054] In this embodiment, by performing N-level frequency division processing on the signal under test, the transition events of the signal under test within the time window are converted into low-frequency frequency division signals step by step. Based on the signal output values ​​of each level of frequency division and their number of reversals, edge transition information reflecting the transition situation of the signal under test is accurately constructed, realizing reliable capture and quantization of ultra-short pulses. This significantly improves the accuracy and comprehensiveness of testing the stability of the chip output signal and effectively overcomes the technical defect of single-point sampling method, which can only reflect the signal state at the sampling moment and cannot detect signal transitions at other times within the window.

[0055] Figure 3 This is a flowchart illustrating step S101 provided in an exemplary embodiment of this application. In some alternative embodiments, such as Figure 3 As shown, step S101 may include the following steps: Step S1011: Receive the input master clock.

[0056] Among them, the master clock is the one that receives the output of the system clock.

[0057] Step S1012: The signal to be tested is used as the clock input for the first-stage frequency division. Frequency division is performed based on the edge information of the clock input to obtain the first-stage frequency division signal. Based on the edge information of the frequency division signal and the edge information of the master clock, the output value of the first-stage frequency division signal is collected.

[0058] This method employs N cascaded frequency divider units to perform N-level frequency division processing on the signal under test, with each frequency divider unit performing a divide-by-two operation. Each frequency divider unit may include a flip-flop and an inverter. The inverter logically inverts the signal output by the flip-flop and feeds the inverted signal back to the flip-flop's data input. The flip-flop can be, for example, a D flip-flop, and the inverter can be, for example, a look-up table (LUT). Edge information may include rising or falling edges. Specifically, at each valid edge of the divided signal, i.e., when the edge information indicates a rising or falling edge, the current level value of the divided signal is captured as the output value of that level of frequency division. Similarly, at each valid edge of the master clock, i.e., when the edge information indicates a rising or falling edge, the current level value of the divided signal is captured as the output value of that level of frequency division.

[0059] In one example, the specific working process of the first-level frequency division is as follows: At the initial moment of the time window (denoted as T0), the data input terminal (D terminal) of the flip-flop is initialized to 0; the signal to be measured is used as the clock input (sampling clock) and connected to the clock input terminal (C terminal) of the flip-flop.

[0060] When the first valid edge of the clock input (e.g., the rising edge) arrives, the flip-flop samples the current value of the D terminal (i.e., the initial value 0) and latches this sampled value to the output terminal (Q terminal). At this time, the latched value 0 output by the Q terminal is the frequency division signal generated by the first-stage frequency divider. This frequency division signal is output to the frequency divider unit of the second-stage frequency divider and sent to the inverter. The inverter performs an inversion operation on the frequency division signal to obtain the logic value 1, and feeds the inverted signal back to the D terminal of the flip-flop, updating the D terminal to 1. When the second valid edge of the clock input arrives, the flip-flop samples the current value of the D terminal again (this time it is 1) and latches this value to the Q terminal, updating the Q terminal to 1. The output is updated to a frequency divider signal of 1. At this time, the frequency divider signal output from Q changes from 0 to 1, generating a rising edge. The latch value 1 corresponding to this rising edge (i.e., the current level value of the frequency divider signal) is acquired and stored as the signal output value of the first-stage frequency divider. Simultaneously, one path of this frequency divider signal is fed back to the inverter to be inverted, obtaining a logic value of 0, which is fed back to the D terminal, restoring the D terminal to 0. The other path is sent to the frequency divider unit of the second-stage frequency divider. This process is repeated, and the output signal of Q terminal completes a complete 0→1→0 flip every two clock input cycles, thereby achieving a 2-fold frequency divide of the input signal (the signal under test), that is, the frequency of the frequency divider signal output from Q terminal is half the frequency of the signal under test. In addition, in response to the arrival of the rising edge of the master clock, the current level value of the frequency divider signal currently output from Q terminal is acquired and stored as the signal output value. That is, the signal output value of the current stage of frequency divider includes the latch value (i.e., the current level value) acquired when the frequency divider signal has a rising edge and the level value of the current frequency divider signal when the master clock has a rising edge.

[0061] Step S1013, Second to N-1 level frequency division execution: The frequency division signal of the previous level is used as the clock input, and frequency division processing is performed based on the edge information of the clock input to obtain the frequency division signal of this level. Based on the edge information of the frequency division signal and the edge information of the master clock, the signal output value of this level frequency division is collected.

[0062] In one implementation, in the second to N-1th level frequency division, each level of frequency division uses the frequency division signal of the previous level as the clock input, which is then connected to the clock input terminal of the frequency division unit of the current level for frequency division by two. The frequency division method and the acquisition and storage method of the signal output value of the second to N-1th levels of frequency division are the same as those of the first level of frequency division. Please refer to the processing method of the first level of frequency division, which will not be repeated here.

[0063] Step S1014, Nth level frequency division execution: The frequency division signal of the (N-1)th level frequency division is used as the clock input. Based on the edge information of the clock input, the frequency division signal of the Nth level frequency division is determined. Based on the edge information of the frequency division signal, the number of toggles is obtained.

[0064] The number of flips of the signal under test is obtained by the effective edge (e.g., rising edge) of the Nth-level frequency divider signal. Specifically, the Nth-level frequency divider unit takes the (N-1)th-level frequency divider signal as its clock input, divides it by two to generate the Nth-level frequency divider signal; within the time window, each time a rising edge (or falling edge) of the Nth-level frequency divider signal is detected, a flip is recorded by a counter. At the end of the time window, the accumulated value of the counter is the number of flips of the signal under test within the time window.

[0065] In this embodiment, by performing N-level frequency division processing on the signal under test, the high-frequency edge transitions of the signal under test are gradually converted into low-frequency frequency division signals. This enables reliable capture of ultra-short pulse transitions (such as picosecond-level glitches) occurring at any moment within the time window without relying on ultra-high sampling rates. This significantly improves the comprehensiveness and accuracy of signal stability testing and reduces the implementation cost and complexity of the test hardware.

[0066] In some alternative implementations, the method may further include the following steps before step S1012 in this application embodiment: in response to the signal under test being at a high level, performing the operation of using the signal under test as the clock input for the first-stage frequency division; or, in response to the signal under test being at a low level, inverting the signal under test and using the inverted signal under test as the clock input for the first-stage frequency division.

[0067] Specifically, the signal under test can be determined to be high when the level value of the signal under test is 1, and low when the level value of the signal under test is 0; or, the signal under test can be determined to be high when the level value of the signal under test is higher than or equal to a preset level threshold, and low when the level value of the signal under test is lower than the level threshold.

[0068] For example, when the signal to be tested is received, the signal to be tested can be determined first. If the signal to be tested is high, the signal to be tested is used as a clock input and connected to the clock input terminal of the first frequency divider unit, and steps S1012-S1014 are executed. If the signal to be tested is low, the signal to be tested is first inverted by an inverter, and then the inverted signal to be tested is used as a clock input and connected to the clock input terminal of the first frequency divider unit, and steps S1012-S1014 are executed.

[0069] In this embodiment, the test signals with different level polarities are uniformly converted into the same edge direction (such as rising edge) by inversion processing as the clock input for frequency division, thereby ensuring that the frequency division always works under the condition of consistent edges, simplifying the circuit design of subsequent multi-level frequency division and edge counting (flipping number), realizing compatibility with both high-level active and low-level active signal types, and improving the adaptability and reliability of signal stability testing without increasing hardware complexity.

[0070] In some optional implementations, the method for determining the signal output value in this application embodiment may include: in response to the edge information of the frequency divider signal meeting a preset trigger condition, or the edge information of the master clock meeting a preset trigger condition, using the current level value of the frequency divider signal as the signal output value; or, in response to the edge information of the frequency divider signal meeting a preset trigger condition, or the edge information of the master clock meeting a preset trigger condition, inverting the current level value of the frequency divider signal and using it as the signal output value.

[0071] For both the frequency division signal and the master clock, the rising edge or falling edge can be selected as the preset trigger condition to control the acquisition of the signal output value. For example, when the signal under test is low, for the first to N-1th frequency division levels, when the frequency division signal of the current level has a rising edge (meeting the preset trigger condition), the trigger register acquires the current level value of the frequency division signal and stores it as the signal output value of the current level; and when the master clock has a rising edge (meeting the preset trigger condition), the registers of each frequency division level are triggered to acquire the current level value of each frequency division signal respectively, and store these level values ​​as the signal output value of the corresponding frequency division level. When the signal under test is high, for the first to N-1th level frequency division processing, when the frequency division signal of the current level occurs with a rising edge, the trigger register collects the inverted value of the current level of the frequency division signal and stores it as the signal output value of the current level. When the master clock occurs with a rising edge, the registers of each level of frequency division are triggered, and the inverted values ​​of the current level of each frequency division signal are collected respectively, and these inverted values ​​are stored as the signal output values ​​of the corresponding level of frequency division.

[0072] In this embodiment of the application, by introducing a configurable signal output value acquisition method, the frequency division signal level value can be directly acquired or inverted before acquisition, thereby significantly enhancing the compatibility and adaptability to signals of different polarities.

[0073] In some optional implementations, step S120 in this application embodiment may include: in response to the inconsistency between the sampled value and the expected value, or the inconsistency between the signal output value of at least one level of frequency division and the corresponding signal output value in the previous time window, or the inconsistency between the number of flips and the number of flips in the previous time window, determining that the test result is that the device under test has failed the test.

[0074] The previous time window refers to an adjacent time window in the test process that has been completed chronologically before the current time window. Inconsistency between the signal output value of at least one frequency division and the corresponding signal output value in the previous time window means that, for any m-th frequency division (a positive integer 1 ≤ m ≤ N), the signal output value collected by that frequency division in the current time window is compared with the signal output value collected by the same frequency division in the previous adjacent time window; if they differ, they are considered inconsistent.

[0075] For example, if the sampled value is equal to the expected value, but the signal output value of at least one frequency divider is inconsistent with the corresponding signal output value in the previous time window, the test result of the device under test (DUT) within the time window is determined to be a failed test; or, if the sampled value is not equal to the expected value, the test result of the DUT within the time window is determined to be a failed test; or, if the sampled value is equal to the expected value, the signal output value of each frequency divider is consistent with the corresponding signal output value in the previous time window, but the number of flips is inconsistent with the number of flips in the previous time window, the test result of the DUT within the time window is determined to be a failed test; if the sampled value is consistent with the expected value, the signal output value of each frequency divider is consistent with the corresponding signal output value in the previous time window, and the number of flips is consistent with the number of flips in the previous time window, the test result of the DUT within the time window is determined to be a passed test.

[0076] In this embodiment, by comprehensively comparing the consistency of the sampled values, the signal output values ​​of each frequency division, and the changes in the number of flips, a multi-dimensional determination of the stability of the signal under test within the time window is achieved. This effectively captures signal jumps that occur at any moment within the window, significantly improving the comprehensiveness and accuracy of the test and ensuring reliable detection of dynamic timing defects in the chip.

[0077] Figure 4 This is a schematic diagram of the structure of a signal detection circuit provided in an exemplary embodiment of this application. Figure 4 As shown, the signal detection circuit 200 includes: a frequency division module 210, a system clock module 220, a frequency division sampling module 230, and a signal sampling module 240.

[0078] The frequency divider module 210 is used to receive the test signal output by the device under test within the time window, and to perform N-level frequency division processing on the test signal to output the frequency divided signal.

[0079] The frequency divider module 210 is used to perform N-level frequency division processing on the signal under test and output the frequency-divided signals generated by each level of frequency division. In one example, the frequency divider module 210 is electrically connected to the PE chip, and the PE chip is electrically connected to the device under test. The PE chip receives the signal under test output by the device under test and performs preprocessing. Then, the PE chip transmits the preprocessed signal under test to the frequency divider module 210 for it to perform N-level frequency division processing.

[0080] The system clock module 220 is used to output the master clock. The system clock module 220 is electrically connected to the frequency division sampling module 230, and the system clock module 220 sends the master clock to the frequency division sampling module 230.

[0081] The frequency division sampling module 230 is used to collect and store the signal output value of at least one level of frequency division based on the edge information of the frequency division signal and the edge information of the master clock, determine the number of toggles of the signal under test based on the edge information of the frequency division signal, and construct the edge transition information of the signal under test based on the signal output value and the number of toggles.

[0082] The frequency division sampling module 230 is electrically connected to the frequency division module 210. For each level of frequency division, when the rising edge of the frequency division signal of that level occurs, the frequency division sampling module 230 collects the current level value of the frequency division signal of that level and stores it as the signal output value of that level; and when the rising edge of the master clock occurs, the frequency division sampling module 230 collects the current level value of the frequency division signal of each level of frequency division and stores these current values ​​as the corresponding frequency division signal output value.

[0083] The frequency division sampling module 230 can determine the number of flips based on the edge information of the frequency division signal at any level of frequency division. For example, within a time window, each rising edge of the frequency division signal at any level of frequency division is considered as a flip. The frequency division sampling module 230 accumulates and records the number of flips. At the end of the window, it determines the number of flips of the signal under test within the time window based on the accumulated number of flips.

[0084] The signal sampling module 240 is used to collect the sampled values ​​of the signal under test at the test time within the time window.

[0085] The signal sampling module 240 is electrically connected to the device under test (DUT) and is used to capture the current level value of the signal under test at the test moment and store it as a sample value. In one implementation, the signal sampling module 240 can be electrically connected to a PE chip, which in turn is electrically connected to the DUT. The signal sampling module 240 can be, for example, a register.

[0086] In one embodiment, the aforementioned steps S100 and S110 can be implemented by the signal detection circuit 200 of this embodiment. The frequency division module 210, the system clock module 220, and the frequency division sampling module 230 cooperate to acquire edge transition information; the signal sampling module 240 acquires the sampled values.

[0087] In this embodiment, the frequency divider module performs N-level frequency division processing on the signal under test, converting high-frequency transition events in the signal under test into low-frequency frequency divider signals step by step, effectively reducing the requirements on circuit processing speed. At the same time, with the help of the frequency divider sampling module, based on the dual triggering mechanism of the edge information of the frequency divider signal and the edge information of the master clock, the signal output values ​​of each level of frequency division are flexibly collected, and the number of flips of the signal under test is accurately obtained by combining the edge information of the frequency divider signal, thereby constructing comprehensive edge transition information. In addition, with the sampling value collected by the signal sampling module at the test time, this circuit can realize multi-dimensional detection of the complete stability of the signal under test (including instantaneous level and dynamic transition) within the time window, effectively overcoming the defect of the traditional single-point sampling method that cannot capture signal transitions at other times within the window, and significantly improving the accuracy and reliability of chip testing.

[0088] In some alternative implementations, in the embodiments of this application, the signal sampling module 240 is specifically used to sample the signal to be tested based on the edge information of the master clock, obtain the sampled value, and store the sampled value.

[0089] The system clock module 220 is also electrically connected to the signal sampling module 240, supplying the master clock to the signal sampling module 240. For example, the test time can be aligned with the rising edge of the master clock output by the system clock module 220. Thus, when each rising edge of the master clock arrives, the signal sampling module 240 is triggered to immediately sample the signal under test, obtain its current level value as the sample value of the test time, and store it.

[0090] Figure 5 This is a schematic diagram of a frequency divider module provided in an exemplary embodiment of this application. In some alternative embodiments, such as… Figure 5 As shown, the frequency divider module 210 may include a high-level sampling chain 211 and a low-level sampling chain 212. The high-level sampling chain 211 is used to perform N-level frequency division processing on the signal under test when the signal under test is high; the low-level sampling chain 212 is used to perform N-level frequency division processing on the signal under test when the signal under test is low.

[0091] The high-level sampling chain 211 and the low-level sampling chain 212 are electrically connected to the device under test. When the signal under test is high, the signal under test is sent to the high-level sampling chain 211, which performs N-level frequency division on the signal under test. When the signal under test is low, the signal under test is sent to the low-level sampling chain 212, which performs N-level frequency division on the signal under test.

[0092] In one embodiment, the signal detection circuit 200 may further include a level determination module, which is electrically connected to the high-level sampling chain 211, the low-level sampling chain 212, and the device under test (DUT). The DUT transmits the signal to be tested to the level determination module, which determines the level type of the signal to be tested and sends the signal to the corresponding sampling chain accordingly. For example, when the level value of the signal to be tested is 1, or its level value is higher than or equal to the level threshold, the level determination module determines that the signal to be tested is high and transmits the signal to be tested to the high-level sampling chain 211. When the level value of the signal to be tested is 0, or its level value is lower than the level threshold, the level determination module determines that the signal to be tested is low and transmits the signal to be tested to the low-level sampling chain 212.

[0093] Figure 6 This is a schematic diagram of the structure of a high-level sampling chain provided in an exemplary embodiment of this application. In some alternative embodiments, such as... Figure 6 As shown, the high-level sampling chain 211 may include N cascaded first frequency division units 2111, and the frequency division sampling module 230 includes multiple first sampling units 231 and a first counting unit 232. Each first sampling unit 231 is electrically connected to any first frequency division unit other than the Nth-level first frequency division unit, and the first counting unit 232 is electrically connected to the Nth-level first frequency division unit 2111.

[0094] For example, Figure 7 This is a schematic diagram of the structure of the first frequency divider unit provided in an exemplary embodiment of this application. Figure 7 As shown, each first frequency divider unit 2111 may include a D flip-flop and a LUT inverter. In each first frequency divider unit, the clock input of the D flip-flop receives a clock input (Clk), and the data output of the D flip-flop outputs a frequency divider signal (Data_o). One path of this frequency divider signal is fed into the LUT inverter, which logically inverts the received frequency divider signal to generate an inverted frequency divider signal (Data_in), and feeds it back to the data input of the D flip-flop. The other path of this frequency divider signal is used as the output of the first frequency divider unit of this stage and sent to the next first-stage frequency divider unit.

[0095] The first-stage first frequency divider unit 2111 is used to take the signal under test as a clock input when the signal under test is high level, perform frequency division processing based on the edge information of the clock input, and output the frequency division signal of the first stage.

[0096] In one example, the initial time of the time window is denoted as T0, and the D terminal (data input terminal) of the flip-flop in the first frequency divider unit 2111 of each stage is initialized to 0.

[0097] For the first-stage first frequency divider unit 2111: the signal under test is used as a clock input and connected to the C terminal (clock input terminal) of the first-stage first frequency divider unit 2111. When the first rising edge of the clock input (signal under test) arrives, the flip-flop samples the initial value 0 at the D terminal, and the Q terminal outputs the first-stage frequency divider signal 0. This frequency divider signal is output to the second-stage first frequency divider unit 2111 and to the inverter in the first-stage first frequency divider unit 2111 to be inverted to obtain 1, and then fed back to the D terminal. When the second rising edge of the clock input (signal under test) arrives, the flip-flop samples the current value 1 at the D terminal, and the Q terminal outputs the first frequency divider signal updated to 1. This frequency divider signal is output to the second-stage first frequency divider unit 2111 and to the inverter to be inverted again to obtain 0, which is then fed back to the D terminal. In this way, the Q terminal output completes a 0→1→0 flip every two clock cycles, realizing the frequency division of the signal under test.

[0098] The second to Nth level first frequency divider unit 2111 is used to take the frequency divider signal output from the previous level first frequency divider unit as the clock input, perform frequency division processing based on the edge information of the clock input, and output the corresponding frequency divider signal.

[0099] In one implementation, the operation of the first frequency divider unit 2111 from the second to the Nth stage is as follows: Let i be a positive integer satisfying 2≤i≤N. The first frequency divider unit of the i-th stage takes the frequency division signal output by the (i-1)th stage first frequency divider unit as the clock input and connects it to the C terminal of the flip-flop in the first frequency divider unit 2111. When the first rising edge of the clock input arrives, the flip-flop samples the initial value 0 of its D terminal and outputs the frequency division signal 0 of the i-th stage at its Q terminal. This frequency division signal is used as the input of the frequency division of this stage. Another path is fed into the inverter of the first frequency divider unit of this stage to obtain 1, and fed back to the D terminal of the flip-flop. When the second rising edge of the clock input arrives, the flip-flop samples the current value 1 of the D terminal, and the Q terminal outputs the frequency divider signal 1 of the i-th stage. One path of this frequency divider signal is used as the output of the i-th stage frequency divider, and the other path is inverted again by the inverter to obtain 0, which is fed back to the D terminal. This cycle continues, and the output of the Q terminal completes a 0→1→0 flip every two input clock cycles, thereby realizing the frequency division of the (i-1)-th stage frequency divider signal by two.

[0100] Each first sampling unit 231 is used to collect and store the corresponding signal output value based on the edge information of the frequency division signal output by the corresponding first frequency division unit and the edge information of the master clock.

[0101] Each first sampling unit 231 is electrically connected to the corresponding first frequency divider unit and the system clock module 220. The system clock module 220 provides the main clock to each first sampling unit 231. The first sampling unit 231 can be implemented using a register, for example.

[0102] In one example, for each first sampling unit 231, when a rising edge occurs in the frequency division signal output by the first frequency divider unit connected to it, the first sampling unit 231, in response to the rising edge, immediately captures the current level value or its inverse value of the frequency division signal and stores it as the signal output value of that frequency division stage. Furthermore, at each rising edge of the master clock, each first sampling unit 231 is simultaneously triggered, acquiring the current level value or its inverse value of the frequency division signal output by the first frequency divider unit of its corresponding stage, and storing the acquired level value as the corresponding signal output value. The current level value of this frequency division signal can be 0 or 1.

[0103] The first counting unit 232 is used to perform a counting operation based on the edge information of the frequency division signal output by the Nth level first frequency division unit to obtain the number of flips.

[0104] The first counting unit 232 can be implemented, for example, using a counter. The first counting unit 232 is electrically connected to the Nth-stage first frequency divider unit and is used to calculate the number of times the frequency-divided signal of the Nth-stage divider experiences a rising edge within a time window, thereby calculating the number of flips of the signal under test within that time window. Specifically, within the time window, whenever the frequency-divided signal output by the Nth-stage first frequency divider unit experiences a rising edge, the first counting unit 232 is triggered to record one flip. At the end of the time window, the accumulated count value of the first counting unit 232 is taken as the number of flips of the signal under test within that time window.

[0105] In one embodiment, when the signal to be tested is at a high level, the aforementioned steps S1011 to S1014 can be achieved collaboratively by the high-level sampling chain 211 and the multiple first sampling units 231 and first counting units 232 in the frequency division sampling module 230.

[0106] In this embodiment, the first frequency division unit is cascaded through N levels to divide the frequency step by step. Each sampling unit collects the signal output value of the corresponding frequency division, and the first counting unit counts the number of flips. This realizes multi-dimensional collaborative monitoring of the dynamic jump and static level of the high-level test signal within the time window, which can reliably capture ultra-short pulse jumps and significantly improve the comprehensiveness and accuracy of chip signal stability testing.

[0107] Figure 8 This is a schematic diagram of the structure of a low-level sampling chain provided in an exemplary embodiment of this application. In some alternative embodiments, such as... Figure 8 As shown, the low-level sampling chain 212 includes an inverting unit 2121 and N cascaded second frequency divider units 2122. The frequency divider sampling module 230 also includes multiple second sampling units 233 and a second counting unit 234. The inverting unit 2121 is electrically connected to the first-stage second frequency divider unit 2122. Each second sampling unit 233 is electrically connected to any second frequency divider unit other than the Nth-stage second frequency divider unit. The second counting unit 234 is electrically connected to the Nth-stage second frequency divider unit 2122.

[0108] The structure of each level of the second frequency division unit 2122 and the frequency division process it performs are the same as those of the first frequency division unit mentioned above, and will not be described again here.

[0109] The inverting unit 2121 is used to invert the signal under test when the signal under test is low level, and output the inverted signal under test to the first-stage second frequency divider unit.

[0110] The inverting unit 2121 can be, for example, a LUT (Logical Under Test). The inverting unit 2121 can also be connected to the circuit of the device under test (DUT) to perform logic inversion processing on the DUT signal when the DUT signal is low. Specifically, the inverting unit 2121 is electrically connected to the PE (Power Provider) chip, and the PE chip is electrically connected to the DUT.

[0111] The first-stage second frequency divider unit 2122 is used to take the inverted signal under test as a clock input, perform frequency division processing based on the edge information of the clock input, and output the frequency division signal of the first-stage frequency divider.

[0112] In one example, the inverted signal under test is used as the clock input and connected to the C terminal of the flip-flop in the first-stage second frequency divider unit 2122. The first-stage second frequency divider unit 2122 performs frequency division by two on the signal and outputs the divided signal. The frequency division method of the first-stage second frequency divider unit 2122 is exactly the same as that of the first-stage first frequency divider unit 2111. For details, please refer to the relevant description of the first-stage first frequency divider unit 2111, which will not be repeated here.

[0113] The second-to-Nth level second frequency divider unit 2122 is used to take the frequency divider signal output from the previous level second frequency divider unit as a clock input, perform frequency division processing based on the edge information of the clock input, and output the frequency divider signal.

[0114] The frequency division method of the second frequency division unit 2122 from the second stage to the Nth stage is the same as that of the first frequency division unit 2111 from the second stage to the Nth stage. The specific frequency division method of the second frequency division unit 2122 from the second stage to the Nth stage can be referred to the relevant description of the first frequency division unit 2111 from the first stage, which will not be repeated here.

[0115] Each second sampling unit 233 is used to collect and store the corresponding signal output value based on the edge information of the frequency division signal output by the corresponding second frequency division unit and the edge information of the master clock.

[0116] Each second sampling unit 233 is connected to the corresponding second frequency divider unit and the system clock module 220. The system clock module 220 provides the main clock to each second sampling unit 233. The second sampling unit 233 can be implemented using registers, for example.

[0117] The second sampling unit 233 acquires and stores signal output values ​​in the same way as the first sampling unit 231 acquires and stores signal output values. The method by which the second sampling unit 233 acquires and stores signal output values ​​can be referred to the method by which the first sampling unit 231 acquires and stores signal output values, and will not be repeated here.

[0118] The second counting unit 234 is used to perform a counting operation based on the edge information of the frequency division signal output by the Nth stage second frequency division unit to obtain the number of flips.

[0119] The second counting unit 234 can be implemented using a counter, for example. The method by which the second counting unit 234 obtains the number of flips is the same as the method by which the first counting unit 232 obtains the number of flips. The method by which the second counting unit 234 obtains the number of flips can be referred to the method by which the first counting unit 232 obtains the number of flips, and will not be repeated here.

[0120] In one embodiment, when the signal to be measured is at a low level, the aforementioned steps S1011 to S1014 can be achieved collaboratively by the low-level sampling chain 212 and the multiple second sampling units 233 and the second counting unit 234 in the frequency division sampling module 230.

[0121] In this embodiment, the low-level signal under test is uniformly converted into the same processing path as the high-level signal by the inverting unit in the low-level sampling chain, thereby reusing the mature frequency division structure of the high-level sampling chain and realizing high-precision transition detection of the low-level signal.

[0122] In one example Figure 9 This is a schematic diagram of the signal detection circuit provided in an application example of this application. Figure 10 This is a schematic diagram of the high-level sampling chain provided in an application example of this application. Figure 11 This is a schematic diagram of another high-level sampling chain provided in an application example of this application.

[0123] like Figure 9-11As shown, the signal detection circuit can be deployed in a Field Programmable Gate Array (FPGA). The device under test (DUT) is electrically connected to the PE chip, and the PE chip is electrically connected to the signal detection circuit.

[0124] The signal detection circuit includes: a high-level sampling chain consisting of five cascaded first frequency divider units (D flip-flops U0~U4 and inverters LUT0~LUT4); a low-level sampling chain consisting of five cascaded second frequency divider units (D flip-flops U'0~U'4, inverters LUT'0~LUT'4 and inverter LUT'11); a frequency divider sampling module consisting of first registers 0~3 (corresponding to U0~U3), second registers 0~3 (corresponding to U'0~U'3), a first counter (corresponding to U4), and a second counter (corresponding to U'4); a signal sampling module consisting of the PE register; and a system clock module consisting of the FPGA's Local clk master clock.

[0125] In the high-level sampling chain: D flip-flop U0 is connected to register 0 and LUT0 respectively; D flip-flop U1 is connected to register 1 and LUT1 respectively; D flip-flop U2 is connected to register 2 and LUT2 respectively; D flip-flop U3 is connected to register 3 and LUT3 respectively; D flip-flop U4 is connected to the first counter and LUT4 respectively. In the low-level sampling chain: D flip-flop U'0 is connected to register 0, LUT'0 and the inverted LUT'11 respectively; D flip-flop U'1 is connected to register 1 and LUT'1 respectively; D flip-flop U'2 is connected to register 2 and LUT'2 respectively; U'3 is connected to register 3 and LUT'3 respectively; U'4 is connected to the second counter and LUT'4 respectively. All the above D flip-flops (U0~U4, U'0~U'4) are implemented by instantiating the FPGA primitive FDRE (single D flip-flop). Each FDRE unit includes: clock input (C), data input (D), output (Q), clock enable (CE), and reset (R).

[0126] Specifically, the frequency division of the signal to be tested includes: 1) Signal input and first-stage frequency division The DUT outputs the signal under test, which is transmitted to the C terminal of U0 via the PE chip as a clock input. The initial value of the D terminal of U0 is 0. At the first rising edge of the signal under test: U0 samples the D terminal value of 0, and the Q terminal outputs 0 (i.e., the first-stage frequency divider signal clk0). One path of this divided signal serves as the clock input of U1, and the other path is inverted by LUT0 to obtain 1 and fed back to the D terminal of U0. At the second rising edge of the signal under test: U0 samples the D terminal value of 1, and the Q terminal outputs 1. This value is inverted by LUT0 to obtain 0 and fed back to the D terminal. Thus, the Q terminal of U0 flips once every two cycles of the signal under test, achieving a two-way frequency divide, with the clk0 frequency being half the frequency of the signal under test.

[0127] 2) Multi-level frequency division and switching rules Similarly, U1~U4 sequentially divide the output frequency divider signal of the previous stage by two to generate frequency divider signals clk1~clk4. The toggling rules of each stage flip-flop are as follows: U0: flips once every 2 transitions of the signal under test; U1: flips once every 4 transitions of the signal under test; U2: flips once every 8 transitions of the signal under test; U3: flips once every 16 transitions of the signal under test; U4: flips once every 32 transitions of the signal under test. When the number of transitions of the signal under test exceeds 32, the first counter counts the rising edge of clk4 output by U4. A count value greater than 0 indicates that the signal under test has transitioned.

[0128] 3) Signal output value acquisition The first registers 0-3 acquire and store the current level value Q or its inverted value ~Q of the corresponding frequency-divided signal as the corresponding signal output value at the following times: Asynchronous acquisition: when the connected frequency-divided signal has a rising edge; Synchronous acquisition: when the main clock output by Localclk has a rising edge, the values ​​acquired synchronously and asynchronously are used as the signal output value. When the main clock output by Localclk has a rising edge, the PE register acquires the current level value of the signal under test as the sample value and stores it.

[0129] 4) Low-level signal processing When the signal under test is active low, the signal under test is first inverted by LUT'11, and then the inverted signal under test is connected to the C terminal of U'0. The subsequent frequency division, sampling, and counting processes are the same as those in the high-level sampling chain.

[0130] Figure 12 This is a schematic diagram of the waveform of the signal under test provided in an exemplary embodiment of this application. For example... Figure 12As shown, the frequency of the master clock CLK is 200 MHz (period 5 ns), and the signal under test is input from the PE chip as the clock input of the signal detection circuit. For ease of explanation, the initial default values ​​of the PE sampling register and the first registers 0~3 and the second registers 0~3 are set to high level (1). The PE sampling register directly samples the level of the signal under test to obtain its transient logic value (0 or 1). The signal under test includes three level transitions: Sig1, Sig2, and Sig3. Sig1 is a low-level pulse with a width of 1 ns, which is significantly smaller than the sampling period of the master clock CLK (5 ns); Sig2 is a low-level pulse with a width of 700 ps, ​​which is also much smaller than the sampling period; Sig3 can be directly captured by the master clock. The signal detection circuit can successfully capture all three transitions of Sig1, Sig2, and Sig3, proving that the signal detection circuit has high-resolution detection capability for narrow pulse signals.

[0131] In another example, Figure 13 This is a schematic diagram of the FPGA structure provided in an application example of this application. For example... Figure 13 As shown, the FPGA integrates a timing generator (TG), which embeds signal detection circuitry. The TG is connected to the PE chip, the Match Fail Capture (MCF), and memory 0; the MCF is also connected to memory 1. The PE chip is connected to the device under test (DUT) (not shown in the figure). Memory 0 and memory 1 can be Double Data Rate 4 (DDR4 SDRAM). Memory 0 stores the test vectors, microinstructions, and the timing window Timingset0. Users can configure the initial and end times of the timing window Timingset0 using the Timing parameter.

[0132] During operation, the expected values ​​in the timing window Timingset0, microinstructions, and pattern are transmitted to the TG. The test signal output by the DUT is input to the FPGA via the PE chip and compared with the expected value. The MCF captures the comparison result (FAIL or PASS) and stores the test result in memory 1.

[0133] Figure 14 This is a schematic diagram of the time window test comparison method provided in an application example of this application. Figure 14 This demonstrates the complete execution flow of the Window Compare function in ATE, covering the entire chain from software configuration to result output. The specific steps are as follows: Startup process: Initialize window comparison test.

[0134] Software configuration timing parameters: Set the timing parameters (Timingset) for window comparison in the test software, that is, define the initial and end times of the time window.

[0135] Compile Test Vectors (PATTERN): Compile the test vector files to generate an executable instruction sequence for the test machine.

[0136] Configure level parameters: Set signal level related parameters (Level), including drive high / low level thresholds, comparator reference voltage, etc.

[0137] Load Configuration and Vectors: Load the compiled test vectors and configuration parameters into the test machine hardware (such as FPGA).

[0138] Run PATTERN: Starts the test vector execution, beginning the stimulation and response acquisition of the chip.

[0139] FPGA hardware execution window comparison: Based on the expected value, the FPGA performs transition detection on the signal under test output by the chip within a specified time window, acquiring the sampled value, the number of toggles, and the signal output value of each frequency divider. The test result is then determined according to the following rules: FAIL condition 1: The sampled value is equal to the expected value, but the signal output value of at least one frequency divider is inconsistent with the signal output value corresponding to the previous time window; FAIL condition 2: The sampled value is not equal to the expected value; FAIL condition 3: The sampled value is equal to the expected value, and the signal output values ​​of each frequency divider are consistent with the previous time window, but the number of toggles is inconsistent with the previous time window; PASS condition: The sampled value is equal to the expected value, the signal output values ​​of each frequency divider are consistent with the previous time window, and the number of toggles is also consistent with the previous time window.

[0140] Result capture: MCF captures the decision result (PASS / FAIL) of the comparison window in each test cycle.

[0141] Results storage: MCF writes the captured test results to memory 1 (using DDR4) in real time to ensure high-speed and reliable data storage.

[0142] Test completion and reporting: After all test cycles are completed, the system will summarize and report the final window comparison test results to the upper-level software or user interface for further analysis or display.

[0143] The signal detection circuit of this application corresponds to the time window comparison method described above, and the relevant content can be referred to each other, which will not be repeated here. The beneficial technical effects of the exemplary embodiment of the signal detection circuit of this application can be referred to the corresponding beneficial technical effects in the exemplary method section above, which will not be repeated here.

[0144] Figure 15 This is a schematic diagram of the structure of a time window comparison system provided in an exemplary embodiment of this application. For example... Figure 15 As shown, the time window comparison system 300 can be deployed in a chip testing device. The time window comparison system includes a vector generator 310 and a timing generator 320.

[0145] Vector generator 310 is used to output the time window and the expected value corresponding to the time window stored in the storage device to timing generator 320; The timing generator 320 is used to receive the test signal output by the device under test (DUT), detect the edge transition information of the test signal within the time window, and collect the sampled value of the test signal at the test moment within the time window; based on the sampled value, expected value and edge transition information, it determines the test result of the DUT within the time window.

[0146] In one embodiment of this application, the timing generator 320 includes: a frequency division submodule and a sampling submodule; The frequency division submodule is used to perform N-level frequency division processing on the signal under test to obtain at least one level of frequency division signal output value and the number of toggles of the signal under test. Based on the signal output value and the number of toggles, edge transition information is constructed. The sampling submodule is used to collect sampled values ​​from the signal under test at the test time.

[0147] In one embodiment of this application, the time window comparison system further includes a clock module; The clock module is used to generate the master clock and output the master clock to the frequency division submodule and the sampling submodule.

[0148] The frequency division submodule is specifically used to take the signal under test as the clock input for the first-level frequency division, perform frequency division processing based on the edge information of the clock input to obtain the first-level frequency division signal, and collect the signal output value of the first-level frequency division based on the edge information of the frequency division signal and the edge information of the master clock. For the second to N-1 level frequency division: the frequency division signal of the previous level is taken as the clock input, and frequency division processing is performed based on the edge information of the clock input to obtain the current level frequency division signal. The signal output value of the current level frequency division is collected based on the edge information of the frequency division signal and the edge information of the master clock. For the Nth level frequency division: the frequency division signal of the N-1 level is taken as the clock input, and the frequency division signal of the Nth level is determined based on the edge information of the clock input. The number of toggle cycles is obtained based on the edge information of the frequency division signal. The sampling submodule is specifically used to sample the signal under test based on the edge information of the master clock, obtain the sampled value, and store the sampled value.

[0149] In one embodiment of this application, the time window comparison system further includes a level judgment module; The level judgment module is used to perform the operation of using the test signal as the clock input for the first-stage frequency division when the test signal is high; and to perform the inversion process on the test signal when the test signal is low, and use the inverted test signal as the clock input for the first-stage frequency division.

[0150] In one embodiment of this application, the frequency division submodule is further configured to, in response to the edge information of the frequency division signal meeting a preset trigger condition, or the edge information of the master clock meeting a preset trigger condition, use the current level value of the frequency division signal as the signal output value; or, in response to the edge information of the frequency division signal meeting a preset trigger condition, or the edge information of the master clock meeting a preset trigger condition, invert the current level value of the frequency division signal and use it as the signal output value.

[0151] In one embodiment of this application, the frequency division submodule is further configured to determine that the device under test has failed the test in response to the inconsistency between the sampled value and the expected value, or the inconsistency between the signal output value of at least one level of frequency division and the corresponding signal output value in the previous time window, or the inconsistency between the number of flips and the number of flips in the previous time window.

[0152] The time window comparison system of this application corresponds to the time window comparison method described above, and the relevant content can be referred to each other, which will not be repeated here. The beneficial technical effects corresponding to the exemplary embodiments of the time window comparison system of this application can be referred to the corresponding beneficial technical effects in the exemplary method section above, which will not be repeated here.

[0153] In addition, embodiments of this application also provide an electronic device, including: Memory, used to store computer programs; A processor is configured to execute a computer program stored in a memory, and when the computer program is executed, implement the time window test comparison method of any of the above embodiments of this application.

[0154] Figure 16 This is a schematic diagram illustrating the structure of an application embodiment of the electronic device of this application. Below, reference is made to… Figure 16 This application describes an electronic device according to embodiments thereof. The electronic device may be either or both of a first device and a second device, or a standalone device independent of them, which may communicate with the first device and the second device to receive acquired input signals from them.

[0155] like Figure 16 As shown, the electronic device includes one or more processors and memory.

[0156] A processor can be a central processing unit (CPU) or other form of processing unit with data processing and instruction execution capabilities, and can control other components in an electronic device to perform desired functions.

[0157] The memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the program instructions to implement the time window test comparison methods of the various embodiments of this application described above and / or other desired functions.

[0158] In one example, the electronic device may also include input devices and output devices, which are interconnected via a bus system and other forms of connection mechanisms (not shown).

[0159] In addition, the input device may include, for example, a keyboard, a mouse, etc.

[0160] This output device can output various information to the outside, including determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0161] Of course, for the sake of simplicity, Figure 16Only some of the components of the electronic device relevant to this application are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0162] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the time window test comparison methods according to various embodiments of this application as described in the foregoing portion of this specification.

[0163] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0164] Furthermore, embodiments of this application may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the time window test comparison method according to various embodiments of this application described in the foregoing portion of this specification.

[0165] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0166] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0167] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0168] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0169] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the word “and,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0170] The methods and apparatus of this application may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the method is for illustrative purposes only, and the steps of the method of this application are not limited to the order specifically described above, unless otherwise specifically stated. Furthermore, in some embodiments, this application may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the method according to this application. Thus, this application also covers recording media storing programs for performing the method according to this application.

[0171] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and recombined. These disassemblies and recombinations should be considered as equivalent solutions of this application.

[0172] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0173] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A time window test comparison method, characterized in that, include: Acquire the edge transition information of the signal under test output by the device under test within the time window; Collect the sampled values ​​of the signal under test at the test time within the time window; Based on the sampled value, the expected value corresponding to the time window, and the edge transition information, the test result of the device under test within the time window is determined.

2. The method according to claim 1, characterized in that, The acquisition of edge transition information of the signal under test output by the device under test within a time window includes: The signal under test is subjected to N-level frequency division processing to obtain at least one level of frequency division signal output value and the number of flips of the signal under test; The edge transition information is constructed based on the signal output value and the number of flips.

3. The method according to claim 2, characterized in that, The step of performing N-level frequency division processing on the signal under test includes: Receive the input master clock; The signal under test is used as the clock input for the first-stage frequency division. Frequency division is performed based on the edge information of the clock input to obtain the first-stage frequency division signal. The output value of the first-stage frequency division signal is collected based on the edge information of the frequency division signal and the edge information of the master clock. Second to N-1 level frequency division execution: The frequency division signal of the previous level is used as the clock input, and frequency division processing is performed based on the edge information of the clock input to obtain the frequency division signal of this level. Based on the edge information of the frequency division signal and the edge information of the master clock, the signal output value of this level frequency division is collected. Nth-level frequency division execution: The frequency division signal of the (N-1)th-level frequency division is used as the clock input. Based on the edge information of the clock input, the frequency division signal of the Nth-level frequency division is determined. Based on the edge information of the frequency division signal, the number of toggles is obtained.

4. The method according to claim 3, characterized in that, Before using the signal under test as the clock input for the first-stage frequency division, the method further includes: In response to the signal under test being high, the operation of using the signal under test as a clock input for the first-stage frequency division is performed; In response to the signal under test being low, the signal under test is inverted, and the inverted signal under test is used as the clock input for the first-stage frequency division.

5. The method according to claim 3, characterized in that, The acquisition of the signal output value of this frequency division based on the edge information of the frequency division signal and the edge information of the master clock includes: In response to the edge information of the frequency division signal meeting a preset trigger condition, or the edge information of the master clock meeting a preset trigger condition, the current level value of the frequency division signal is used as the signal output value; or, In response to the edge information of the frequency division signal meeting a preset trigger condition, or the edge information of the master clock meeting a preset trigger condition, the current level value of the frequency division signal is inverted and used as the signal output value.

6. The method according to any one of claims 2-5, characterized in that, The step of determining the test result of the device under test within the time window based on the sampled value, the expected value corresponding to the time window, and the edge transition information includes: In response to the inconsistency between the sampled value and the expected value, or the inconsistency between the signal output value of at least one frequency division and the corresponding signal output value in the previous time window, or the inconsistency between the number of flips and the number of flips in the previous time window, the test result is determined to be that the device under test has failed the test.

7. A signal detection circuit, characterized in that, include: The frequency divider module is used to receive the test signal output by the device under test within a time window, and to perform N-level frequency division processing on the test signal to output the frequency divided signal. The system clock module is used to output the master clock. The frequency division sampling module is used to collect and store the signal output value of at least one level of frequency division based on the edge information of the frequency division signal and the edge information of the master clock, determine the number of toggles of the signal under test based on the edge information of the frequency division signal, and construct the edge transition information of the signal under test based on the signal output value and the number of toggles. The signal sampling module is used to collect the sampled values ​​of the signal under test at the test time within the time window.

8. The circuit according to claim 7, characterized in that, The frequency division module includes a high-level sampling chain and a low-level sampling chain; The high-level sampling chain is used to perform N-level frequency division processing on the signal under test when the signal under test is high level; The low-level sampling chain is used to perform N-level frequency division processing on the signal under test when the signal under test is low.

9. The circuit according to claim 8, characterized in that, The high-level sampling chain includes N cascaded first frequency division units, and the frequency division sampling module includes a first counting unit and multiple first sampling units. Each first sampling unit is connected to any first frequency division unit except for the Nth-level first frequency division unit. The first counting unit is connected to the Nth-level first frequency division unit. The first-stage first frequency divider unit is used to take the signal under test as a clock input when the signal under test is high level, perform frequency division processing based on the edge information of the clock input, and output the frequency division signal of the first-stage frequency divider. The second to Nth level first frequency divider units are used to take the frequency divider signal output from the previous level first frequency divider unit as the clock input, perform frequency division processing based on the edge information of the clock input, and output the corresponding frequency divider signal. Each of the first sampling units is used to collect and store the corresponding signal output value based on the edge information of the frequency division signal output by the corresponding first frequency division unit and the edge information of the master clock. The first counting unit is used to perform a counting operation based on the edge information of the frequency division signal output by the Nth-level first frequency division unit to obtain the number of flips.

10. The circuit according to claim 8 or 9, characterized in that, The low-level sampling chain includes an inverting unit and N cascaded second frequency divider units. The frequency divider sampling module also includes a second counting unit and multiple second sampling units. The inverting unit is connected to the first-level second frequency divider unit. Each second sampling unit is connected to any second frequency divider unit other than the Nth-level second frequency divider unit. The second counting unit is connected to the Nth-level second frequency divider unit. The inverting unit is used to invert the signal under test when the signal under test is low level, and output the inverted signal under test to the first-stage second frequency divider unit. The first-stage second frequency divider unit is used to take the inverted signal under test as a clock input, perform frequency division processing based on the edge information of the clock input, and output the frequency division signal of the first-stage frequency divider. The second to Nth level second frequency divider units are used to take the frequency divider signal output from the previous level second frequency divider unit as a clock input, perform frequency division processing based on the edge information of the clock input, and output the frequency divider signal. Each of the second sampling units is used to collect and store the corresponding signal output value based on the edge information of the frequency division signal output by the corresponding second frequency division unit and the edge information of the master clock, respectively. The second counting unit is used to perform a counting operation based on the edge information of the frequency division signal output by the Nth-level second frequency division unit to obtain the number of flips.

11. The circuit according to any one of claims 7-10, characterized in that, The signal sampling module specifically samples the signal under test based on the edge information of the master clock, obtains the sampled value, and stores the sampled value.

12. A time window comparison system, characterized in that, include: The vector generator is used to output the time window and the expected value corresponding to the time window stored in the storage device to the timing generator; The timing generator is used to detect the edge transition information of the signal under test within the time window when receiving the signal under test output by the device under test, and to collect the sampled value of the signal under test at the test time within the time window. Based on the sampled value, the expected value, and the edge transition information, the test result of the device under test within the time window is determined.

13. The system according to claim 12, characterized in that, The timing generator includes a frequency division submodule and a sampling submodule; The frequency division submodule is used to perform N-level frequency division processing on the signal under test to obtain at least one level of frequency division signal output value and the number of flips of the signal under test, and to construct the edge transition information based on the signal output value and the number of flips; The sampling submodule is used to collect the sampled value from the signal under test at the test time.

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