A high-density integrated chip design method based on three-dimensional packaging structure

Abstract

This invention relates to the field of integrated circuit packaging and design technology, and discloses a high-density integrated chip design method based on a three-dimensional packaging structure. The method includes: Step 1, system structure model: establishing a structural model of the three-dimensional packaged chip according to functional requirements, determining the allocation of each chip layer and module, and clarifying the communication relationships between modules; Step 2, module communication requirement matrix: analyzing the communication frequency and bandwidth requirements between modules, constructing a communication requirement matrix, and identifying frequently communicating module pairs; Step 3, chip area partitioning: dividing the chip functional areas based on the communication requirement matrix to reduce communication distance. This invention establishes a system structure model of the three-dimensional packaged chip and, combined with the module communication requirement matrix, rationally divides the chip functional areas, making frequently communicating modules as close as possible in space, thereby effectively shortening the communication path between modules, reducing signal transmission delay and power consumption, and improving the overall data transmission efficiency and system performance of the three-dimensional packaged chip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit packaging and design technology, specifically to a high-density integrated chip design method based on a three-dimensional packaging structure. Background Technology

[0002] As integrated circuits continue to evolve towards higher performance, higher bandwidth, and higher integration, traditional two-dimensional packaging, due to its long interconnect distances, large signal delays, and high power consumption, can no longer meet the demands of advanced applications. Three-dimensional packaging technology based on vertical interconnects, especially through TSV (Through-Screen Vias) to achieve vertical interconnects of multiple layers of chips, can significantly shorten signal paths, increase bandwidth, and reduce power consumption, thus becoming an important direction for modern high-density chip design.

[0003] In 3D packaging, the layout of internal circuit modules and the location of TSVs (Transport Storage Devices) need to be precisely coordinated. However, due to the complexity of the circuit structure and the large number of modules, the introduction of TSVs often causes spatial conflicts with the original layout. To resolve these conflicts, designers often need to repeatedly adjust the circuit layout, which not only increases design complexity but also extends the design cycle.

[0004] The placement of TSVs in critical areas can affect circuit density and functional performance, and existing methods lack a unified collaborative optimization mechanism. With the increase in the number of TSVs and the growing demand for inter-layer communication, frequent layout adjustments reduce chip area utilization and increase communication latency and power consumption. Therefore, how to achieve efficient collaboration between circuit layout and TSV layout, reduce conflicts, and optimize chip performance is a pressing technical problem that needs to be solved in current 3D packaging design. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a high-density integrated chip design method based on a three-dimensional packaging structure, thereby solving the problems mentioned in the background section.

[0006] To achieve the above objectives, the present invention provides a high-density integrated chip design method based on a three-dimensional packaging structure, comprising the following steps:

[0007] Step 1: System structure model. Based on the functional requirements, establish a structural model of the three-dimensional packaged chip, determine the allocation of each chip layer and module, and clarify the communication relationship between modules.

[0008] Step 2: Module communication requirement matrix. Analyze the communication frequency and bandwidth requirements between modules, construct a communication requirement matrix, and identify module pairs that communicate frequently.

[0009] Step 3: Chip area partitioning. Based on the communication demand matrix, the chip functional areas are divided to reduce communication distance and reserve space for interconnection channels.

[0010] Step 4: TSV pre-planning area. Set up the TSV pre-planning area according to communication requirements, determine the number and spacing of TSVs, and avoid dense circuit areas.

[0011] Step 5: Collaborative Constraint Model. Establish a collaborative constraint model between TSV and circuit layout, considering location, circuit layout, and communication path factors, and optimize the layout of both.

[0012] Step 6: Optimize layout calculation. Based on the collaborative constraint model, optimize the layout of TSV and circuit to reduce layout conflicts, shorten communication paths, and improve area utilization.

[0013] Step 7: Package structure design. Based on the optimized layout results, determine the final chip circuit and TSV positions, generate 3D package layout data, and complete the design.

[0014] Preferably, step 1 includes:

[0015] Step 1.1 Based on the functional requirements of the target 3D packaged chip, perform a system-level analysis of the overall chip function, determine the required functional module types and their functional attributes, and establish a system functional module set;

[0016] Step 1.2 Based on the design requirements of the three-dimensional packaging structure, the functional module set is hierarchically divided, the distribution relationship of each functional module in different chip layers is determined, and a chip hierarchical structure model is established.

[0017] Step 1.3 Based on the data interaction requirements between each functional module, determine the data transmission direction, communication frequency, and bandwidth requirements between modules, and establish a communication relationship model between modules;

[0018] Step 1.4 Integrate the hierarchical distribution relationship and module communication relationship of the functional modules to construct a system structure model of the three-dimensional packaged chip, which is used to describe the chip hierarchical structure, module allocation relationship and inter-module communication relationship.

[0019] Preferably, step 2 includes:

[0020] Step 2.1 Based on the established system structure model, obtain the data interaction relationships between each functional module and determine the set of modules participating in the communication;

[0021] ,

[0022] Representation module With modules They have a communication relationship. This indicates that there is no communication relationship.

[0023] Step 2.2 Perform statistical analysis on the data interaction behavior between each functional module to obtain parameters such as data transmission frequency, data transmission volume, and bandwidth requirements between modules;

[0024] Communication frequency: ,

[0025] For module With modules Communication frequency between them For statistical time periods;

[0026] Data transfer volume: ,

[0027] For module With modules Total data transfer volume between them For module With modules In the Data transmission volume in this communication For module With modules The number of communications between them;

[0028] Bandwidth requirement quantification: ,

[0029] For module With modules Bandwidth requirements between For module With modules Data transmission delay between them;

[0030] Step 2.3 Using functional modules as rows and columns of a matrix, the communication requirements between any two functional modules are quantitatively characterized, and the data transmission frequency, data transmission volume or bandwidth requirements are used as communication weights to establish the module communication requirement relationship.

[0031] The formula for calculating communication weight: ,

[0032] For module With modules Communication weights between them , , These are weighting coefficients, corresponding to the degree of influence of communication frequency, data transmission volume, and bandwidth requirements on the weights, respectively.

[0033] Step 2.4 Construct a module communication demand matrix based on the communication weights, which is used to represent the communication strength and communication demand between each functional module;

[0034] Module communication requirements matrix: ,

[0035] For the module communication requirement matrix, For module With modules Communication weights between them;

[0036] Step 2.5 Based on the communication weights in the module communication demand matrix, sort or threshold-filter the communication relationships between modules to identify module pairs that communicate frequently or have high communication demands, which will serve as the basis for subsequent chip functional area division and layout planning.

[0037] Ranking metrics: ,

[0038] For module Total communication requirements For module With modules Communication weights between them;

[0039] Threshold filtering: ,

[0040] The threshold is used to filter module pairs with high communication requirements.

[0041] Preferably, step 3 includes:

[0042] Step 3.1 Based on the established module communication requirement matrix, extract the communication weight parameters between each functional module and construct the module communication correlation evaluation index;

[0043] Step 3.2 Based on the communication correlation evaluation index, perform cluster analysis or grouping processing on the functional modules, and divide the modules with higher communication weight into the same functional area to reduce the physical distance between high-frequency communication modules.

[0044] Step 3.3 Establish an initial region partitioning model on the chip plane. Based on the module area requirements, power consumption distribution and process constraints, perform spatial mapping on each functional region to determine the position and boundary of each functional region on the chip plane.

[0045] Step 3.4 Reserve interconnection channel space between adjacent functional areas for subsequent cabling resource allocation and inter-layer interconnection structure layout, so as to avoid cabling congestion in high communication density areas;

[0046] Step 3.5 Iteratively optimizes the functional area division results, taking into account the module area utilization rate, area compactness and communication path length, and adjusts the area boundary position to minimize the average communication distance of highly communication-related modules, while ensuring that the overall chip layout meets the design rule constraints.

[0047] Preferably, step 4 includes:

[0048] Step 4.1 Based on the module communication requirement matrix and the chip functional area division results, identify functional module pairs that have cross-layer data transmission requirements between different chip layers, and determine the corresponding cross-layer communication requirement parameters;

[0049] Step 4.2 Based on the cross-layer communication requirement parameters, perform statistical analysis on the cross-layer data transmission volume, communication frequency and bandwidth requirements between each functional area to determine the intensity of inter-layer interconnection requirements between each area;

[0050] Step 4.3 Based on the required intensity of inter-layer interconnection, pre-planned areas for inter-layer interconnection structures are set between corresponding functional areas for arranging TSVs;

[0051] Step 4.4 Calculate the required number of TSVs based on the cross-layer communication bandwidth requirements between each region, and determine the arrangement and spacing between TSVs by combining TSV size parameters and process design rules;

[0052] Step 4.5 Position constraints are applied to the pre-planned TSV area in the chip layout to avoid functional module areas with high circuit density and to coordinate with chip wiring resources and power network planning, so as to reduce the impact on circuit layout and wiring resources.

[0053] Step 4.6 Based on the overall chip area utilization and interlayer interconnection efficiency, adjust and optimize the location, size and distribution of the TSV pre-planned area to form a TSV pre-planned scheme that meets the cross-layer communication requirements.

[0054] Preferably, step 5 includes establishing a collaborative constraint model between TSV and circuit layout. By comprehensively considering factors such as TSV location, circuit module layout, and inter-module communication paths, the TSV location and circuit module layout are jointly optimized. Specifically, this includes the following steps:

[0055] Step 5.1 Establish the circuit module set With TSV collection Among them, the circuit module The geometric center coordinates are TSV The position coordinates are And construct the module-TSV spatial coupling distance function:

[0056] ,

[0057] : No. The circuit module and the first Spatial coupling distance between TSVs : Center coordinates of the circuit module TSV location coordinates : No. The load factor of a TSV is used to represent the vertical communication volume carried by that TSV.

[0058] Step 5.2 Establish the module communication path cost function:

[0059] ,

[0060] Module With modules The overall communication path length between them : Path indicator variable, indicating whether the communication path passes through the first... One TSV, : No. Vertical interconnect height of each TSV, : TSV conduction efficiency coefficient;

[0061] Step 5.3 Construct the communication path coupling enhancement strength number:

[0062] ,

[0063] The strength of communication coupling between modules. Inter-module communication weights Path length nonlinear amplification factor Communication stability coefficient Stability adjustment coefficient;

[0064] Step 5.4 The communication stability coefficient is defined as follows:

[0065] ,

[0066] Standard deviation of module communication traffic Average module communication traffic.

[0067] Preferably, step 5 further includes:

[0068] Step 5.5 Constructing the TSV spatial distribution constraint function:

[0069] ,

[0070] TSV spatial density index Distance decay index;

[0071] Step 5.6 Construct the module layout crowding function:

[0072] ,

[0073] Number of regions in the chip Module Is it located in the area? Indicator variables, Area Congestion penalty coefficient;

[0074] Step 5.7 Construct the objective function for co-optimization of TSV and circuit layout:

[0075] ,

[0076] : Collaborative optimization objective function, Weighting adjustment coefficient.

[0077] Preferably, step 6 includes optimizing the TSV location and circuit module layout based on the collaborative constraint model established in step 5, in order to reduce layout conflicts, shorten communication paths, and improve chip area utilization. Specifically, it includes the following steps:

[0078] Step 6.1 Define the conflict degree function:

[0079] ,

[0080] Chip layout conflict index Indicator module With modules Are there any potential overlaps or conflicts? : The boundary spacing between modules or TSVs : Conflict threshold spacing; values ​​below this are considered potential conflicts. Conflict sensitivity adjustment coefficient;

[0081] Step 6.2 Communication path optimization function:

[0082] ,

[0083] Total cost of communication paths between modules Inter-module communication weights The Manhattan distance index parameter can be adjusted as a non-integer to allow for path "flexibility". via TSV The module pairs of the set, TSV load factor: This indicates the impact of communication traffic through this TSV. TSV vertical interconnect height;

[0084] Step 6.3 Area utilization optimization function:

[0085] ,

[0086] Effective chip area utilization rate Module Area occupied Total chip area TSV Area occupied Module and The overlapping area, Overlapping area penalty coefficient;

[0087] Step 6.4 Comprehensive optimization of the objective function:

[0088] ,

[0089] : Layout optimization comprehensive objective function, : Conflict level, communication path, and area utilization rate weighting coefficients : Conflict degree function Communication path function Area utilization rate function.

[0090] Preferably, step 7 includes:

[0091] Step 7.1 Based on the optimized circuit layout in Step 6, determine the final location of the circuit modules. The location of the module was determined by comprehensively considering factors such as inter-module conflict level, communication path optimization, and area utilization efficiency. The final location of the module was determined as follows:

[0092] ,

[0093] Circuit module The final location, Module With TSV The coupling distance between them :piece With modules The strength of communication coupling between them Layout congestion;

[0094] Step 7.2 Based on the optimization results of Step 6, the final location of each TSV is determined. The TSV positions are adjusted according to the weights in the objective function to ensure their rationality. The goal of TSV position optimization is to minimize chip hotspots and reduce communication latency between circuit modules.

[0095] ,

[0096] TSV The final location, Circuit module With TSV The coupling distance between them TSV spatial density;

[0097] Step 7.3 After determining the final locations of the circuit modules and TSVs, generate the 3D package layout data of the chip. This data includes the coordinate information of all modules and TSVs on the chip, as well as the chip circuit connection information. The calculation method for generating the package layout is as follows:

[0098] ,

[0099] : Package layout data, Module Area occupied TSV The area occupied.

[0100] Preferably, step 7.4 designs the chip's packaging structure based on the final circuit module and TSV location, including the chip's external pin configuration, the selection of packaging materials, and the packaging type;

[0101] Step 7.5 Based on the final chip layout, optimize the package structure to reduce hot spots and improve package reliability and performance:

[0102] ,

[0103] : Encapsulation structure optimization objective function, Module thermal load, TSV Power loss, : Weighting coefficients for heat load and power loss;

[0104] After completing the package structure design in step 7.6, the corresponding package layout data is generated, including the spatial layout of each module and TSV in the package, the position of external pins and electrical connections. The generated package layout data will be used for subsequent manufacturing verification and testing to ensure that the package structure matches the circuit function of the chip.

[0105] This invention provides a high-density integrated chip design method based on a three-dimensional packaging structure. It has the following advantages:

[0106] 1. This invention establishes a system structure model of a three-dimensional packaged chip and rationally divides the chip's functional areas by combining the module communication requirement matrix. This allows modules with frequent communication to be as close as possible in space, thereby effectively shortening the communication path between modules, reducing signal transmission delay and power consumption, and improving the overall data transmission efficiency and system performance of the three-dimensional packaged chip.

[0107] 2. This invention sets up a pre-planned TSV area in the early stage of chip design and rationally plans the number and spacing of TSVs in combination with communication requirements, while avoiding dense circuit areas. This allows the TSV layout to form a good spatial coordination relationship with the circuit layout in the design stage, thereby reducing spatial conflicts between TSVs and circuit layout, reducing the design complexity of repeated adjustments to the circuit layout in the later stage, and significantly improving design efficiency.

[0108] 3. This invention establishes a collaborative constraint model between TSV and circuit layout, and performs optimization calculations on the layout based on this model. This enables comprehensive optimization of TSV position, circuit layout, and communication path, which not only reduces layout conflicts but also improves chip area utilization and optimizes the overall layout quality of the three-dimensional packaging structure, thereby enhancing the chip's integration and stability. Attached Figure Description

[0109] Figure 1 This is a flowchart of the present invention;

[0110] Figure 2 These are experimental data for this invention. Detailed Implementation

[0111] To enable those skilled in the art to understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort should fall within the scope of protection of the present invention.

[0112] The present invention will now be described in detail with reference to the accompanying drawings:

[0113] Example:

[0114] Please see the appendix Figures 1 to 2 This invention provides a high-density integrated chip design method based on a three-dimensional packaging structure, comprising:

[0115] Step 1: System structure model. Based on the functional requirements, establish a structural model of the three-dimensional packaged chip, determine the allocation of each chip layer and module, and clarify the communication relationship between modules.

[0116] Step 2: Module communication requirement matrix. Analyze the communication frequency and bandwidth requirements between modules, construct a communication requirement matrix, and identify module pairs that communicate frequently.

[0117] Step 3: Chip area partitioning. Based on the communication demand matrix, the chip functional areas are divided to reduce communication distance and reserve space for interconnection channels.

[0118] Step 4: TSV pre-planning area. Set up the TSV pre-planning area according to communication requirements, determine the number and spacing of TSVs, and avoid dense circuit areas.

[0119] Step 5: Collaborative Constraint Model. Establish a collaborative constraint model between TSV and circuit layout, considering location, circuit layout, and communication path factors, and optimize the layout of both.

[0120] Step 6: Optimize layout calculation. Based on the collaborative constraint model, optimize the layout of TSV and circuit to reduce layout conflicts, shorten communication paths, and improve area utilization.

[0121] Step 7: Package structure design. Based on the optimized layout results, determine the final chip circuit and TSV positions, generate 3D package layout data, and complete the design.

[0122] Please see the appendix Figures 1 to 2 The step 1 includes:

[0123] Step 1.1 Based on the functional requirements of the target 3D packaged chip, perform a system-level analysis of the overall chip function, determine the required functional module types and their functional attributes, and establish a system functional module set;

[0124] Step 1.2 Based on the design requirements of the three-dimensional packaging structure, the functional module set is hierarchically divided, the distribution relationship of each functional module in different chip layers is determined, and a chip hierarchical structure model is established.

[0125] Step 1.3 Based on the data interaction requirements between each functional module, determine the data transmission direction, communication frequency, and bandwidth requirements between modules, and establish a communication relationship model between modules;

[0126] Step 1.4 Integrate the hierarchical distribution relationship and module communication relationship of the functional modules to construct a system structure model of the three-dimensional packaged chip, which is used to describe the chip hierarchical structure, module allocation relationship and inter-module communication relationship.

[0127] Specifically, by conducting a system-level analysis of chip functional requirements, a set of functional modules is constructed. These modules are then hierarchically divided using a 3D packaging structure. Simultaneously, a data communication relationship model between modules is established. This further integrates to form a complete 3D packaged chip system structure model. This allows for a clear understanding of the chip's hierarchical structure, module distribution, and module communication relationships in the early stages of design. This provides an accurate structural foundation for subsequent communication requirement analysis, TSV planning, and circuit collaborative layout, thereby improving the systematicness and rationality of 3D packaged chip design, reducing subsequent design adjustments, and increasing overall design efficiency.

[0128] Please see the appendix Figures 1 to 2 The step 2 includes:

[0129] Step 2.1 Based on the established system structure model, obtain the data interaction relationships between each functional module and determine the set of modules participating in the communication;

[0130] ,

[0131] Representation module With modules They have a communication relationship. This indicates that there is no communication relationship.

[0132] Step 2.2 Perform statistical analysis on the data interaction behavior between each functional module to obtain parameters such as data transmission frequency, data transmission volume, and bandwidth requirements between modules;

[0133] Communication frequency: ,

[0134] For module With modules Communication frequency between them For statistical time periods;

[0135] Data transfer volume: ,

[0136] For module With modules Total data transfer volume between them For module With modules In the Data transmission volume in this communication For module With modules The number of communications between them;

[0137] Bandwidth requirement quantification: ,

[0138] For module With modules Bandwidth requirements between For module With modules Data transmission delay between them;

[0139] Step 2.3 Using functional modules as rows and columns of a matrix, the communication requirements between any two functional modules are quantitatively characterized, and the data transmission frequency, data transmission volume or bandwidth requirements are used as communication weights to establish the module communication requirement relationship.

[0140] The formula for calculating communication weight: ,

[0141] For module With modules Communication weights between them , , These are weighting coefficients, corresponding to the degree of influence of communication frequency, data transmission volume, and bandwidth requirements on the weights, respectively.

[0142] Step 2.4 Construct a module communication demand matrix based on the communication weights, which is used to represent the communication strength and communication demand between each functional module;

[0143] Module communication requirements matrix: ,

[0144] For the module communication requirement matrix, For module With modules Communication weights between them;

[0145] Step 2.5 Based on the communication weights in the module communication demand matrix, sort or threshold-filter the communication relationships between modules to identify module pairs that communicate frequently or have high communication demands, which will serve as the basis for subsequent chip functional area division and layout planning.

[0146] Ranking metrics: ,

[0147] For module Total communication requirements For module With modules Communication weights between them;

[0148] Threshold filtering: ,

[0149] The threshold is used to filter module pairs with high communication requirements.

[0150] Specifically, by statistically analyzing the data interaction relationships between functional modules based on a system architecture model, the communication frequency, data transmission volume, and bandwidth requirements between modules are quantified. A module communication requirement matrix is ​​established, and communication weights are calculated, thereby accurately quantifying the communication strength and requirements between each functional module. By sorting or filtering the communication weights based on thresholds, module pairs with frequent communication or high requirements are identified, providing a basis for subsequent chip functional area division and layout planning. This optimizes the communication efficiency and layout rationality of the chip design, improving overall system performance.

[0151] Please see the appendix Figures 1 to 2 The step 3 includes:

[0152] Step 3.1 Based on the established module communication requirement matrix, extract the communication weight parameters between each functional module and construct the module communication correlation evaluation index;

[0153] Step 3.2 Based on the communication correlation evaluation index, perform cluster analysis or grouping processing on the functional modules, and divide the modules with higher communication weight into the same functional area to reduce the physical distance between high-frequency communication modules.

[0154] Step 3.3 Establish an initial region partitioning model on the chip plane. Based on the module area requirements, power consumption distribution and process constraints, perform spatial mapping on each functional region to determine the position and boundary of each functional region on the chip plane.

[0155] Step 3.4 Reserve interconnection channel space between adjacent functional areas for subsequent cabling resource allocation and inter-layer interconnection structure layout, so as to avoid cabling congestion in high communication density areas;

[0156] Step 3.5 Iteratively optimizes the functional area division results, taking into account the module area utilization rate, area compactness and communication path length, and adjusts the area boundary position to minimize the average communication distance of highly communication-related modules, while ensuring that the overall chip layout meets the design rule constraints.

[0157] Specifically, by extracting communication weights based on the module communication demand matrix and constructing a communication correlation evaluation index, functional modules are clustered and divided, allowing modules with frequent communication to be spatially concentrated, thereby effectively shortening high-frequency communication paths and reducing signal delay and power consumption. At the same time, an initial region division model is established by combining module area, power distribution, and process constraints, and interconnection channel space is reserved to avoid wiring congestion. On this basis, the region boundaries are iteratively optimized to achieve a comprehensive balance between module area utilization, region compactness, and communication path length, thereby improving the rationality, wiring feasibility, and design stability of the overall chip layout.

[0158] Please see the appendix Figures 1 to 2 The step 4 includes:

[0159] Step 4.1 Based on the module communication requirement matrix and the chip functional area division results, identify functional module pairs that have cross-layer data transmission requirements between different chip layers, and determine the corresponding cross-layer communication requirement parameters;

[0160] Step 4.2 Based on the cross-layer communication requirement parameters, perform statistical analysis on the cross-layer data transmission volume, communication frequency and bandwidth requirements between each functional area to determine the intensity of inter-layer interconnection requirements between each area;

[0161] Step 4.3 Based on the required intensity of inter-layer interconnection, pre-planned areas for inter-layer interconnection structures are set between corresponding functional areas for arranging TSVs;

[0162] Step 4.4 Calculate the required number of TSVs based on the cross-layer communication bandwidth requirements between each region, and determine the arrangement and spacing between TSVs by combining TSV size parameters and process design rules;

[0163] Step 4.5 Position constraints are applied to the pre-planned TSV area in the chip layout to avoid functional module areas with high circuit density and to coordinate with chip wiring resources and power network planning, so as to reduce the impact on circuit layout and wiring resources.

[0164] Step 4.6 Based on the overall chip area utilization and interlayer interconnection efficiency, adjust and optimize the location, size and distribution of the TSV pre-planned area to form a TSV pre-planned scheme that meets the cross-layer communication requirements.

[0165] Specifically, cross-layer data transmission requirements are identified based on the module communication requirement matrix and functional area division. Statistical analysis of inter-layer communication frequency, bandwidth requirements, and data transmission volume determines the intensity of cross-layer interconnection requirements. Furthermore, TSV layout areas are pre-planned between functional areas, the number and arrangement of TSVs are calculated, and the TSV positions and spacing are optimized according to process rules to avoid impacting areas with high circuit density. Simultaneously, routing resources and power networks are coordinated, and finally, the TSV distribution scheme is adjusted to meet cross-layer communication requirements, optimizing the overall chip layout and inter-layer interconnection efficiency.

[0166] Please see the appendix Figures 1 to 2 Step 5 includes establishing a collaborative constraint model between TSVs and circuit layout. By comprehensively considering factors such as TSV location, circuit module layout, and inter-module communication paths, the TSV location and circuit module layout are jointly optimized. Specifically, this includes the following steps:

[0167] Step 5.1 Establish the circuit module set With TSV collection Among them, the circuit module The geometric center coordinates are TSV The position coordinates are And construct the module-TSV spatial coupling distance function:

[0168] ,

[0169] : No. The circuit module and the first Spatial coupling distance between TSVs : Center coordinates of the circuit module TSV location coordinates : No. The load factor of a TSV is used to represent the vertical communication volume carried by that TSV.

[0170] Step 5.2 Establish the module communication path cost function:

[0171] ,

[0172] Module With modules The overall communication path length between them : Path indicator variable, indicating whether the communication path passes through the first... One TSV, : No. Vertical interconnect height of each TSV, : TSV conduction efficiency coefficient;

[0173] Step 5.3 Construct the communication path coupling enhancement strength number:

[0174] ,

[0175] The strength of communication coupling between modules. Inter-module communication weights Path length nonlinear amplification factor Communication stability coefficient Stability adjustment coefficient;

[0176] Step 5.4 The communication stability coefficient is defined as follows:

[0177] ,

[0178] Standard deviation of module communication traffic Average module communication traffic.

[0179] Please see the appendix Figures 1 to 2 The step 5 further includes:

[0180] Step 5.5 Constructing the TSV spatial distribution constraint function:

[0181] ,

[0182] TSV spatial density index Distance decay index;

[0183] Step 5.6 Construct the module layout crowding function:

[0184] ,

[0185] Number of regions in the chip Module Is it located in the area? Indicator variables, Area Congestion penalty coefficient;

[0186] Step 5.7 Construct the objective function for co-optimization of TSV and circuit layout:

[0187] ,

[0188] : Collaborative optimization objective function, Weighting adjustment coefficient.

[0189] Specifically, by establishing a collaborative constraint model for TSV and circuit module layout, the TSV location, circuit module spatial layout, and inter-module communication paths are modeled in a unified manner. The module-TSV spatial coupling distance function, communication path cost function, and communication coupling strength index are introduced. Furthermore, by combining TSV spatial distribution constraints and module layout congestion constraints, a comprehensive optimization objective function is constructed to jointly optimize the TSV location and circuit module layout. This reduces communication path length and layout congestion while ensuring cross-layer communication efficiency, optimizes TSV distribution density and circuit layout coordination, and improves the interconnection efficiency, layout rationality, and overall design performance of the 3D packaged chip.

[0190] Please see the appendix Figures 1 to 2 Step 6 includes optimizing the TSV location and circuit module layout based on the collaborative constraint model established in step 5, in order to reduce layout conflicts, shorten communication paths, and improve chip area utilization. Specifically, it includes the following steps:

[0191] Step 6.1 Define the conflict degree function:

[0192] ,

[0193] Chip layout conflict index Indicator module With modules Are there any potential overlaps or conflicts? : The boundary spacing between modules or TSVs : Conflict threshold spacing; values ​​below this are considered potential conflicts. Conflict sensitivity adjustment coefficient;

[0194] Step 6.2 Communication path optimization function:

[0195] ,

[0196] Total cost of communication paths between modules Inter-module communication weights The Manhattan distance index parameter can be adjusted as a non-integer to allow for path "flexibility". via TSV The module pairs of the set, TSV load factor: This indicates the impact of communication traffic through this TSV. TSV vertical interconnect height;

[0197] Step 6.3 Area utilization optimization function:

[0198] ,

[0199] Effective chip area utilization rate Module Area occupied Total chip area TSV Area occupied Module and The overlapping area, Overlapping area penalty coefficient;

[0200] Step 6.4 Comprehensive optimization of the objective function:

[0201] ,

[0202] : Layout optimization comprehensive objective function, : Conflict level, communication path, and area utilization rate weighting coefficients : Conflict degree function Communication path function Area utilization rate function.

[0203] Specifically, based on the established collaborative constraint model between TSVs and circuit modules, a layout conflict degree function, a communication path optimization function, and an area utilization optimization function are introduced to jointly optimize the spatial layout of TSV locations and circuit modules. The conflict degree function evaluates the potential overlap and spacing conflict between modules or TSVs. The communication path cost function comprehensively considers the communication weight between modules, path distance, and TSV vertical interconnect load to reduce communication overhead. The area utilization function constrains the area occupied by modules and TSVs and imposes overlap penalties to improve chip space utilization. Finally, a comprehensive optimization objective function is constructed to coordinate the trade-offs between conflict degree, communication path length, and area utilization, thereby reducing layout conflicts, shortening communication paths, and improving the overall chip layout efficiency and area utilization.

[0204] Please see the appendix Figures 1 to 2 Step 7 includes:

[0205] Step 7.1 Based on the optimized circuit layout in Step 6, determine the final location of the circuit modules. The location of the module was determined by comprehensively considering factors such as inter-module conflict level, communication path optimization, and area utilization efficiency. The final location of the module was determined as follows:

[0206] ,

[0207] Circuit module The final location, Module With TSV The coupling distance between them :piece With modules The strength of communication coupling between them Layout congestion;

[0208] Step 7.2 Based on the optimization results of Step 6, the final location of each TSV is determined. The TSV positions are adjusted according to the weights in the objective function to ensure their rationality. The goal of TSV position optimization is to minimize chip hotspots and reduce communication latency between circuit modules.

[0209] ,

[0210] TSV The final location, Circuit module With TSV The coupling distance between them TSV spatial density;

[0211] Step 7.3 After determining the final locations of the circuit modules and TSVs, generate the 3D package layout data of the chip. This data includes the coordinate information of all modules and TSVs on the chip, as well as the chip circuit connection information. The calculation method for generating the package layout is as follows:

[0212] ,

[0213] : Package layout data, Module Area occupied TSV The area occupied.

[0214] Please see the appendix Figures 1 to 2 The step 7 further includes:

[0215] Step 7.4 Based on the final circuit module and TSV location, design the chip packaging structure, including the external pin configuration of the chip, the selection of packaging materials, and the packaging type;

[0216] Step 7.5 Based on the final chip layout, optimize the package structure to reduce hot spots and improve package reliability and performance:

[0217] ,

[0218] : Encapsulation structure optimization objective function, Module thermal load, TSV Power loss, : Weighting coefficients for heat load and power loss;

[0219] After completing the package structure design in step 7.6, the corresponding package layout data is generated, including the spatial layout of each module and TSV in the package, the position of external pins and electrical connections. The generated package layout data will be used for subsequent manufacturing verification and testing to ensure that the package structure matches the circuit function of the chip.

[0220] Specifically, based on the circuit layout optimized in step 6, the positions of circuit modules and TSVs are finally determined, taking into account inter-module conflict, communication path optimization, and area utilization efficiency. After optimization, 3D package layout data is generated, including the coordinates of modules and TSVs and circuit connection information. Further design of the package structure is undertaken, optimizing external pin configuration, package material selection, and package type to ensure reduced hotspots and improved package reliability and performance. The final package layout data provides a basis for subsequent manufacturing verification and testing.

[0221] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-density integrated chip design method based on a three-dimensional packaging structure, characterized in that, include: Step 1: System structure model. Based on the functional requirements, establish a structural model of the three-dimensional packaged chip, determine the allocation of each chip layer and module, and clarify the communication relationship between modules. Step 2: Module communication requirement matrix. Analyze the communication frequency and bandwidth requirements between modules, construct a communication requirement matrix, and identify module pairs that communicate frequently. Step 3: Chip area partitioning. Based on the communication demand matrix, the chip functional areas are divided to reduce communication distance and reserve space for interconnection channels. Step 4: TSV pre-planning area. Set up the TSV pre-planning area according to communication requirements, determine the number and spacing of TSVs, and avoid dense circuit areas. Step 5: Collaborative Constraint Model. Establish a collaborative constraint model between TSV and circuit layout, considering location, circuit layout, and communication path factors, and optimize the layout of both. Step 6: Optimize layout calculation. Based on the collaborative constraint model, optimize the layout of TSV and circuit to reduce layout conflicts, shorten communication paths, and improve area utilization. Step 7: Package structure design. Based on the optimized layout results, determine the final chip circuit and TSV positions, generate 3D package layout data, and complete the design.

2. The high-density integrated chip design method based on a three-dimensional packaging structure according to claim 1, characterized in that, The step 1 includes: Step 1.1 Based on the functional requirements of the target 3D packaged chip, perform a system-level analysis of the overall chip function, determine the required functional module types and their functional attributes, and establish a system functional module set; Step 1.2 Based on the design requirements of the three-dimensional packaging structure, the functional module set is hierarchically divided, the distribution relationship of each functional module in different chip layers is determined, and a chip hierarchical structure model is established. Step 1.3 Based on the data interaction requirements between each functional module, determine the data transmission direction, communication frequency, and bandwidth requirements between modules, and establish a communication relationship model between modules; Step 1.4 Integrate the hierarchical distribution relationship and module communication relationship of the functional modules to construct a system structure model of the three-dimensional packaged chip, which is used to describe the chip hierarchical structure, module allocation relationship and inter-module communication relationship.

3. The high-density integrated chip design method based on a three-dimensional packaging structure according to claim 1, characterized in that, The step 2 includes: Step 2.1 Based on the established system structure model, obtain the data interaction relationships between each functional module and determine the set of modules participating in the communication; ， Representation module With modules They have a communication relationship. This indicates that there is no communication relationship. Step 2.2 Perform statistical analysis on the data interaction behavior between each functional module to obtain parameters such as data transmission frequency, data transmission volume, and bandwidth requirements between modules; Communication frequency: , For module With modules Communication frequency between them For statistical time periods; Data transfer volume: , For module With modules Total data transfer volume between them For module With modules In the Data transmission volume in this communication For module With modules The number of communications between them; Bandwidth requirement quantification: , For module With modules Bandwidth requirements between For module With modules Data transmission delay between them; Step 2.3 Using functional modules as rows and columns of a matrix, the communication requirements between any two functional modules are quantitatively characterized, and the data transmission frequency, data transmission volume or bandwidth requirements are used as communication weights to establish the module communication requirement relationship. The formula for calculating communication weight: , For module With modules Communication weights between them , , These are weighting coefficients, corresponding to the degree of influence of communication frequency, data transmission volume, and bandwidth requirements on the weights, respectively. Step 2.4 Construct a module communication demand matrix based on the communication weights, which is used to represent the communication strength and communication demand between each functional module; Module communication requirements matrix: , For the module communication requirement matrix, For module With modules Communication weights between them; Step 2.5 Based on the communication weights in the module communication demand matrix, sort or threshold-filter the communication relationships between modules to identify module pairs that communicate frequently or have high communication demands, which will serve as the basis for subsequent chip functional area division and layout planning. Ranking metrics: , For module Total communication requirements For module With modules Communication weights between them; Threshold filtering: , The threshold is used to filter module pairs with high communication requirements.

4. The high-density integrated chip design method based on a three-dimensional packaging structure according to claim 1, characterized in that, The step 3 includes: Step 3.1 Based on the established module communication requirement matrix, extract the communication weight parameters between each functional module and construct the module communication correlation evaluation index; Step 3.2 Based on the communication correlation evaluation index, perform cluster analysis or grouping processing on the functional modules, and divide the modules with higher communication weight into the same functional area to reduce the physical distance between high-frequency communication modules. Step 3.3 Establish an initial region partitioning model on the chip plane. Based on the module area requirements, power consumption distribution and process constraints, perform spatial mapping on each functional region to determine the position and boundary of each functional region on the chip plane. Step 3.4 Reserve interconnection channel space between adjacent functional areas for subsequent cabling resource allocation and inter-layer interconnection structure layout, so as to avoid cabling congestion in high communication density areas; Step 3.5 Iteratively optimizes the functional area division results, taking into account the module area utilization rate, area compactness and communication path length, and adjusts the area boundary position to minimize the average communication distance of highly communication-related modules, while ensuring that the overall chip layout meets the design rule constraints.

5. The high-density integrated chip design method based on a three-dimensional packaging structure according to claim 1, characterized in that, The step 4 includes: Step 4.1 Based on the module communication requirement matrix and the chip functional area division results, identify functional module pairs that have cross-layer data transmission requirements between different chip layers, and determine the corresponding cross-layer communication requirement parameters; Step 4.2 Based on the cross-layer communication requirement parameters, perform statistical analysis on the cross-layer data transmission volume, communication frequency and bandwidth requirements between each functional area to determine the intensity of inter-layer interconnection requirements between each area; Step 4.3 Based on the required intensity of inter-layer interconnection, pre-planned areas for inter-layer interconnection structures are set between corresponding functional areas for arranging TSVs; Step 4.4 Calculate the required number of TSVs based on the cross-layer communication bandwidth requirements between each region, and determine the arrangement and spacing between TSVs by combining TSV size parameters and process design rules; Step 4.5 Position constraints are applied to the pre-planned TSV area in the chip layout to avoid functional module areas with high circuit density and to coordinate with chip wiring resources and power network planning, so as to reduce the impact on circuit layout and wiring resources. Step 4.6 Based on the overall chip area utilization and interlayer interconnection efficiency, adjust and optimize the location, size and distribution of the TSV pre-planned area to form a TSV pre-planned scheme that meets the cross-layer communication requirements.

6. The high-density integrated chip design method based on a three-dimensional packaging structure according to claim 1, characterized in that, Step 5 involves establishing a collaborative constraint model between TSVs and circuit layout. By comprehensively considering factors such as TSV location, circuit module layout, and inter-module communication paths, the model jointly optimizes the TSV location and circuit module layout. Specifically, it includes the following steps: Step 5.1 Establish the circuit module set With TSV collection Among them, the circuit module The geometric center coordinates are TSV The position coordinates are And construct the module-TSV spatial coupling distance function: ， : No. The circuit module and the first Spatial coupling distance between TSVs : Center coordinates of the circuit module TSV location coordinates : No. The load factor of a TSV is used to represent the vertical communication volume carried by that TSV. Step 5.2 Establish the module communication path cost function: ， Module With modules The overall communication path length between them : Path indicator variable, indicating whether the communication path passes through the first... One TSV, : No. Vertical interconnect height of each TSV, : TSV conduction efficiency coefficient; Step 5.3 Construct the communication path coupling enhancement strength number: ， The strength of communication coupling between modules. Inter-module communication weights Path length nonlinear amplification factor Communication stability coefficient Stability adjustment coefficient; Step 5.4 The communication stability coefficient is defined as follows: ， Standard deviation of module communication traffic Average module communication traffic.

7. The high-density integrated chip design method based on a three-dimensional packaging structure according to claim 6, characterized in that, The step based on step 5 also includes: Step 5.5 Constructing the TSV spatial distribution constraint function: ， TSV spatial density index Distance decay index; Step 5.6 Construct the module layout crowding function: ， Number of regions in the chip Module Is it located in the area? Indicator variables, Area Congestion penalty coefficient; Step 5.7 Construct the objective function for co-optimization of TSV and circuit layout: ， : Collaborative optimization objective function, Weighting adjustment coefficient.

8. The high-density integrated chip design method based on a three-dimensional packaging structure according to claim 1, characterized in that, Step 6 includes optimizing the TSV location and circuit module layout based on the collaborative constraint model established in Step 5, in order to reduce layout conflicts, shorten communication paths, and improve chip area utilization. Specifically, it includes the following steps: Step 6.1 Define the conflict degree function: ， Chip layout conflict index Indicator module With modules Are there any potential overlaps or conflicts? : The boundary spacing between modules or TSVs : Conflict threshold spacing; values ​​below this are considered potential conflicts. Conflict sensitivity adjustment coefficient; Step 6.2 Communication path optimization function: ， Total cost of communication paths between modules Inter-module communication weights The Manhattan distance index parameter can be adjusted as a non-integer to allow for path "flexibility". via TSV The module pairs of the set, TSV load factor: This indicates the impact of communication traffic through this TSV. TSV vertical interconnect height; Step 6.3 Area utilization optimization function: ， Effective chip area utilization rate Module Area occupied Total chip area TSV Area occupied Module and The overlapping area, Overlapping area penalty coefficient; Step 6.4 Comprehensive optimization of the objective function: , : Layout optimization comprehensive objective function, : Conflict level, communication path, and area utilization rate weighting coefficients : Conflict degree function Communication path function Area utilization rate function.

9. The high-density integrated chip design method based on a three-dimensional packaging structure according to claim 1, characterized in that, The step based on step 7 includes: Step 7.1 Based on the optimized circuit layout in Step 6, determine the final location of the circuit modules. The location of the module was determined by comprehensively considering factors such as inter-module conflict level, communication path optimization, and area utilization efficiency. The final location of the module was determined as follows: ， Circuit module The final location, Module With TSV The coupling distance between them :piece With modules The strength of communication coupling between them Layout congestion; Step 7.2 Based on the optimization results of Step 6, the final location of each TSV is determined. The TSV positions are adjusted according to the weights in the objective function to ensure their rationality. The goal of TSV position optimization is to minimize chip hotspots and reduce communication latency between circuit modules. ， TSV The final location, Circuit module With TSV The coupling distance between them TSV spatial density; Step 7.3 After determining the final locations of the circuit modules and TSVs, generate the 3D package layout data of the chip. This data includes the coordinate information of all modules and TSVs on the chip, as well as the chip circuit connection information. The calculation method for generating the package layout is as follows: ， : Package layout data, Module Area occupied TSV The area occupied.

10. The high-density integrated chip design method based on a three-dimensional packaging structure according to claim 1, characterized in that, The step based on step 7 also includes: Step 7.4 Based on the final circuit module and TSV location, design the chip packaging structure, including the external pin configuration of the chip, the selection of packaging materials, and the packaging type; Step 7.5 Based on the final chip layout, optimize the package structure to reduce hot spots and improve package reliability and performance: ， : Encapsulation structure optimization objective function, Module thermal load, TSV Power loss, : Weighting coefficients for heat load and power loss; After completing the package structure design in step 7.6, the corresponding package layout data is generated, including the spatial layout of each module and TSV in the package, the position of external pins and electrical connections. The generated package layout data will be used for subsequent manufacturing verification and testing to ensure that the package structure matches the circuit function of the chip.

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