Refresh control circuit, memory and refresh control method

Abstract

This application relates to the field of memory, providing a refresh control circuit, a memory, and a refresh control method. The refresh control circuit includes a page table, a first comparison circuit, and a second comparison circuit. The page table is configured to store multiple row addresses and their activation counts. The first comparison circuit, connected to the page table, is configured to receive the currently active row address and its activation count, and compare the currently active row address and its activation count with the multiple row addresses and their activation counts stored in the page table. When a first preset condition is met, the currently active row address and its activation count are stored in the page table. The second comparison circuit, connected to the page table, is configured to compare the activation counts of the multiple row addresses in the page table and output the row address with the highest activation count as a candidate row address.

Description

Technical Field

[0001] This application relates to the field of memory, and in particular to a refresh control circuit and refresh control method for memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) suffers from a hardware vulnerability known as row hammering. When a row is accessed, its adjacent rows are electrically affected due to coupling effects. When a particular row is accessed frequently (i.e., "hammered"), the charge of its adjacent rows may be incorrectly flipped, leading to data corruption. This phenomenon is called row hammering.

[0003] To address the row hammer problem, the industry has adopted various protective measures, such as increasing the refresh rate, implementing Target Row Refresh (TRR), and using Error Correcting Code (ECC) circuitry. With technological advancements, a new technique called Per-Row Activation Counting (PRAC) has emerged, which precisely calculates the number of DRAM activations at the row level. When the DRAM detects excessive activation counts for a particular row, it alerts the system to pause activation, read, and write operations and specifies a timeframe for mitigation measures. Through close coordination between the DRAM and the system, this provides a fundamentally accurate and predictable method for addressing data integrity challenges. However, DRAM contains more than 64K rows, and real-time monitoring of activation counts for all 64K rows places a significant burden on the memory's workload and is inefficient. Summary of the Invention

[0004] This application provides a refresh control circuit, a memory, and a refresh control method, which can solve the problem that the current hammer refresh scheme places a heavy burden on the memory and is inefficient.

[0005] According to some embodiments of this application, one aspect of this application provides a refresh control circuit, including a page table, a first comparison circuit, and a second comparison circuit; wherein, the page table is configured to store multiple row addresses and the activation counts of the multiple row addresses; the first comparison circuit is connected to the page table and is configured to receive the currently active row address and its activation count, and compare the currently active row address and its activation count with the multiple row addresses and their activation counts stored in the page table, and when a first preset condition is met, store the currently active row address and its activation count into the page table; the second comparison circuit is connected to the page table and is configured to compare the activation counts of the multiple row addresses in the page table, and output the row address with the largest activation count as a candidate row address.

[0006] In some embodiments, the refresh control circuit is configured to generate an avoidance warning signal when a second preset condition is met; wherein the avoidance warning signal is a flag signal in the memory used to pause read / write operations and perform a refresh operation.

[0007] In some embodiments, the second preset condition is: the minimum number of activations of all row addresses in the page table is greater than a preset threshold.

[0008] In some embodiments, the page table is configured to store the row address output by the first comparator circuit and its activation count during a first time period; the page table is also configured to store the row address output by the third comparator circuit during a second time period, and to increment the count value corresponding to the row address stored in the page table by 1.

[0009] In some embodiments, the refresh control circuit is configured to periodically receive refresh commands, refresh one or more rows adjacent to the candidate row address based on the refresh commands, and delete the candidate row address from the page table.

[0010] In some embodiments, the first preset condition includes: there is a free position in the page table where no row address is stored; the currently activated row address is the same as the row address stored in the page table; or the activation count of the currently activated row address is greater than the minimum of the activation counts of multiple row addresses stored in the page table.

[0011] According to some embodiments of this application, another aspect of this application provides a memory, the memory including the refresh control circuit and storage body described in any of the foregoing embodiments, the storage body including a plurality of storage rows, the storage rows storing storage data and activation counts.

[0012] According to some embodiments of this application, another aspect of this application provides a refresh control method, including: determining whether the currently activated row address is the same as the row address stored in the page table; if they are the same, updating the activation count corresponding to the row address in the page table to the activation count carried by the currently activated row address; if they are different, comparing the activation count carried by the currently activated row address with the minimum activation count in the page table, and determining whether the activation count carried by the currently activated row address is greater than the minimum activation count in the page table; if the activation count carried by the currently activated row address is greater than the minimum activation count in the page table, replacing the row address and its activation count corresponding to the minimum activation count in the page table with the currently activated row address and its activation count; if the activation count carried by the currently activated row address is less than the minimum activation count in the page table, the data in the page table remains unchanged.

[0013] In some embodiments, the refresh control method further includes: comparing the minimum number of activations in the page table with a preset threshold; if the minimum number of activations in the page table is greater than the preset threshold, generating an avoidance warning signal; wherein the avoidance warning signal is a flag signal in the memory used to pause read / write operations and perform refresh operations.

[0014] In some embodiments, the refresh control method further includes: refreshing one or more rows adjacent to the row address with the highest number of activations in the page table.

[0015] The technical solution provided in this application has at least the following advantages:

[0016] A refresh control circuit is provided. By storing the active row address and its activation count in a page table, and comparing the currently active row address and its activation count with the row addresses and their activation counts stored in the page table each time, row addresses that meet the conditions can be filtered according to preset rules. This avoids real-time monitoring and tracking of all rows in the memory, reducing the monitoring burden on the memory. Furthermore, since the row address with the highest activation count in the page table is output as the candidate row address, adjacent rows can be refreshed periodically, thereby reducing the frequency of memory pause operations and improving memory efficiency. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 A schematic diagram of a storage medium provided in an embodiment of this disclosure;

[0019] Figure 2 A schematic diagram of a refresh control circuit provided in an embodiment of this disclosure;

[0020] Figure 3 A schematic diagram of a memory provided for an embodiment of this disclosure;

[0021] Figure 4 A flowchart of a refresh control method provided in an embodiment of this disclosure;

[0022] Figure 5 This is a schematic diagram illustrating the dynamic changes of data within a page table, as provided in an embodiment of this disclosure. Detailed Implementation

[0023] Hereinafter, exemplary embodiments of the invention will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily practice the invention. As will be appreciated by those skilled in the art, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. For example, the exemplary embodiments provided herein are thought to be implementable by combining them, in whole or in part. Specifically, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, can be understood as a description relating to another exemplary embodiment, unless a contrary or contradictory description is provided therein.

[0024] Throughout this specification, when any part is referred to as being “connected” to another part, it includes cases where any part and another part are “indirectly connected” to each other due to the presence of another part between them, as well as cases where any part and another part are “directly connected” to each other. For example, it should be understood that when an element is referred to as being “connected” or “attached” or “on another element” to another element, it may be directly connected or attached to or on that other element, or there may be an intermediate element present. Conversely, when an element is referred to as being “directly connected” or “directly attached” to another element, or referred to as being “in contact” or “in contact” with another element, there is no intermediate element at the point of contact.

[0025] Furthermore, "electrical connection" conceptually includes both physical connection and physical disconnection. It is understood that when an element is referred to using terms such as "first" and "second," the element is not limited in this respect. These terms may be used only to distinguish the element from other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

[0026] As the background technology explains, Row Activation Counting (PRAC) counts and stores the activation count of each row, and monitors and detects the activation count of that row. When an excessive activation count is detected in a row, the system is alerted to pause activation, read, and write operations and take mitigation measures within a specified time. However, DRAM contains more than 64K rows, and detecting the activation count of 64K rows places a significant burden on the memory's workload. Furthermore, once an excessive activation count is detected in a row, triggering a pause operation, the memory will stop the current activation, read, and write operations, which also reduces the memory's operating efficiency.

[0027] Therefore, this application provides a refresh control circuit, including a page table, a first comparison circuit, and a second comparison circuit; wherein, the page table is configured to store multiple row addresses and the activation counts of the multiple row addresses; the first comparison circuit is connected to the page table and is configured to receive the currently active row address and its activation count, and compare the currently active row address and its activation count with the multiple row addresses and their activation counts stored in the page table, and when a first preset condition is met, store the currently active row address and its activation count in the page table; the second comparison circuit is connected to the page table and is configured to compare the activation counts of the multiple row addresses in the page table, and output the row address with the largest activation count as a candidate row address. By storing the active row address and its activation count in the page table, and comparing the currently active row address and its activation count with the row addresses and their activation counts stored in the page table each time, row addresses that meet the conditions can be filtered according to preset rules. This avoids real-time monitoring and tracking of all rows in the memory, reducing the monitoring burden on the memory. Furthermore, since the row address with the highest activation count in the page table is output as the candidate row address, its neighboring rows can be refreshed periodically, thereby reducing the frequency of memory pause operations and improving memory efficiency.

[0028] Furthermore, the scheme in this application differs from conventional page tables. Conventional page tables are essentially probabilistically refreshed, storing randomly sampled addresses in the page table, which is highly dependent on the randomness of sampling, the capacity of the page table, and the refresh frequency. In contrast, this application directly utilizes the currently active row address and its activation count, thus avoiding the shortcomings of random sampling, preventing omissions, and being more accurate due to directly obtaining the activation count.

[0029] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] Figure 1 This is a schematic diagram of a memory bank provided in an embodiment of this application. The memory includes multiple memory banks, each of which is composed of multiple memory cells arranged in a row and column array. A row of memory cells constitutes a memory row. Each memory row contains multiple memory cells. Some memory cells store memory data, while others store the activation count (AC) of that memory row. For each activation operation (ACT), the memory can obtain the row address of the activated row and the activation count of that row.

[0031] Figure 2 This is a schematic diagram of a refresh control circuit provided in an embodiment of this application. The refresh control circuit 20 includes a page table 210, a first comparison circuit 220, and a second comparison circuit 230; wherein,

[0032] Page table 210 is configured to store multiple row addresses and the number of times the multiple row addresses are activated;

[0033] The first comparison circuit 220 is connected to the page table 210 and is configured to receive the currently active row address and its activation count, and compare the currently active row address and its activation count with multiple row addresses and their activation counts stored in the page table. When the first preset condition is met, the currently active row address and its activation count are stored in the page table.

[0034] The second comparison circuit 230 is connected to the page table 210 and is configured to compare the activation counts of multiple row addresses in the page table 210 and output the row address with the highest activation count as a candidate row address.

[0035] Specifically, in some embodiments, the page table can be composed of a storage structure within the memory, such as a First In First Out (FIFO) register group. This FIFO register group can be used to store information. A set of FIFO registers may include a status register 211, a row address register 212, and an activation count register 213, forming a row of the page table 210. Figure 2 The page table shown has six rows. Correspondingly, the first-in-first-out (FIFO) register set includes six registers, which can store six row addresses and their related information. The information stored in the status register 211 indicates whether the row in the page table stores a row address, i.e., whether the row is occupied. The information stored in the row address register 212 is the row address information written to the page table. The information stored in the activation count register 213 is the activation count corresponding to the row address stored in that row. In some embodiments, the activation count register 213 can also be constructed using a counter. In still other embodiments, the page table can also be constructed from a portion of the storage cells in the storage array.

[0036] The activation count of a row address refers to the number of times a row address is activated within a refresh cycle or a counting cycle. If the row is refreshed, the activation count is reset, and the calculation of the activation count restarts.

[0037] refer to Figure 2 The first comparator circuit 220 receives the currently active row address and its activation count. Combined with... Figure 1The currently activated row address is the row address of the memory cell corresponding to the current activation instruction, and the activation count of the currently activated row address is the activation count stored in the corresponding row of the memory array, which can be directly read from the memory row. Since the first comparison circuit 220 can directly receive the currently activated row address and its activation count, processing logic can be omitted compared to other methods such as random sampling. Furthermore, because the first comparison circuit 220 operates in accordance with the current row activation, it can cover a wider range of row addresses that may be subject to row hammer attacks, avoiding omissions.

[0038] The first comparison circuit 220 is also connected to the page table 210, and compares the currently active row address and its activation count with multiple row addresses and their activation counts stored in the page table. When a first preset condition is met, the currently active row address and its activation count are stored in the row address register and activation count register of the page table. In some embodiments, if the row address to be written to the page table already exists in the page table, only the activation count can be written to the activation count register of the page table.

[0039] The first comparison circuit can be formed using a comparator. The comparator can be used to compare each of the row addresses stored in row address register 212 with the currently active row address to determine if they are the same. The comparator can also be used to compare each of the activation counts of all row addresses stored in activation count register 213 with the activation count of the currently active row address to determine their magnitude; alternatively, the comparator can also be used to compare the minimum activation count of all row addresses stored in activation count register 213 with the activation count of the currently active row address to determine the magnitude of the minimum value. By using the comparison circuit of the first comparison circuit, the complexity of monitoring at least 64K rows of operations can be reduced.

[0040] The second comparison circuit 230 can be formed using a comparator. The second comparison circuit 230 is connected to the page table 210, compares the activation counts of multiple or all row addresses within the page table 210, and outputs the row address with the highest activation count as a candidate row address. Specifically, the second comparison circuit 230 is connected to the row address register 212 and the activation count register 213, compares the multiple or all activation counts stored in the activation count register 213, and outputs the row address with the highest activation count as a candidate row address.

[0041] During the operation of the refresh control circuit, each time the row address stored in the page table changes, the first comparison circuit and the second comparison circuit both change accordingly. The row address corresponding to the minimum activation count pointed to by the first comparison circuit may change, and the row address corresponding to the maximum activation count pointed to by the second comparison circuit may also change.

[0042] Since the second comparison circuit 230 compares the row address with the maximum number of activations, the refresh control circuit can use the row address with the most activations in the page table as the row hammer address and refresh it periodically, reducing the number of times the pause operation is triggered and improving the system's defense performance.

[0043] Therefore, by storing the active row address and its activation count in the page table, and comparing the currently active row address and its activation count with the row address and its activation count stored in the page table each time, row addresses that meet the conditions can be filtered out according to preset rules. This avoids real-time monitoring, tracking, and comparison operations on all rows of the memory, reducing the monitoring burden on the memory. Furthermore, since the row address with the highest activation count in the page table is output as the candidate row address, its neighboring rows can be refreshed periodically, thereby reducing the frequency of memory pause operations and improving the working efficiency of the memory.

[0044] In some embodiments, the first preset conditions include: there are free positions in the page table where no row address is stored; the currently activated row address is the same as the row address stored in the page table; or the activation count of the currently activated row address is greater than the minimum of the activation counts of multiple row addresses stored in the page table.

[0045] Specifically, such as Figure 2 In the page table, status register 211 can store one bit of data. When the data bit is valid (e.g., high level), it indicates that information is stored in the row address register 212 and the activation count register 213 for that row. When the data bit is invalid (e.g., low level), it indicates that no information is stored in the row address register and the activation count register 213 for that row. If status register 211 indicates that at least one row in the page table is not occupied (i.e., at least one row's row address register and activation count register 213 do not store information), then there are still free spaces in the page table that do not store row addresses. In this case, the first preset condition is met, and the currently active row address and its activation count can be stored in page table 210.

[0046] Alternatively, if the first comparison circuit 220 finds that the currently active row address is the same as a row address stored in the page table, since the activation count carried by the currently active row address has been updated, the activation count carried by the currently active row address can be directly updated into the page table 210, replacing the original activation count in the activation count register 213 corresponding to that row address.

[0047] Alternatively, if the first comparison circuit 220 finds that the activation count of the currently active row address is greater than the minimum activation count of the multiple row addresses stored in the page table, then the currently active row address and its associated activation count can be directly updated into the page table 210, replacing the row address and its activation count corresponding to the minimum activation count of the multiple row addresses stored in the page table. In this case, the data stored in the row address register 212 and the activation count register 213 are both updated.

[0048] Therefore, the currently active row address and its activation count can be temporarily stored in the page table, and the activation count can be updated in real time. By comparing the minimum activation count, the row address with the larger activation count is retained. This makes it simple and easy to monitor and compare all row addresses and their activation counts, avoiding the heavy workload of monitoring and comparing the activation counts of each of the 64K storage rows.

[0049] In some embodiments, the refresh control circuit is further configured to generate an Alert Back-off (ABO) signal when a second preset condition is met; wherein the Alert Back-off signal is a flag signal in the memory used to suspend read / write operations and perform a refresh operation. Once the Alert Back-off signal is triggered, the memory stops all other operations (including read operations, write operations, activation operations, etc.) and only performs a refresh operation. The Alert Back-off signal is triggered by the memory and received by the memory controller. When the memory controller receives the Alert Back-off signal, it immediately controls the memory to suspend read / write operations and perform a refresh.

[0050] In some embodiments, the second preset condition may be: the minimum number of activations of all row addresses in page table 210 is greater than a preset threshold. Since the first comparison circuit 220 compares the currently active row address and its activation count with the row addresses and their activation counts in the page table, the first comparison circuit 220 can be used to compare the minimum number of activations of all row addresses in page table 210 with the preset threshold. If the minimum number of activations of all row addresses in page table 210 is greater than the preset threshold, an avoidance warning signal is issued.

[0051] In other embodiments, the second preset condition may be: the activation count of three row addresses in page table 210 is greater than a preset threshold. That is, there are three data values ​​in activation count register 213 that are greater than the preset threshold. The present invention is not limited to this; the second preset condition may also be: the activation count of two or four row addresses in page table 210 is greater than the preset threshold, etc.

[0052] The specific value of the preset threshold can be determined by a single factor or a combination of factors such as process yield, operating frequency, and refresh rate. In some embodiments, the preset threshold can be set to, for example, 3000.

[0053] Therefore, by setting a trigger condition for an avoidance warning signal through a second preset condition, the memory can be refreshed in a timely manner when the activation count of a certain row or rows is too high, thus fixing vulnerabilities and correcting errors. Furthermore, by setting the avoidance warning signal to be triggered when the minimum activation count of all row addresses in the page table exceeds a preset threshold, the first comparison circuit can be reused, saving circuit processing logic and reducing chip area.

[0054] In some embodiments, page table 210 is configured to store the row address output by the first comparison circuit 220 and its activation count during a first time period; page table 210 is also configured to store the row address output by the third comparison circuit (not shown) during a second time period, and to increment the count value corresponding to the row address stored in the page table by 1.

[0055] Specifically, the first comparison circuit 220 receives the currently active row address and its activation count. The third comparison circuit (not shown) receives the randomly sampled row address received by the random sampling circuit. The third comparison circuit selects and discovers candidate row addresses for the row hammer by matching the sampled address with the address stored in the page table and comparing the count value corresponding to the row address stored in the page table. The comparison mode of the third comparison circuit differs from that of the first comparison circuit 220. Correspondingly, in the first time period, page table 210 and the first comparison circuit 220 perform the selection and operation of row address and activation count in PRAC mode; in the second time period, page table 210 and the third comparison circuit perform the selection and operation of randomly sampled row address and its activation count in DLUT (Dynamic Look-up Table) mode. Therefore, page tables can be reused in different time periods and under different functions.

[0056] In DLUT mode, a dynamic lookup table is used to identify frequently accessed memory rows and refresh the adjacent rows of the frequently accessed candidate row addresses. In DLUT mode, since the activation count is not stored within the memory row, the activation count register 213 in the page table cannot directly obtain the activation count. Therefore, the activation count register 213 in the page table correspondingly stores the count value of the sampled row, and each time the sampled row address matches the row address stored in the page table, the count value of that row address is incremented by 1. When the sampled row address does not match the row address stored in the page table, the sampled row address is placed in an empty space in the page table (if one exists), and the counter is set to 1. This is how the access count is counted. In this case, the activation count register 213 functions as a counter, which can be implemented using a counter.

[0057] Since PRAC mode and DLUT mode are not used at the same time, page table 210 can be reused in both modes, thus saving memory area consumed by the large page table. Page table 210 is reset each time the memory restarts or switches modes, thereby avoiding data conflicts.

[0058] In some embodiments, the first and third comparator circuits can each be connected to page table 210 and the power supply via switches. In PRAC mode, the connection of the third comparator circuit to page table 210 and the power supply can be disabled; in DLUT mode, the connection of the third comparator circuit to page table 210 and the power supply can be disabled, thereby saving power consumption. In other embodiments, since PRAC and DLUT modes are not enabled simultaneously, this switch may not be required. When PRAC is not enabled, DLUT mode can be used to prevent row hammer attacks and ensure circuit data integrity.

[0059] In some embodiments, the refresh control circuit 20 is configured to periodically (i.e., at fixed or variable intervals) receive refresh commands, refresh one or more rows adjacent to the candidate row address based on the refresh commands, and delete the candidate row address from the page table.

[0060] The refresh command may include a Row Hammer Refresh (RHR) command and a Refresh Management (RFM) command issued by the system. The refresh control circuit 20 may also include a refresh circuit (not shown), connected to the second comparison circuit 230. The refresh circuit receives the candidate row address, determines one or more row addresses adjacent to the candidate row address based on the candidate row address, refreshes the one or more row addresses adjacent to the candidate row address, and deletes the candidate row address from the page table 210 after the refresh. After deletion, a free space is created in the page table 210, which may be indicated by the status register 211.

[0061] Therefore, by monitoring the row addresses with the highest activation count and periodically performing row hammer refresh protection on these row addresses, the possibility of data flipping due to the accumulation of activation counts can be reduced. This advance prediction can reduce the triggering of the Avoidance Warning (ABO) mechanism, effectively improve system performance, and avoid system pauses and reduced efficiency caused by the triggering of the Avoidance Warning (ABO) mechanism.

[0062] like Figure 3As shown, this application embodiment also provides a memory 1, which includes the refresh control circuit 20 and the memory bank 10 described in any of the foregoing embodiments. The memory bank 10 includes multiple memory rows, and the memory rows store stored data and activation counts.

[0063] In this system, a storage row is a row composed of multiple storage units, and the stored data is the information that can be normally stored in each storage row. The activation count is the number of times the storage row is activated within a counting cycle (or refresh cycle, or other cycles). In some embodiments, each activation inputs the row address and the activation count of that row into the refresh control circuit 20 for refresh control operation, and after the row is refreshed, the activation count of that row is reset (initialized). In some embodiments, not every activation inputs the row address and activation count of the currently activated row into the refresh control circuit 20. Instead, activations of a portion of the row can be selectively filtered according to certain rules, and the row addresses and activation counts of these activated rows are input into the refresh control circuit 20 for refresh control operation.

[0064] In some embodiments, the memory 1 includes a plurality of memory banks 10 and a plurality of refresh control circuits 20, with each memory bank corresponding to a refresh control circuit.

[0065] In some embodiments, the memory 1 also includes an avoidance warning signal transmitting circuit (not shown). The avoidance warning signal transmitting circuit receives the avoidance warning signal and adjusts the avoidance warning signal to the waveform required by the memory controller. For example, it converts a high-level active signal to a low-level active signal, or it reshapes the waveform, adjusting a pulse of one level period to a pulse of two periods, and it performs path driving on the avoidance warning signal. The avoidance warning signal transmitting circuit sends the avoidance warning signal to the memory controller. The memory controller receives the avoidance warning signal (ABO) and, based on the avoidance warning signal, issues a row hammer refresh command RHR or a refresh management command RFM to the memory, instructing the memory to refresh. Correspondingly, a mode register (MR) can be added inside the memory, such as MR70. When the mode register is a specific value, such as MR70:OP[1]=1B, the PRAC mode is enabled.

[0066] Therefore, the above design avoids the need for real-time monitoring and tracking of all rows in the memory, reducing the monitoring burden on the memory; and since adjacent rows can be refreshed periodically, the frequency of memory pause operations is reduced, which helps to improve the working efficiency of the memory.

[0067] Figure 4This is a flowchart illustrating a refresh control method provided in an embodiment of this disclosure. The refresh control method can be implemented using the refresh control circuit and memory described in any of the above embodiments. Figure 4 Refresh control methods include:

[0068] Determine if the currently active row address is the same as the row address stored in the page table. Figure 4 S3);

[0069] If they are the same, then update the activation count corresponding to the row address in the page table to the activation count carried by the currently active row address. Figure 4 in S4);

[0070] If they are not the same, the activation count carried by the currently active row address is compared with the minimum activation count in the page table to determine whether the activation count carried by the currently active row address is greater than the minimum activation count in the page table. Figure 4 S7);

[0071] If the activation count carried by the currently active row address is greater than the minimum activation count in the page table, then the row address and activation count corresponding to the minimum activation count in the page table are replaced with the currently active row address and activation count. Figure 4 S8);

[0072] If the activation count carried by the currently active row address is less than the minimum activation count in the page table, the data in the page table remains unchanged. Figure 4 S9).

[0073] In step S3, if the page table stores multiple row addresses, it is determined whether the currently active row address is the same as any of the multiple row addresses stored in the page table. If the currently active row address is the same as any of the multiple row addresses stored in the page table, the condition for updating the activation count is met; therefore, the activation count of the row address that is the same as the one in the page table is updated and replaced. Step S3 can be achieved through... Figure 2 The first comparator circuit 220 is implemented in the middle.

[0074] In step S4, the activation count carried by the currently activated row address refers to the activation count corresponding to the currently activated row address. This activation count can be stored in the currently activated storage row and read from the storage row during activation, or it can be stored or calculated in other ways. The activation count updated in step S4 can be an updated... Figure 2 The activation count in the activation count register 213.

[0075] Step S7 can be performed by Figure 2The first comparison circuit 220 in the page table can find the minimum activation count in the page table, and the comparison between the activation count carried by the currently active row address and the minimum activation count in the page table can also be completed by the first comparison circuit 220.

[0076] In step S9, the data in the page table remains unchanged, and the currently active row address and its activation count can be discarded outside the page table.

[0077] Therefore, by storing the activated row address and its activation count in the page table, and comparing the currently activated row address and its activation count with the row address and its activation count stored in the page table each time, the row address with the most activation count can be filtered out, thereby avoiding real-time monitoring and tracking of all rows in the memory and reducing the monitoring burden of the memory.

[0078] In some embodiments, prior to step S3, the following steps are also performed: initializing the row address register and activation count register in the page table ( Figure 4 Step S1); where the row address register and the activation count register can be Figure 2 The row address register 212 and the activation count register 213 are in the middle.

[0079] Read the address of the currently active row and its activation count. Figure 4 In step S2), the row address of the currently active storage row and its activation count are transmitted to the first comparison circuit 220 for comparison operation;

[0080] Between step S4 and step S7, the following is also set:

[0081] If the currently active row address is different from the row address stored in the page table, then check if there is any free space in the page table. Figure 4 Step S5);

[0082] If there are still free slots in the page table, then the address of the currently active row and its activation count are placed in the free slot in the page table. Figure 4 Step S6);

[0083] If there are no free spaces in the page table, proceed to step S7 for comparison and judgment.

[0084] In some embodiments, the refresh control method further includes:

[0085] The minimum number of activations in the page table is compared with a preset threshold. If the minimum number of activations in the page table is greater than the preset threshold, an Alert Back-off (ABO) signal is generated; otherwise, no Alert Back-off signal is generated.

[0086] The avoidance warning signal is a flag signal in the memory used to pause read / write operations and perform refresh operations.

[0087] Once the avoidance warning signal is triggered, the memory stops all other operations (including read, write, and activation operations) and only performs a refresh operation. The avoidance warning signal is triggered by the memory and received by the memory controller. When the memory controller receives the avoidance warning signal, it immediately controls the memory to suspend read and write operations and perform a refresh.

[0088] The specific value of the preset threshold can be determined by a single factor or a combination of factors such as process yield, operating frequency, and refresh rate. In some embodiments, the preset threshold can be set to, for example, 3000.

[0089] In other embodiments, an avoidance warning signal can be generated when a predetermined number of activations (e.g., three or four) in the page table exceed a preset threshold. This reduces the triggering conditions for the avoidance warning signal and improves data stability.

[0090] Therefore, by setting a trigger condition for an avoidance warning signal, the memory can be refreshed in a timely manner when the activation count of a certain row or rows is too high, thus fixing vulnerabilities and correcting errors. Furthermore, by setting the trigger condition to activate the avoidance warning signal when the minimum activation count of all row addresses within the page table exceeds a preset threshold, the circuit processing logic can be simplified, and the chip area can be reduced.

[0091] In some embodiments, the refresh control method further includes: finding the row address with the highest activation count in the page table through comparison, and refreshing one or more rows adjacent to the row address with the highest activation count in the page table. After refreshing, the row address with the highest activation count can be deleted from the page table. This comparison can be implemented by the second comparison circuit 230.

[0092] By comparing and finding the row address with the highest number of activations in the page table, and periodically refreshing the rows adjacent to the row address with the highest number of activations in the page table, row hammer protection can be performed on rows with a high number of activations in advance, reducing the frequency of memory pause operations and improving memory efficiency.

[0093] Figure 5 This is a schematic diagram illustrating the dynamic changes of data within a page table, as provided in an embodiment of this application. Figure 5 The Chinese address register includes 5 rows, and the second preset condition is that the minimum number of activations in the page table is greater than a preset threshold, with the preset threshold being 2400 as an example. Figure 5 The row address is represented in hexadecimal.

[0094] After a period of operation, the five row addresses stored in the page table are 001A (corresponding to 120 activations), 0052 (corresponding to 220 activations), 0034 (corresponding to 232 activations), 0049 (corresponding to 524 activations), and 007E (corresponding to 114 activations).

[0095] Subsequently, the memory was activated, with the row address being 0052, corresponding to activation count 265. According to... Figure 4 According to the process shown, based on step S3, the currently activated row address is the same as the row address stored in the second row of the page table. Therefore, the activation count of the second row address is updated to the activation count 265 carried by the currently activated row address.

[0096] Subsequently, the memory was activated, with the row address being 0031, corresponding to an activation count of 101. According to... Figure 4 According to the process shown, based on step S3, the currently activated row address is different from the row addresses of all rows in the page table; based on step S5, there are no empty spaces in the page table; based on step S7, the activation count of the currently activated row address is less than the minimum activation count of 114 in the page table, therefore, the data in the page table remains unchanged.

[0097] Subsequently, the memory was activated, with the row address being 0035, corresponding to activation count 126. According to... Figure 4 The flowchart shows that after steps S3, S5, and S7, since the activation count of the currently active row address is greater than the minimum activation count of 114 in the page table, step S8 is executed. This replaces the row address and activation count corresponding to the minimum value in the page table with the currently active row address and its activation count. At this point, the fifth row of the page table is replaced with 0035, which corresponds to an activation count of 126.

[0098] Subsequently, the memory receives the row hammer refresh command RHR. According to the second comparison circuit 230, the maximum value of the activation count, 524, is compared. The row address of the fourth row of the page table is output to perform the row hammer protection refresh operation. Furthermore, the row address and activation count of the fourth row in the page table are cleared.

[0099] After multiple operations, the five row addresses stored in the page table are 001A (corresponding to 3320 activations), 0052 (corresponding to 2650 activations), 0034 (corresponding to 3210 activations), 0089 (corresponding to 2860 activations), and 0035 (corresponding to 1200 activations). Subsequently, the memory is activated, with row address 0079 activated, corresponding to 2410 activations. When this row address enters the page table via step S8, the minimum activation count of the row address in the page table exceeds the preset threshold of 2400. At this point, the refresh control circuit generates an avoidance warning signal, instructing the controller to suspend memory operations and perform a refresh.

[0100] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A refresh control circuit, characterized in that, Includes a page table, a first comparator circuit, and a second comparator circuit; wherein, The page table is configured to store multiple row addresses and the number of times the multiple row addresses are activated; The first comparison circuit is connected to the page table and is configured to receive the currently active row address and its activation count, and compare the currently active row address and its activation count with multiple row addresses and their activation counts stored in the page table. When the first preset condition is met, the currently active row address and its activation count are stored in the page table. The second comparison circuit is connected to the page table and is configured to compare the activation counts of multiple row addresses in the page table and output the row address with the highest activation count as a candidate row address.

2. The refresh control circuit according to claim 1, characterized in that, The refresh control circuit is configured to generate an avoidance warning signal when a second preset condition is met; wherein, the avoidance warning signal is a flag signal in the memory used to pause read / write operations and perform refresh operations.

3. The refresh control circuit according to claim 2, characterized in that, The second preset condition is: the minimum number of activations of all row addresses in the page table is greater than a preset threshold.

4. The refresh control circuit according to claim 1, characterized in that, The page table is configured to store the row address output by the first comparator circuit and its activation count during a first time period; the page table is also configured to store the row address output by the third comparator circuit during a second time period, and to increment the count value corresponding to the row address stored in the page table by 1.

5. The refresh control circuit according to claim 1, characterized in that, The refresh control circuit is configured to periodically receive refresh commands, and based on the refresh commands, refresh one or more rows adjacent to the candidate row address, and delete the candidate row address from the page table.

6. The refresh control circuit according to claim 1, characterized in that, The first preset conditions include: there are free positions in the page table where no row address is stored; the currently activated row address is the same as the row address stored in the page table; or the activation count of the currently activated row address is greater than the minimum value of the activation counts of multiple row addresses stored in the page table.

7. A memory comprising a refresh control circuit and a storage body as described in any one of claims 1-6, the storage body comprising a plurality of storage rows, wherein the storage rows store stored data and activation counts.

8. A refresh control method, comprising: Determine if the currently active row address is the same as the row address stored in the page table; If they are the same, then update the activation count corresponding to the row address in the page table to the activation count carried by the currently active row address; If they are not the same, the activation count carried by the currently active row address is compared with the minimum activation count in the page table to determine whether the activation count carried by the currently active row address is greater than the minimum activation count in the page table. If the activation count carried by the currently active row address is greater than the minimum activation count in the page table, then the row address and activation count corresponding to the minimum activation count in the page table will be replaced with the currently active row address and activation count. If the activation count carried by the currently active row address is less than the minimum activation count in the page table, the data in the page table remains unchanged.

9. The refresh control method according to claim 8, characterized in that, The refresh control method further includes: The minimum number of activations in the page table is compared with a preset threshold. If the minimum number of activations in the page table is greater than the preset threshold, an avoidance warning signal is generated. The avoidance warning signal is a flag signal in the memory used to pause read / write operations and perform refresh operations.

10. The refresh control method according to claim 8, characterized in that, The refresh control method further includes: Refresh one or more rows adjacent to the row address with the highest number of activations in the page table.

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